Method of manufacturing a semiconductor device

Abstract

The application provides a semiconductor device manufacturing method. After forming a medium-voltage gate oxide layer covering at least a medium-voltage region and a low-voltage region, and before forming a patterned mask layer for defining the medium-voltage gate oxide layer to be reserved on the medium-voltage region, the mask layer on the medium-voltage gate oxide layer in the low-voltage region is opened, and the mask layer on the bird beak region of the high-voltage gate oxide layer in the high-voltage region is also opened. Thus, when the medium-voltage gate oxide layer on the low-voltage region is thinned or removed by using a wet etching process, the bird beak region of the high-voltage gate oxide layer in the high-voltage region is also thinned or removed. Therefore, the additional mask cost and process cost can be avoided, the problem that the source-drain ions injected into the source region in the subsequent process are blocked due to the excessive thickness of the bird beak region can be solved, the lateral distance between the metal silicide and the contact plug on the source region and the channel in the subsequent process can be shortened, the resistance of the source region can be reduced, and the device performance can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor device manufacturing, and particularly relates to a manufacturing method of a semiconductor device. BACKGROUND

[0002] In some current integrated circuit products, MOS transistors of different working voltages need to be integrated to achieve the required functions and performance, for example, high-voltage transistors, medium-voltage transistors and low-voltage transistors are manufactured together on the same substrate through a CMOS process. Among them, the manufacturing of gate oxide layer is one of the most important process steps in the manufacturing process of such products, which directly affects the threshold voltage, saturation current, gate leakage current, gate breakdown voltage and reliability of each transistor, and the thicknesses of the gate oxide layers required by the high-voltage transistors, the medium-voltage transistors and the low-voltage transistors are different, among which the thickness of the gate oxide layer of the high-voltage transistor is relatively thick compared with those of the other transistors.

[0003] In addition, for more and more application scenarios, in order to achieve the effects of reducing layout area, facilitating low-power and low-cost control and the like, an asymmetric HVMOS transistor is widely used, which separates the drain region 100d from the gate (not shown, which is formed on the high-voltage gate oxide layer HOX 103) through shallow trench isolation (STI), so as to form an asymmetric structure at the source region 100s and the drain region 100d, and high voltage is applied on the drain region and the gate during operation.

[0004] The high-voltage gate oxide layer HOX 103 of the above asymmetric HVMOS transistor is usually formed through a thermal oxidation process. Since a longer thermal oxidation process time is required to form a thicker high-voltage gate oxide layer HOX 103, oxygen will laterally diffuse to the surface layer of the source region 100s which is masked by the silicon nitride mask layer 102 in the vicinity of the high-voltage gate oxide layer HOX 103 region, forming a beak structure 103a. On the one hand, the beak structure 103a will block the subsequent source-drain ion implantation in the source region 100s, the thicker the beak structure 103a, the more the source-drain ion dose loss in the source region 100s, and thus the device performance is reduced; on the other hand, the beak structure 103a occupies a certain area of the source region 100s, causing the metal silicide formed on the source region 100s to relatively move outward and reduce in area, and thus the area of the metal silicide at the bottom of the contact plug formed subsequently is too small, causing the contact resistance to increase, and the lateral distance between the contact plug on the source region 100s and the channel (i.e. the active region below the high-voltage gate oxide layer HOX 103) is inevitably increased by the lateral extension length of the beak structure 103a, which also causes the source resistance to increase, and thus the device performance is reduced.

[0005] The above problems can also exist in symmetric HVMOS transistors.

[0006] Therefore, there is a need for a new solution to improve the defects caused by the bird beak structure of the high voltage transistor region. SUMMARY

[0007] The present application aims to provide a manufacturing method of a semiconductor device, which can improve the defects caused by the bird beak structure of the high voltage transistor region.

[0008] To achieve the above-mentioned purpose, the present application provides a manufacturing method of a semiconductor device, comprising the following steps:

[0009] providing a substrate, forming a plurality of shallow trench isolation structures in the substrate to define a high voltage region, a medium voltage region and a low voltage region;

[0010] masking the substrate surface of the medium voltage region and the low voltage region and exposing the substrate surface of the high voltage region, and forming a high voltage gate oxide layer on the high voltage region by using a first thermal oxidation process, the high voltage gate oxide layer having a bird beak region;

[0011] exposing at least the substrate surface of the low voltage region and the medium voltage region, and forming a medium voltage gate oxide layer covering at least the substrate surface of the medium voltage region and the low voltage region;

[0012] forming a patterned mask layer, the patterned mask layer masking the medium voltage gate oxide layer to be reserved on the medium voltage region and exposing the medium voltage gate oxide layer on the low voltage region and the bird beak region of the high voltage gate oxide layer;

[0013] using a wet etching process to thin or remove the medium voltage gate oxide layer on the low voltage region and the bird beak region of the high voltage gate oxide layer with the patterned mask layer as a mask.

[0014] Optionally, at the end of the wet etching process, the remaining medium voltage gate oxide layer on the low voltage region serves as the required thickness of the low voltage gate oxide layer of the low voltage region; or, after removing the medium voltage gate oxide layer on the low voltage region and exposing the substrate surface of the low voltage region by using the wet etching process, the manufacturing method further comprises: removing the patterned mask layer and forming a low voltage gate oxide layer on the substrate surface of the low voltage region exposed by using a third thermal oxidation process or a chemical vapor deposition process.

[0015] Optionally, the thickness of the low voltage gate oxide layer, the medium voltage gate oxide layer and the high voltage gate oxide layer increases in turn.

[0016] Optionally, after removing the patterned mask layer and forming the low voltage gate oxide layer, the manufacturing method further comprises:

[0017] forming a gate electrode on the high-voltage gate oxide layer of the high-voltage region, the medium-voltage gate oxide layer of the medium-voltage region and the low-voltage gate oxide layer of the low-voltage region;

[0018] forming a sidewall on the sidewall of the gate electrode;

[0019] forming a source region and a drain region in the substrate on both sides of the gate electrode by using a source-drain ion implantation process;

[0020] forming a metal silicide on the top of the gate electrode, the source region and the drain region by using a metal silicide process;

[0021] forming a contact plug on the metal silicide on the top of the gate electrode, the source region and the drain region.

[0022] Optionally, the source region and the drain region of the high-voltage region are of an asymmetric structure.

[0023] Optionally, the drain region of the high-voltage region is spaced apart from the gate electrode by a corresponding shallow trench isolation structure, and the gate electrode continuously extends from the high-voltage gate oxide layer to the shallow trench isolation structure between the gate electrode and the drain region.

[0024] Optionally, the source region and the drain region of the high-voltage region are of a first conductivity type, and the manufacturing method further comprises: before forming the high-voltage gate oxide layer, forming a well of a second conductivity type in the high-voltage region, forming a drift region of the first conductivity type in the well on both sides of the high-voltage gate oxide layer and a drift region of the second conductivity type outside the drift region of the first conductivity type, and forming a body contact region in the drift region of the second conductivity type after forming the sidewall and before forming the metal silicide; wherein the source region and the drain region of the high-voltage region are respectively formed in the drift region of the first conductivity type on both sides of the high-voltage gate oxide layer.

[0025] Optionally, after forming the high-voltage gate oxide layer, the high-voltage region is first masked and the substrate surfaces of the medium-voltage region and the low-voltage region are exposed, and a medium-voltage gate oxide layer is formed on the medium-voltage region and the low-voltage region by using a corresponding second thermal oxidation process or a vapor deposition process; wherein, before the high-voltage region is masked, the hard mask layer is removed, or, after the medium-voltage gate oxide layer on the low-voltage region and the beak region of the high-voltage gate oxide layer are thinned or removed by using the wet etching process, the hard mask layer is removed.

[0026] Optionally, after forming the high-voltage gate oxide layer, the hard mask layer is removed to expose the substrate surface of the low-voltage region and the medium-voltage region and the remaining surface of the high-voltage region, and a corresponding second thermal oxidation process or vapor deposition process is used to form the medium-voltage gate oxide layer on the high-voltage region, the bird-beak region, the medium-voltage region and the low-voltage region.

[0027] Compared with the prior art, in the technical scheme of the present application, after forming the medium-voltage gate oxide layer covering at least the medium-voltage region and the low-voltage region and before forming the patterned mask layer for defining the medium-voltage gate oxide layer to be reserved on the medium-voltage region, the mask layer on the medium-voltage gate oxide layer of the low-voltage region is opened, and the mask layer on the bird-beak region of the high-voltage gate oxide layer of the high-voltage region is also opened, so that the bird-beak region of the high-voltage gate oxide layer of the high-voltage region is thinned or removed at the same time when the medium-voltage gate oxide layer on the low-voltage region is thinned or removed by using a wet etching process, thereby avoiding the increase of additional mask cost and process cost on the one hand, and improving the problem that the source-drain ions injected into the source region in the subsequent process are blocked due to the excessive thickness of the bird-beak region, and avoiding the problem that the device performance is reduced due to the decrease of ion dopant amount in the source region of the high-voltage region. In addition, at least part of the bird-beak region of the high-voltage gate oxide layer is removed, which can shorten the lateral distance between the metal silicide and the contact plug on the source region and the channel in the subsequent process, reduce the resistance of the source region, and improve the device performance. BRIEF DESCRIPTION OF DRAWINGS

[0028] Those skilled in the art will understand that the provided drawings are for the purpose of better illustrating the present application and do not constitute any limitation on the scope of the present application. Among them:

[0029] Figure 1 is a device cross-sectional structure schematic diagram of a high-voltage gate oxide layer of a high-voltage transistor in the prior art.

[0030] Figure 2 is a flowchart of a manufacturing method of a semiconductor device according to an embodiment of the present application.

[0031] Figures 3A to 3E is a device cross-sectional structure schematic diagram in the manufacturing method of a semiconductor device according to an embodiment of the present application.

[0032] Figures 4 to 5 is a cross-sectional structure schematic diagram of a high-voltage transistor formed in the manufacturing method of a semiconductor device according to an embodiment of the present application.

[0033] Figures 6A to 6E is a device cross-sectional structure schematic diagram in the manufacturing method of a semiconductor device according to another embodiment of the present application. DETAILED DESCRIPTION

[0034] In the following description, numerous specific details are set forth to provide a more thorough understanding of the present application. However, it will be apparent to one of skill in the art upon reading this disclosure that the present application can be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present application. It should be understood that the present application can be practiced with departure from these specific details, and that specific details can be implemented only in some embodiments. There are many

[0035] The technical solutions of the present application will be further described in detail below in combination with the drawings and specific embodiments. The advantages and features of the present application will be more apparent according to the following description. It should be noted that the drawings are very simplified and use non-precise proportions, only for the purpose of facilitating and clearly assisting the description of the embodiments of the present application.

[0036] Please refer to Figure 2 An embodiment of the present application provides a manufacturing method of a semiconductor device, comprising the following steps:

[0037] S1, providing a substrate, forming a plurality of shallow trench isolation structures in the substrate to define a high-voltage region, a medium-voltage region and a low-voltage region;

[0038] S2, masking the substrate surface of the medium-voltage region and the low-voltage region and exposing the substrate surface of the high-voltage region, and forming a high-voltage gate oxide layer on the high-voltage region by using a first thermal oxidation process, the high-voltage gate oxide layer having a beak region;

[0039] S3, exposing at least the substrate surface of the low-voltage region and the medium-voltage region, and forming a medium-voltage gate oxide layer, the medium-voltage gate oxide layer covering at least the substrate surface of the medium-voltage region and the low-voltage region;

[0040] S4, forming a patterned mask layer, which masks the middle voltage gate oxide layer to be reserved on the middle voltage region and exposes the middle voltage gate oxide layer on the low voltage region and the bird's beak region of the high voltage gate oxide layer;

[0041] S5, thinning or removing the middle voltage gate oxide layer on the low voltage region and the bird's beak region of the high voltage gate oxide layer by using a wet etching process with the patterned mask layer as a mask.

[0042] Please refer to Figure 3A In step S1, the substrate 200 provided can be any suitable semiconductor substrate material such as bulk silicon, silicon-on-insulator, silicon carbide, etc. A pad oxide layer (not shown) is then formed on the substrate 200 by a thermal oxidation process, and a hard mask layer (not shown) is deposited by a chemical vapor deposition process or the like using a material such as silicon nitride. Next, a plurality of shallow trench isolation structures STI are formed by a shallow trench isolation process including: coating a photoresist on the hard mask layer, and performing photolithography on the photoresist; etching the hard mask layer 202 with the photoresist after lithography as a mask and the pad oxide layer as an etching stop layer; then removing the photoresist, and etching the pad oxide layer and the substrate 200 with the hard mask layer as a mask, thereby forming shallow trenches (not shown) in the substrate 200; forming a liner oxide layer (not shown) on the sidewalls and bottom surface of the shallow trenches and filling an insulating dielectric material (not shown) such as silicon oxide into the shallow trenches by a deposition process; and performing chemical mechanical polishing or etching back on the top surface of the filled insulating dielectric material, thereby forming the shallow trench isolation structures STI filled in the shallow trenches; and then removing the remaining hard mask layer and pad oxide layer.

[0043] Please refer to Figure 3A In step S1, a part of the shallow trench isolation structures STI is located at the boundary between different device regions, thereby defining a high voltage region HV (i.e. an active region of a high voltage element) for forming a high voltage transistor and the like high voltage element with a high working voltage, a middle voltage region MV (i.e. an active region of a middle voltage element) for forming a middle voltage transistor and the like middle voltage element with a middle working voltage, and a low voltage region LV (i.e. an active region of a low voltage element) for forming a low voltage transistor and the like low voltage element with a low working voltage in the substrate 200. Another part of the shallow trench isolation structures STI can be formed in the high voltage region HV, the middle voltage region MV or the low voltage region LV for realizing local isolation in these active regions, for example, a corresponding shallow trench isolation structure STI is provided in the high voltage region HV, which is used as a spacing structure between a subsequently formed gate and drain region in the high voltage region HV, and makes the subsequently formed source and drain regions in the high voltage region HV asymmetric, thereby making the high voltage transistor formed in the high voltage region HV an asymmetric high voltage transistor.

[0044] Optionally, before or after forming the shallow trench isolation structures STI to define the high voltage region HV, the medium voltage region MV and the low voltage region LV, corresponding N-type or P-type ion implantation is performed to form wells, drift regions, etc. in the substrate 200 of the high voltage region HV, the medium voltage region MV or the low voltage region LV. For example, before or after forming the shallow trench isolation structures STI to define the high voltage region HV, ions of the second conductivity type (e.g. P-type) are implanted into the substrate 200 of the high voltage region HV to form a high voltage well (HVPW) 200e of the second conductivity type in the substrate 200 of the high voltage region HV, and further, ions of the first conductivity type (e.g. N-type) are implanted into the substrate 200 of the high voltage region HV on both sides of the high voltage gate oxide HOX to be formed to form the required drift regions (e.g. N drift) 200a, 200b of the first conductivity type, and ions of the second conductivity type (e.g. P-type) are implanted into the substrate 200 outside the drift regions to form the required drift regions (e.g. P drift) 200c, 200e of the second conductivity type. Please refer to Figure 3A and Figure 4 for more information. The drift region 200a is used to provide an area for forming the drain region 200d later, the drift region 200b is used to provide an area for forming the source region 200s later, and the drift regions 200c, 200e are used to provide areas for forming the body contact regions 200p later.

[0045] In step S2, any suitable high voltage gate oxide process can be used to form the high voltage gate oxide (HOX) 203 required on the high voltage region HV.

[0046] As an example, please refer to Figure 3A In step S2, the step of forming the high voltage gate oxide (HOX) 203 includes:

[0047] First, a material such as silicon oxide is deposited on the substrate 200 and the shallow trench isolation structures STI to form an etching protection layer 201, and further, a material such as silicon nitride is deposited on the etching protection layer 201 to form a hard mask layer 202;

[0048] Next, a patterned photoresist layer is formed by photoresist coating, exposure, development, etc. to define the formation area of the high voltage gate oxide 203, and the hard mask layer 202 and the etching protection layer 201 of the high voltage region HV are etched to open, with the patterned photoresist layer as a mask. Thus, the patterned hard mask layer 202 can mask the medium voltage region MV and the low voltage region LV while exposing the surface of the substrate 200 of the high voltage region HV to be formed with the high voltage gate oxide 203, and then the patterned photoresist layer is removed.

[0049] Then, the substrate exposed by the hard mask layer 202 is etched to form a first trench (not shown) with a desired depth, or a sacrificial oxide layer (not shown) is formed by a thermal oxidation process on the substrate exposed by the hard mask layer 202, and the sacrificial oxide layer is etched to form a first trench (not shown) with a desired depth. Then, the substrate 200 exposed by the first trench is thermally oxidized by a first thermal oxidation process such as a high-temperature furnace tube oxidation process to form a high-voltage gate oxide layer 203 with a desired thickness. The first thermal oxidation process has a long process time, and in the first thermal oxidation process, the oxygen mainly diffuses vertically to form the high-voltage gate oxide layer 203 with a large thickness, but there is also a certain degree of horizontal diffusion of oxygen, which diffuses horizontally to the substrate 200 in the high-voltage area HV around the first trench and forms a beak area 203a of the high-voltage gate oxide layer 203.

[0050] In step S3, a medium-voltage gate oxide layer (GOX) 204a with a desired thickness can be formed on the medium-voltage area MV by any suitable medium-voltage gate oxide process. In this step, the medium-voltage gate oxide process also forms a medium-voltage gate oxide layer (GOX) 204b with the same thickness as the medium-voltage gate oxide layer (GOX) 204a on the high-voltage area HV and the low-voltage area LV.

[0051] As an example of the present embodiment, in step S3, the step of forming the medium-voltage gate oxide layer includes:

[0052] First, referring to Figure 3B , the hard mask layer 202 and the etching protection layer 201 thereunder are removed, so that not only the surfaces of the substrate 200 in the medium-voltage area MV and the low-voltage area LV and the high-voltage gate oxide layer 203, but also the top of the shallow trench isolation structure STI in each area, the beak area 203a of the high-voltage area HV, and the surface of the substrate 200 in the region of the high-voltage area HV where the high-voltage gate oxide layer 203 is not formed are exposed.

[0053] Then, a second thermal oxidation process (which has a shorter process time than the first thermal oxidation process) such as a high-temperature furnace tube oxidation process is used to thermally oxidize the exposed substrate 200 surface in the high-voltage region HV, the low-voltage region LV, and the medium-voltage region MV. The exposed silicon of the substrate 200 in each of the high-voltage region HV, the low-voltage region LV, and the medium-voltage region MV reacts with oxygen, thereby forming a medium-voltage gate oxide layer on the exposed substrate 200 surface in the high-voltage region HV (including the exposed substrate in the bird's beak region and other regions), the low-voltage region LV, and the medium-voltage region MV. The silicon of the substrate 200 in other regions is not exposed to oxygen because it is shielded by the hard mask layer 202 and the high-voltage gate oxide layer 203. The medium-voltage gate oxide layer 204b is formed on the substrate 200 in the low-voltage region LV, the medium-voltage gate oxide layer 204a is formed on the substrate 200 in the medium-voltage region MV, and the medium-voltage gate oxide layer 204c is formed on the substrate 200 in the high-voltage region HV. In addition, oxygen molecules in the second thermal oxidation process also diffuse longitudinally and laterally near the bird's beak region 203a of the high-voltage region HV, thereby further thickening the oxide layer of the bird's beak region 203a of the high-voltage region HV.

[0054] As another example of the present embodiment, in step S3, after removing the hard mask layer 202 and the etching protection layer 201 thereunder, a vapor deposition process such as chemical vapor deposition, atomic layer deposition, plasma-enhanced deposition, or the like can be used to replace the second thermal oxidation process described above, thereby depositing and forming a medium-voltage gate oxide layer GOX on the exposed device surface. The medium-voltage gate oxide layer GOX formed at this time not only covers the exposed substrate surface, but also covers the surfaces of the shallow trench isolation structure STI, the high-voltage gate oxide layer 203, and the bird's beak region 203a. Moreover, the thickness of the high-voltage gate oxide layer 203 and the medium-voltage gate oxide layer GOX thereon needs to meet the thickness requirement range of the gate oxide required for device manufacturing in the high-voltage region.

[0055] In step S4, please refer to Figure 3CIn the surface of the high-voltage gate oxide layer 203 and the medium-voltage gate oxide layers 204a, 204b, 204c and the shallow trench isolation structure STI, etc., a photoresist is coated, and the coated photoresist is exposed by means of a photo mask used for defining the medium-voltage gate oxide layer to be reserved in the medium-voltage region MV, and the exposed photoresist is developed, etc., to form a patterned photoresist layer as a required patterned mask layer 301. The patterned mask layer 301 can mask the medium-voltage gate oxide layer 204a to be reserved in the medium-voltage region MV and the area of the high-voltage gate oxide layer 203 in the high-voltage region HV except the bird's beak region 203a, etc., and expose the surface of the medium-voltage gate oxide layer 204b on the low-voltage region LV, the top of the bird's beak region 203a and the medium-voltage gate oxide layer 204c in the high-voltage region HV. In this embodiment, the patterned mask layer 301 also exposes part or all of the top surface of the shallow trench isolation structure near the medium-voltage gate oxide layer. In this step, compared with the prior art, the number of photo masks is not increased, and only the pattern of the photo mask is modified, specifically, a pattern (for example, an opening) for opening the bird's beak region 203a is added in the photo mask used for defining the gate oxide layer to be reserved in the medium-voltage region MV.

[0056] Reference is made to Figure 3D In step S5, the medium-voltage gate oxide layers 204b, 204c exposed on the low-voltage region LV and the high-voltage region HV and the bird's beak region 203a exposed on the high-voltage region HV are thinned or removed by means of any suitable wet etching process under the mask of the patterned mask layer 301. As an example, the medium-voltage gate oxide layers 204b, 204c exposed on the low-voltage region LV and the high-voltage region HV and the bird's beak region 203a exposed on the high-voltage region HV are wet etched by means of any suitable etching liquid such as HF acid solution, SPM (a mixture of H2SO4, H2O2 and H2O) or SC1 (a mixture of NH4OH, H2O2 and H2O), etc., until the medium-voltage gate oxide layer 204b exposed on the low-voltage region LV is thinned to a low-voltage gate oxide layer (not shown) with a required thickness on the low-voltage region LV. At this time, the bird's beak region 203a exposed on the high-voltage region HV is also thinned by the wet etching or even partially or completely removed in the lateral direction. Even if the bird's beak region 203a is partially removed, the remaining bird's beak region 203a will be continuously removed in subsequent steps of wafer cleaning, and the part of the bird's beak will not affect the formation quality of the metal silicide before the metal silicide is formed, i.e., will not affect the formation quality of the subsequent contact plug, so that the lateral distance between the metal silicide on the source region and the contact plug to the channel can be shortened, the resistance of the source region is reduced, and the device performance is improved. In this example, the medium-voltage gate oxide layers 204b, 204c exposed on the low-voltage region LV and the high-voltage region HV are completely removed, and the bird's beak region 203a exposed on the high-voltage region HV is also completely removed by the wet etching.

[0057] It should be understood that the manufacturing method of the present embodiment does not increase the number of masks compared with the prior art, and only increases a pattern (e.g. an opening) for opening the bird beak region 203a in the mask used to define the medium voltage gate oxide, so that the bird beak region 203a of the high voltage gate oxide 203 can be thinned or removed at the same time as the medium voltage gate oxide on the low voltage region LV is thinned or removed in the subsequent process, thereby improving the defects caused by the bird beak region 203a in the prior art without increasing the number of masks and process steps.

[0058] Optionally, after step S5, please refer to Figure 3E The patterned mask layer 301 is also removed, and a third thermal oxidation process or a chemical vapor deposition process is further used to form a low voltage gate oxide 212 on the substrate 200 surface exposed by the low voltage region LV. Optionally, the thicknesses of the formed low voltage gate oxide 212, the remaining medium voltage gate oxide 204a and the remaining high voltage gate oxide 203 increase in turn.

[0059] As an example, the third thermal oxidation process or the chemical vapor deposition process forms a low voltage oxide layer on the substrate surface of the high voltage region HV exposed after the bird beak region 203a and the medium voltage gate oxide 204c are removed, while forming the low voltage gate oxide 212 on the low voltage region LV. The low voltage oxide layer can be retained as a protective layer of the substrate in the coverage area in the subsequent process, or can be removed by any suitable process at any suitable process node, for example, being etched and removed together when the deposited metal silicide barrier layer (SAB) is etched in the subsequent process.

[0060] Optionally, after the patterned mask layer 301 is removed and the above-mentioned low voltage gate oxide 212 is formed, the manufacturing method of the present embodiment further includes:

[0061] (1), please refer to Figure 3E and Figure 4 A etch stop layer 205 is deposited on the top surface of the substrate 200, the high voltage gate oxide 203, the medium voltage gate oxide 204a, the low voltage gate oxide 212 and the shallow trench isolation structure STI.

[0062] (2), please continue to refer to Figure 3E and Figure 4 A gate 206 is formed on the high voltage gate oxide 203 of the high voltage region HV, the medium voltage gate oxide 204a of the medium voltage region MV and the low voltage gate oxide 212 of the low voltage region LV by any suitable gate process, and optionally, the gate 206 of the high voltage region HV extends from above part of the top of the high voltage gate oxide 203 to above part of the top of the adjacent shallow trench isolation structure STI.

[0063] (3), please continue to refer toFigure 3E and Figure 4 By any suitable sidewall process, sidewalls 207 are formed on the sidewalls of each of the gates 206.

[0064] (4), please continue to refer to Figure 3E and Figure 4 By a source-drain ion implantation process, ions of a first conductivity type (for example, N-type) are implanted into the substrate 200 (i.e., drift regions 200a and 200b) on both sides of each of the gates 206, forming source regions and drain regions. Optionally, a source region 200s is formed in the substrate 200 on one side of the gate 206 of the high-voltage region HV, and the source region 200s and the gate 206 are not separated by a shallow trench isolation structure STI. A drain region 200d is formed in the substrate 200 on the other side of the gate 206 of the high-voltage region HV, and the drain region 200d and the gate 206 are separated by a shallow trench isolation structure STI. Thus, the drain region 200d and the source region 200s formed in the high-voltage region HV constitute an asymmetric structure.

[0065] Optionally, ions of a second conductivity type are implanted into the drift regions 200c and 200e, forming body contact regions 200p on the outside of the source region 200s and on the outside of the drain region 200d. As an example, the source region 200s and the body contact region 200p adjacent thereto are immediately adjacent to each other, and the drain region 200d and the body contact region 200p adjacent thereto are separated by a shallow trench isolation structure STI.

[0066] It should be understood that in this step, the original beak region 203a of the high-voltage region HV is thinned or at least partially removed in the lateral direction, so that when the source-drain ion implantation is performed, the beak region 203a will not block the source-drain ion implantation due to its excessive thickness in the longitudinal direction, thereby reducing the blocking loss of the source-drain ions implanted in the drift region 200 compared to the prior art. The implantation depth and implantation dose of the source-drain ions in the source region 200s can be guaranteed, and the problem of reduced device performance due to reduced performance of the source region 200s is avoided.

[0067] (5), please refer to Figure 5, a metal silicide 209 is formed on top of the gate 206, the source region and the drain region by a metal silicidation process, for example, a silicide barrier layer 208 is first deposited and etched by a lithography and etching process to open the silicide barrier layer 208 on top of the gate 206, the source region and the drain region and the thermal oxide layer on top of the source region 200s of the high voltage region HV and the etching protection layer 205, then a metal such as cobalt is deposited and two annealing processes are performed and the unreacted metal is removed to form the metal silicide 209. In this step, since the original beak region 203a of the high voltage region HV is thinned in the longitudinal direction or at least partially removed in the lateral direction, when the metal silicide 209 is formed on the source region 200s in the high voltage region HV, the problem that the metal silicide 209 formed on the source region 200s is too small in area or relatively far away from the gate 206 due to the beak region 203a being too long in the lateral direction will not occur, thereby ensuring that the bottom of the contact plug 211s formed subsequently contacts the metal silicide 209 with sufficient area, so as to reduce the resistance at the end of the source region 200s and improve the performance of the high voltage transistor.

[0068] (6), a contact hole (not shown) is formed on the metal silicide on top of the gate 206, the source region and the drain region by first depositing an interlayer dielectric layer 210 and etching a contact hole, then a metal is filled into the contact hole by a copper electroplating or tungsten deposition process, and then a corresponding contact plug is formed on top of the gate 206, the source region and the drain region, for example, the contact plug 211g is formed on top of the gate 206 of the high voltage region HV, the contact plug 211s is formed on top of the source region 200s, and the contact plug 211d is formed on top of the drain region 200d. Since the bottom of the contact plug 211d has a metal silicide 209 with a large enough area, the contact resistance is reduced. In addition, since the beak region 203a of the high voltage gate oxide layer 203 is at least partially removed in the lateral direction, the occupation of the contact area of the metal silicide formed on the silicon substrate can be reduced, that is, the lateral distance between the metal silicide 209 on the source region 200s and the contact plug 211s to the channel (i.e., the substrate 200 region near the remaining high voltage gate oxide layer 203) is shortened, the resistance of the source region 200s is reduced, and the device performance is improved.

[0069] In the above embodiment, the hard mask layer 202 and the etching protection layer 201 are first removed in step S3, so that the medium voltage gate oxide layer GOX can be formed on the high voltage region HV, the medium voltage region MV and the low voltage region LV at one time, but the technical solution of the present application is not limited to this.

[0070] In other embodiments of the present application, in step S3, the high voltage region HV can also be masked, only exposing the substrate surface of the medium voltage region MV and the low voltage region LV, so that when the medium voltage gate oxide layer is formed on the substrate surface of the medium voltage region MV and the low voltage region LV, the medium voltage gate oxide layer is not formed on the substrate surface of the high voltage region HV. The process is as follows:

[0071] Referring to Figure 6A , a patterned photoresist layer 300 is formed by photoresist coating, exposure, development and other photolithography processes. In an example, the patterned photoresist layer 300 not only covers the hard mask layer 202 and the high voltage thermal oxide layer 203 of the high voltage region HV outside the bird beak region 203a, but also covers the top part of the hard mask layer 202 above the shallow trench isolation structure STI at the boundary of the low voltage region LV and the medium voltage region MV, and exposes the top part of the hard mask layer 202 of the low voltage region LV and the medium voltage region MV, thereby defining the formation region of the medium voltage gate oxide layer on the low voltage region LV and the medium voltage region MV. In another example, the patterned photoresist layer 300 only covers the hard mask layer 202 and the high voltage thermal oxide layer 203 of the high voltage region HV outside the bird beak region 203a, thereby exposing the hard mask layer 202 on the low voltage region LV and the medium voltage region MV, and the shallow trench isolation structure STI at the boundary of the low voltage region LV and the medium voltage region MV.

[0072] Then, referring to Figure 6A , using the patterned photoresist layer 300 as a mask, the hard mask layer 202 of the low voltage region and the medium voltage region is etched simultaneously by dry etching process until the substrate 200 surface of the low voltage region LV and the medium voltage region MV is exposed. Optionally, the substrate 200 exposed by the low voltage region LV and the medium voltage region MV is further etched to form a second trench (not shown), which is used for forming the medium voltage gate oxide layer in the subsequent process and for reducing the height of the top surface of the formed medium voltage gate oxide layer, and the depth of the bottom surface of the second trench is shallower than the depth of the bottom surface of the first trench formed before the high voltage gate oxide layer 203 is formed.

[0073] Then, referring to Figure 6B, any suitable stripping process, such as dry stripping or wet stripping, is used to remove the patterned photoresist layer 300, and any suitable second thermal oxidation process (which has a shorter process time than the first thermal oxidation process) such as a high-temperature furnace tube oxidation process is used to thermally oxidize the substrate 200 exposed in the low-voltage region LV and the medium-voltage region MV. The exposed silicon of the substrate 200 in the low-voltage region LV and the medium-voltage region MV reacts with oxygen, thereby forming a medium-voltage gate oxide layer on the surface of the substrate 200 exposed in the low-voltage region LV and the medium-voltage region MV. The silicon of the substrate 200 in other regions is not exposed to oxygen because it is shielded by the hard mask layer 202 and the high-voltage gate oxide layer 203. In this way, a medium-voltage gate oxide layer 204b is formed on the substrate 200 in the low-voltage region LV, and a medium-voltage gate oxide layer 204a is formed on the substrate 200 in the medium-voltage region MV.

[0074] Optionally, in the above embodiment, in step S4, please refer to Figure 6C , the hard mask layer 202 is retained, and photoresist is coated on the hard mask layer 202, the high-voltage gate oxide layer 203, and the medium-voltage gate oxide layers 204a and 204b. The coated photoresist is exposed using a mask used to define the gate oxide of the medium-voltage region MV, and the exposed photoresist is developed, and so on, to form a patterned photoresist layer as a required patterned mask layer 301. The patterned mask layer 301 not only masks the medium-voltage gate oxide layer 204a of the medium-voltage region MV and the high-voltage gate oxide layer 203 of the high-voltage region HV except for the beak region 203a, but also exposes the surface of the medium-voltage gate oxide layer 204b on the low-voltage region LV and the hard mask layer 202 above the top of the beak region 203a. In this step, the number of masks is not increased compared to the prior art, and only the pattern of the mask is modified, specifically, a pattern (for example, an opening) for opening the beak region 203a is added to the mask used to define the gate oxide of the medium-voltage region MV. In step S5, the patterned mask layer 301 is used as a mask, and any suitable wet etching process is used to thin (as shown in Figure 6D ) or remove (as shown in Figure 6E ) the medium-voltage gate oxide layer 204b exposed on the low-voltage region LV and the beak region 203a exposed on the high-voltage region HV. Then, the patterned mask layer 301 and the hard mask layer 202 and the etching protection layer 201 are removed, and subsequent low-voltage gate oxide layer formation processes, gate and side wall processes, and so on are performed.

[0075] In summary, in the technical scheme of the present application, after forming the medium voltage gate oxide layer covering at least the medium voltage region and the low voltage region, and when forming the patterned mask layer for defining the medium voltage gate oxide layer to be reserved on the medium voltage region, the mask layer on the medium voltage gate oxide layer in the low voltage region is opened, and the mask layer on the bird beak region of the high voltage gate oxide layer in the high voltage region is also opened, so that the bird beak region of the high voltage gate oxide layer is thinned or removed at the same time when the medium voltage gate oxide layer on the low voltage region is thinned or removed by using the wet etching process, thereby on the one hand, the additional mask cost and process cost can be avoided, and on the other hand, the problem that the subsequent source-drain ion implantation is blocked due to the thickness of the bird beak region can be improved, and the problem that the device performance is reduced due to the decrease of the ion dopant amount in the source region of the high voltage region can be avoided. In addition, the bird beak region of the high voltage gate oxide layer is at least partially removed in the lateral direction, so that the lateral distance between the metal silicide and the contact plug on the source region and the channel can be shortened, the resistance of the source region can be reduced, and the device performance can be improved.

[0076] The above description is only a description of the preferred embodiments of the present application, and does not limit the scope of the present application. Any modification or change made by a person skilled in the art according to the above disclosure is within the protection scope of the technical scheme of the present application.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The method comprises the following steps: providing a substrate, forming a plurality of shallow trench isolation structures in the substrate to define a high-voltage region, a medium-voltage region and a low-voltage region; masking the medium-voltage region and the low-voltage region and exposing the substrate surface of the high-voltage region, and forming a high-voltage gate oxide layer on the high-voltage region by using a first thermal oxidation process, the high-voltage gate oxide layer having a beak region; exposing at least the substrate surface of the low-voltage region and the medium-voltage region, and forming a medium-voltage gate oxide layer covering at least the substrate surface of the low-voltage region and the medium-voltage region; forming a patterned mask layer, the patterned mask layer masking the medium-voltage gate oxide layer to be reserved on the medium-voltage region and exposing the medium-voltage gate oxide layer on the low-voltage region and the beak region of the high-voltage gate oxide layer; using the patterned mask layer as a mask, thinning or removing the medium-voltage gate oxide layer on the low-voltage region and the beak region of the high-voltage gate oxide layer by using a wet etching process.

2. The method for manufacturing a semiconductor device according to Claim 1, wherein At the end of the wet etching process, the medium-voltage gate oxide layer remaining on the low-voltage region after being thinned serves as a low-voltage gate oxide layer with a required thickness for the low-voltage region. Alternatively, after removing the medium-voltage gate oxide layer on the low-voltage region and exposing the substrate surface of the low-voltage region by using the wet etching process, the method further comprises: removing the patterned mask layer, and forming a low-voltage gate oxide layer on the substrate surface of the low-voltage region by using a third thermal oxidation process or a chemical vapor deposition process.

3. The method for manufacturing a semiconductor device according to Claim 2, wherein The thicknesses of the low-voltage gate oxide layer, the medium-voltage gate oxide layer and the high-voltage gate oxide layer increase in sequence.

4. The method for manufacturing a semiconductor device according to Claim 2, wherein After removing the patterned mask layer and forming the low-voltage gate oxide layer, the method further comprises: forming gates on the high-voltage gate oxide layer of the high-voltage region, the medium-voltage gate oxide layer of the medium-voltage region and the low-voltage gate oxide layer of the low-voltage region; forming sidewalls on the gates; forming source regions and drain regions in the substrate on both sides of the gates by using a source-drain ion implantation process; forming metal silicides on the top of the gates, the source regions and the drain regions by using a metal silicidation process; forming contact plugs on the metal silicides on the top of the gates, the source regions and the drain regions.

5. The method for manufacturing a semiconductor device according to Claim 4, wherein The source region and the drain region of the high-voltage region are in an asymmetric structure.

6. The method for manufacturing a semiconductor device according to Claim 5, wherein The drain region and the gate in the high-voltage region are spaced apart by a corresponding shallow trench isolation structure, and the gate continuously extends from the high-voltage gate oxide layer to the shallow trench isolation structure between the gate and the drain region.

7. The method for manufacturing a semiconductor device according to Claim 4, wherein The source region and the drain region of the high-voltage region are of a first conductivity type, and the method further comprises: before forming the high-voltage gate oxide layer, forming a well of a second conductivity type in the high-voltage region, forming drift regions of the first conductivity type in the well on both sides of the high-voltage gate oxide layer and drift regions of the second conductivity type outside the drift regions of the first conductivity type, and after forming the sidewalls and before forming the metal silicides, forming body contact regions in the drift regions of the second conductivity type; wherein the source region and the drain region of the high-voltage region are respectively formed in the drift regions of the first conductivity type on both sides of the high-voltage gate oxide layer.

8. The method for manufacturing a semiconductor device according to Claim 1, wherein The step of masking the substrate surface of the high-voltage region, the medium-voltage region and the low-voltage region and exposing the substrate surface of the medium-voltage region and the low-voltage region and forming the medium-voltage gate oxide layer on the medium-voltage region and the low-voltage region by a first thermal oxidation process comprises: depositing a hard mask layer on the substrate and opening the hard mask layer of the high-voltage region by a lithography and etching process to expose the substrate surface of the high-voltage region; etching the substrate to form a trench by using the hard mask layer as a mask, or, first forming a sacrificial oxide layer by a thermal oxidation process and etching the sacrificial oxide layer to form a trench; forming the high-voltage thermal oxide layer at the trench by a first thermal oxidation process.

9. The method for manufacturing a semiconductor device according to Claim 8, wherein After forming the high-voltage gate oxide layer, first masking the substrate surface of the high-voltage region and exposing the substrate surface of the medium-voltage region and the low-voltage region, and forming the medium-voltage gate oxide layer on the medium-voltage region and the low-voltage region by a corresponding second thermal oxidation process or a vapor deposition process; wherein, before masking the high-voltage region, the hard mask layer is removed, or, after thinning or removing the beak region of the medium-voltage gate oxide layer and the high-voltage gate oxide layer on the low-voltage region by the wet etching process, the hard mask layer is removed.

10. The method for manufacturing a semiconductor device according to Claim 8, wherein After forming the high-voltage gate oxide layer, the hard mask layer is removed to expose the substrate surface of the low-voltage region and the medium-voltage region and the remaining surface of the high-voltage region, and the medium-voltage gate oxide layer is formed on the high-voltage region, the beak region, the medium-voltage region and the low-voltage region by a corresponding second thermal oxidation process or a vapor deposition process.

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