Silicon-based geometric diode and preparation method thereof

Abstract

The invention discloses a silicon-based geometric diode and a preparation method thereof. The silicon-based geometric diode comprises a P-type silicon substrate, and the P-type silicon substrate comprises a first region, a second region and a third region; the first region comprises a silicon dioxide layer and a first electrode which are stacked; the second region comprises a silicon nanocone array which is arranged in an array; a second electrode is arranged on one side, far away from the P-type silicon substrate, of the silicon nanocone, the second electrode is electrically connected with the top surface of the silicon nanocone, and the second electrode is electrically connected with the first electrode; the material of the silicon nanocone is the same as that of the P-type silicon substrate; the resistivity of the P-type silicon substrate is greater than 1 omega.cm; and the third region comprises a third electrode arranged on one side of the P-type silicon substrate. The diode provided by the invention is good in rectification effect and can be used in the high-frequency fields such as terahertz.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and more particularly, to a silicon-based geometric diode and a method for manufacturing the same. Background Art

[0002] A diode is a two-terminal electronic component with unidirectional conductivity and is widely used, which can play roles such as rectification, detection, voltage regulation, switching, and optoelectronic conversion. Currently, the commonly used diodes are two types of devices: PN junction diodes and Schottky diodes. PN junction diodes are bipolar devices with a relatively slow response speed. Schottky diodes are majority carrier devices suitable for high-frequency applications, but they are highly sensitive to temperature and are prone to breakdown. Geometric diodes have a novel structure, a relatively simple manufacturing process, and their response speed is theoretically only limited by the ballistic motion and flight time of carriers, so they have become a research hotspot in the industry.

[0003] To construct geometric diodes by taking advantage of the asymmetry of the material itself, currently it mainly relies on the silicon nanowire process. Specifically, a bottom-up vapor-liquid-solid (V-L-S) material growth method is adopted, and a variety of processes such as non-uniform doping and wet etching processes are combined to prepare ratchet-shaped silicon-based geometric diodes. However, when preparing geometric diodes by relying on the silicon nanowire process combined with techniques such as wet etching: 1. The process is complex, has high requirements for the preparation environment, and the cost is high; 2. Due to the rectifying characteristics caused by non-uniform doping, it will affect the performance of geometric diodes.

[0004] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present invention, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0005] The purpose of the present invention is to overcome the deficiencies of the above-mentioned prior art and provide a silicon-based geometric diode and a method for manufacturing the same. The technical problems to be solved by the present invention are realized through the following technical solutions:

[0006] In a first aspect, the present invention provides a silicon-based geometric diode, including a P-type silicon substrate, and the P-type silicon substrate includes a first region, a second region, and a third region;

[0007] The first region includes a silicon dioxide layer and a first electrode stacked on one side of the P-type silicon substrate;

[0008] The second region includes a silicon nanocone array disposed on the same side of the P-type silicon substrate; the silicon nanocone array includes a plurality of silicon nanocones arranged in an array, the bottom surface of the silicon nanocone is connected to the P-type silicon substrate, the top surface of the silicon nanocone is located on the side away from the P-type silicon substrate of the bottom surface of the silicon nanocone, and the area of the bottom surface of the silicon nanocone is larger than the area of the top surface of the silicon nanocone; a second electrode is disposed on the top surface of the silicon nanocone, the second electrode is electrically connected to the top surface of the silicon nanocone, and the second electrode is electrically connected to the first electrode;

[0009] The material of the silicon nanocone is the same as that of the P-type silicon substrate; the resistivity of the P-type silicon substrate is greater than 1 Ω·cm;

[0010] The third region includes a third electrode disposed on the same side of the P-type silicon substrate.

[0011] In one embodiment of the present invention, the top surface of the silicon nanocone is a circular surface, and the diameter of the circular surface is less than 40 nm.

[0012] In one embodiment of the present invention, the second region of the P-type silicon substrate has a groove, and the groove includes a plurality of silicon nanocones arranged in an array;

[0013] The bottom surface of the silicon nanocone is connected to the bottom surface of the groove.

[0014] In one embodiment of the present invention, the first electrode, the second electrode, and the third electrode are all gold electrodes or platinum electrodes.

[0015] In a second aspect, the present invention provides a method for manufacturing the above-mentioned silicon-based geometric diode, including the following steps:

[0016] S10. Obtain a P-type silicon substrate, and form a silicon dioxide layer on one side of the P-type silicon substrate;

[0017] S20. Etch the silicon dioxide layer, retain the silicon dioxide layer in the first region, and expose the P-type silicon substrate in the second region and the third region;

[0018] S30. Form a first electrode on the side away from the P-type silicon substrate of the silicon dioxide layer in the first region, and form a third electrode on the exposed P-type silicon substrate in the third region;

[0019] S40. Process the exposed P-type silicon substrate in the second region to obtain a silicon nanocone array;

[0020] S50. Form a second electrode on the side away from the P-type silicon substrate of the silicon nanocone array, and the second electrode is electrically connected to the first electrode to obtain a silicon-based geometric diode.

[0021] In one embodiment of the present invention, in step S40, the processing of the exposed P-type silicon substrate in the second region to obtain a silicon nanocone array includes:

[0022] S401. Form a monolayer of polystyrene spheres on the P-type silicon substrate in the second region, and use a plasma etching method to etch the polystyrene spheres in the monolayer of polystyrene spheres into a preset diameter; the periodic distance between two adjacent polystyrene spheres with the preset diameter is equal to the preset spacing between two adjacent silicon nanocones in the corresponding silicon nanocone array;

[0023] S402. Using the monolayer of polystyrene spheres with polystyrene spheres of a preset diameter as a mask, etch the P-type silicon substrate in the second region by inductively coupled plasma-reactive ion etching process to obtain a silicon nanocone array.

[0024] In one embodiment of the present invention, in step S40, the processing of the exposed P-type silicon substrate in the second region to obtain a silicon nanocone array includes:

[0025] Wet-etch the P-type silicon substrate in the second region with an alkaline solution to obtain a silicon nanocone array.

[0026] In one embodiment of the present invention, in step S50, forming a second electrode on the side of the silicon nanocone array away from the P-type silicon substrate includes: using a PDMS dry transfer method to transfer the second electrode to the side of the silicon nanocone array away from the P-type silicon substrate, so that the second electrode is electrically connected to the top surface of the silicon nanocones in the silicon nanocone array.

[0027] In one embodiment of the present invention, the PDMS dry transfer method includes:

[0028] Form a prefabricated second electrode on a growth substrate, attach PDMS to the side of the prefabricated second electrode away from the growth substrate, and peel off the PDMS to obtain PDMS with a prefabricated second electrode;

[0029] Attach the PDMS with a prefabricated second electrode to the side of the silicon nanocone array away from the P-type silicon substrate and at least partially attach it to the side of the first electrode away from the P-type silicon substrate, heat at 110-125 °C, press for 15-25 min, and peel off the PDMS to obtain a second electrode.

[0030] Compared with the prior art, the beneficial effects of the present invention:

[0031] 1. The silicon-based geometric diode provided by the present invention belongs to a majority carrier device, and the ballistic transport principle is locally applicable to this silicon-based geometric diode; the second electrode is in ohmic contact with the top surface of the silicon nanocone, such that the electrical rectification ability of the silicon-based geometric diode device mainly stems from the physical asymmetry of the device itself. The response speed of the silicon-based geometric diode provided by the present invention is theoretically only limited by the ballistic motion and flight time of carriers, and is not restricted by the barrier capacitance and diffusion capacitance. Since the application frequency of the geometric diode is much higher than that of the PN junction diode and the Schottky junction diode, it can be applied as a rectifying diode in a terahertz rectenna system, capable of realizing the AC-DC conversion at terahertz frequencies, and having great application potential in high-frequency fields such as terahertz.

[0032] 2. The device structure of the silicon-based geometric diode provided by the present invention is simple, and the contact area between the top surface of the silicon nanocone and the second electrode is small, such that under different bias voltages, the ease of carrier (hole) transport is different, thereby achieving electrical rectification.

[0033] 3. Compared with the complex process conditions and strict preparation environment required when preparing devices relying on the silicon nanowire process, the preparation method provided by the present invention is simple and easy to implement with low cost. At the same time, it avoids the non-uniform doping process in the preparation process of geometric diodes in the prior art, explores a mature, reliable, economical and applicable preparation method for silicon-based geometric diodes, and provides a new option for the preparation of silicon-based geometric diodes.

[0034] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present invention.

[0035] The present invention will be further described in detail below with reference to the drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present invention, and are used together with the specification to explain the principles of the present invention. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0037] Figure 1 It is a schematic cross-sectional view of a silicon-based geometric diode in an embodiment of the present invention;

[0038] Figure 2 It is a schematic diagram of the electrical transport principle of a silicon-based geometric diode in an embodiment of the present invention;

[0039] Figure 3 It is a schematic diagram of the electrical transport principle of a silicon-based geometric diode in an embodiment of the present invention;

[0040] Figure 4 In one embodiment of the present invention, it is a flowchart of a preparation method of a silicon-based geometric diode;

[0041] Figure 5 In one embodiment of the present invention, it is a top view of a silicon-based geometric diode;

[0042] Figure 6 is Figure 5 the characterization diagram of area A in

[0043] Figure 7 In one embodiment of the present invention, it is a schematic diagram of a dry etching preparation process of a silicon nanocone array;

[0044] Figure 8 In one embodiment of the present invention, it is a schematic diagram of a wet etching preparation process of a silicon nanocone array;

[0045] Figure 9 In one embodiment of the present invention, it is a schematic diagram of current detection results of a silicon-based geometric diode device under forward bias and reverse bias.

[0046] The reference numerals are as follows:

[0047] 1 - P-type silicon substrate, 2 - silicon dioxide layer, 3 - first electrode, 4 - third electrode, 5 - second electrode, 6 - silicon nanocone array, 61 - silicon nanocone. Detailed embodiments

[0048] Now, example embodiments will be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this invention will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted. In addition, the drawings are only schematic illustrations of the present invention and are not necessarily drawn to scale.

[0049] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification only for convenience, for example, according to the directions of the examples described in the accompanying drawings. It can be understood that if the device of the icon is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" another structure, it may mean that a structure is integrally formed on another structure, or that a structure is "directly" disposed on another structure, or that a structure is "indirectly" disposed on another structure through another structure.

[0050] The terms "a", "an", "the", and "said" are used to indicate the presence of one or more elements / components / etc.; the terms "comprising" and "having" are used to mean an open inclusion and refer to the possibility of the existence of additional elements / components / etc. in addition to the listed elements / components / etc.; the terms "first", "second", "third", etc. are used only as labels and do not limit the quantity of their objects. In the description of the present invention, "a plurality of" means two or more, unless otherwise specifically defined.

[0051] Due to the influence of factors such as the etching process, the vertex of the term "silicon nanocone" is not strictly the vertex of a cone, but a top surface with nanoscale dimensions, and the silicon nanocone includes a bottom surface area much larger than the top surface area.

[0052] An embodiment of the present invention provides a silicon-based geometric diode, as Figure 1 shown. The silicon-based geometric diode includes a P-type silicon substrate 1, and the P-type silicon substrate 1 includes a first region, a second region, and a third region. The first region includes a silicon dioxide layer 2 and a first electrode 3 stacked on one side of the P-type silicon substrate; the second region includes a silicon nanocone array 6 provided on the same side of the P-type silicon substrate; the silicon nanocone array 6 includes a plurality of silicon nanocones 61 arranged in an array, and the bottom surface of the silicon nanocone is connected to the P-type silicon substrate; the top surface of the silicon nanocone 61 is located on the side away from the P-type silicon substrate 1 of the bottom surface of the silicon nanocone 61, and the area of the bottom surface of the silicon nanocone 61 is larger than the area of the top surface of the silicon nanocone 61; a second electrode 5 is provided on the top surface of the silicon nanocone 6, the second electrode 5 is electrically connected to the top surface of the silicon nanocone 61, and the second electrode 5 is electrically connected to the first electrode 3. The material of the silicon nanocone 61 is the same as that of the P-type silicon substrate 1; the resistivity of the P-type silicon substrate 1 is greater than 1 Ω·cm. The third region includes a third electrode 4 provided on the same side of the P-type silicon substrate 1.

[0053] In this embodiment, by forming a silicon nanocone array 6 on one side of the P-type substrate, and forming a second electrode 5 at the top surface end of the silicon nanocone 61 in the silicon nanocone array 6, the second electrode 5 is electrically connected to both the top surface of the silicon nanocone 61 and the first electrode 3. Thus, the contact area between the top surface of the silicon nanocone 61 and the second electrode 5 is extremely small, making the transport ease of carriers (holes) different under different bias voltages, thereby achieving electrical rectification.

[0054] In addition, in the related art, commonly used diodes are divided into two categories: PN junction diodes and Schottky junction diodes. PN junction diodes are minority carrier devices that need to consider the minority carrier storage effect. They also have diffusion capacitance and barrier capacitance, and their operating frequency is relatively low. Schottky junction diodes are majority carrier devices that do not have a minority carrier storage effect, have an extremely short reverse recovery time, and have an operating frequency much higher than that of PN junction diodes. However, Schottky junction diodes are still limited by barrier capacitance, so the operating frequency of Schottky junction diodes still cannot reach the terahertz band. The silicon-based geometric diode provided by the present invention is a majority carrier device that locally applies the ballistic transport principle; the second electrode 5 and the top plane contact of the silicon nanocone 61 are ohmic contacts, so that the electrical rectification capability of the silicon-based geometric diode device mainly comes from the physical asymmetry of the device itself. The response speed of the silicon-based geometric diode provided by the present invention is theoretically limited only by the ballistic motion and flight time of the carriers, and is not constrained by barrier capacitance and diffusion capacitance, which makes the silicon-based geometric diode have great application potential in high-frequency fields such as terahertz.

[0055] In this embodiment, the silicon nanocones 61 are made of the same material as the P-type silicon substrate 1 and have a resistivity greater than 1 Ω·cm. This prevents the silicon nanocones 61 from having too low a resistivity, which could lead to excessive carrier congestion on the top surface of the silicon nanocones 61 under the influence of the applied bias voltage during operation, thus reducing the rectifying effect.

[0056] See also Figure 2 and Figure 3 The electrical transport principle of the silicon-based geometric diode provided in this embodiment is as follows: the outer diameter of the top surface of the silicon nanocone 61 of the silicon-based geometric diode is similar to the mean free path of carriers in silicon. Therefore, the quasi-ballistic transport model is applicable in the extremely small area where the top surface of the silicon nanocone 61 contacts the second electrode 5. That is, the carriers are less scattered during transport in the medium, and Newton's second law plays a major guiding role. The substrate of the silicon-based geometric diode is P-type Si material, so the majority carriers of the silicon-based geometric diode are holes. Figure 2 As shown in FIG. 1 , when a positive bias is applied to the second electrode 5, under the influence of the positive bias, more holes will gather on the side of the second electrode 5 close to the silicon nanocone 61. On the one hand, the holes (indicated by h in the figure) will reflect and lose some hole carriers on the side of the second electrode 5 close to the silicon nanocone 61. On the other hand, because the connection interface between the second electrode 5 and the top surface of the silicon nanocone 61 is small, the narrow opening for the holes to pass through is very narrow, so only a small number of holes can pass through the narrow opening and move from the second electrode 5 to the silicon nanocone 61. Figure 3As shown, when a negative bias voltage is applied to the second electrode 5, under the influence of the negative bias voltage, more holes in the silicon nanocones 61 will move and accumulate in the direction close to the second electrode 5. During the accumulation of holes, a relatively large number of holes will be reflected on the side walls of the silicon nanocones 61, and because the angle between the side walls of the silicon nanocones 61 and the bottom surface of the silicon nanocones 61 is an acute angle, the reflected holes still have a moving component in the direction of the second electrode 5. In this way, a relatively large number of holes can pass through the narrow opening at the interface between the second electrode 5 and the top surface of the silicon nanocones 61, thereby realizing the rectification effect.

[0057] In an embodiment of the present invention, the top surface of the silicon nanocone 61 is a circular surface, and the diameter of the circular surface is less than 40 nm. According to the electrical transport principle of the silicon-based geometric diode, the smaller the contact area between the top surface of the silicon nanocone 61 and the second electrode 5, when a positive bias voltage is applied to the second electrode 5, due to the limitation of reflection and the narrow opening, fewer holes will pass through, thereby improving the rectification ratio of the silicon-based geometric diode.

[0058] In an embodiment of the present invention, the second region of the P-type silicon substrate 1 has a groove, and the groove includes a plurality of silicon nanocones 61 arranged in an array; the bottom surface of the silicon nanocone 61 is connected to the bottom surface of the groove. In this embodiment, the silicon nanocones 61 are arranged in the groove of the P-type silicon substrate 1, which reduces the thickness of the silicon-based geometric diode compared with forming the silicon nanocones 61 on the surface of one side of the P-type silicon substrate 1, facilitating the thinning and lightening of the device.

[0059] In an embodiment of the present invention, the first electrode 3, the second electrode 5, and the third electrode 4 are all gold electrodes or platinum electrodes.

[0060] The present invention also provides a preparation method of the above-mentioned silicon-based geometric diode, as Figure 4 shown, this method includes the following steps S10 - S50.

[0061] S10. Obtain a P-type silicon substrate 1, and form a silicon dioxide layer 2 on one side of the P-type silicon substrate 1.

[0062] Exemplarily, in step S10, the P-type silicon substrate 1 can be first cleaned, and then a silicon dioxide layer 2 is deposited on one side of the P-type silicon substrate 1 by plasma enhanced chemical vapor deposition (PECVD).

[0063] S20. Etch the silicon dioxide layer 2, retain the silicon dioxide layer 2 in the first region, and expose the P-type silicon substrate 1 in the second region and the third region.

[0064] Exemplarily, photolithography and reactive ion etching (RIE) are used to remove the silicon dioxide corresponding to the second region and the third region, exposing the P-type silicon substrate 1 in the second region for preparing the silicon nanocone array 6, and exposing the P-type silicon substrate 1 in the third region for forming the third electrode 4.

[0065] S30. A first electrode 3 is formed on the side of the silicon dioxide layer 2 in the first region away from the P-type silicon substrate 1, and a third electrode 4 is formed on the exposed P-type silicon substrate 1 in the third region.

[0066] Exemplarily, a vapor deposition process can be used to simultaneously form the first electrode 3 in the first region and the third electrode 4 in the third region through a mask plate.

[0067] S40. As shown in Figure 5 and Figure 6 shown, the exposed P-type silicon substrate 1 in the second region is processed to obtain the silicon nanocone array 6.

[0068] In one example, nanosphere lithography technology is used to obtain a periodic nanocone array on the surface of the P-type silicon substrate 1. As shown in Figure 7 shown, it includes:

[0069] S401. A single-layer polystyrene sphere (PS sphere) layer is formed on the P-type silicon substrate 1 (Si substrate) in the second region. The polystyrene spheres in the single-layer polystyrene sphere layer are etched into a preset diameter by a plasma etching method; the periodic distance between two adjacent polystyrene spheres with the preset diameter is equal to the preset spacing between two adjacent silicon nanocones 61 in the corresponding silicon nanocone array 6.

[0070] S402. Using the single-layer polystyrene sphere layer with polystyrene spheres of the preset diameter as a mask, the P-type silicon substrate 1 in the second region is etched by an inductively coupled plasma-reactive ion etching process to obtain the silicon nanocone array 6.

[0071] In another example, as shown in Figure 8 shown, a pyramid-shaped silicon nanocone array 6 is prepared by wet etching with an alkaline solution. For example, the P-type silicon substrate 1 in the second region is wet-etched with a KOH solution to obtain the silicon nanocone array 6. The KOH solution does not react with the first electrode 3 and the third electrode 4 (Au electrode), while the reaction rate of the KOH solution with the Si substrate is fast and selective. The etching rate of the KOH solution on the (100) crystal plane is the fastest, causing the surface of the Si substrate in the second region to be etched into an irregular nano-pyramid structure.

[0072] S50. A second electrode 5 is formed on the side of the silicon nanocone array 6 away from the P-type silicon substrate 1. The second electrode 5 is electrically connected to the first electrode 3 to obtain a silicon-based geometric diode.

[0073] In one example, a dry transfer method using PDMS (polydimethylsiloxane film) is adopted to transfer the second electrode 5 to the side of the silicon nanocone array 6 away from the P-type silicon substrate 1, so that the second electrode 5 is electrically connected to the top surface of the silicon nanocones 61 in the silicon nanocone array 6.

[0074] When the second electrode 5 is dry transferred using PDMS, since the contact area between the top surface of the silicon nanocone 61 and the surface of the second electrode is very small, it is rather difficult to lay the second electrode 5. In one embodiment, the PDMS dry transfer method includes: forming a prefabricated second electrode 5 on a growth substrate, attaching PDMS to the side of the prefabricated second electrode away from the growth substrate, peeling off the PDMS to obtain PDMS with the prefabricated second electrode 5; attaching the PDMS with the prefabricated second electrode 5 to the side of the silicon nanocone array 6 away from the P-type silicon substrate 1 and at least partially attaching it to the side of the first electrode 3 away from the P-type silicon substrate 1, heating at 110 - 125 °C, pressing for 15 - 25 min, and peeling off the PDMS to obtain the second electrode 5. For example, the heating temperature can be 110 °C, 115 °C, 118 °C, 120 °C or 125 °C; the pressing time can be 15 min, 18 min, 20 min, 22 min or 25 min.

[0075] The preparation method and performance of the silicon-based geometric diode are further described below through specific examples.

[0076] Example 1

[0077] S10. Obtain a P-type silicon substrate and form a silicon dioxide layer on one side of the P-type silicon substrate.

[0078] S20. Etch the silicon dioxide layer, retain the silicon dioxide layer in the first region, and expose the P-type silicon substrate in the second and third regions.

[0079] S30. Adopt an evaporation process to simultaneously form a first electrode on the side of the silicon dioxide layer in the first region away from the P-type silicon substrate and form a third electrode on the exposed P-type silicon substrate in the third region.

[0080] S40. Treat the exposed P-type silicon substrate in the second region to obtain a silicon nanocone array. In this example, a dry etching method is used to obtain the silicon nanocone array, which specifically includes steps S401 to S403.

[0081] S401. Using the Langmuir - Blodgett technique (monolayer preparation technique), form a monolayer of polystyrene spheres on the P - type silicon substrate in the second region. The monolayer of polystyrene spheres self - assembles on the P - type silicon substrate in the second region to form a monolayer of hexagonal close - packed structure. Using the plasma etching (oxygen plasma etching) method, etch to control the diameter of the polystyrene spheres to a preset diameter; the periodic distance between two adjacent polystyrene spheres with the preset diameter is equal to the preset spacing between two adjacent silicon nanocones in the corresponding silicon nanocone array.

[0082] S402. Using the monolayer of polystyrene spheres with the preset diameter as a mask, adopt the inductively coupled plasma - reactive ion etching process (ICP - RIE), introduce a mixture of SF6 and C4F8 to etch the P - type silicon substrate in the second region, and then rinse the substrate with tetrahydrofuran to remove the PS spheres, obtaining a silicon nanocone array.

[0083] S50. Adopt the PDMS dry transfer method to form a second electrode on the side of the silicon nanocone array away from the P - type silicon substrate. The second electrode overlaps with the first electrode to obtain a silicon - based geometric diode. Specifically, it includes steps S501 to S502.

[0084] S501. Form a pre - fabricated second electrode on the growth substrate, attach PDMS to the side of the pre - fabricated second electrode away from the growth substrate, and peel off the PDMS to obtain PDMS with the pre - fabricated second electrode.

[0085] S502. Attach the PDMS with the pre - fabricated second electrode to the side of the silicon nanocone array away from the P - type silicon substrate and at least partially attach it to the side of the first electrode away from the P - type silicon substrate, heat at 120 °C, press for 20 min, and peel off the PDMS to obtain the second electrode.

[0086] Example 2

[0087] The difference between Example 2 and Example 1 is that in step S40, in this example, wet etching is adopted. Specifically: place the silicon substrate in a KOH solution, react the KOH solution with the P - type silicon substrate in the second region. After the P - type silicon substrate starts to bubble, heat the KOH solution to 60 °C and continue the reaction for 5 min, then place the P - type silicon substrate in deionized water for ultrasonic oscillation cleaning, and then perform a drying treatment on the substrate surface by air blowing to obtain a P - type silicon substrate with a silicon nanocone array in the second region.

[0088] Perform a rectification ratio detection on the silicon - based geometric diode prepared by Example 2. As Figure 9 shown, apply a negative 1 V bias voltage to the second electrode, and the detected current is 1.20946*10 -8 A; apply a positive 1 V bias voltage to the second electrode, and the detected current is 1.00131*10-10 A. The rectification ratio of the silicon-based geometric diode exceeds two orders of magnitude, showing a good rectification effect.

[0089] Those skilled in the art will readily conceive of other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present invention, which follow the general principles of the present invention and include known common general knowledge or conventional technical means in the technical field not disclosed in the present invention.

Claims

1. A silicon-based geometric diode, characterized in that, It includes a P-type silicon substrate, and the P-type silicon substrate includes a first region, a second region, and a third region; The first region includes a silicon dioxide layer and a first electrode stacked on one side of the P-type silicon substrate; The second region includes a silicon nanocone array disposed on the same side of the P-type silicon substrate; the silicon nanocone array includes a plurality of silicon nanocones arranged in an array, the bottom surface of the silicon nanocone is connected to the P-type silicon substrate, the top surface of the silicon nanocone is located on the side away from the P-type silicon substrate of the bottom surface of the silicon nanocone, and the area of the bottom surface of the silicon nanocone is larger than the area of the top surface of the silicon nanocone; a second electrode is disposed on the top surface of the silicon nanocone, the second electrode is electrically connected to the top surface of the silicon nanocone, and the second electrode is electrically connected to the first electrode; The material of the silicon nanocone is the same as that of the P-type silicon substrate; the resistivity of the P-type silicon substrate is greater than 1 Ω·cm; The third region includes a third electrode disposed on the same side of the P-type silicon substrate.

2. The silicon-based geometric diode according to claim 1, wherein The top surface of the silicon nanocone is a circular surface, and the diameter of the circular surface is less than 40 nm.

3. The silicon-based geometric diode according to claim 1, wherein The second region of the P-type silicon substrate has a groove, and the groove includes a plurality of silicon nanocones arranged in an array; The bottom surface of the silicon nanocone is connected to the bottom surface of the groove.

4. The silicon-based geometric diode according to any one of claims 1-3, characterized in that, The first electrode, the second electrode, and the third electrode are all gold electrodes or platinum electrodes.

5. A method for preparing a silicon-based geometric diode according to any one of claims 1-4, characterized in that, It includes the following steps: S10. Obtain a P-type silicon substrate and form a silicon dioxide layer on one side of the P-type silicon substrate; S20. Etch the silicon dioxide layer, retain the silicon dioxide layer in the first region, and expose the P-type silicon substrate in the second region and the third region; S30. Form a first electrode on the side away from the P-type silicon substrate of the silicon dioxide layer in the first region, and form a third electrode on the exposed P-type silicon substrate in the third region; S40. Process the exposed P-type silicon substrate in the second region to obtain a silicon nanocone array; S50. Form a second electrode on the side away from the P-type silicon substrate of the silicon nanocone array, and the second electrode is electrically connected to the first electrode to obtain a silicon-based geometric diode.

6. The manufacturing method of the silicon-based geometric diode according to claim 5, characterized in that, In step S40, the processing of the exposed P-type silicon substrate in the second region to obtain a silicon nanocone array includes: S401. Form a single-layer polystyrene sphere layer on the P-type silicon substrate in the second region, and use a plasma etching method to etch the polystyrene spheres in the single-layer polystyrene sphere layer into a preset diameter; the periodic distance between two adjacent polystyrene spheres with a preset diameter is equal to the preset spacing between two adjacent silicon nanocones in the corresponding silicon nanocone array; S402. Use the single-layer polystyrene sphere layer with polystyrene spheres of a preset diameter as a mask, and use an inductively coupled plasma-reactive ion etching process to etch the P-type silicon substrate in the second region to obtain a silicon nanocone array.

7. The manufacturing method of the silicon-based geometric diode according to claim 5, characterized in that, In step S40, the processing of the exposed P-type silicon substrate in the second region to obtain a silicon nanocone array includes: Wet-etch the P-type silicon substrate in the second region with an alkaline solution to obtain a silicon nanocone array.

8. The preparation method of the silicon-based geometric diode according to any one of claims 5-7, characterized in that, In step S50, forming a second electrode on the side of the silicon nanocone array away from the P-type silicon substrate includes: using a PDMS dry transfer method to transfer the second electrode to the side of the silicon nanocone array away from the P-type silicon substrate, so that the second electrode is electrically connected to the top surface of the silicon nanocones in the silicon nanocone array.

9. The manufacturing method of the silicon-based geometric diode according to claim 8, characterized in that, The PDMS dry transfer method includes: Forming a prefabricated second electrode on a growth substrate, attaching PDMS to the side of the prefabricated second electrode away from the growth substrate, and peeling off the PDMS to obtain PDMS with the prefabricated second electrode; Attaching the PDMS with the prefabricated second electrode to the side of the silicon nanocone array away from the P-type silicon substrate and at least partially attaching it to the side of the first electrode away from the P-type silicon substrate, heating at 110-125 °C, pressing for 15-25 min, and peeling off the PDMS to obtain the second electrode.

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