Single photon avalanche diode and image sensing device including same

Abstract

The invention relates to a single photon avalanche diode and an image sensing device including the same. A single photon avalanche diode (SPAD) and an image sensing device are disclosed. In an embodiment, a single photon avalanche diode (SPAD) includes: an impurity junction region configured to include a plurality of depletion regions, where each depletion region is a junction formed between a first doped region doped with an impurity of a first conductivity type and a second doped region doped with an impurity of a second conductivity type; an output node formed over the impurity junction region and in contact with one surface of the substrate; a guard ring region formed to surround the impurity junction region; and a bias node spaced apart from the guard ring region and disposed on one side of the guard ring region.

Description

Technical Field

[0001] The technologies and implementations disclosed in this patent document generally relate to single-photon avalanche diodes (SPADs) and image sensing devices including the same. Background Art

[0002] Time-of-flight (TOF) technology, which has recently received significant attention, measures the distance to a target object by emitting pulsed light from a light source near the sensor, capturing the light reflected from the target object, calculating the round-trip time using the emitted and reflected light, and generating the distance to the target object using the calculated round-trip time.

[0003] For accurate TOF measurement, the reflected light needs to be detected immediately after reaching the sensor. This requires a highly sensitive photoelectric conversion element.

[0004] For this purpose, research has been conducted on single-photon avalanche diodes (SPADs) that can be manufactured using CMOS manufacturing technology. A single-photon avalanche diode (SPAD) is an optical device with very high gain characteristics and high enough photoelectric conversion efficiency to detect even a single photon.

[0005] A single-photon avalanche diode (SPAD) can use the avalanche multiplication effect to amplify the emitted photons for detection, thereby enabling accurate TOF measurement. Summary of the Invention

[0006] Various embodiments of the disclosed technology relate to an image sensing device designed to maximize the photon detection probability.

[0007] In an embodiment of the disclosed technology, a single-photon avalanche diode (SPAD) may include: an impurity junction region configured to include a plurality of depletion regions, where each depletion region is a junction formed between a first doped region doped with impurities of a first conductivity type and a second doped region doped with impurities of a second conductivity type; an output node formed above the impurity junction region and in contact with one surface of the substrate; a guard ring region formed to surround the impurity junction region; and a bias node spaced apart from the guard ring region and disposed on one side of the guard ring region.

[0008] In some implementations, the output node may be doped with impurities of the same conductivity type as the guard ring region, and the bias node may be doped with impurities of a different conductivity type from the output node.

[0009] In some implementations, the output node may include a higher concentration of impurities than the guard ring region.

[0010] In some implementations, the absolute value of the difference between the second bias voltage applied to the output node and the first bias voltage applied to the bias node is greater than the absolute value of the breakdown voltage of the single-photon avalanche diode (SPAD).

[0011] In some implementations, the substrate can be doped with impurities of the same conduction type as the bias node.

[0012] In some implementations, the bias node can have a higher concentration of impurities than the substrate.

[0013] In some implementations, the single-photon avalanche diode (SPAD) can further include a well region formed to extend from one surface of the substrate to the other surface of the substrate facing or opposite to the one surface. The output node, the impurity junction region, and the guard ring region are disposed within the well region.

[0014] In some implementations, the well region can be doped with impurities of a conduction type different from that of the substrate, and the well region can be doped with impurities of the same conduction type as the bias node.

[0015] In some implementations, as the well region is located closer to one surface of the substrate, the well region has a lower concentration of impurities.

[0016] In some implementations, the bias node can have a higher concentration of impurities than the well region.

[0017] In some implementations, the output node can be in contact with the guard ring region.

[0018] In some implementations, the impurity junction region has a first depth relative to one surface of the substrate, and the guard ring region has a second depth relative to one surface of the substrate, where the first depth is greater than the second depth.

[0019] In some implementations, the impurity junction region has a first depth relative to one surface of the substrate, and the guard ring region has a second depth relative to one surface of the substrate, where the first depth is less than the second depth.

[0020] In some implementations, the guard ring region can be doped with impurities of the same conduction type as the second doping region, where the guard ring region has a higher concentration of impurities than the second doping region.

[0021] In some implementations, the bias node can be doped with impurities of the same conduction type as the first doping region, where the bias node has a higher concentration of impurities than the first doping region.

[0022] In some implementations, the bias node can be formed to surround the guard ring region while being spaced apart from the guard ring region.

[0023] In another embodiment of the disclosed technology, an image sensing device may include: an array of unit pixels that detect the distance of an object from the image sensing device, where each unit pixel includes: a single photon avalanche diode for detecting the distance of the object from the image sensing device; a quenching circuit coupled to the single photon avalanche diode to change the bias voltage of the single photon avalanche diode; and a readout circuit coupled to the single photon avalanche diode to convert the output of the single photon avalanche diode into a pulse signal, where the single photon avalanche diode includes: an impurity junction region that generates an electrical signal representative of absorbed light in response to light and is configured to include a plurality of depletion regions, where each depletion region is a junction formed between a first doped region doped with impurities of a first conduction type and a second doped region doped with impurities of a second conduction type; an output node formed above the impurity junction region and in contact with one surface of the substrate and configured to output a voltage pulse generated due to avalanche breakdown of the impurity junction region; a guard ring region formed to surround the impurity junction region and the output node and configured to provide electrical isolation; and a bias node spaced apart from the guard ring region and disposed on one side of the guard ring region to receive a bias voltage for creating an electric field.

[0024] It is to be understood that both the foregoing general description and the following detailed description of the disclosed technology are exemplary and explanatory and are intended to provide further explanation of the claimed disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and other features and advantageous aspects of the disclosed technology will become apparent from the following detailed description when considered in conjunction with the accompanying drawings.

[0026] Figure 1 is a block diagram illustrating an example of an imaging device including an image sensing device based on an embodiment of the disclosed technology.

[0027] Figure 2 is a circuit diagram illustrating an example of an equivalent circuit of a unit pixel included in a pixel array based on an embodiment of the disclosed technology.

[0028] Figure 3 is a plan view illustrating an example of a single photon avalanche diode (SPAD) based on an embodiment of the disclosed technology.

[0029] Figure 4 is a plan view illustrating an example of a single photon avalanche diode (SPAD) based on another embodiment of the disclosed technology.

[0030] Figure 5Is a plan view of a single-photon avalanche diode (SPAD) illustrating another embodiment based on the disclosed technology.

[0031] Figure 6 Is an illustration along Figure 3 A cross-sectional view of an exemplary cross-section of a single-photon avalanche diode (SPAD) taken along the first cutting line shown.

[0032] Figure 7 Is a plan view of a single-photon avalanche diode (SPAD) illustrating another embodiment based on the disclosed technology.

[0033] Figure 8 Is an illustration along Figure 7 A cross-sectional view of an exemplary cross-section of a single-photon avalanche diode (SPAD) taken along the second cutting line shown. Detailed implementation

[0034] This patent document provides implementations and examples of single-photon avalanche diodes (SPADs) and image sensing devices including SPADs. In some embodiments, the SPAD and the image sensing device including the SPAD can be used to solve one or more technical and / or engineering problems and alleviate limitations or drawbacks encountered in the image sensing device. Some implementations of the disclosed technology relate to image sensing devices capable of maximizing the photon detection probability. To solve the above problems, the disclosed technology can be implemented in some embodiments to provide a single-photon avalanche diode (SPAD) and an image sensing device including the SPAD that can enhance photon collection sensitivity while operating at high speed.

[0035] Now, embodiments of the disclosed technology will be described in detail, and examples thereof are illustrated in the drawings. As much as possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts. Although the present disclosure is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings. However, the present disclosure should not be construed as being limited to the embodiments set forth herein.

[0036] Hereinafter, various embodiments will be described with reference to the drawings. However, it should be understood that the disclosed technology is not limited to specific embodiments, but includes various modifications, equivalents, and / or alternatives of the embodiments. Embodiments of the disclosed technology can provide various effects that can be directly or indirectly recognized by the disclosed technology.

[0037] The accompanying drawings may not necessarily be drawn to scale, and in some examples, the scale of at least some structures in the drawings may be exaggerated to clearly show the features of the embodiments or implementations. When a multi-layer structure having two or more layers is disclosed in the drawings or the detailed description, the relative positional relationship or arrangement order of the layers only reflects a specific embodiment, and the scope or spirit of the disclosed technology is not limited thereto, and it should be noted that the relative positional relationship or arrangement order of the layers can also be changed as needed. In addition, the drawings or detailed description of the multi-layer structure may not reflect all the layers present in a specific multi-layer structure (for example, one or more additional layers may exist between the two shown layers). As a specific example, when the first layer in a multi-layer structure is referred to as being "on" or "above" the second layer or "on" or "above" the substrate, the first layer may be formed directly on the second layer or the substrate, but it may also represent a structure in which one or more other layers exist between the first layer and the second layer or between the first layer and the substrate.

[0038] Hereinafter, examples of a single-photon avalanche diode (SPAD) and an image sensing device including the SPAD based on various embodiments of the disclosed technology will be described in detail with reference to the accompanying drawings.

[0039] Figure 1 is a block diagram illustrating an example of an imaging device (ID) including an image sensing device 100 according to an embodiment of the disclosed technology.

[0040] Referring to Figure 1 , the imaging device (ID) may refer to a device such as a digital still camera for capturing still images or a digital video camera for recording videos. For example, the imaging device (ID) may be implemented as a digital single-lens reflex (DSLR) camera, a mirrorless camera, a smart phone, and others. Examples of the imaging device (ID) may include a device including a lens and an image pickup element, enabling it to capture or photograph a target object and create its image. In some implementations, the imaging device (ID) may be implemented as a Lidar (light detection and ranging) sensor.

[0041] The imaging device (ID) may include an image sensing device 100 and an image signal processor (ISP) 150.

[0042] The image sensing device 100 may be a complementary metal oxide semiconductor image sensor (CIS) for converting incident light into an electrical signal. The image sensing device 100 may include a light source 10, a lens module 20, a light source driver 30, a pixel array 110, a sensor driver 120, a readout circuit 130, and a timing controller 140.

[0043] The light source 10 can emit light toward the target object 1 when receiving a control signal from the light source driver 30. The light source 10 can be a laser diode (LD) or a light emitting diode (LED) for emitting light having a specific wavelength band (e.g., near-infrared (NIR) light, infrared (IR) light, or visible light), or can be one of a near-infrared laser (NIR), a point light source, a monochromatic light source combined with a white light, or a monochromator, and a combination of other laser sources. For example, the light source 10 can emit infrared light having a wavelength of 800 nm to 1000 nm. Additionally, the light emitted from the light source 10 can be pulsed with specific characteristics such as a predetermined period, amplitude, and pulse width. Although Figure 1 a single light source 10 is shown for simplicity of illustration, the disclosed technology is not limited thereto, and multiple light sources can also be located near the lens module 20.

[0044] The lens module 20 can collect the light reflected from the target object 1 and can allow the collected light to be focused on the pixels (PX) of the pixel array 110. For example, the lens module 20 can include a focusing lens having a surface formed of glass or plastic or another cylindrical optical element having a surface formed of glass or plastic. The lens module 20 can include a plurality of lenses arranged to focus along the optical axis.

[0045] The light source driver 30 can operate the light source 10 under the control of the timing controller 140. In some implementations, the light source driver 30 can control or adjust the waveform (e.g., period, amplitude, pulse width, etc.) of the emitted light (EL) output from the light source 10.

[0046] The pixel array 110 can include a plurality of pixels (PX) continuously arranged in a two-dimensional (2D) matrix structure (e.g., continuously arranged along the column direction and / or the row direction). Each of the plurality of pixels (PX) can generate a pixel signal by sensing the light incident through the lens module 20 under the control of the sensor driver 120.

[0047] Each pixel (PX) can be an infrared pixel for generating a pixel signal by sensing incident light including reflected light (RL) generated when the emitted light (EL) from the light source 10 is reflected from the target object 1. In one embodiment, the infrared pixel can be used as a depth pixel for calculating the distance to the target object 1. In another embodiment, the infrared pixel can generate an infrared image by sensing infrared light incident on the scene without relying on the reflected light. In another embodiment, the pixel (PX) can include a pixel for generating a color image by sensing visible light from the scene. Hereinafter, a specific pixel design example in which each pixel (PX) includes a single photon avalanche diode (SPAD) pixel for detecting the distance to the target object 1 using the direct time-of-flight (ToF) method is described. The detailed structure and operation of each unit pixel (PX) will be described with reference to Figures 2 - 8 be described.

[0048] The sensor driver 120 can operate the pixels (PX) of the pixel array 110 in response to the timing signal generated by the timing controller 140. For example, the sensor driver 120 can generate a control signal to select the pixels (PX) within at least one row line from the plurality of row lines in the pixel array 110 and control the selected pixels (PX).

[0049] The readout circuit 130 can process the pixel signals received from the pixel array 110 under the control of the timing controller 140, and can generate and store depth data for detecting the distance to the target object 1. Specifically, the readout circuit 130 can calculate the time-of-flight (TOF) corresponding to the SPAD pulses generated by each pixel (PX) sensing the incident light including the reflected light (RL), and can store the time-of-flight (TOF) corresponding to the SPAD pulses on a sub-frame basis. The readout circuit 130 can send the time-of-flight (TOF) stored on a sub-frame basis to the image signal processor 150 under the control of the timing controller 140.

[0050] The timing controller 140 can generate timing signals to control the light source driver 30, the sensor driver 120, and the readout circuit 130. In some implementations, the timing controller 140 can generate timing signals according to the data received from the readout circuit 130 or the requests received from the image signal processor 150. In some implementations, the timing controller 140 can include a logic control circuit, a phase-locked loop (PLL) circuit, a timing control circuit, a communication interface circuit, and others.

[0051] The image signal processor 150 may perform at least one image signal processing on the image data (IDATA) received from the image sensing device 100, thereby generating processed image data. The image signal processor 150 may reduce the noise of the image data (IDATA) and may perform various image signal processes for image quality improvement on the image data (e.g., interpolation of the image data (IDATA), lens distortion correction, etc.).

[0052] The image data (IDATA) may include time-of-flight (TOF) stored for each sub-frame. The image signal processor 150 may generate a histogram for one frame by accumulating the data stored in units of sub-frames and may determine the target time-of-flight (TOF) for the frame based on the histogram.

[0053] The target time-of-flight (TOF) may be determined for each pixel (PX), and the image signal processor 150 may determine the target distance (e.g., the distance to the target object 1 detected by each pixel PX) based on the target time-of-flight (TOF) of each pixel (PX).

[0054] The image signal processor 150 may send the processed image data to a host device (not shown).

[0055] The processed image data may include information about the target distance, which represents the distance to the target object 1 detected by each pixel (PX).

[0056] In some implementations, an external device (not shown) may include a processor (e.g., an application processor) for processing the image data that has undergone image signal processing (ISP) received from the image signal processor 150, a memory (e.g., a non-volatile memory) for storing the ISP image data, a display device (e.g., a liquid crystal display (LCD)) for visually displaying the ISP image data, and others.

[0057] The processor included in the external device may generate a depth image of the target object 1 based on the set or total of the target distances corresponding to the pixels.

[0058] The image signal processor 150 may send a control signal for controlling the operation of the image sensing device 100 (e.g., whether to operate, operation timing, operation mode, etc.) to the image sensing device 100.

[0059] Figure 2 It is a circuit diagram showing an example of an equivalent circuit of a part of a unit pixel (PX) included in a pixel array having a single photon avalanche diode (SPAD) that illustrates an embodiment based on the disclosed technology.

[0060] Refer toFigure 2 A unit pixel (PX) may include a single photon avalanche diode (SPAD), a quenching circuit (QX), and an SPAD output circuit in the form of a pixel buffer (B_P).

[0061] The single photon avalanche diode (SPAD) may detect a single photon reflected by the target object 1 and may generate a voltage pulse corresponding to the detected single photon.

[0062] The SPAD may operate as a photodiode including a photosensitive P-N junction. Since the avalanche breakdown is triggered by a single photon incident in the Geiger mode under a reverse bias voltage, the SPAD may generate a voltage pulse when the cathode-anode voltage (e.g., the voltage between the cathode and the anode) is higher than the breakdown voltage. In some implementations, this process of triggering the avalanche breakdown by a single photon to generate a voltage pulse is defined as an avalanche process.

[0063] The SPAD may include a cathode and an anode. One of these terminals (the cathode and the anode) may be used as an output node for the voltage pulse, and the other terminal may be used as a bias node.

[0064] Figure 2 The equivalent circuit diagram shown represents an SPAD including an anode used as an output node and a cathode used as a bias node.

[0065] The cathode of the SPAD may receive a first bias voltage (Vbd), which is a reverse bias voltage capable of operating the single photon avalanche diode in the Geiger mode. The first bias voltage (Vbd) may be a voltage that applies a reverse bias voltage higher than the breakdown voltage to the SPAD.

[0066] For example, the first bias voltage (Vbd) may be a voltage such that the value obtained by subtracting a second bias voltage (-Vex) from the first bias voltage (Vbd) produces a negative voltage with an absolute value greater than the breakdown voltage. The anode of the SPAD may be connected to a sensing node (SN), and the SPAD may output the voltage pulse generated by sensing photons to the sensing node (SN).

[0067] After a voltage pulse is generated due to avalanche breakdown and the voltage of the sensing node (SN) increases, the quenching circuit (QX) may perform a quenching operation to return the voltage of the sensing node (SN) to the second bias voltage (-Vex) (or return the SPAD to the Geiger mode). One terminal of the quenching circuit (QX) may receive the second bias voltage (-Vex) such that a reverse bias voltage capable of operating in the Geiger mode can be applied to the SPAD.

[0068] For example, the second bias voltage (-Vex) can be a voltage such that the value obtained by subtracting the second bias voltage (-Vex) from the first bias voltage (Vbd) results in a negative voltage whose absolute value is greater than the breakdown voltage. The other terminal of the quenching circuit (QX) can be connected to the sensing node (SN), and when the quenching circuit (QX) is turned on, the voltage of the sensing node (SN) can return to the second bias voltage (-Vex).

[0069] In some implementations, the quenching circuit (QX) can be an N-channel metal-oxide-semiconductor (NMOS) transistor that receives a quenching control voltage (Vqch) through a gate terminal. When the voltage of the sensing node (SN) increases due to the generation of a voltage pulse, the quenching control voltage (Vgch) can have a turn-on voltage, and when the voltage of the sensing node (SN) returns to the second bias voltage (-Vex), the quenching control voltage (Vgch) can have a turn-off voltage. For example, the quenching control voltage (Vgch) can be provided by the sensor driver 120 or can be provided by the sensing node (SN).

[0070] In this example, the SPAD output circuit is a pixel buffer (B_P) that samples the analog voltage pulse generated at the sensing node SN and converts the sampled analog voltage pulse into a digital pulse signal (e.g., a single-photon avalanche diode (SPAD) pulse). Here, the sampling method can include converting the voltage pulse into a pulse signal having a logic level of 0 or 1 based on whether the level of the voltage pulse is a threshold level or higher. However, the disclosed technology is not limited to the sampling method discussed above.

[0071] The analog voltage pulse generated at the sensing node (SN) can exhibit a waveform that instantaneously increases from the second bias voltage (-Vex) due to the avalanche process and then returns to the second bias voltage (-Vex) due to the quenching operation. Therefore, since the pixel buffer (B_P) converts the voltage pulse into a digital pulse signal, the pixel signal (PX_OUT) serving as the output signal of the pixel buffer (B_P) can exhibit a waveform in which the pixel signal (PX_OUT) has a logic level of 0, then instantaneously changes to a logic level of 1 when the voltage pulse occurs, and finally returns to the logic level of 0 (or logic low level).

[0072] In some implementations, the pulse of the pixel signal (PX_OUT) generated by the pixel buffer (B_P) can hereinafter be referred to as a single-photon avalanche diode (SPAD) pulse.

[0073] Although Figure 2A single-photon avalanche diode (SPAD) is illustrated as receiving a first bias voltage (Vbd) through a cathode, but the disclosed technology is not limited thereto, and it should be noted that the SPAD can also receive the first bias voltage (Vbd) through an anode. When the anode receives the first bias voltage (Vbd), the anode can be used as a bias node and the cathode can be used as an output node. However, in this case, the voltage levels of the first bias voltage and the second bias voltage (Vbd, -Vex) can be configured such that the SPAD can operate in Geiger mode.

[0074] Figure 3 is a plan view showing an example of a single-photon avalanche diode (SPAD) illustrating an embodiment based on the disclosed technology.

[0075] Figure 1 of the unit pixel and Figure 2 each of the unit pixels (PX) of can include a single-photon avalanche diode (SPAD).

[0076] Referring to Figure 3 the plan view (2a) of, the single-photon avalanche diode (SPAD) can include a substrate 200, an output node 220, a guard ring region 230, and a bias node 240.

[0077] In Figure 3 it, the output node 220 can be the anode region of the SPAD, and the bias node 240 can be the cathode region of the SPAD.

[0078] Figure 3 the plan view (2a) of can illustrate the SPAD on one surface of the substrate 200 in a direction perpendicular to the surface of the substrate 200 (e.g., the Z-axis direction).

[0079] The single-photon avalanche diode (SPAD) can further include an impurity junction region between a p-doped region and an n-doped region (not shown), and the impurity junction region collects photons to generate associated electrical signals such as photocurrent due to the absorption of the collected photons. The impurity junction region (not shown) can overlap with the output node 220, and is omitted from Figure 3 the plan view (2a) of.

[0080] The substrate 200 can include a bulk single-crystalline silicon wafer, a silicon-on-insulator (SOI) wafer, a Si-Ge compound semiconductor wafer, a silicon epitaxial layer wafer, etc.

[0081] The substrate 200 can be a single-crystalline silicon wafer doped with impurities of a first conductivity type (e.g., N-type impurities).

[0082] The region visible in the plan view (2a) can be a surface (or one side) of the substrate 200. For example, one surface of the substrate 200 can be the front surface (or front side) of the substrate 200. In some implementations, the control circuit for controlling the SPAD can be arranged on one surface of the substrate 200.

[0083] The control circuit can be driven by the sensor driver 120 and can provide a preset bias voltage to the output node 220 and / or the bias node 240 included in the SPAD.

[0084] The surface of the substrate 200 facing one surface or opposite to one surface can be referred to as the other surface of the substrate 200, and the other surface of the substrate 200 can be referred to as the back surface (or back side). In some implementations, light can be incident on the other surface of the substrate 200, and an optical component such as an optical filter or a microlens can be provided on the other surface of the substrate 200.

[0085] The single-photon avalanche diode (SPAD) can include an output node 220 in contact with one surface of the substrate 200. An impurity junction region (not shown) can be provided below the output node 220.

[0086] The output node 220 can overlap with the impurity junction region (not shown). The impurity junction region (not shown) can be a region where carriers are generated by incident photons.

[0087] The output node 220 can be used as a region to which a second bias voltage is applied. Applying the second bias voltage to the output node 220 can generate a high electric field, which affects the carriers generated in the impurity junction region (not shown). The high electric field can trigger an avalanche phenomenon when the carriers move, amplifying the carriers generated by photons. By using the amplified carriers, the image sensing device 100 can detect a small number of photons.

[0088] The output node 220 can refer to a region doped with impurities of a second conductivity type (e.g., P-type impurities).

[0089] The output node 220 can be formed by doping impurities of a second conductivity type (P-type impurities) from one surface of the substrate 200 to a predetermined depth.

[0090] When viewed from a direction perpendicular to one surface of the substrate 200 (e.g., the Z-axis direction), the output node 220 can have a polygonal shape (e.g., a rectangular shape) to ensure that the output node 220 overlaps with the impurity junction region (not shown).

[0091] In another embodiment, the output node 220 can have a rectangular shape with rounded vertices, and the output node 220 having a rectangular shape with rounded vertices will be described later with reference toFigure 5 Detailed description.

[0092] In another embodiment, the output node 220 can have various shapes, such as a square shape, a circular shape, an oval shape, etc.

[0093] The output node 220 can be in contact with the guard ring region 230. The guard ring region 230 can be formed to surround an impurity junction region (not shown).

[0094] In another embodiment, the output node 220 and the guard ring region 230 can be formed to be spaced apart from each other.

[0095] The guard ring region 230 can extend from one surface of the substrate 200 to the other surface of the substrate 200 and can be formed to surround the output node 220.

[0096] The guard ring region 230 can be doped with impurities of a second conductivity type (e.g., P-type impurities).

[0097] The concentration of impurities included in the output node 220 can be higher than the concentration of impurities included in the guard ring region 230.

[0098] To achieve a high light reception efficiency in the SPAD, it is necessary to generate a uniform electric field in an impurity junction region (not shown) by applying a bias voltage to both the output node 220 and the bias node 240. Specifically, the bias voltages applied to the output node 220 and the bias node 240 create a uniform electric field within the depletion region of the impurity junction region (not shown). The depletion region can refer to the region where impurities of different conductivity types in the impurity junction region (not shown) are combined.

[0099] Due to the structural characteristics of the SPAD, when the p-n junction in the impurity junction region is reverse-biased, breakdown may occur at the outer edge of the impurity junction region (not shown) before photons are introduced into the SPAD.

[0100] In this case, the breakdown that occurs at the outer edge of the impurity junction region (not shown) or the outer edge of the output node 220 before the incident light enters the SPAD can be referred to as premature edge breakdown (PEB). When such PEB occurs, it becomes difficult to accurately measure the number of photons incident on the SPAD. Therefore, the guard ring region 230 can be formed around the output node 220 and the impurity junction region.

[0101] The impurity concentration of the guard ring region 230 can be higher than the impurity concentration of the region of impurities of the second conductivity type (e.g., the second doping region) included in the impurity junction region (not shown).

[0102] The bias node 240 may refer to a region adjacent to the guard ring region 230 and doped with impurities of a first conductivity type (e.g., N-type impurities).

[0103] The bias node 240 may be a region to which a first bias voltage is applied. The impurity concentration of the bias node 240 may be higher than the impurity concentration of the first conductivity type impurity region (e.g., the first doped region) included in the impurity junction region (not shown).

[0104] Additionally, when the substrate 200 is doped with impurities of a first conductivity type, the concentration of the first conductivity type impurities included in the bias node 240 may be higher than the concentration of the first conductivity type impurities included in the substrate 200.

[0105] The bias node 240 may have a square, polygonal, or circular shape. By adjusting the shape of the bias node 240, the electric field stress occurring in the corner or vertex region of the bias node 240 can be alleviated. The shape of the bias node 240 will be described in detail later with reference to Figure 4 and Figure 5 detailed description.

[0106] <s Figure 4 is a plan view (2b) illustrating an example of a single photon avalanche diode (SPAD) according to another embodiment based on the disclosed technology.

[0107] Referring to Figure 4 the plan view (2b), the bias node 240b may be formed to surround the guard ring region 230.

[0108] Since the bias node 240b is formed to surround the guard ring region 230, charges can be easily output through the bias node 240b. When the bias node 240b has a shape surrounding the guard ring region 230, a sufficient area of the bias node 240b can be ensured. Since the area of the bias node 240b is large enough, the carriers amplified in the impurity junction region (not shown) can be easily output through the bias node 240b.

[0109] The depth of the bias node 240b in a direction perpendicular to one surface of the substrate 200 (e.g., the Z-axis direction) may vary according to the charge collection ability of the bias node 240b. For example, in order to easily collect the carriers amplified in a relatively deep impurity junction region (not shown) in a direction perpendicular to one surface of the substrate 200 (e.g., the Z-axis direction), the bias node

[0110] Figure 5 is a plan view (2c) illustrating an example of a single photon avalanche diode (SPAD) according to another embodiment based on the disclosed technology.

[0111] Referring to Figure 5 the plan view (2c) of [[reference]], which shows an output node 220c having a rectangular shape with rounded vertices, a guard ring region 230c having a rectangular shape with rounded vertices, and a bias node 240c having a rectangular shape with rounded vertices.

[0112] Since the vertices of the output node 220c, the guard ring region 230c, and the bias node 240c are formed in a rectangular shape with rounded vertices, the electric field stress that may occur at the vertices and / or corners of the output node 220c, the guard ring region 230c, and the bias node 240c can be reduced.

[0113] Figure 6 is an example cross-sectional view (3) illustrating a cross-section of a single-photon avalanche diode (SPAD) taken along the first cutting line A - A' shown in [[reference]]. Figure 3 The cross-sectional view (3) shown can illustrate the cross-section of the SPAD taken along the first cutting line A - A' shown in [[reference]].

[0114] Figure 6 Referring to [[reference]], the SPAD may include a substrate 200, an output node 220, a guard ring region 230, a bias node 240, and an impurity junction region 250. Figure 3

[0115] Figure 6 Referring to [[reference]], the impurity junction region 250 may include a plurality of first doping regions 252 and a plurality of second doping regions 254.

[0116] To simplify the description, the content identical to that described above is omitted herein.

[0117] Figure 6 Referring to [[reference]], each first doping region 252 may be a region doped with impurities of a first conductivity type (e.g., N-type impurities), and each second doping region 254 may be a region doped with impurities of a second conductivity type (e.g., P-type impurities).

[0118] The concentration of the impurities of the first conductivity type included in the first doping region 252 may be less than or equal to the concentration of the impurities of the first conductivity type included in the substrate 200. Additionally, the concentration of the impurities of the first conductivity type included in the first doping region 252 may be less than the concentration of the impurities of the first conductivity type included in the bias node 240.

[0119]

[0120] The concentration of the impurities of the second conductivity type included in the second doping region 254 may be less than the concentration of the impurities of the second conductivity type included in the output node 220, and may be less than the concentration of the impurities of the second conductivity type included in the guard ring region 230.​​

[0121] Although the impurity junction region 250 is shown in Figure 6 as including three first doping regions 252 and three second doping regions 254, this is merely an example, and it should be noted that the number of first doping regions 252 included in the impurity junction region 250 and the number of second doping regions 254 included in the impurity junction region 250 can vary.

[0122] Since the impurity junction region 250 includes a plurality of first doping regions 252 and a plurality of second doping regions 254, the area size of the depletion region (or amplification region) to be formed between the first doping region 252 and the second doping region 254 can be adjusted. Here, the depletion region can be the region where the regions 252 and 254 doped with impurities of different conductivity types in the impurity junction region 250 are joined.

[0123] The depletion region can refer to the region where the carriers generated by photons initiate an avalanche phenomenon.

[0124] In an embodiment of the disclosed technology, since a plurality of depletion regions are formed in the impurity junction region 250, the capacitance of the SPAD can be reduced, and at the same time, the photon collection ability can be improved.

[0125] Since the impurity junction region 250 including a plurality of depletion regions is formed under the output node 220, the absolute value of the breakdown voltage at which carriers are amplified and detected can be reduced.

[0126] In other words, since the impurity junction region 250 is formed as described above, even if the absolute value of the difference between the second bias voltage applied to the output node 220 and the first bias voltage applied to the bias node (for example, the absolute value obtained by subtracting the second bias voltage applied to the output node 220 from the first bias voltage applied to the bias node 240) is small, carriers can trigger an avalanche phenomenon.

[0127] When the capacitance of the SPAD is reduced, the time required to detect the carriers amplified by the avalanche phenomenon can be shortened. In addition, when the capacitance of the SPAD is reduced, the dead time during which a voltage pulse caused by photons is first detected and then the SPAD is quenched can be shortened.

[0128] Since the impurity junction region 250 is formed to have a plurality of first doping regions 252 and a plurality of second doping regions 254, the depth of the depletion region (also referred to as the "amplification region") formed with respect to one surface of the substrate 200 can be adjusted.

[0129] By adjusting the depth at which the depletion region is formed, the collection sensitivity of the SPAD to each incident light can be adjusted. More specifically, as the depth of the depletion region formed with respect to one surface of the substrate 200 increases, the collection sensitivity to light having a longer wavelength band can increase.

[0130] Referring to Figure 6 , the depth D1 of the impurity junction region 250 with respect to one surface of the substrate 200 can be adjusted according to the depth D2 of the guard ring region 230 with respect to one surface of the substrate 200.

[0131] Referring to Figure 6 in the cross-sectional view (3), the depth D1 of the impurity junction region 250 can be equal to the depth D2 of the guard ring region 230.

[0132] In another embodiment, the impurity junction region 250 can be located deeper than the guard ring region 230 such that the depth D1 of the impurity junction region 250 is greater than the depth D2 of the guard ring region 230.

[0133] The guard ring region 230 can be a region doped with impurities of a second conductivity type having a concentration lower than that of the output node 220. Here, the depth D2 of the guard ring region 230 can be adjusted according to the electrical characteristics of the SPAD.

[0134] For example, when premature edge breakdown (PEB) mainly occurs at the outer edge of the output node 220 of the SPAD, the depth D2 of the guard ring region 230 can be less than the depth D1 of the impurity junction region 250.

[0135] Alternatively, when premature edge breakdown (PEB) mainly occurs at the outer edge of the impurity junction region 250, the depth D2 of the guard ring region 230 can be greater than the depth D1 of the impurity junction region 250.

[0136] Figure 7 is a plan view (4) of a single photon avalanche diode (SPAD) illustrating another embodiment based on the disclosed technology.

[0137] Referring to Figure 7 in the plan view (4), the SPAD can include a substrate 300, a well region 310, an output node 320, a guard ring region 330, and a bias node 340.

[0138] The plan view (4) can illustrate the SPAD as shown when penetrating in a direction perpendicular to one surface of the substrate 300 (e.g., the Z-axis direction).

[0139] For simplicity of description, the content identical to that described with reference to Figures 1 - 6 will be omitted herein.

[0140] The SPAD shown in the plan view (4) may include a substrate 300 containing impurities of a second conductivity type (e.g., P-type impurities) and a well region 310 containing impurities of a first conductivity type (e.g., N-type impurities).

[0141] For example, the substrate 300 may be a single-crystalline silicon wafer doped with impurities of a second conductivity type (e.g., P-type impurities).

[0142] The well region 310 may be a region formed within the substrate 300 and extending from one surface of the substrate 300 to the other surface.

[0143] The well region 310 may be a region doped with impurities of a first conductivity type (e.g., N-type impurities).

[0144] The output node 320, the guard ring region 330, the bias node 340, and an impurity junction region (not shown) may be formed in the well region 310.

[0145] The well region 310 may be formed by implanting impurities of a first conductivity type in at least a portion of the substrate 300.

[0146] According to the present embodiment, the well region 310 may have different impurity concentrations depending on the depth from one surface of the substrate 300.

[0147] For example, as the well region 310 is located closer to one surface of the substrate 300, the concentration of impurities of the first conductivity type may decrease.

[0148] The characteristics of the impurity junction region (not shown) formed in the well region 310 may be adjusted by varying the impurity concentration of the well region 310.

[0149] For example, the concentration of impurities of the first conductivity type included in the well region 310 adjacent to one surface of the substrate 300 may be adjusted to be lower than the concentration of impurities of the first conductivity type (i.e., the first doping region) included in the impurity junction region (not shown). Conversely, the concentration of impurities of the first conductivity type included in the well region 310 located away from one surface of the substrate 300 may be adjusted to be higher than the impurity concentration of the first doping region. This adjustment enables precise control of the depth at which a depletion region is formed below the output node 320.

[0150] When a depletion region is formed below the output node 320, the collection sensitivity of the SPAD to collect photons in a longer wavelength band may increase. Additionally, the capacitance of the SPAD may decrease, such that the photon collection ability may increase and the dead time required for quenching may be reduced.

[0151] Figure 8 is illustrative along Figure 7Cross-sectional view of an exemplary cross-section of a single-photon avalanche diode (SPAD) taken along the second cutting line B-B' shown.

[0152] Referring to Figure 8 , the SPAD may include a substrate 300, a well region 310, an output node 320, a guard ring region 330, a bias node 340, and an impurity junction region 350.

[0153] For simplicity of explanation, the content that is the same as that described with reference to Figures 1 - 6 will be omitted herein.

[0154] Referring to Figure 8 , the well region 310 may be a region extending from one surface of the substrate 300 to the other surface.

[0155] The output node 320, the guard ring region 330, the bias node 340, and the impurity junction region 350 may be formed in the well region 310.

[0156] The impurity junction region 350 may include a plurality of first doping regions 352 and a plurality of second doping regions 354.

[0157] The first doping region 352 may be a region doped with impurities of a first conduction type (e.g., N-type impurities), and the second doping region 354 may be a region doped with impurities of a second conduction type (e.g., P-type impurities).

[0158] The concentration of the first conduction type impurities included in the first doping region 352 may be less than the concentration of the first conduction type impurities included in the bias node 340.

[0159] The concentration of the second conduction type impurities included in the second doping region 354 may be less than or equal to the concentration of the second conduction type impurities included in the substrate 300.

[0160] Although the impurity junction region 350 is shown in Figure 8 as including three first doping regions 352 and three second doping regions 354, this is merely an example, and it should be noted that the number of the first doping regions 352 included in the impurity junction region 350 and the number of the second doping regions 354 included in the impurity junction region 350 may vary.

[0161] Since the impurity junction region 350 includes a plurality of first doping regions 352 and a plurality of second doping regions 354, the area of the depletion region (or amplification region) formed at the junction between the first doping region 352 and the second doping region 354 can be adjusted.

[0162] In an embodiment, the characteristics of the SPAD can be controlled by adjusting the concentration of the first conductivity type impurities included in the well region 310 according to the depth from a surface of the substrate 300.

[0163] Additionally, since the depth of the guard ring region 330 from a surface of the substrate 300 is adjusted, premature edge breakdown (PEB) that may occur at the outer edge of the output node 320 or the impurity junction region 350 can be prevented.

[0164] It is apparent from the above description that an image sensing device based on some embodiments of the disclosed technology can exhibit improved photon collection sensitivity and can operate at high speed.

[0165] Embodiments of the disclosed technology can provide various effects that can be directly or indirectly identified through the above-mentioned patent documents.

[0166] Although multiple exemplary embodiments have been described, it should be understood that modifications and enhancements to the disclosed embodiments, as well as other embodiments, can be conceived based on what is described and / or illustrated in this patent document.

[0167] Cross - reference to related applications

[0168] This patent document claims the priority and benefit of Korean Patent Application No. 10 - 2024 - 0016087, filed on February 1, 2024, the disclosure of which is incorporated herein by reference in its entirety as part of the disclosure of this patent document.

Claims

1. A single - photon avalanche diode, the single - photon avalanche diode comprising: An impurity junction region, the impurity junction region including a plurality of depletion regions, wherein each depletion region is a junction formed between a first doped region doped with impurities of a first conduction type and a second doped region doped with impurities of a second conduction type; An output node, the output node being formed above the impurity junction region and in contact with one surface of a substrate; A guard - ring region, the guard - ring region being formed to surround the impurity junction region; and A bias node, the bias node being spaced apart from the guard - ring region and disposed on one side of the guard - ring region.

2. The single - photon avalanche diode according to claim 1, wherein, The output node is doped with impurities of the same conduction type as the guard - ring region, and The bias node is doped with impurities of a conduction type different from that of the output node.

3. The single - photon avalanche diode according to claim 2, wherein, The output node includes a higher concentration of impurities than the guard - ring region.

4. The single - photon avalanche diode according to claim 1, wherein, The absolute value of the difference between the second bias voltage applied to the output node and the first bias voltage applied to the bias node is greater than the absolute value of the breakdown voltage of the single - photon avalanche diode.

5. The single - photon avalanche diode according to claim 1, wherein, The substrate is doped with impurities of the same conduction type as the bias node.

6. The single - photon avalanche diode according to claim 5, wherein, The bias node has a higher concentration of impurities than the substrate.

7. The single - photon avalanche diode according to claim 1, the single - photon avalanche diode further comprising: A well region, the well region being formed to extend from the one surface of the substrate to the other surface of the substrate facing the one surface or opposite to the one surface, Wherein the output node, the impurity junction region, and the guard - ring region are disposed within the well region.

8. The single - photon avalanche diode according to claim 7, wherein, The well region is doped with impurities of a conduction type different from that of the substrate, and The well region is doped with impurities of the same conduction type as the bias node.

9. The single - photon avalanche diode according to claim 7, wherein, As the well region is located closer to one surface of the substrate, the impurities in the well region have a lower concentration.

10. The single - photon avalanche diode according to claim 8, wherein, The bias node has a higher concentration of impurities than the well region.

11. The single - photon avalanche diode according to claim 1, wherein, The output node is in contact with the guard - ring region.

12. The single - photon avalanche diode according to claim 1, wherein, The impurity junction region has a first depth relative to the one surface of the substrate, and the guard - ring region has a second depth relative to the one surface of the substrate, wherein the first depth is greater than the second depth.

13. The single - photon avalanche diode according to claim 1, wherein, The impurity junction region has a first depth relative to the one surface of the substrate, and the guard ring region has a second depth relative to the one surface of the substrate, wherein the first depth is less than the second depth.

14. The single-photon avalanche diode according to claim 1, wherein, the guard ring region is doped with impurities of the same conduction type as the second doped region, wherein the guard ring region has a higher concentration of impurities than the second doped region.

15. The single-photon avalanche diode according to claim 1, wherein, the bias node is doped with impurities of the same conduction type as the first doped region, wherein the bias node has a higher concentration of impurities than the first doped region.

16. The single-photon avalanche diode according to claim 1, wherein, the bias node is formed to surround the guard ring region and is spaced apart from the guard ring region.

17. An image sensing device, the image sensing device comprising: an array of unit pixels that detect the distance of an object from the image sensing device, wherein each unit pixel includes: a single-photon avalanche diode for detecting the distance of the object from the image sensing device; a quenching circuit coupled to the single-photon avalanche diode to change the bias voltage of the single-photon avalanche diode; and a readout circuit coupled to the single-photon avalanche diode to convert the output of the single-photon avalanche diode into a pulse signal, wherein the single-photon avalanche diode includes: an impurity junction region including a plurality of depletion regions, wherein each depletion region is a junction formed between a first doped region doped with impurities of a first conduction type and a second doped region doped with impurities of a second conduction type; an output node formed above the impurity junction region and in contact with one surface of the substrate; a guard ring region formed to surround the impurity junction region; and a bias node spaced apart from the guard ring region and disposed on one side of the guard ring region.

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