Solar cell and manufacturing method thereof, laminated cell and photovoltaic module

Abstract

The invention relates to a solar cell and a manufacturing method thereof, a laminated cell and a photovoltaic module, and relates to the technical field of solar cells. According to the solar cell, the substrate doped with the antimony element is adopted, so that the multi-carrier concentration is improved, the carrier transmission efficiency of the cell is optimized, and the filling factor of the cell is improved; meanwhile, the concentration of the antimony element in the first semiconductor layer is controlled to be larger than that of the antimony element in the second semiconductor layer, the electrical properties of the first semiconductor layer and the second semiconductor layer are optimized, the carrier recombination rate of the cell can be optimized, the passivation effect of the second semiconductor layer is improved, and the performance of the cell is improved. And the overall passivation effect of the solar cell is further improved.

Description

Technical Field

[0001] This application relates to the technical field of solar cells, and particularly to a solar cell, a manufacturing method thereof, a tandem cell, and a photovoltaic module. Background Art

[0002] For a back-contact solar cell, both the positive and negative electrodes are disposed on the back of the cell, and there is no grid line occlusion on the front of the cell, reducing the shading loss on the front of the cell, maximizing the utilization of the incident light on the front of the cell, and improving the cell conversion rate.

[0003] However, there are still many deficiencies in back-contact solar cells, which affect the yield and industrialization of back-contact solar cells. Summary of the Invention

[0004] Based on this, it is necessary to provide a solar cell, a manufacturing method thereof, a tandem cell, and a photovoltaic module for the problems in the prior art.

[0005] In a first aspect, this application provides a solar cell, including:

[0006] A substrate having a first conductivity type, and the substrate is doped with antimony element;

[0007] A first semiconductor layer disposed on the back of the substrate, and the first semiconductor layer has the same conductivity type as the substrate;

[0008] A second semiconductor layer disposed on the back of the substrate, and the second semiconductor layer and the first semiconductor layer are alternately arranged on the back of the substrate, and the second semiconductor layer has a conductivity type opposite to that of the substrate;

[0009] The concentration of antimony element in the first semiconductor layer is greater than the concentration of antimony element in the second semiconductor layer.

[0010] Optionally, the diffusion depth of the antimony element in the first semiconductor layer is greater than the diffusion depth of the antimony element in the second semiconductor layer.

[0011] Optionally, the solar cell further includes:

[0012] An isolation region located between the first semiconductor layer and the second semiconductor layer;

[0013] A passivation layer covering the back of the substrate of the first semiconductor layer, the second semiconductor layer, and the isolation region.

[0014] Optionally, the solar cell further includes:

[0015] a first metal electrode, disposed on a side of the first semiconductor layer away from the substrate, the first metal electrode being electrically connected to the first semiconductor layer;

[0016] The second metal electrode is arranged on a side of the second semiconductor layer away from the substrate, and the second metal electrode is electrically connected to the second semiconductor layer.

[0017] Optionally, the doping concentration of antimony in the first semiconductor layer is 1×10 9 cm -3 -1×10 14 cm -3 The doping concentration of antimony in the second semiconductor layer is 1×10 8 cm -3 -1×10 13 cm -3 .

[0018] Optionally, the doping concentration of antimony element in the substrate is 1×10 14 cm -3 -1×10 18 cm -3 .

[0019] Optionally, the first semiconductor layer is doped with a first element having a first conductivity type, and the doping concentration of the first element in the first semiconductor layer is 1×10 20 cm -3 -5×10 20 cm -3 ;

[0020] The second semiconductor layer has a second element of a second conductivity type, and the doping concentration of the second element in the second semiconductor layer is 2×10 19 cm -3 -5×10 20 cm -3 .

[0021] Optionally, the total amount of antimony elements in the first semiconductor layer is greater than the total amount of antimony elements in the second semiconductor layer.

[0022] Optionally, an average concentration of antimony in the first semiconductor layer is greater than an average concentration of antimony in the second semiconductor layer.

[0023] Optionally, at the same distance from the substrate, the concentration of antimony in the first semiconductor layer is greater than the concentration of antimony in the second semiconductor layer.

[0024] In a second aspect, the present application provides a method for manufacturing a solar cell, wherein the solar cell is the solar cell described in the first aspect, and the manufacturing method comprises:

[0025] Provide a substrate, the back surface of the substrate including a first region and a second region;

[0026] Form a first semiconductor layer in the first region, and dope a first element having a first conduction type into the first semiconductor layer;

[0027] Form a second semiconductor layer in the second region, and dope a second element having a second conduction type into the second semiconductor layer.

[0028] Optionally, the first element includes a Group VA element; the second element includes a Group IIIA element.

[0029] In a third aspect, the present application provides a stacked cell, including a bottom cell and a top cell stacked on the bottom cell;

[0030] Wherein, the bottom cell includes the solar cell as described in the first aspect, or includes a solar cell manufactured by the manufacturing method of the solar cell as described in the second aspect; the top cell includes a perovskite cell.

[0031] In a fourth aspect, the present application provides a photovoltaic module, including the solar cell as described in the first aspect, or includes a solar cell manufactured by the manufacturing method of the solar cell as described in the second aspect, or includes the stacked cell as described in the third aspect.

[0032] The solar cell, its manufacturing method, the stacked cell, and the photovoltaic module of the present application adopt a substrate doped with antimony element, which can increase the majority carrier concentration of the substrate, optimize the carrier transport efficiency of the cell, improve the fill factor of the cell. At the same time, doping the substrate with antimony element can reduce the interface state density at the contact between the substrate and the first tunneling layer and the second tunneling layer, which is beneficial to improving the passivation effect of the cell, thereby improving the cell stability, and is beneficial to improving the yield and industrialization of the cell; by controlling the concentration of antimony element in the first semiconductor layer to be greater than the concentration of antimony element in the second semiconductor layer, optimizing the electrical properties of the first semiconductor layer and the second semiconductor layer, the carrier recombination rate of the cell can be optimized, and at the same time, it is beneficial to improving the passivation effect of the second semiconductor layer, further improving the overall passivation effect of the solar cell. Description of the Drawings

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0034] Figure 1Schematic diagram of the structure of a solar cell provided in an embodiment;

[0035] Figure 2 Doping concentration curve of antimony element in the first semiconductor layer and the substrate below it provided in an embodiment;

[0036] Figure 3 Doping concentration curve of antimony element in the second semiconductor layer and the substrate below it provided in an embodiment;

[0037] Figure 4 Process flow chart of the manufacturing method of a solar cell provided in an embodiment;

[0038] Figure 5 Schematic diagram of the structure after forming a first tunneling layer, a first amorphous silicon layer, and a phosphosilicate glass layer on the back of the substrate in an embodiment;

[0039] Figure 6 Schematic diagram of the structure after doping a first element into the first amorphous silicon layer in an embodiment;

[0040] Figure 7 Schematic diagram of the structure after removing the first semiconductor layer and the first tunneling layer outside the first region in an embodiment;

[0041] Figure 8 Schematic diagram of the structure after forming a second tunneling layer, a second amorphous silicon layer, and a borosilicate glass layer on the back of the substrate in an embodiment;

[0042] Figure 9 Schematic diagram of the structure after doping a second element into the second amorphous silicon layer in an embodiment;

[0043] Figure 10 Schematic diagram of the structure after removing the second semiconductor layer and the second tunneling layer outside the second region in an embodiment;

[0044] Figure 11 Schematic diagram of the structure after texturing the isolation region in an embodiment;

[0045] Figure 12 Schematic diagram of the structure after forming a passivation layer in an embodiment;

[0046] Figure 13 Connection schematic diagram of the top cell and the bottom cell of a tandem cell provided in an embodiment;

[0047] Figure 14 Connection schematic diagram of the top cell and the bottom cell of a tandem cell provided in another embodiment;

[0048] Figure 15Schematic diagram of the connection between the top cell and the bottom cell of the stacked cell provided in another embodiment.

[0049] Description of the reference numerals:

[0050] 21. Substrate; 21a. Back surface; 21b. Front surface; 22. First tunneling layer; 23. First semiconductor layer; 23a. First amorphous silicon layer; 25. Phosphosilicate glass layer; 26. Second tunneling layer; 27. Second semiconductor layer; 27a. Second amorphous silicon layer; 29. Borosilicate glass layer; 30. Passivation layer; 31. Aluminum oxide layer; 32. Silicon nitride layer; 41. First metal electrode; 42. Second metal electrode; A1. First region; A2. Second region; A3. Isolation region; 20. Bottom cell; 50. Top cell; 1. Stacked cell. Detailed implementation manners

[0051] For the convenience of understanding the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the description of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0053] As described in the background art, there are still many deficiencies in back-contact solar cells, which affect the yield and industrialization of back-contact cells. The cell efficiency of back-contact solar cells still needs to be improved, and the passivation short board of back-contact solar cells is determined by the passivation effect of the p-region doping layer, and the passivation effect of the p-region doping layer directly affects the yield and industrialization of back-contact cells.

[0054] According to an exemplary embodiment, the present embodiment provides a solar cell, such as Figure 1As shown, the solar cell includes a substrate 21, a first semiconductor layer 23, and a second semiconductor layer 27. The substrate 21 has a first conductivity type, the substrate 21 has a front surface 21b and a back surface 21a which are oppositely arranged, and the substrate 21 is doped with antimony element. The first semiconductor layer 23 is disposed on the back surface 21a of the substrate 21, the first semiconductor layer 23 has the same conductivity type as the substrate 21, and a first tunneling layer 22 is provided between the first semiconductor layer 23 and the substrate 21. The first tunneling layer 22 can be a silicon oxide layer. The second semiconductor layer 27 is disposed on the back surface 21a of the substrate 21, the second semiconductor layer 27 and the first semiconductor layer 23 are alternately arranged on the back surface 21a of the substrate 21, the second semiconductor layer 27 has a conductivity type opposite to that of the substrate 21, and a second tunneling layer 26 is provided between the second semiconductor layer 27 and the substrate 21. The second tunneling layer 26 can be a silicon oxide layer; the concentration of antimony element in the first semiconductor layer 23 is greater than the concentration of antimony element in the second semiconductor layer 27.

[0055] In this embodiment, the first conductivity type is n-type, the substrate 21 is doped with phosphorus element and antimony element; the first semiconductor layer 23 is n-type; the second semiconductor layer 27 is p-type. The solar cell of this embodiment is obtained by sequentially forming an n-type first semiconductor layer 23 and a p-type second semiconductor layer 27 on an n-type substrate 21 doped with antimony element. The first semiconductor layer 23 is formed earlier, and the number of times the first semiconductor layer 23 is heat-treated is more than the number of times the second semiconductor layer 27 is heat-treated, so that the concentration of antimony element in the first semiconductor layer 23 is greater than the concentration of antimony element in the second semiconductor layer 27.

[0056] The doping concentrations of antimony element in the first semiconductor layer 23 and the substrate 21 below it and the doping concentrations of antimony element in the second semiconductor layer 27 and the substrate 21 below it in this embodiment are detected by electrochemical voltage (ECV), and respectively obtained Figure 2 、 Figure 3 。

[0057] Referring to Figure 2 , Figure 2 is the doping concentration curve of antimony element obtained by detecting the first semiconductor layer 23 and the substrate 21 below it from the surface of the first semiconductor layer 23 away from the substrate 21 towards the substrate 21, Figure 2 In which, the horizontal axis is the detection depth and the vertical axis is the doping concentration of antimony element. Figure 2 The doping concentration of antimony element in the first semiconductor layer 23 is on the left side of the inflection point P1 in Figure 2The doping concentration of antimony in the substrate 21 under the first semiconductor layer 23 is on the right side of the inflection point P1. From the surface of the first semiconductor layer 23 far from the substrate 21 towards the substrate 21, the doping concentration of antimony in the first semiconductor layer 23 gradually increases. Antimony is detected at a detection depth of about 0.11 μm in the first semiconductor layer 23, and the slope of the antimony element curve in the first semiconductor layer 23 is relatively large. It can be seen that the closer the first semiconductor layer 23 is to the substrate 21, the greater the concentration of antimony in the first semiconductor layer 23.

[0058] Refer to Figure 3 , Figure 3 is the doping concentration curve obtained by detecting antimony in the second semiconductor layer 27 and the substrate 21 below it from the surface of the second semiconductor layer 27 far from the substrate 21 towards the substrate 21, Figure 3 in which the horizontal axis is the detection depth and the vertical axis is the doping concentration of antimony. Figure 3 On the left side of the inflection point P2 in Figure 3 is the doping concentration of antimony in the second semiconductor layer 27, and on the right side of the inflection point P2 in Figure 3 is the doping concentration of antimony in the substrate 21 under the second semiconductor layer 27. From the surface of the second semiconductor layer 27 far from the substrate 21 towards the substrate 21, the doping concentration of antimony in the second semiconductor layer 27 gradually increases. Antimony is detected at a detection depth of about 0.13 μm in the second semiconductor layer 27, and the slope of the antimony element curve in the second semiconductor layer 27 is smaller than that of the first semiconductor layer 23. The increasing rate of antimony in the second semiconductor layer 27 is less than that of antimony in the first semiconductor layer 23.

[0059] Refer to Figure 2 , Figure 3 , the doping concentration of antimony in the first semiconductor layer 23 is 1×10 9 cm -3 -1×10 14 cm -3 , and the doping concentration of antimony in the second semiconductor layer 27 is 1×10 8 cm -3 -1×10 13 cm -3 . The doping concentration of antimony in the first semiconductor layer 23 is greater than that in the second semiconductor layer 27.

[0060] Refer to Figure 2 , Figure 3 as shown, the doping concentration of antimony in the substrate 21 under the first semiconductor layer 23 is the same as that in the substrate 21 under the second semiconductor layer 27; the doping concentration of antimony in the substrate 21 is 1×10 14 cm -3 -1×10 18 cm -3 .

[0061] The solar cell of this embodiment uses a substrate 21 doped with antimony elements, which can increase the concentration of majority carriers in the substrate 21, optimize the carrier transport efficiency of the cell, and improve the fill factor of the cell. At the same time, doping the substrate 21 with antimony elements can reduce the interface state density at the contact between the substrate 21 and the first tunneling layer 22 and the second tunneling layer 26, which is beneficial to improving the passivation effect of the cell, thereby enhancing the cell stability, and is conducive to improving the yield and industrialization of the cell; by controlling the concentration of antimony elements in the first semiconductor layer 23 to be greater than that in the second semiconductor layer 27, the electrical properties of the first semiconductor layer 23 and the second semiconductor layer 27 are optimized, the carrier recombination rate of the cell can be optimized, and at the same time, it is beneficial to improving the passivation effect of the second semiconductor layer 27, further enhancing the overall passivation effect of the solar cell.

[0062] In some embodiments, referring to Figure 1 , the diffusion depth of antimony elements in the first semiconductor layer 23 is greater than that in the second semiconductor layer 27.

[0063] Referring to Figure 2 , Figure 3 As shown, starting from the surface of the first semiconductor layer 23 away from the substrate 21 towards the substrate 21, antimony elements are detected at a detection depth of about 0.11 μm, and starting from the surface of the second semiconductor layer 27 away from the substrate 21 towards the substrate 21, antimony elements are detected at a detection depth of about 0.13 μm. Thus, it can be seen that the diffusion depth of antimony elements in the first semiconductor layer 23 is greater than that in the second semiconductor layer 27.

[0064] In some embodiments, referring to Figure 2 , Figure 3 , the total amount of antimony elements in the first semiconductor layer 23 is greater than that in the second semiconductor layer 27.

[0065] In some embodiments, the average concentration of antimony elements in the first semiconductor layer 23 is greater than that in the second semiconductor layer 27.

[0066] In some embodiments, at the same distance from the substrate 21, the concentration of antimony elements in the first semiconductor layer 23 is greater than that in the second semiconductor layer 27.

[0067] In some embodiments, referring to Figure 2 , the first semiconductor layer 23 is doped with a first element having a first conduction type, and the doping concentration of the first element in the first semiconductor layer 23 is 1×10 20 cm -3 -5×10 20 cm -3 .

[0068] Referring toFigure 3 , the second semiconductor layer 27 is doped with a second element having a second conductivity type, and the doping concentration of the second element in the second semiconductor layer 27 is 2×10 19 cm -3 -5×10 20 cm -3 .

[0069] In this embodiment, the first element includes elements of Group VA; for example, the first element can be at least one of phosphorus and arsenic; the second element includes elements of Group IIIA; for example, the second element can be at least one of boron and aluminum.

[0070] In some embodiments, as shown in Figure 1 , the solar cell further includes an isolation region A3, and the isolation region A3 is located between the first semiconductor layer 23 and the second semiconductor layer 27. In this way, the first semiconductor layer 23 and the second semiconductor layer 27 are isolated by the isolation region A3 to prevent the first semiconductor layer 23 and the second semiconductor layer 27 from contacting, so that the first semiconductor layer 23 and the second semiconductor layer 27 are electrically isolated, avoiding the recombination of majority carriers and minority carriers at the interface and reducing the cell efficiency.

[0071] In some embodiments, as shown in Figure 1 , the isolation region A3 has a pyramid structure.

[0072] In some embodiments, as shown in Figure 1 , the solar cell further includes a passivation layer 30, and the passivation layer 30 covers the back surface 21a of the first semiconductor layer 23, the second semiconductor layer 27, and the substrate 21 of the isolation region A3.

[0073] As shown in Figure 1 , the passivation layer 30 may include at least one of an aluminum oxide layer, a silicon oxide layer, and a silicon nitride layer, or the passivation layer 30 may include multiple stacked layers. The passivation layer 30 covers the first semiconductor layer 23, the second semiconductor layer 27, and the substrate 21 of the isolation region A3.

[0074] Exemplarily, as shown in Figure 1 , the passivation layer 30 may include an aluminum oxide layer 31 and a silicon nitride layer 32 stacked in sequence. The aluminum oxide layer 31 can effectively block the erosion of impurities and moisture in the external environment on the inside of the cell. At the same time, the aluminum oxide can also reduce the number of dangling bonds on the surface of the substrate 21, thereby reducing the surface recombination rate and increasing the open-circuit voltage and short-circuit current of the cell. The silicon nitride layer 32 has good insulation performance and corrosion resistance, and can further reduce the recombination loss on the surface of the substrate 21.

[0075] In some embodiments, as shown in Figure 1As shown, the solar cell further includes a first metal electrode 41 and a second metal electrode 42. The first metal electrode 41 is disposed on a side of the first semiconductor layer 23 away from the substrate 21, and the first metal electrode 41 is electrically connected to the first semiconductor layer 23; the second metal electrode 42 is disposed on a side of the second semiconductor layer 27 away from the substrate 21, and the second metal electrode 42 is electrically connected to the second semiconductor layer 27.

[0076] Referring to Figure 1 As shown, the passivation layer 30 covers the surfaces of the first semiconductor layer 23 and the second semiconductor layer 27 on the side away from the substrate 21. The first metal electrode 41 passes through the passivation layer 30 and is electrically connected to the first semiconductor layer 23, and the second metal electrode 42 passes through the passivation layer 30 and is electrically connected to the second semiconductor layer 27.

[0077] According to an exemplary embodiment, this embodiment provides a method for manufacturing a solar cell. The solar cell is the solar cell in the above embodiment. Referring to Figure 4 As shown, the method for manufacturing a solar cell includes the following steps:

[0078] Step S101: Provide a substrate, and the back surface of the substrate includes a first region and a second region. In this embodiment, the substrate is doped with antimony.

[0079] Step S102: Form a first semiconductor layer in the first region, and dope a first element having a first conductivity type into the first semiconductor layer.

[0080] Step S103: Form a second semiconductor layer in the second region, and dope a second element having a second conductivity type into the second semiconductor layer.

[0081] In the method for manufacturing a solar cell of this embodiment, by using the substrate 21 doped with antimony, the concentration of majority carriers in the substrate 21 can be increased, the carrier transport efficiency of the battery can be optimized, and the fill factor of the battery can be improved. By optimizing the process flow, first form the first semiconductor layer 23 doped with the first element on the back surface of the substrate 21, and then form the second semiconductor layer 27 doped with the first element on the back surface of the substrate 21, which can reduce the number of times and duration of the second semiconductor layer 27 being subjected to high-temperature treatment, thereby reducing the diffusion of antimony in the substrate 21 into the second semiconductor layer 27, so that the content of antimony in the second semiconductor layer 27 is less than that in the first semiconductor layer 23, which can reduce the influence of antimony on the performance of the second semiconductor layer 27, is beneficial to improving the encapsulation effect of the second semiconductor layer 27, and further improves the encapsulation effect of the solar cell, improves the efficiency, reliability and stability of the battery, and is beneficial to improving the yield and industrialization of the battery.

[0082] In some embodiments, the substrate 21 is of n-type. The first semiconductor layer 23 is of n-type, and the second semiconductor layer 27 is of p-type.

[0083] The first element includes a Group VA element; for example, the first element may be at least one of phosphorus and arsenic; the second element includes a Group IIIA element; for example, the second element may be at least one of boron and aluminum.

[0084] In this way, more antimony elements are doped in the first semiconductor layer 23, which can improve the conductivity of the first semiconductor layer 23 and reduce the contact resistance between the first semiconductor layer 23 and the first metal electrode 41. The amount of antimony element doped in the second semiconductor layer 27 is small, which can reduce the combination of minority carriers in the second semiconductor layer 27 with antimony elements, increase the number of minority carriers in the second semiconductor layer 27, be beneficial to improving the conductivity of the second semiconductor layer 27, can improve the passivation effect of the second semiconductor layer 27, be beneficial to improving the passivation effect of the battery, and be beneficial to the yield and industrialization of the battery.

[0085] In step S101, as shown in Figure 5 In this embodiment, the selected substrate 21 is a silicon substrate. In other embodiments, a substrate made of a semiconductor material such as a silicon-germanium substrate or a germanium substrate can also be selected to fabricate the battery. The back surface of the substrate 21 includes an alternately arranged first region A1 and second region A2.

[0086] In this embodiment, the substrate 21 has an n-type conductivity type, and the substrate 21 is doped with antimony elements. The concentration of antimony elements in the substrate 21 is 1×10 14 cm -3 -1×10 18 cm -3 , and the resistivity of the substrate 21 is 10Ω - 50Ω. In this embodiment, the substrate 21 is doped with antimony elements, which can significantly increase the concentration of majority carriers in the substrate 21, thereby improving the short-circuit current and open-circuit voltage of the battery, and being beneficial to improving the long-term stability and lifespan of the battery. In this embodiment, the substrate 21 is also doped with phosphorus elements, and the concentration of phosphorus elements is greater than 1×10 14 cm -3 -1×10 18 cm -3 .

[0087] In some embodiments, after providing the substrate 21, the front surface 21b and the back surface 21a of the substrate 21 are subjected to alkaline polishing. After polishing, the surface reflectivity of the substrate 21 is 35% - 45%.

[0088] In step S102, in this embodiment, as shown in Figure 5 A first tunneling layer 22 and a first amorphous silicon layer 23a can be sequentially formed on the back surface 21a of the substrate 21 by low-pressure chemical vapor deposition (LPCVD).

[0089] Exemplarily, the temperature for depositing and forming the first amorphous silicon layer 23a is 500°C - 650°C. For example, it can be 500°C, 510°C, 520°C, 535°C, 545°C, 550°C, 560°C, 570°C, 580°C, 590°C, 610°C, 630°C or 650°C.

[0090] Exemplarily, the thickness of the first tunneling layer 22 is 0.5 nm - 3 nm, and the thickness of the first amorphous silicon layer 23a is 50 nm - 350 nm.

[0091] Then, the first element is doped into the first amorphous silicon layer 23a to form the first semiconductor layer 23. The following implementation manners can be adopted in this embodiment: Refer to Figure 5 As shown, a layer of phosphosilicate glass layer 25 is deposited on the side of the first amorphous silicon layer 23a away from the substrate 21 by atomic layer deposition. Refer to Figure 6 As shown, the substrate 21 is subjected to a thermal annealing treatment at a temperature of 800°C - 1000°C to diffuse the phosphorus element of the phosphosilicate glass layer 25 into the first amorphous silicon layer 23a to form the first semiconductor layer 23, and the first semiconductor layer 23 has an n-type conductivity type. The thermal annealing causes part of the antimony element in the substrate 21 to diffuse into the first semiconductor layer 23 through the first tunneling layer 22, so that part of the antimony element is doped in the first semiconductor layer 23.

[0092] The first semiconductor layer 23 is doped with a first element having a first conductivity type, and the doping concentration of the first element in the first semiconductor layer 23 is 1×10 20 cm -3 -5×10 20 cm -3 . In this embodiment, the first element is a phosphorus element.

[0093] As Figure 2 shows the doping concentration curves of the antimony element in the first semiconductor layer 23 and the substrate 21 below it. The doping concentration of the antimony element in the first semiconductor layer 23 is 1×10 9 cm -3 -1×10 14 cm -3 .

[0094] In this embodiment, after doping the first element into the first amorphous silicon layer 23a to form the first semiconductor layer 23, a mask layer (not shown in the figure) is formed on the side of the phosphosilicate glass layer 25 away from the substrate 21, and the mask layer covers the phosphosilicate glass layer 25 in the first region A1. Refer to Figure 7 As shown, according to the mask layer, the phosphosilicate glass layer 25, the first semiconductor layer 23 and the first tunneling layer 22 outside the first region A1 are etched away, exposing the back surface 21a of the substrate 21 in the second region A2, and the first region A1 and the second region A2 are alternately arranged on the back surface 21a of the substrate 21.

[0095] Exemplarily, a dry process or a wet process can be used to etch the phosphosilicate glass layer 25, the first semiconductor layer 23, and the first tunneling layer 22.

[0096] In step S103, referring to Figure 8 as shown, a second tunneling layer 26 and a second amorphous silicon layer 27a can be sequentially formed on the back surface 21a of the substrate 21 by low pressure chemical vapor deposition (LPCVD). The second tunneling layer 26 and the second amorphous silicon layer 27a cover the exposed back surface 21a of the substrate 21, and the second tunneling layer 26 and the second amorphous silicon layer 27a also cover the first tunneling layer 22, the first semiconductor layer 23, and the phosphosilicate glass layer 25 in the first region A1. The second tunneling layer 26 is a silicon oxide layer.

[0097] Exemplarily, the temperature for depositing and forming the second amorphous silicon layer 27a is 500°C - 650°C. For example, it can be 500°C, 510°C, 520°C, 530°C, 550°C, 565°C, 575°C, 585°C, 595°C, 605°C, 615°C, 625°C, 635°C, 645°C, or 650°C.

[0098] Exemplarily, the thickness of the second tunneling layer 26 is 0.5 nm - 3 nm, and the thickness of the second amorphous silicon layer 27a is 50 nm - 350 nm.

[0099] Then, a second element is doped into the second amorphous silicon layer 27a to form a second semiconductor layer 27. Referring to Figure 8 as shown, a borosilicate glass layer 29 can be first deposited on the side of the second amorphous silicon layer 27a away from the substrate 21 by atomic layer deposition. Referring to Figure 9 as shown, a thermal annealing treatment is performed on the substrate 21 at a temperature of 900°C - 1100°C to diffuse the boron element in the borosilicate glass layer 29 into the second amorphous silicon layer 27a to form the second semiconductor layer 27. In this embodiment, the second element is a boron element.

[0100] During the thermal annealing process, part of the antimony element in the substrate 21 further diffuses into the first semiconductor layer 23, so that the concentration of the antimony element in the first semiconductor layer 23 is higher, the antimony element is more uniformly distributed in the first semiconductor layer 23, so that the number of majority carriers in the first semiconductor layer 23 is more, and the conductivity of the first semiconductor layer 23 is better.

[0101] Referring to Figure 3 shows the doping concentration curves of the antimony element in the second semiconductor layer 27 and the substrate 21 below it after doping. The doping concentration of the antimony element in the second semiconductor layer 27 after doping is 1×10 8 cm -3 -1×10 13cm -3 。

[0102] In some embodiments, during the process of doping the second element into the second semiconductor layer 27, a part of the antimony element in the substrate 21 also diffuses into the second semiconductor layer 27, and the concentration of the antimony element in the first semiconductor layer 23 is greater than that in the second semiconductor layer 27.

[0103] It can be understood that the first semiconductor layer 23 is subjected to high-temperature treatment more times and for a longer duration. Along the thickness direction of the first semiconductor layer 23, the antimony element exists in the first semiconductor layer 23, and the antimony element is uniformly distributed in the first semiconductor layer 23. The first semiconductor layer 23 has high uniformity and smaller resistance, which can improve the electrical performance of the first semiconductor layer 23.

[0104] The second semiconductor layer 27 is subjected to high-temperature treatment fewer times and for a shorter duration. The doped antimony element in the second semiconductor layer 27 is less. Along the thickness direction of the second semiconductor layer 27, the content of the antimony element on the side of the second semiconductor layer 27 far from the substrate 21 is less than that on the side of the second semiconductor layer 27 close to the substrate 21, which can reduce the adverse effect of the antimony element on the passivation effect of the second semiconductor layer 27 and improve the passivation effect of the second semiconductor layer 27. It can be understood that the passivation effect of the second semiconductor layer 27 is the lowest point of the passivation of the solar cell. In this embodiment, the passivation effect of the second semiconductor layer 27 is improved, which is equivalent to improving the passivation effect of the solar cell, thereby being beneficial to improving the yield and industrialization of the battery.

[0105] In some embodiments, referring to Figure 2 、 Figure 3 , the total amount of the antimony element in the first semiconductor layer 23 is greater than that in the second semiconductor layer 27.

[0106] In some embodiments, the average concentration of the antimony element in the first semiconductor layer 23 is greater than that in the second semiconductor layer 27.

[0107] In some embodiments, at the same distance from the substrate 21, the concentration of the antimony element in the first semiconductor layer 23 is greater than that in the second semiconductor layer 27.

[0108] In some embodiments, this embodiment provides a method for manufacturing a solar cell. After step S103, the following steps are further executed:

[0109] Step S104: Pattern the second semiconductor layer 27 and the second tunneling layer 26, and remove the second semiconductor layer 27 and the second tunneling layer 26 located outside the second region A2.

[0110] In this embodiment, referring to Figure 10As shown, a mask layer (not shown in the figure) is formed on the side of the borosilicate glass layer 29 away from the substrate 21. The mask layer covers the borosilicate glass layer 29 in the second region A2. According to the mask layer, the borosilicate glass layer 29, the second semiconductor layer 27, and the second tunneling layer 26 outside the second region A2 are etched away.

[0111] Step S105: After patterning the second semiconductor layer 27 and the second tunneling layer 26, the back surface 21a of the substrate 21 in the isolation region A3 is exposed. Refer to Figure 10 As shown, the isolation region A3 is used to isolate the first semiconductor layer 23 and the second semiconductor layer 27, preventing the majority carriers and minority carriers from recombining at the interface between the first semiconductor layer 23 and the second semiconductor layer 27 and reducing the battery efficiency.

[0112] Then, the film layers deposited on the side and front surfaces 21b of the substrate 21 are etched away to expose the side and front surfaces 21b of the substrate 21 for facilitating the processing of the substrate 21.

[0113] Step S106: Refer to Figure 11 , the isolation regions A3 on the front surface 21b and the back surface 21a of the substrate 21 are textured to form a pyramid structure. In this way, the light-receiving area of the substrate 21 can be increased, and the photoelectric conversion efficiency of the battery can be improved. The base width of the pyramid structure is 5 μm - 30 μm.

[0114] Step S107: Refer to Figure 11 , the phosphosilicate glass layer 25 and the borosilicate glass layer 29 are removed. In this embodiment, the phosphosilicate glass layer 25 and the borosilicate glass layer 29 can be etched away by a wet process.

[0115] Step S108: A passivation layer 30 is formed, and the passivation layer 30 covers the first semiconductor layer 23, the second semiconductor layer 27, and the back surface 21a of the substrate 21 in the isolation region A3. Refer to Figure 12 As shown, in this embodiment, the passivation layer 30 is deposited on both the front surface 21b and the back surface 21a of the substrate 21. The passivation layer 30 is used to protect the first semiconductor layer 23, the second semiconductor layer 27, and the substrate 21, which is beneficial to improving the photoelectric conversion efficiency and stability of the solar cell.

[0116] In this embodiment, refer to Figure 12 As shown, the passivation layer 30 may include a sequentially stacked aluminum oxide layer 31 and silicon nitride layer 32.

[0117] Exemplarily, an aluminum oxide layer 31 can be formed by atomic layer deposition. The aluminum oxide layer 31 covers the first tunneling layer 22 and the first semiconductor layer 23 in the first region A1. The aluminum oxide layer 31 also covers the second tunneling layer 26 and the second semiconductor layer 27 in the second region A2. The aluminum oxide layer 31 further covers the isolation region A3 on the back surface 21a of the substrate 21 and the front surface 21b of the substrate 21. The aluminum oxide layer 31 can effectively block the erosion of impurities and moisture in the external environment on the inside of the battery. At the same time, the aluminum oxide can also reduce the number of dangling bonds on the surface of the substrate 21, thereby reducing the surface recombination rate and increasing the open-circuit voltage and short-circuit current of the battery.

[0118] Exemplarily, a silicon nitride layer 32 can be formed by atomic layer deposition. The silicon nitride layer 32 covers the aluminum oxide layer 31. The silicon nitride layer 32 has good insulation performance and corrosion resistance, and can further reduce the recombination loss on the surface of the substrate 21.

[0119] Both the aluminum oxide layer 31 and the silicon nitride layer 32 have good light transmittance, which is beneficial to improving the photoelectric conversion efficiency of the solar cell.

[0120] Step S109: A first metal electrode 41 is formed on the side of the first semiconductor layer 23 away from the substrate 21, and the first metal electrode 41 is electrically connected to the first semiconductor layer 23; a second metal electrode 42 is formed on the side of the second semiconductor layer 27 away from the substrate 21, and the second metal electrode 42 is electrically connected to the second semiconductor layer 27.

[0121] Refer to Figure 1 As shown, the first metal electrode 41 passes through the passivation layer 30 and is electrically connected to the first semiconductor layer 23. Since the first semiconductor layer 23 is doped with more antimony elements, the number of majority carriers in the first semiconductor layer 23 is larger. The first metal electrode 41 forms a good ohmic contact with the first semiconductor layer 23, which is beneficial to reducing the contact resistance between the first metal electrode 41 and the first semiconductor layer 23.

[0122] Refer to Figure 1 As shown, the second metal electrode 42 passes through the passivation layer 30 and is electrically connected to the second semiconductor layer 27. Since the second semiconductor layer 27 is doped with fewer antimony elements, the number of minority carriers in the second semiconductor layer 27 is larger. The second metal electrode 42 forms a good ohmic contact with the second semiconductor layer 27, which is beneficial to reducing the contact resistance between the second metal electrode 42 and the second semiconductor layer 27. In this way, it is beneficial to reduce the overall resistance of the solar cell, reduce the electrical loss caused by the resistance, and is beneficial to further improving the photoelectric conversion efficiency of the solar cell.

[0123] Exemplarily, the first metal electrode 41 and the second metal electrode 42 can be formed by screen printing.

[0124] According to an exemplary embodiment, this embodiment provides a stacked battery 1. Refer toFigure 13 , Figure 14 , Figure 15 As shown in Figure 15 , the tandem cell 1 includes a bottom cell 20 and a top cell 50 stacked on the bottom cell 20. Among them, the bottom cell 20 includes the solar cell of the above embodiment or the solar cell manufactured by the manufacturing method of the solar cell in the above embodiment; the top cell 50 includes a perovskite cell. Among them, the perovskite cell includes a transparent electrode layer, an electron transport layer, a perovskite light absorption layer, and a hole transport layer stacked in sequence on the solar cell. The tandem cell 1 in this embodiment can be a two-terminal tandem cell, a three-terminal tandem cell, or a four-terminal tandem cell. The solar cell and the perovskite cell of the tandem cell 1 in this embodiment are adapted, and have advantages such as high current matching, high process tolerance, and a wider range of outdoor use scenarios, and have higher development and application potential.

[0125] In one example, as Figure 13 shown. The tandem cell 1 is a two-terminal tandem cell. The perovskite cell is disposed on the back side of the solar cell, and the perovskite cell and the solar cell are connected in series. The positive electrode of the solar cell is connected to the negative electrode of the perovskite cell, and the positive electrode of the perovskite cell is used as the positive electrode of the tandem cell 1, and the negative electrode of the solar cell is used as the negative electrode of the tandem cell 1. An intermediate connection layer may also be provided between the perovskite cell and the solar cell, and the negative electrode of the perovskite cell is connected to the positive electrode of the solar cell through the intermediate connection layer. The intermediate connection layer may be a transparent conductive oxide layer or a composite layer.

[0126] In another example, as Figure 14 shown, the tandem cell 1 is a three-terminal tandem cell. The tandem cell 1 includes a solar cell, a perovskite cell, and a common electrode layer. The perovskite cell is stacked on the solar cell, and the common electrode layer is disposed between the perovskite cell and the perovskite cell. The first metal electrode of the solar cell is the positive electrode of the solar cell, and the second metal electrode is the negative electrode of the solar cell. The negative electrode of the perovskite cell and the positive electrode of the solar cell are connected to the common electrode layer. The common electrode layer is a transparent conductive material or a composite material layer with specific optical properties, which is used to optimize the transport and distribution of photo-generated charges. The positive electrode of the perovskite cell is connected to its transparent electrode layer. In this way, the top cell 50 and the bottom cell 20 of the tandem cell 1 each have independent output electrodes, and both achieve partial charge sharing with the common electrode layer through optical coupling or electrical connection; the photo-generated currents of the top cell 50 and the bottom cell 20 can be partially independently output or integrated through the current of the common electrode layer.

[0127] In yet another example, as Figure 15As shown, the tandem cell 1 is a four-terminal tandem cell. The tandem cell 1 includes a solar cell and a perovskite cell stacked on the solar cell. The solar cell and the perovskite cell achieve efficient utilization of light energy through optical coupling, but are electrically completely independent. The perovskite cell and the solar cell each have independent positive and negative electrodes, which are respectively used to collect and transport photo-generated charges; the electrodes of the perovskite cell and the solar cell are independently connected to an external circuit to achieve the output of their respective photo-generated currents; there is no direct electrical connection between the perovskite cell and the solar cell, and only spectral splitting and light energy distribution are achieved through optical design.

[0128] According to an exemplary embodiment, this embodiment provides a photovoltaic module, which includes the solar cell in the above embodiment, or a solar cell manufactured by the manufacturing method of the solar cell in the above embodiment, or a tandem cell in the above embodiment.

[0129] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope described in this specification.

[0130] The above-described embodiments only represent several implementation manners of the present application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A solar cell, characterized in that, Comprising: A substrate having a first conductivity type, wherein the substrate is doped with antimony elements; A first semiconductor layer provided on the back surface of the substrate, the first semiconductor layer having the same conductivity type as the substrate; A second semiconductor layer provided on the back surface of the substrate, the second semiconductor layer and the first semiconductor layer being alternately arranged on the back surface of the substrate, the second semiconductor layer having a conductivity type opposite to that of the substrate; The concentration of antimony elements in the first semiconductor layer is greater than the concentration of antimony elements in the second semiconductor layer; The doping concentration of antimony element in the first semiconductor layer is 1×10 9 cm -3 -1×10 14 cm -3 , and the doping concentration of antimony element in the second semiconductor layer is 1×10 8 cm -3 -1×10 13 cm -3 .

2. The solar cell according to claim 1, wherein, The diffusion depth of antimony elements in the first semiconductor layer is greater than the diffusion depth of antimony elements in the second semiconductor layer.

3. The solar cell according to claim 1, characterized in that, The solar cell further comprises: An isolation region located between the first semiconductor layer and the second semiconductor layer; A passivation layer covering the back surface of the substrate of the first semiconductor layer, the second semiconductor layer, and the isolation region.

4. The solar cell according to claim 3, characterized in that, The solar cell further comprises: A first metal electrode provided on the side of the first semiconductor layer away from the substrate, the first metal electrode being electrically connected to the first semiconductor layer; A second metal electrode provided on the side of the second semiconductor layer away from the substrate, the second metal electrode being electrically connected to the second semiconductor layer.

5. The solar cell according to claim 4, characterized in that, The doping concentration of antimony element in the substrate is 1×10 14 cm -3 -1×10 18 cm -3 .

6. The solar cell according to claim 1, characterized in that, The first semiconductor layer is doped with a first element having a first conductivity type, and the doping concentration of the first element in the first semiconductor layer is 1×10 20 cm -3 -5×10 20 cm -3 ; The second semiconductor layer has a second element of a second conductivity type, and the doping concentration of the second element in the second semiconductor layer is 2×10 19 cm -3 -5×10 20 cm -3 .

7. The solar cell according to claim 1, wherein The total amount of antimony elements in the first semiconductor layer is greater than the total amount of antimony elements in the second semiconductor layer.

8. The solar cell according to claim 1, wherein The average concentration of antimony elements in the first semiconductor layer is greater than the average concentration of antimony elements in the second semiconductor layer.

9. The solar cell according to claim 1, wherein At the same distance from the substrate, the concentration of antimony elements in the first semiconductor layer is greater than the concentration of antimony elements in the second semiconductor layer.

10. A method for manufacturing a solar cell, wherein the solar cell is the solar cell according to any one of claims 1-9, characterized in that, The manufacturing method comprises: Providing a substrate, the back surface of the substrate including a first region and a second region; Forming a first semiconductor layer in the first region and doping a first element having a first conductivity type into the first semiconductor layer; Forming a second semiconductor layer in the second region and doping a second element having a second conductivity type into the second semiconductor layer; The formation of the first semiconductor layer includes at least two thermal annealings; the formation of the second semiconductor layer includes one thermal annealing; the doping concentration of antimony in the first semiconductor layer is 1×10 9 cm -3 -1×10 14 cm -3 , and the doping concentration of antimony in the second semiconductor layer is 1×10 8 cm -3 -1×10 13 cm -3 .

11. The method for manufacturing a solar cell according to claim 10, wherein, The first element includes elements of Group VA; the second element includes elements of Group IIIA.

12. A stacked battery, characterized in that, Comprising a bottom cell and a top cell stacked on the bottom cell; Wherein, the bottom cell comprises the solar cell according to any one of claims 1-9, or a solar cell manufactured by the manufacturing method of the solar cell according to claim 10 or 11; the top cell comprises a perovskite cell.

13. A photovoltaic module, characterized in that, Comprising the solar cell according to any one of claims 1-9, or a solar cell manufactured by the manufacturing method of the solar cell according to claim 10 or 11, or a tandem cell according to claim 12.

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