Back contact battery and photovoltaic module

Abstract

The invention discloses a back contact battery and a photovoltaic module, relates to the technical field of photovoltaic, and aims to reduce the risk of electric leakage, reduce the risk of problems such as bending and fragments of the back contact battery and improve the working performance of the back contact battery. The back contact cell includes a semiconductor substrate, a P-type doped semiconductor portion, and an N-type doped semiconductor portion. The surface of the isolation region is lower than the surfaces of the first region and the second region in the direction from the second surface to the first surface, so that a groove is formed. The surface of the second region and the surface of the first region are staggered along the thickness direction of the semiconductor substrate, and the height difference between the surface of the first region and the surface of the second region is greater than or equal to 1 [mu] m. The P-type doped semiconductor part is arranged on the first region, extends along the direction close to the second region and is suspended above the groove. In the arrangement direction of the first region and the second region, the length of the part, suspended above the groove, of the P-type doped semiconductor part is smaller than or equal to 0.2 [mu] m. The N-type doped semiconductor portion is disposed within or on the second region.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaic technology, and in particular to a back contact cell and a photovoltaic module. Background Art

[0002] A back-contact cell refers to a solar cell in which the light-facing side of the cell has no electrode, and both the positive and negative electrodes are arranged on the backlight side of the cell. This can reduce the shading of the electrode on the cell, increase the short-circuit current of the cell, and improve the energy conversion efficiency of the cell.

[0003] However, the existing back-contact battery has a high risk of leakage, which is not conducive to improving the working performance of the back-contact battery. Summary of the Invention

[0004] The object of the present invention is to provide a back-contact cell and a photovoltaic module for reducing the risk of leakage between the P-type doped semiconductor part and the N-type doped semiconductor part included in the back-contact cell and improving the working performance of the back-contact cell.

[0005] In order to achieve the above-mentioned objectives, in a first aspect, the present invention provides a back-contact battery, which includes: a semiconductor substrate, a P-type doped semiconductor portion and an N-type doped semiconductor portion. The semiconductor substrate includes a first surface and a second surface relative to each other. The first surface includes a first region and a second region spaced apart, and an isolation region located between the first region and the second region. Along the direction from the second surface to the first surface, the surface of the isolation region is lower than the surface of the first region and the second region to form a groove. The surface of the second region and the surface of the first region are staggered along the thickness direction of the semiconductor substrate, and the height difference between the surface of the first region and the surface of the second region is greater than or equal to 1 μm. The P-type doped semiconductor portion is arranged on the first region, and extends in a direction close to the second region and is suspended above the groove. Along the arrangement direction of the first region and the second region, the length of the portion of the P-type doped semiconductor portion suspended above the groove is less than or equal to 0.2 μm. The N-type doped semiconductor portion is arranged in or on the second region.

[0006] When the above technical solution is adopted, when the back-contact cell provided by the present invention is in operation, the semiconductor substrate absorbs light and generates photogenerated carriers. The P-type doped semiconductor portion and the N-type doped semiconductor portion, spaced apart on the first surface of the semiconductor substrate, can shunt and collect the photogenerated carriers generated within the semiconductor substrate, which are then conducted through the conductive electrode to form a photocurrent. Furthermore, the surface of the second region is staggered with the surface of the first region along the thickness direction of the semiconductor substrate to remove the portion (residue) of the P-type doped semiconductor portion and the N-type doped semiconductor portion deposited earlier during the manufacturing process, located in the region corresponding to the other, as well as the internal doping region that may have been formed within the semiconductor substrate by the earlier deposited portion. This reduces the risk of leakage while allowing the later-formed portion to collect more carriers, thereby improving the conversion efficiency of the back-contact cell. In the above case, in the back-contact cell provided by an embodiment of the present invention, the height difference between the surface of the first region and the surface of the second region is greater than or equal to 1 μm, and the length of the portion of the P-type doped semiconductor portion suspended above the groove is less than or equal to 0.2 μm. In this case, the height difference between the surfaces of the first and second regions is set within an appropriate range, and the length of the portion of the P-type doped semiconductor portion overhanging the groove is relatively short. This prevents electrical connection between the P-type doped semiconductor portion and the N-type doped semiconductor portion at the portion overhanging the groove and / or through residues on the isolation region and the inner doped region within the isolation region, thereby increasing the effective doping concentration of the N-type doped semiconductor portion and promoting the generation of more carriers in the N-type doped semiconductor portion. Furthermore, the length of the portion of the P-type doped semiconductor portion overhanging the groove can be made much shorter than the height difference between the surfaces of the first and second regions, thereby providing a larger separation distance between the P-type doped semiconductor portion and the N-type doped semiconductor portion. Even if residues from the fabrication of the N-type doped semiconductor portion remain at the portion of the P-type doped semiconductor portion overhanging the groove, the larger distance between the portion of the P-type doped semiconductor portion overhanging the groove and the N-type doped semiconductor portion (i.e., the width of the portion of the isolation region exposed outside the P-type doped semiconductor portion is appropriate) can reduce the risk of leakage at the portion of the P-type doped semiconductor portion overhanging the groove, thereby improving the conversion efficiency of the back-contact cell. Furthermore, along the direction from the second surface to the first surface, the surface of the isolation region is lower than the surfaces of the first region and the second region, respectively, and a groove is formed to remove the portions (residues) of the P-type doped semiconductor portion and the N-type doped semiconductor portion deposited on the isolation region during the manufacturing process, as well as at least the inner-expanded doped region formed in the isolation region when the P-type doped semiconductor portion is manufactured. That is, the leakage path between the P-type doped semiconductor portion and the N-type doped semiconductor portion is completely interrupted by the setting of the groove, while avoiding leakage at the portion of the P-type doped semiconductor portion suspended above the groove, thereby improving the conversion efficiency of the back-contact battery.In addition, the portion of the P-type doped semiconductor portion suspended above the groove can also cooperate with the surface of the adjacent region to change the light transmission path, so that the light emitted from the surface of the isolation region can return to the semiconductor substrate under the action of the portion of the P-type doped semiconductor portion suspended above the groove, improving the power generation efficiency of the back contact battery.

[0007] As a possible implementation solution, the height difference between the surface of the first region and the surface of the second region is less than or equal to 1.5 μm. In this case, an appropriate height difference is provided between the P-type doped semiconductor portion and the N-type doped semiconductor portion, and the depth of the portion of the semiconductor substrate corresponding to the first region or the second region etched is relatively shallow, that is, not over-etched, so as to reduce the leakage risk while enabling the portions of the semiconductor substrate corresponding to the first region and the second region to have a relatively wide light absorption wavelength, improving the light utilization rate of the semiconductor substrate. Moreover, the portions of the semiconductor substrate corresponding to the first region and the second region both have a relatively high anti-mechanical load capacity, reducing the risk of problems such as bending and fragmentation of the back contact battery. At the same time, even if the height difference between the surface of the first region and the surface of the second region can be set in a relatively large range greater than or equal to 1 μm and less than or equal to 1.5 μm (relative to the length of the portion of the P-type doped semiconductor portion suspended above the groove), the length of the portion of the P-type doped semiconductor portion suspended above the groove is still small. Even if the P-type doped semiconductor portion and the N-type doped semiconductor portion with opposite conduction types overlap at the eaves position, their overlapping area is small, and the leakage path between the P-type doped semiconductor portion and the N-type doped semiconductor portion can be cut off by a sufficient height difference. Thus, the anti-leakage effect is enhanced in the above two aspects, improving the conversion efficiency of the back contact battery.

[0008] As a possible implementation solution, the ratio of the length of the portion of the P-type doped semiconductor portion suspended above the groove to the height difference between the surface of the first region and the surface of the second region is greater than or equal to 0 and less than or equal to 20%. In this case, the length of the portion of the P-type doped semiconductor portion suspended above the groove is small, so that even if the P-type doped semiconductor portion and the N-type doped semiconductor portion with opposite conduction types overlap at the eaves position, their overlapping area is small. Moreover, the height difference between the surface of the first region and the surface of the second region is large, and the leakage path between the P-type doped semiconductor portion and the N-type doped semiconductor portion can be cut off by a sufficient height difference. Thus, the anti-leakage effect is enhanced in the above two aspects, improving the conversion efficiency of the back contact battery.

[0009] As a possible implementation solution, the doping concentration of the P-type doped semiconductor portion is greater than or equal to 5E19 cm -3 and less than or equal to 1E20 cm -3 .

[0010] In the case of adopting the above technical solution, the optional window of the doping concentration corresponding to the P-type doped semiconductor part is relatively large, which is beneficial to improving the applicability of the back-contact battery provided by the present invention in different application scenarios. In addition, the doping concentration of the P-type doped semiconductor part can also be selected to be greater than the conventional doping concentration (the general upper limit is 6E19 cm -3 ), so as to improve the field passivation effect of the P-type doped semiconductor part and have good contact performance with the electrode, reduce Rs, thereby improving FF, increasing the wavelength range of light absorption, improving the bending of the battery and reducing the fragmentation rate. At the same time, even if the doping concentration of the P-type doped semiconductor part is relatively high, in the manufacturing process of the back-contact battery provided by the embodiments of the present invention, by changing the composition of the alkaline etching solution and the parameter ranges such as the etching time and the etching temperature, the etching rate difference between the P-type doped semiconductor part and the semiconductor substrate can be reduced, so that on the premise of ensuring that the P-type doped semiconductor part has a high field passivation effect and good contact performance, the length of the part of the P-type doped semiconductor part suspended on the groove is small, reducing the leakage risk; and the surface height difference between the corresponding first region and the second region of the semiconductor substrate is also relatively small, preventing the part of the semiconductor substrate corresponding to the isolation region and the second region from being over-etched, reducing the risk of the battery being bent and fragmented, and improving the ability of the component to resist mechanical load.

[0011] As a possible implementation, the P-type doped semiconductor part includes a P-type doped polysilicon layer. With such a setting, it is beneficial to improve the carrier lateral transport ability of the P-type doped semiconductor part and reduce the transport loss.

[0012] As a possible implementation, the thickness of the P-type doped semiconductor part is greater than or equal to 60 nm and less than or equal to 350 nm. In this case, the P-type doped semiconductor part has a relatively large thickness, and when the P-type doped semiconductor part has a relatively large doping concentration, it is beneficial to make the P-type doped semiconductor part have a high field passivation effect and good contact performance with the conductive electrode. At the same time, although in the back-contact battery provided by the embodiments of the present invention, the P-type doped semiconductor part can have a relatively large doping concentration and a relatively large thickness, increasing the etching difficulty and etching rate corresponding to the P-type doped semiconductor part, as described above, in the actual manufacturing process, by changing the composition of the alkaline etching solution and the parameter ranges such as the etching time and the etching temperature, the length of the part of the P-type doped semiconductor part suspended on the groove can be made small, reducing the leakage risk, and further by having a suitable height difference between the surface of the first region 12 and the surface of the second region 13, interrupting the leakage path. It can be seen that the back-contact battery provided by the embodiments of the present invention can take into account the high field passivation effect and contact performance of the P-type doped semiconductor part and the low leakage risk.

[0013] As a possible implementation solution, the N-type doped semiconductor portion includes an N-type doped crystalline silicon layer disposed on the second region. Wherein, the thickness of the N-type doped crystalline silicon layer is greater than or equal to 30 nm and less than or equal to 250 nm; and / or, along the direction from the first region to the second region, the distance by which the sidewall of the N-type doped crystalline silicon layer indents inward relative to the adjacent sidewall in the groove is less than or equal to 100 nm; and / or, the height difference between the bottom surface of the groove and the surface of the second region is greater than or equal to 3 μm and less than or equal to 4 μm.

[0014] In the case of adopting the above technical solution, when the thickness of the N-type doped crystalline silicon layer included in the N-type doped semiconductor portion is greater than or equal to 30 nm and less than or equal to 250 nm, on the premise of enabling the N-type doped crystalline silicon layer to have a good passivation effect, it is possible to prevent the high optical parasitic absorption of itself caused by the excessive thickness of the N-type doped crystalline silicon layer, which is beneficial to improving the conversion efficiency of the back contact battery. In addition, when the distance by which the sidewall of the N-type doped crystalline silicon layer indents inward relative to the adjacent sidewall in the groove is less than or equal to 100 nm, the formation range of the N-type doped crystalline silicon layer on the second region is larger, which is beneficial to enabling the N-type doped crystalline silicon layer to have a high field passivation effect and reducing the carrier recombination rate.

[0015] In addition, it can be understood that after patterning the N-type doped semiconductor portion, it may be necessary to remove the inner diffusion doped region formed at least in the isolation region during the manufacture of the N-type doped semiconductor portion to reduce leakage. In this case, the height difference between the surface of the second region and the bottom surface of the groove is within the above range, which is beneficial to preventing the inner diffusion doped region from not being completely removed due to the too small height difference, so as to interrupt the leakage path between the P-type doped semiconductor portion and the N-type doped semiconductor portion through the groove in the isolation region. At the same time, it can also prevent the part of the semiconductor substrate corresponding to the isolation region from being over-etched due to the too large height difference, reduce the risk of the battery being bent and fragmented, and improve the ability of the component to resist mechanical load; and, it can also reduce the etching effect of the etchant on the N-type doped semiconductor portion located in the second region, which is beneficial to controlling the length by which the edge of the N-type doped semiconductor portion indents inward relative to the edge of the second region to be relatively small, and the ratio tends to be 5%-20%. For example, it can increase the passivation contact area between the N-type doped semiconductor portion and the semiconductor substrate, reduce carrier recombination, and is beneficial to more current being exported and utilized.

[0016] As a possible implementation solution, the first surface has a first tower-based texture structure; the first tower-based texture structure includes a plurality of first sub-structures, and the bottom surface of the first sub-structure indents into the semiconductor substrate relative to the surface of the second region. And, the first tower-based texture structure is at least distributed on the surface of the second region. In the first tower-based texture structure, the first sub-structure with a complete bottom surface is defined as the target sub-structure; the one-dimensional size of at least one target sub-structure is greater than or equal to 12 μm and less than or equal to 35 μm.

[0017] Under the above technical solution, compared with surface texture structures with relatively sharp surfaces such as the pyramid structure, since the top surface of the first tower-base-shaped texture structure is relatively flat, when the surface of the second region has the first tower-base-shaped texture structure, the surface of the second region is macroscopically flat, which is beneficial to improving the formation quality and film thickness of the surface passivation layer formed on the second region, and improving the passivation effect of the part of the surface passivation layer corresponding to the second region. In addition, when the N-type doped semiconductor part includes a doped semiconductor layer formed on the second region, it is also beneficial to improving the formation quality of the N-type doped semiconductor part, improving the field passivation effect of the N-type doped semiconductor part, and reducing the carrier recombination rate.

[0018] In addition, it can be understood that the etchant used in the texturing operation to form the first tower-base-shaped texture structure on the surface of the second region etches at least the part of the semiconductor substrate corresponding to the second region, thereby forming the corresponding surface topography. When the P-type doped semiconductor part is first formed on the first surface, the process of patterning the P-type doped semiconductor part is the above-mentioned process of etching the second region, and is also the process of forming the height difference between the surfaces of the first region and the second region, and the part of the P-type doped semiconductor part suspended above the groove. That is, the same etching process needs to take into account the above three aspects of etching. Based on this, when the one-dimensional size of at least one target sub-structure included in the first tower-base-shaped texture structure is within the above range, it is possible to take into account the surface topography requirements of the second region, that is, to prevent the surface of the second region from being too flat or too rough due to the one-dimensional size of the target sub-structure being too large or too small, ensuring that the surface passivation layer has a high passivation effect on the second region (or when the N-type doped semiconductor part is disposed on the second region, ensuring that the surface passivation layer and the N-type doped semiconductor part have a high passivation effect), and making the N-type doped semiconductor part have a suitable contact area with the conductive electrode, improving the contact performance. At the same time, it is also possible to prevent the surface of the second region represented by the one-dimensional size of the target sub-structure being too small from being etched to a small extent by the etchant after patterning the P-type doped semiconductor part, preventing the internal diffusion doping region formed by manufacturing the P-type doped semiconductor part from remaining in the second region, reducing the leakage risk, and being beneficial to improving the carrier collection efficiency of the N-type doped semiconductor part. Secondly, it is also possible to prevent the surface of the second region represented by the large size of the target sub-structure from being etched too much, that is, to prevent the part of the semiconductor substrate corresponding to the second region from being over-etched, and to prevent the length of the part of the P-type doped semiconductor part suspended above the groove from being large. The part of the semiconductor substrate corresponding to the second region has a high anti-mechanical load capacity, reducing the risk of problems such as bending and fragmentation of the back-contact battery. And, reducing the leakage risk at the part of the P-type doped semiconductor part suspended above the groove.

[0019] As a possible implementation, the surface of the second region also has a second tower-base-like texture structure. The second tower-base-like texture structure includes a plurality of second sub-structures disposed within the first sub-structure, and the bottom surface of the second sub-structure is recessed into the semiconductor substrate relative to the surface of the first sub-structure. Among them, the one-dimensional size of at least one second sub-structure is greater than or equal to 0.03 times and less than or equal to 0.1 times the one-dimensional size of the target sub-structure; and / or, the number of second sub-structures disposed in at least one target sub-structure is greater than or equal to 10 and less than or equal to 30.

[0020] In the case of adopting the above technical solution, the second tower-base-like texture structure includes a plurality of second sub-structures disposed within the first sub-structure and recessed into the semiconductor substrate relative to the surface of the first sub-structure, so that the undulating degree of the surface of the first tower-base-like texture structure with undulating topography is superimposed on the undulating degree of the second tower-base-like texture structure, which is conducive to increasing the specific surface area of the surface of the second region. Additionally, if the N-type doped semiconductor portion is disposed in the second region, the surface of the second region is the surface of the N-type doped semiconductor portion facing away from the semiconductor substrate. If the N-type doped semiconductor portion includes a doped semiconductor layer disposed on the second region, since the doped semiconductor layer is disposed on the second region through a deposition process, the surface of the doped semiconductor layer facing away from the semiconductor substrate has substantially the same undulation as the surface of the second region. Based on this, when the surface of the second region has a large specific surface area, the surface of the N-type doped semiconductor portion facing away from the semiconductor substrate also has a large specific surface area, which is conducive to increasing the contact area between the N-type doped semiconductor portion and the electrode and improving the contact performance therebetween. Furthermore, when the N-type doped semiconductor portion includes a doped semiconductor layer disposed on the second region, increasing the specific surface area of the surface of the second region can also increase the passivation contact area between the doped semiconductor layer and the second region, which is conducive to the shunt and collection of carriers.

[0021] In addition, as described above, the etchant used for texturing the second region surface forms the corresponding surface topography by etching at least the portion of the semiconductor substrate corresponding to the second region. When the P-type doped semiconductor portion is first formed on the first surface, the process of patterning the P-type doped semiconductor portion is the above-mentioned process of etching the second region, and is also the process of forming the height difference between the surfaces of the first region and the second region, and the portion of the P-type doped semiconductor portion suspended above the groove. Therefore, when the one-dimensional size of the second sub-structure is within the above range, it is not only beneficial to prevent the second region surface from being microscopically too rough due to an excessive number of second sub-structures arranged in the second region surface caused by the too small one-dimensional size of the second sub-structure, improving the formation quality of the N-type doped semiconductor portion and / or the surface passivation layer, so that the N-type doped semiconductor portion and / or the surface passivation layer have a high passivation effect. Moreover, it can prevent the second region surface from having a too small roughness microscopically due to too few second sub-structures arranged in the second region surface caused by the too large one-dimensional size of the second sub-structure, which is beneficial to increasing the contact area between the N-type doped semiconductor portion and the electrode and improving the contact performance (or, when the N-type doped semiconductor portion includes a doped semiconductor layer, it is also beneficial to increasing the contact area between the N-type doped semiconductor portion and the semiconductor substrate and facilitating the reduction of the carrier recombination rate). It can also prevent the etching degree of the etchant on at least the portion of the semiconductor substrate corresponding to the second region from being too low due to the too small one-dimensional size of the second sub-structure, prevent the residual internal diffusion doping region formed during the manufacture of the P-type doped semiconductor portion in the second region, reduce the leakage risk, and facilitate the improvement of the carrier collection efficiency of the N-type doped semiconductor portion. Furthermore, it can also prevent the etching degree of at least the second region surface represented by the too large one-dimensional size of the second sub-structure from being too large, that is, prevent the portion of the semiconductor substrate corresponding to the second region from being over-etched and prevent the length of the portion of the P-type doped semiconductor portion suspended above the groove from being too large. The portion of the semiconductor substrate corresponding to the second region has a high anti-mechanical load capacity, reducing the risk of problems such as bending and fragmentation of the back-contact battery. Moreover, it reduces the leakage risk at the portion of the P-type doped semiconductor portion suspended above the groove.

[0022] As a possible implementation, the first tower-based texture structure and the second tower-based texture structure are also distributed on the surface of the first region, and the distribution density of the second tower-based texture structure in the first region is less than the distribution density of the second tower-based texture structure in the second region. In this case, the surface of the first region has a smaller number of second tower-based texture structures, and, when the doping concentration of the P-type doped semiconductor portion is set within a relatively high numerical range (for example, it can be set to be greater than 6E19 cm -3) When it is still possible to make the surface of the first region flatter than the surface of the second region, on the basis of improving the contact resistance between the P-type doped semiconductor portion and the conductive electrode, the formation quality of the P-type doped semiconductor portion on the first region can be improved, and the field passivation effect of the P-type doped semiconductor portion can be enhanced. At the same time, when the N-type doped semiconductor portion includes a doped semiconductor layer, increasing the specific surface area of the second region is also beneficial to controlling the formation thickness and uniformity of the doped semiconductor layer, reducing the optical parasitic absorption of the doped semiconductor layer, and improving the bifaciality of the back contact cell. It can be seen that the back contact cell provided by the present invention can improve the light utilization rate of the back contact cell while improving the contact performance of the P-type doped semiconductor portion.

[0023] As a possible implementation solution, the first tower-base-shaped texture structure is also distributed on the surface of the first region, and the second tower-base-shaped texture structure is not provided on the surface of the first region. The application principle of the beneficial effects in this case can refer to the application principle of the beneficial effects that the distribution density of the second tower-base-shaped texture structure in the first region is less than the distribution density of the second tower-base-shaped texture structure in the second region described above, and will not be elaborated here.

[0024] As a possible implementation solution, the surface of the groove has a matte structure.

[0025] In the case of adopting the above technical solution, when setting a matte structure on the surface of the groove, it is necessary to further etch a part of the semiconductor substrate corresponding to the isolation region with an etchant. At this time, the inner diffusion doped region formed in the isolation region during the manufacture of the P-type doped semiconductor portion (or the P-type doped semiconductor portion and the N-type doped semiconductor portion) can be further removed, which is beneficial to interrupting the leakage path between the P-type doped semiconductor portion and the N-type doped semiconductor portion through the isolation region and reducing the leakage risk. At the same time, the light trapping effect of the isolation region can also be improved, and the bifaciality of the back contact cell can be enhanced.

[0026] As a possible implementation solution, along the direction from the second surface to the first surface, the surface of the second region is lower than the surface of the first region.

[0027] As a possible implementation solution, along the direction from the second surface to the first surface, the surface of the second region is lower than the surface of the first region, and the sum of the height difference between the surface of the first region and the bottom surface of the groove and the height difference between the surface of the second region and the bottom surface of the groove is less than or equal to 20 μm.

[0028] In the case of adopting the above technical solution, the sum of the height differences between the surface of the first region and the bottom surface of the groove and between the surface of the second region and the bottom surface of the groove is small, which is conducive to reducing the transmission path length corresponding to the carriers bypassing the groove and being collected by the P-type doped semiconductor part or the N-type doped semiconductor part, reducing the transmission loss, and being conducive to improving the conversion efficiency and component power of the back contact battery. Further, in the case of improving the battery efficiency, if the width of the isolation region 14 is reduced to be less than or equal to 100 μm, the influence of the setting size of the above height difference on the transmission of carriers between the P-type doped semiconductor part and the N-type doped semiconductor part will become particularly obvious. Therefore, controlling the sum of the above two height differences is conducive to significantly improving the component power.

[0029] In a second aspect, the present invention provides a photovoltaic module, which includes: a battery string and a packaging layer. The battery string is formed by electrically connecting a plurality of back contact batteries provided in the first aspect and its various implementation manners; the packaging layer covers the surface of the battery string.

[0030] For the beneficial effects of the second aspect and its various implementation manners of the present invention, reference can be made to the analysis of the beneficial effects in the first aspect and its various implementation manners, which will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The drawings described herein are used to provide a further understanding of the present invention, and constitute a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings:

[0032] Figure 1 is a longitudinal sectional schematic view of the first structure of the back contact battery provided by the embodiment of the present invention Figure 1 ;

[0033] Figure 2 is a longitudinal sectional schematic view of the first structure of the back contact battery provided by the embodiment of the present invention Figure 2 ;

[0034] Figure 3 is a longitudinal sectional schematic view of the first structure of the back contact battery provided by the embodiment of the present invention Figure 3 ;

[0035] Figure 4 is a longitudinal sectional schematic view of the first structure of the back contact battery provided by the embodiment of the present invention Figure 4 ;

[0036] Figure 5 is a longitudinal sectional schematic view of the first structure of the back contact battery provided by the embodiment of the present invention Figure 5 ;

[0037] Figure 6Longitudinal sectional schematic view of the first structure of the back contact battery provided by the embodiment of the present invention Figure 5 ;

[0038] Figure 7 Longitudinal sectional schematic view of the first structure of the back contact battery provided by the embodiment of the present invention Figure 5 ;

[0039] Figure 8 Longitudinal sectional schematic view of the first structure of the back contact battery provided by the embodiment of the present invention Figure 5 ;

[0040] Figure 9 Structural schematic view of the back contact battery provided by the embodiment of the present invention during the manufacturing process Figure 1 ;

[0041] Figure 10 Structural schematic view of the back contact battery provided by the embodiment of the present invention during the manufacturing process Figure 2 ;

[0042] Figure 11 Structural schematic view of the back contact battery provided by the embodiment of the present invention during the manufacturing process Figure 3 ;

[0043] Figure 12 Structural schematic view of the back contact battery provided by the embodiment of the present invention during the manufacturing process Figure 4 ;

[0044] Figure 13 Structural schematic view of the back contact battery provided by the embodiment of the present invention during the manufacturing process Figure 5 ;

[0045] Figure 14 SEM image of the back contact battery provided by the embodiment of the present invention during the manufacturing process, after patterning the P-type doped semiconductor portion and etching a part of the thickness of the semiconductor substrate

[0046] Reference numerals: 11 is a semiconductor substrate, 12 is a first region, 13 is a second region, 14 is an isolation region, 15 is a groove, 16 is a P-type doped semiconductor portion, 17 is an N-type doped semiconductor portion, 18 is an N-type doped crystalline silicon layer, 19 is a first tower-based texture structure, 20 is a second tower-based texture structure, 21 is a first interface passivation layer, 22 is a second interface passivation layer, and 23 is a surface passivation layer. Detailed implementation manners

[0047] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present invention.

[0048] Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. These figures are not drawn to scale, where in order to express more clearly, some details are enlarged and some details may be omitted. The shapes of various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary. In practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art can design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0049] In the context of the present invention, when a layer / component is referred to as being "on" another layer / component, the layer / component can be directly on the other layer / component, or there can be an intermediate layer / component between them. Additionally, if a layer / component is "on" another layer / component in one orientation, then when the orientation is reversed, the layer / component can be "under" the other layer / component. In order to make the technical problems, technical solutions, and beneficial effects to be solved by the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0050] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality" means two or more, unless otherwise specifically defined. "Several" means one or more, unless otherwise specifically defined.

[0051] In the description of the present invention, it should be noted that unless otherwise clearly specified and limited, the terms "mounted", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal communication of two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0052] A solar cell is a device that can convert the light energy of the sun into electrical energy. Specifically, when the solar cell is in a working state, sunlight shines on the semiconductor p-n junction of the solar cell, forming new hole-electron pairs. Under the action of the built-in electric field in the p-n junction, the photo-generated holes flow to the p region, and the photo-generated electrons flow to the n region. After connecting the circuit, an electric current can be generated.

[0053] Among them, a solar cell in which both the positive electrode and the negative electrode are on the back surface of the battery is a back-contact battery. Compared with a double-sided contact solar cell, the front surface of the back-contact battery has no metal electrode blocking, so that the light-facing side of the back-contact battery has a higher light utilization rate. Therefore, the back-contact battery has a higher short-circuit current and photoelectric conversion efficiency, and is one of the current technical directions for realizing high-efficiency crystalline silicon batteries.

[0054] In a first aspect, an embodiment of the present invention provides a back-contact battery. As Figure 1 and Figure 2 shown, the back-contact battery provided by the embodiment of the present invention includes: a semiconductor substrate 11, a P-type doped semiconductor portion 16, and an N-type doped semiconductor portion 17. The semiconductor substrate 11 includes opposite first and second surfaces. The first surface includes a first region 12 and a second region 13 arranged at intervals, and an isolation region 14 located between the first region 12 and the second region 13. The P-type doped semiconductor portion 16 is at least disposed on the first region 12. The N-type doped semiconductor portion 17 is disposed in or on the second region 13.

[0055] When the back-contact battery provided by the embodiment of the present invention is in a working state, the battery absorbs light and generates photo-generated carriers. The P-type doped semiconductor portion and the N-type doped semiconductor portion arranged at intervals on the first surface of the semiconductor substrate can shunt and collect the photo-generated carriers generated in the semiconductor substrate, and then form a photocurrent after being led out through a conductive electrode.

[0056] In the actual application process, the embodiment of the present invention does not specifically limit the conductivity type of the semiconductor substrate. Exemplarily, the semiconductor substrate can be a P-type semiconductor substrate, an N-type semiconductor substrate, or an intrinsic semiconductor substrate.

[0057] The semiconductor substrate includes opposite first and second surfaces. Among them, the first surface of the semiconductor substrate corresponds to the back surface of the back-contact battery, and the second surface of the semiconductor substrate corresponds to the front surface of the back-contact battery.

[0058] The ranges corresponding to the first region, the second region, and the isolation region included in the first surface of the semiconductor substrate can be determined according to the range requirements for the P-type doped semiconductor portion and the N-type doped semiconductor portion in the actual application scenario, as well as the anti-leakage requirements between the P-type doped semiconductor portion and the N-type doped semiconductor portion, and no specific limitation is made here. Specifically, since the P-type doped semiconductor portion included in the back-contact battery is at least disposed on the first region, the distribution range of the first region on the first surface can be determined according to the distribution requirements for the portion of the P-type doped semiconductor portion directly disposed on the semiconductor substrate in the actual application scenario. Since the N-type doped semiconductor portion included in the back-contact battery is disposed in or on at least a part of the second region on the first surface, the approximate distribution range of the second region on the first surface can be determined according to the distribution requirements for the N-type doped semiconductor portion on the semiconductor substrate in the actual application scenario.

[0059] It should be noted that the P-type doped semiconductor portion can be only disposed on the first region. At this time, the orthographic projection range of the P-type doped semiconductor portion included in the back-contact battery on the first surface is the range where the first region is located.

[0060] Or, as Figure 1 、 Figure 2 and Figure 14 shown, the P-type doped semiconductor portion 16 can be disposed on the first region 12, and extends along the direction close to the second region 13 and is suspended above the isolation region 14 (such as the annotation L in Figure 14 ). With such a setting, the portion of the P-type doped semiconductor portion 16 suspended above the groove 15 can also cooperate with the surface of the adjacent region to change the light transmission path, so that the light emitted from the surface of the isolation region 14 can return to the semiconductor substrate 11 under the action of the portion of the P-type doped semiconductor portion 16 suspended above the groove 15, improving the power generation efficiency of the back-contact battery. In this case, it is necessary to determine the distribution range of the first region on the first surface according to the portion of the P-type doped semiconductor portion disposed on the semiconductor substrate.

[0061] Exemplarily, the P-type doped semiconductor portion is disposed on the first region, extends along the direction close to the second region, and is suspended above the groove; along the arrangement direction of the first region and the second region, the length of the portion of the P-type doped semiconductor portion suspended above the groove (such as the annotation L in Figure 14 ) is less than or equal to 0.2 μm.

[0062] As for the isolation region, after the approximate ranges of the first region and the second region are determined, the approximate range of the isolation region is determined.

[0063] In terms of the surface setting height, as Figure 1 and Figure 2As shown, along the direction from the second surface to the first surface, the surface of the isolation region 14 can be lower than the surfaces of the first region 12 and the second region 13 to form a groove 15. In this case, along the direction from the second surface to the first surface, the surface of the isolation region 14 is respectively lower than the surfaces of the first region 12 and the second region 13, and the groove 15 is formed to remove the portions (residues) of the P-type doped semiconductor portion 16 and the N-type doped semiconductor portion 17 deposited on the isolation region 14 during the manufacturing process, and at least remove the internal diffusion doped region formed in the isolation region 14 when manufacturing the P-type doped semiconductor portion 16. That is, it is beneficial to completely interrupt the leakage path between the P-type doped semiconductor portion 16 and the N-type doped semiconductor portion 17 through the setting of the groove 15, and at the same time, it is beneficial to avoid leakage at the portion (especially the eaves portion) of the P-type doped semiconductor portion 16 close to the N-type doped semiconductor portion 17, thereby improving the conversion efficiency of the back contact battery.

[0064] When the surface of the isolation region is lower than the surfaces of the first region and the second region to form a groove, after the general ranges of the first region and the second region are determined, the range of the isolation region can be determined according to the set height of the surface of the region between the two. Specifically, in the first surface, the region located between the first region and the second region and with a concave surface is the isolation region. As Figure 1 and Figure 2 shown, along the arrangement direction of the first region 12 and the second region 13, the boundaries between the isolation region 14 and the first region 12 and the second region 13 can be determined based on the side walls of the groove 15 in the isolation region 14.

[0065] As for the height differences between the grooves of the isolation region relative to the surfaces of the first region and the second region respectively, they can be determined according to the set height relationship between the surface of the second region and the surface of the first region, and no specific limitation is made here.

[0066] Exemplarily, as Figure 1 and Figure 2 shown, the surface of the second region 13 and the surface of the first region 12 can be staggeredly arranged along the thickness direction of the semiconductor substrate 11. In this case, it is beneficial to remove the portions (residues) of one of the P-type doped semiconductor portion 16 and the N-type doped semiconductor portion 17 that are deposited first during the manufacturing process and are located in the corresponding region of the other, and the internal diffusion doped region that the first-deposited one may form in the semiconductor substrate 11. While reducing the leakage risk, it is beneficial for the later-formed one to collect more carriers and improve the conversion efficiency of the back contact battery.

[0067] In terms of the set surface height, the staggered arrangement of the surface of the second region and the surface of the first region along the thickness direction of the semiconductor substrate can mean that: as Figure 5As shown, the surface of the first region 12 is higher than the surface of the second region 13. At this time, in the actual manufacturing process, the surface of the first region 12 can be made higher by first manufacturing the P-type doped semiconductor portion 16 and then forming the N-type doped semiconductor portion 17. Additionally, in this case, the surface of the isolation region 14 needs to be lower than the surface of the second region 13.

[0068] Alternatively, the surface of the second region can be higher than the surface of the first region. At this time, in the actual manufacturing process, the surface of the second region can be made higher by first manufacturing the N-type doped semiconductor portion and then forming the P-type doped semiconductor portion. Additionally, in this case, the surface of the isolation region needs to be lower than the surface of the first region. The following will be described by taking the case of first manufacturing the P-type doped semiconductor portion and then forming the N-type doped semiconductor portion as an example.

[0069] As for the height difference between the surface of the first region and the surface of the second region, it can be set according to actual requirements.

[0070] Exemplarily, the height difference between the surface of the first region and the surface of the second region can be greater than or equal to 1 μm. For example: the height difference between the surface of the first region and the surface of the second region can be 1 μm, 1.1 μm, 1.15 μm, 1.2 μm, 1.25 μm, 1.3 μm, 1.35 μm, 1.4 μm, 1.45 μm, or 1.5 μm, etc. In this case, it is possible to suppress the incomplete removal of the inward diffusion doped regions formed in the isolation region and the second region at least when manufacturing the P-type doped semiconductor portion, reduce and even eliminate the residue of the inward diffusion doped regions in the isolation region and the second region when manufacturing the P-type doped semiconductor portion, which is beneficial for the N-type doped semiconductor portion to collect more carriers, and subsequently, the isolation region can completely interrupt the leakage path between the P-type doped semiconductor portion and the N-type doped semiconductor portion, improving the conversion efficiency of the back contact battery.

[0071] In the field of photovoltaics, the existing back-contact batteries have a relatively high risk of leakage. Specifically, during the actual manufacturing process of back-contact batteries, after forming a P-type doped semiconductor portion disposed as a whole layer on a semiconductor substrate, when patterning the P-type doped semiconductor portion by using a traditional alkaline etching method, in order to fully remove the P-type doped semiconductor portion located in the spacer region and the N-type doped semiconductor portion, as well as the P-type doped inner diffusion region in the semiconductor substrate, it is necessary to etch the P-type doped semiconductor portion and the exposed semiconductor substrate sufficiently. However, the etching rate of the traditional alkaline etching method for the P-type doped semiconductor portion is slow, while the etching rate for the semiconductor substrate is fast. Therefore, as the etching time increases, the length of the eaves of the P-type doped semiconductor portion suspended above the etched surface of the silicon substrate, and the height difference between the two region surfaces of the semiconductor substrate corresponding to the P-type doped semiconductor portion and the N-type doped semiconductor portion will both become larger. Moreover, the length of the P-type doped semiconductor portion suspended above the etched surface of the silicon substrate formed by the traditional alkaline etching method, and the magnitude of the height difference between the two region surfaces of the semiconductor substrate corresponding to the P-type doped semiconductor portion and the N-type doped semiconductor portion are basically equal. At this time, the length of the eaves of the P-type doped semiconductor portion suspended above the etched surface of the silicon substrate is relatively long. Once there is a doped portion with a conductivity type opposite to that of the P-type doped semiconductor portion suspended above the etched surface of the silicon substrate, the leakage risk will increase. Secondly, the height difference between the two region surfaces of the semiconductor substrate corresponding to the P-type doped semiconductor portion and the N-type doped semiconductor portion is also not easy to control, and it is easy to overly thin the semiconductor substrate, resulting in an increase in risks such as deformation and fragmentation of the battery, which is not conducive to improving the working performance of the back-contact battery.

[0072] Exemplarily, as Figure 1 and Figure 2 shown, in the back-contact battery provided in the embodiment of the present invention, the first surface of the semiconductor substrate 11 includes a first region 12 and a second region 13 arranged at intervals, and an isolation region 14 located between the first region 12 and the second region 13. Along the direction from the second surface to the first surface, the surface of the isolation region 14 is lower than the surfaces of the first region 12 and the second region 13 to form a groove 15. The surface of the second region 13 and the surface of the first region 12 are arranged in a staggered manner along the thickness direction of the semiconductor substrate 11, and the height difference between the surface of the first region 12 and the surface of the second region 13 is greater than or equal to 1 μm; along the arrangement direction of the first region 12 and the second region 13, the length of the portion of the P-type doped semiconductor portion 16 suspended above the groove 15 is less than or equal to 0.2 μm.

[0073] As Figure 1 and Figure 2As shown, the surface of the second region 13 is offset from the surface of the first region 12 in the thickness direction of the semiconductor substrate 11, and the height difference between the surface of the first region and the surface of the second region is greater than or equal to 1 μm. When the P-type doped semiconductor portion 16 is patterned, a part (residue) of the one that is deposited earlier in the manufacturing process in the P-type doped semiconductor portion 16 and the N-type doped semiconductor portion 17, and the inward diffusion doping region that may be formed by the one deposited earlier in the semiconductor substrate 11 are removed, reducing the leakage risk while facilitating the one formed later to collect more carriers and improving the conversion efficiency of the back-contact battery. During the above patterning process, a part of the P-type doped semiconductor portion 16 will be formed to be suspended above the groove 15. This part can cooperate with the surface of the adjacent region to change the light transmission path, so that the light emitted from the surface of the isolation region 14 can return to the semiconductor substrate 11 under the action of the part of the P-type doped semiconductor portion 16 suspended above the groove 15, improving the power generation efficiency of the back-contact battery. At this time, on the basis that the height difference between the surfaces of the first region 12 and the second region 13 is controlled within a suitable range, the length of the part of the P-type doped semiconductor portion 16 suspended above the groove 15 is also small, less than or equal to 0.2 μm, which can prevent the P-type doped semiconductor portion 16 and the N-type doped semiconductor portion 17 from being electrically connected at the part suspended above the groove 15 and / or through the residue on the isolation region 14 and the inward diffusion doping region in the isolation region 14, further increasing the effective doping concentration of the N-type doped semiconductor portion and prompting the N-type doped semiconductor portion to form more carriers; further, it can make the length of the part of the P-type doped semiconductor portion 16 suspended above the groove 15 much smaller than the height difference between the surfaces of the first region 12 and the second region 13 (for example: the ratio of the length of the part of the P-type doped semiconductor portion 16 suspended above the groove 15 to the height difference between the surfaces of the first region 12 and the second region 13 is in the range of 0% - 20%), so that there is a large spacing distance between the P-type doped semiconductor portion 16 and the N-type doped semiconductor portion 17. Even if there is a residue from the manufacturing of the N-type doped semiconductor portion remaining at the part of the P-type doped semiconductor portion 16 suspended above the groove 15, due to the suitable distance between the part of the P-type doped semiconductor portion 16 suspended above the groove 15 and the N-type doped semiconductor portion 17 (that is, the width of the part of the isolation region 14 exposed outside the P-type doped semiconductor portion 16 is appropriate), the leakage risk at the part of the P-type doped semiconductor portion 16 suspended above the groove 15 can be reduced, and the conversion efficiency of the back-contact battery can be improved.Furthermore, along the direction from the second surface to the first surface, the surfaces of the isolation region 14 are respectively lower than the surfaces of the first region 12 and the second region 13, and a groove 15 is formed to remove the portions (residues) of the P-type doped semiconductor portion 16 and the N-type doped semiconductor portion 17 deposited on the isolation region 14 during the manufacturing process, and at least remove the inwardly diffused doped region formed in the isolation region 14 when manufacturing the P-type doped semiconductor portion 16. That is, by providing the groove 15, the leakage path between the P-type doped semiconductor portion 16 and the N-type doped semiconductor portion 17 is completely interrupted, and at the same time, leakage at the portion where the P-type doped semiconductor portion 16 is suspended above the groove 15 is avoided, thereby improving the conversion efficiency of the back contact battery.

[0074] Optionally, the difference in the etching rates of the base on the P-type doped semiconductor portion and the semiconductor substrate is reduced through a one-step etching process, such as reducing the etching rate of the base on the semiconductor substrate and / or increasing the etching rate of the base on the P-type doped semiconductor portion, to cooperatively control the height difference between the surface of the first region and the surface of the second region, and the length of the portion where the P-type doped semiconductor portion is suspended above the groove within the above ranges.

[0075] Exemplarily, the height difference between the surface of the first region and the surface of the second region may be less than or equal to 1.5 μm. In this case, in the back contact battery provided by the embodiment of the present invention, the height difference between the surface of the first region 12 and the surface of the second region 13 is less than or equal to 1.5 μm. At this time, the height difference between the surfaces of the first region 12 and the second region 13 can be controlled within a suitable range, and the length of the portion where the P-type doped semiconductor portion 16 is suspended above the groove 15 is also small, which can prevent the P-type doped semiconductor portion 16 and the N-type doped semiconductor portion 17 from being electrically connected at the portion suspended above the groove 15 and / or through the residues on the isolation region 14 and the inwardly diffused doped region in the isolation region 14, further increasing the effective doping concentration of the N-type doped semiconductor portion pair and promoting the formation of more carriers in the N-type doped semiconductor portion; at the same time, it also ensures that the depth of the portion of the semiconductor substrate 11 corresponding to the first region 12 or the second region 13 etched is relatively shallow, that is, not over-etched, so as to reduce the leakage risk while enabling the portions of the semiconductor substrate 11 corresponding to the first region 12 and the second region 13 to have a wider light absorption wavelength range, improving the light utilization rate of the semiconductor substrate 11. And, it enables the portions of the semiconductor substrate 11 corresponding to the first region 12 and the second region 13 to have a higher resistance to mechanical loads, reducing the risk of problems such as bending and fragmentation of the back contact battery.

[0076] As for the height difference between the isolation region and the first region and the second region respectively, it can be determined according to the anti-leakage requirements between the P-type doped semiconductor portion and the N-type doped semiconductor portion in the actual application scenario and the etching degree requirements of the portion of the semiconductor substrate corresponding to the isolation region, and no specific limitation is made here.

[0077] Exemplarily, as Figure 5 shown, the sum of the height difference between the surface of the first region 12 and the bottom surface of the groove 15 and the height difference between the second region 13 and the bottom surface of the groove 15 can be less than or equal to 20 μm. For example, the sum of the height difference between the surface of the first region 12 and the bottom surface of the groove 15 and the height difference between the second region 13 and the bottom surface of the groove 15 can be 4 μm, 5 μm, 8 μm, 10 μm, 12 μm, 15 μm, 18 μm or 20 μm, etc. In this case, the sum of the height difference between the surface of the first region 12 and the bottom surface of the groove 15 and the height difference between the second region 13 and the bottom surface of the groove 15 is small, which is conducive to reducing the transmission path length corresponding to the carriers bypassing the groove 15 and being collected by the P-type doped semiconductor portion 16 or the N-type doped semiconductor portion 17, reducing the transmission loss, and being conducive to improving the conversion efficiency and component power of the back contact battery. Further, in the case of improving the battery efficiency, if the width of the isolation region 14 is reduced to less than or equal to 100 μm, the influence of the setting size of the above height difference on the transmission of carriers between the P-type doped semiconductor portion and the N-type doped semiconductor portion will become particularly obvious. Therefore, controlling the sum of the above two height differences is conducive to significantly improving the component power.

[0078] It should be noted that when the surface of the groove has a textured structure, the height difference between the surface of the first region and the bottom surface of the groove refers to the height difference between the main surface of the first region (when the surface of the first region is not provided with a textured structure, the main surface of the first region is the entire surface of the first region; when the surface of the first region has at least a first tower-shaped textured structure, the main surface of the first region is the surface corresponding to the top of the first tower-shaped textured structure in the first region) and the bottom of the textured structure on the bottom surface of the groove.

[0079] When the surface of the groove has a textured structure, the height difference between the surface of the second region and the bottom surface of the groove refers to the height difference between the main surface of the second region (when the surface of the second region is not provided with a textured structure, the main surface of the second region is the entire surface of the second region; when the surface of the second region has at least a first tower-shaped textured structure, the main surface of the second region is the surface corresponding to the top of the first tower-shaped textured structure in the second region) and the bottom of the textured structure on the bottom surface of the groove.

[0080] Exemplarily, in the direction from the second surface to the first surface, when the surface of the second region is lower than the surface of the first region, the height difference between the surface of the second region and the bottom surface of the groove may be greater than or equal to 3 μm and less than or equal to 4 μm. It can be understood that after patterning the N-type doped semiconductor portion, it may be necessary to remove the inner diffusion doped region formed at least in the isolation region during the manufacture of the N-type doped semiconductor portion to reduce leakage current. In this case, the height difference between the surface of the second region and the bottom surface of the groove within the above range helps to prevent the inner diffusion doped region from not being completely removed due to the too small height difference, so as to interrupt the leakage path between the P-type doped semiconductor portion and the N-type doped semiconductor portion through the groove in the isolation region. At the same time, it can also prevent the part of the semiconductor substrate corresponding to the isolation region from being over-etched due to the too large height difference, reduce the risk of the battery bending and fragmenting, and improve the ability of the component to resist mechanical load; and it can also reduce the etching effect of the etchant on the N-type doped semiconductor portion located in the second region, which is beneficial to controlling the length of the edge of the N-type doped semiconductor portion retracted inward relative to the edge of the second region to be relatively small, and the ratio tends to be 5%-20%. For example, it increases the passivation contact area between the N-type doped semiconductor portion and the semiconductor substrate, reduces carrier recombination, and is beneficial to more current being exported and utilized. Further, forming a textured surface in the groove can further reduce the doping concentration of the semiconductor substrate at the groove, interrupt the leakage path brought by the N-type doped semiconductor portion and the N-type inner diffusion, and completely eliminate the leakage risk, while the textured surface in the groove can further improve the light utilization rate.

[0081] Optionally, by a one-step etching process, the difference in the etching rates of the base on the N-type doped semiconductor portion and the semiconductor substrate is reduced, such as increasing the etching rate of the base on the semiconductor substrate and / or reducing the etching rate of the base on the N-type doped semiconductor portion, and cooperatively controlling the height difference between the surface of the isolation region and the surface of the second region, and the length of the edge of the N-type doped semiconductor portion retracted inward relative to the edge of the second region within the above range.

[0082] In terms of surface topography, the second surface of the semiconductor substrate can be a flat surface or a textured surface. When the second surface is a textured surface, the light utilization rate of the semiconductor substrate can be improved, and the conversion efficiency of the back contact battery can be improved. The types, distribution and sizes of the textured surface structures of the second surface in the embodiments of the present invention are not specifically limited and can be set according to actual needs.

[0083] As for the surface topography of the first region, the second region and the isolation region in the first surface, it can be determined according to actual needs and the P-type doped semiconductor portion and the N-type doped semiconductor portion respectively provided in the first region and the second region. Exemplarily, the surface of at least one of the first region, the second region and the isolation region can be a flat surface or a textured surface.

[0084] Exemplarily, such as Figure 3and Figure 4 As shown, a first tower base-like texture structure 19 may be provided on the first surface; the first tower base-like texture structure 19 includes a plurality of first sub-structures, and the first tower base-like texture structure 19 is at least distributed in the second region 13. Moreover, the bottom surface of the first sub-structure is recessed into the semiconductor substrate 11 with respect to the surface of the second region 13. In this case, as Figure 3 , Figure 4 and Figure 8 shown, compared with a texture structure with a relatively sharp surface such as a pyramid structure, since the top surface of the first tower base-like texture structure 19 is relatively flat, when the surface of the second region 13 has the first tower base-like texture structure 19, the surface of the second region 13 is macroscopically flat, which is beneficial to improving the formation quality and film thickness of the surface passivation layer 23 formed on the second region 13, and improving the passivation effect of the part of the surface passivation layer 23 corresponding to the second region 13. In addition, when the N-type doped semiconductor portion 17 includes a doped semiconductor layer formed on the second region 13, it is also beneficial to improving the formation quality of the N-type doped semiconductor portion 17, improving the field passivation effect of the N-type doped semiconductor portion 17, and reducing the carrier recombination rate.

[0085] The bottom surface of the first sub-structure included in the first tower base-like texture structure may be a regular or irregular polygonal bottom surface (such as a quadrilateral bottom surface, a pentagonal bottom surface, a hexagonal bottom surface, or an octagonal bottom surface, etc.; the polygon may be a regular polygon with the same side length or a polygon with different side lengths), and the angles of the polygonal bottom surface may be sharp corners or may be rounded corners with a smooth transition; alternatively, the bottom surface of the first sub-structure may also be an irregular bottom surface with an arc-shaped contour.

[0086] As for the size of the first sub-structure included in the first tower base-like texture structure, it can be determined according to the roughness requirement of the surface of the second region and the etching degree requirement of the surface of the second region in the actual application scenario, and no specific limitation is made here.

[0087] Exemplarily, in the first tower base-shaped texture structure, the first sub-structure with a complete bottom surface is defined as the target sub-structure. Based on this, the one-dimensional size of at least one target sub-structure can be greater than or equal to 12 μm and less than or equal to 35 μm. For example: the one-dimensional size of at least one target sub-structure can be 12 μm, 15 μm, 17 μm, 20 μm, 22 μm, 25 μm, 28 μm, 30 μm, 32 μm, 35 μm, etc. In this case, it can be understood that the etchant used in the texturing operation to form the first tower base-shaped texture structure on the second region surface forms the corresponding surface topography by etching at least the part of the semiconductor substrate corresponding to the second region. When the P-type doped semiconductor part is first formed on the first surface, the process of patterning the P-type doped semiconductor part is the above-mentioned process of etching the second region, and it is also the process of forming the height difference between the surfaces of the first region and the second region, and the part of the P-type doped semiconductor part suspended above the groove, that is, the same etching process needs to take into account the etching of the above three aspects in coordination. Based on this, when the one-dimensional size of at least one target sub-structure included in the first tower base-shaped texture structure is within the above range, it is possible to take into account the requirements of the second region surface topography, that is, to prevent the second region surface from being too flat or too rough due to the too large or too small one-dimensional size of the target sub-structure, ensure that the surface passivation layer has a high passivation effect on the second region (that is, when the N-type doped semiconductor part is arranged on the second region, ensure that the surface passivation layer and the N-type doped semiconductor part have a high passivation effect), and make the N-type doped semiconductor part have a suitable contact area with the conductive electrode to improve the contact performance. At the same time, it is also beneficial to prevent the etching degree of the second region surface represented by the too small one-dimensional size of the target sub-structure after patterning the P-type doped semiconductor part by the etchant from being too small, prevent the internal diffusion doping region formed by manufacturing the P-type doped semiconductor part from remaining in the second region, reduce the leakage risk, and be beneficial to improving the carrier collection efficiency of the N-type doped semiconductor part. Secondly, it is also possible to prevent the etching degree of the second region surface represented by the too large size of the target sub-structure from being too large, that is, to prevent the part of the semiconductor substrate corresponding to the second region from being over-etched, and prevent the length of the part of the P-type doped semiconductor part suspended above the groove from being too large. The part of the semiconductor substrate corresponding to the second region has a high anti-mechanical load capacity, reducing the risk of problems such as bending and fragmentation of the back-contact battery. And reduce the leakage risk at the part of the P-type doped semiconductor part suspended above the groove.

[0088] It should be noted that in the actual manufacturing process, the different first sub-structures in the first tower base-shaped texture structure on the second region surface are formed by the same process and simultaneously, so the topography and one-dimensional size of the different first sub-structures on the second region surface are roughly the same (although there may be slight differences, but the degree of difference is small), and as Figure 3 and Figure 4As shown, the different first sub-structures on the surface of the second region 13 may overlap, resulting in different topographies of the areas that can be exposed on the bottom surface of each first sub-structure. Based on this, since the overlapping ratios between different first sub-structures may vary, the surfaces of the exposed areas on the bottom surfaces of the corresponding first sub-structures are also different; while the bottom surface of the target sub-structure in the first tower-shaped texture structure 19 is a complete figure, which does not overlap with other first sub-structures, or although there is overlap, a complete bottom surface contour can be shown. By defining the size of the one-dimensional dimension of the target sub-structure, the surface roughness of the surface of the second region 13 can be accurately regulated, improving the conversion efficiency of the back-contact battery. As for whether the bottom surface of a single first sub-structure in the first tower-shaped texture structure 19 is a complete figure, it can be determined according to the bottom surface topography and one-dimensional dimension of the first sub-structures on the surface of the second region 13.

[0089] For example: As Figure 3 and Figure 4 shown, when the bottom surfaces of most of the first sub-structures among all the first sub-structures on the surface of the second region 13 are quadrilateral in shape, if, on the surface of the second region 13, the bottom surface of a certain first sub-structure is a complete quadrilateral and is recessed into the semiconductor substrate 11, then this first sub-structure is the target sub-structure.

[0090] In addition, the one-dimensional dimension of the first sub-structure can be the side length (length of the bottom arc segment) of the bottom surface of the first sub-structure, the length of the bottom surface diagonal, or the recessed depth (it should be noted that the recessed depth of the first sub-structure is the recessed depth relative to the main surface of the second region).

[0091] Exemplarily, as Figure 3 and Figure 4As shown, when the surface of the second region 13 has the first tower-base-shaped texture structure 19, the surface of the second region 13 may further have a second tower-base-shaped texture structure 20. The second tower-base-shaped texture structure 20 includes a plurality of second sub-structures disposed within the first sub-structure, and the bottom surface of the second sub-structure is recessed into the semiconductor substrate 11 relative to the surface of the first sub-structure. In this case, the second tower-base-shaped texture structure 20 includes a plurality of second sub-structures disposed within the first sub-structure and recessed into the semiconductor substrate 11 relative to the surface of the first sub-structure, such that the surface of the first tower-base-shaped texture structure 19 with a undulating topography is superimposed on the undulating degree of the second tower-base-shaped texture structure 20, which is conducive to increasing the specific surface area of the surface of the second region 13. Additionally, if the N-type doped semiconductor portion 17 is disposed within the second region 13, the surface of the second region 13 is the side surface of the N-type doped semiconductor portion 17 facing away from the semiconductor substrate 11. If the N-type doped semiconductor portion 17 includes a doped semiconductor layer disposed on the second region 13, since the doped semiconductor layer is disposed on the second region 13 through a deposition process, the surface of the doped semiconductor layer on the side facing away from the semiconductor substrate 11 has substantially the same undulation as the surface of the second region 13. Based on this, when the surface of the second region 13 has a large specific surface area, the side of the N-type doped semiconductor portion 17 facing away from the semiconductor substrate 11 also has a large specific surface area, which is conducive to increasing the contact area between the N-type doped semiconductor portion 17 and the conductive electrode and improving the contact performance therebetween. Furthermore, when the N-type doped semiconductor portion 17 includes a doped semiconductor layer disposed on the second region 13, increasing the specific surface area of the surface of the second region 13 can also increase the passivation contact area between the doped semiconductor layer and the second region 13, which is conducive to the shunting and collection of carriers.

[0092] As for the bottom surface topography of the second tower-base-shaped texture structure, it can be described with reference to the bottom surface topography of the first sub-structure described above, which will not be elaborated here. The size and distribution of the second sub-structures included in the second tower-base-shaped texture structure can be determined according to the roughness requirements for the surface of the second region and the etching degree requirements for the surface of the second region in the actual application scenario, and no specific limitation is made here.

[0093] Exemplarily, the one-dimensional dimension of at least one second sub-structure can be greater than or equal to 0.03 times and less than or equal to 0.1 times the one-dimensional dimension of the target sub-structure. In this case, as described above, the etchant used for the texturing operation on the second region surface forms the corresponding surface topography by etching at least the portion of the semiconductor substrate corresponding to the second region. When the P-type doped semiconductor portion is first formed on the first surface, the process of patterning the P-type doped semiconductor portion is the above-mentioned process of etching the second region, and is also the process of forming the height difference between the surfaces of the first region and the second region, and the portion of the P-type doped semiconductor portion suspended above the groove. Therefore, when the one-dimensional dimension of the second sub-structure is within the above range, it is not only beneficial to prevent the second region surface from being too rough microscopically due to too many second sub-structures being provided in the second region surface due to the too small one-dimensional dimension of the second sub-structure, improving the formation quality of the N-type doped semiconductor portion and / or the surface passivation layer, so that the N-type doped semiconductor portion and / or the surface passivation layer have a high passivation effect. Also, it prevents the second region surface from having a too small roughness microscopically due to too few second sub-structures being provided in the second region surface due to the too large one-dimensional dimension of the second sub-structure, which is beneficial to increasing the contact area between the N-type doped semiconductor portion and the electrode, improving the contact performance (or, when the N-type doped semiconductor portion includes a doped semiconductor layer, it is also beneficial to increasing the contact area between the N-type doped semiconductor portion and the semiconductor substrate, which is beneficial to reducing the carrier recombination rate). It can also prevent the etchant from etching the portion of the semiconductor substrate corresponding to the second region too little due to the too small one-dimensional dimension of the second sub-structure, preventing the internal diffusion doping region formed during the manufacture of the P-type doped semiconductor portion from remaining in the second region, reducing the leakage risk, and being beneficial to improving the carrier collection efficiency of the N-type doped semiconductor portion. And, it can also prevent the at least second region surface represented by the too large one-dimensional dimension of the second sub-structure from being etched too much, that is, preventing the portion of the semiconductor substrate corresponding to the second region from being over-etched and preventing the length of the portion of the P-type doped semiconductor portion suspended above the groove from being too large. The portion of the semiconductor substrate corresponding to the second region has a high anti-mechanical load capacity, reducing the risk of problems such as bending and fragmentation of the back-contact battery. And, it reduces the leakage risk at the portion of the P-type doped semiconductor portion suspended above the groove.

[0094] It should be noted that the one-dimensional dimension of the second sub-structure can be the bottom side length (bottom arc segment length), the bottom diagonal length or the recess depth of the second sub-structure (it should be noted that the recess depth of the second sub-structure is the recess depth relative to the bottom surface of the first sub-structure).

[0095] Exemplarily, the number of second sub-structures provided in at least one target sub-structure may be greater than or equal to 10 and less than or equal to 30. For example: the number of second sub-structures provided in at least one target sub-structure may be 10, 12, 15, 18, 20, 22, 25, 28 or 30. The application principle of the beneficial effects in this case may refer to the application principle of the beneficial effects that the one-dimensional size of at least one second sub-structure is greater than or equal to 0.03 times and less than or equal to 0.1 times the one-dimensional size of the target sub-structure described above, which will not be elaborated here.

[0096] Of course, when the surface of the second region has the first tower base-shaped texture structure, the surface of the second region may not have the above-mentioned second tower base-shaped texture structure.

[0097] As for the surface of the first region, exemplarily, the first tower base-shaped texture structure and the second tower base-shaped texture structure may also be distributed on the surface of the first region; at this time, the surface of the first region is relatively flat, which is beneficial to improving the formation quality of the P-type doped semiconductor part.

[0098] In addition, exemplarily, when the surface of the first region also has the first tower base-shaped texture structure and the second tower base-shaped texture structure, the distribution density of the second tower base-shaped texture structure in the first region may be less than the distribution density of the second tower base-shaped texture structure in the second region. In this case, the surface of the first region has a smaller number of second tower base-shaped texture structures, and when the doping concentration of the P-type doped semiconductor part is set in a relatively high numerical range (for example, it can be set to be greater than 6E19 cm -3 ), it can still make the surface of the first region flatter than the surface of the second region. Furthermore, on the basis of improving the contact resistance between the P-type doped semiconductor part and the metal electrode, the formation quality of the P-type doped semiconductor part on the first region can be improved, and the field passivation effect of the P-type doped semiconductor part can be enhanced. At the same time, when the N-type doped semiconductor part includes a doped semiconductor layer, the surface of the second region is provided with a larger number of second tower base-shaped texture structures, which can increase the specific surface area of the second region, and is also beneficial to controlling the formation thickness and uniformity of the doped semiconductor layer included in the N-type doped semiconductor part, reducing the optical parasitic absorption of the doped semiconductor layer, and improving the bifaciality of the back contact battery. It can be seen that the back contact battery provided by the embodiments of the present invention can improve the contact performance of the P-type doped semiconductor part while improving the light utilization rate of the back contact battery.

[0099] Alternatively, the distribution density of the second tower base-shaped texture structure in the first region may also be equal to the distribution density of the second tower base-shaped texture structure in the second region, so as to increase the contact area between the P-type doped semiconductor part and the first region and the electrode respectively, which is beneficial to carrier collection and reduces the transmission loss of carriers.

[0100] The difference in the distribution density of the second tower base-like texture structure between the first region and the second region can be set according to actual requirements and will not be specifically limited here.

[0101] In another example, the first tower base-like texture structure can also be distributed on the surface of the first region, and the second tower base-like texture structure is not provided on the surface of the first region. The application principle of the beneficial effects in this case can refer to the application principle of the beneficial effects that the distribution density of the second tower base-like texture structure in the first region is less than that in the second region described above, and will not be elaborated here.

[0102] Regarding the surface topography of the isolation region, exemplarily, as Figure 5 shown, the surface of the groove 15 can have a matte structure. In this case, to provide a matte structure on the surface of the groove 15, the corresponding part of the semiconductor substrate 11 in the isolation region 14 needs to be further etched with an etchant. At this time, the internal diffusion doping region formed in the isolation region 14 during the manufacture of the P-type doped semiconductor portion 16 (or the P-type doped semiconductor portion 16 and the N-type doped semiconductor portion 17) can be further removed, further reducing the doping concentration in the isolation region 14, which is beneficial to interrupting the leakage path between the P-type doped semiconductor portion 16 and the N-type doped semiconductor portion 17 at the brim position (i.e., the part where the P-type doped semiconductor portion 16 is suspended above the groove 15) through the isolation region 14 and reducing the leakage risk. At the same time, the light trapping effect of the isolation region 14 can also be improved, and the bifaciality of the back contact battery can be increased.

[0103] The embodiments of the present invention do not specifically limit the type, distribution, and size of the matte structure on the surface of the groove, as long as it can be applied to the back contact battery provided by the embodiments of the present invention.

[0104] For the P-type doped semiconductor portion, in terms of materials, the materials of the P-type doped semiconductor portion can include any semiconductor material such as silicon, silicon-germanium, or germanium. In terms of the arrangement form of substances, the crystal phase of the P-type doped semiconductor portion can be amorphous, microcrystalline, nanocrystalline, single crystal, or polycrystalline, etc. Optionally, the P-type doped semiconductor portion can include a P-type doped polysilicon layer.

[0105] In terms of doping, any one of P-type dopants such as boron, aluminum, or gallium can be doped in the P-type doped semiconductor portion. Among them, when boron is doped in the P-type doped semiconductor portion, the presence of the boron doping element causes the conventional alkaline etchant used for patterning the P-type doped semiconductor portion to have a relatively slow etching rate for the P-type doped semiconductor portion, while the etching rate of the conventional alkaline etchant for the semiconductor substrate is relatively fast. This easily leads to a relatively large length of the portion of the P-type doped semiconductor portion suspended above the groove, resulting in a relatively high leakage risk; and causes a relatively large depth of the groove, and the semiconductor substrate is over-etched. In this case, during the manufacturing process of the back-contact battery provided by the embodiments of the present invention, the patterning process of the P-type doped semiconductor portion and the etching operations of the corresponding isolation region and the second region of the semiconductor substrate can be combined into one step, and by adjusting the composition of the alkaline etchant and parameters such as the etching time and the etching temperature, the etching rate of the alkaline etchant for the semiconductor substrate can be slowed down, so that the length of the portion of the P-type doped semiconductor portion suspended above the groove becomes smaller, and the leakage risk is reduced; at the same time, the depth of the groove is relatively small, preventing the corresponding isolation region and the second region of the semiconductor substrate from being over-etched, facilitating the formation of carriers, and reducing the risk of the battery bending and fragmenting problems, and improving the mechanical load resistance of the battery.

[0106] As for the doping concentration of the P-type doped semiconductor portion, it can be set according to actual requirements. Exemplarily, the doping concentration of the P-type doped semiconductor portion can be greater than or equal to 5E19 cm -3 and less than or equal to 1E20 cm -3 . For example: the doping concentration of the P-type doped semiconductor portion can be 5E19 cm -3 , 6E19 cm -3 , 7E19 cm -3 , 8E19 cm -3 , 9E19 cm -3 or 1E20 cm -3 etc. In this case, the optional window of the corresponding doping concentration of the P-type doped semiconductor portion is relatively large, which is beneficial to improving the applicability of the back-contact battery provided by the embodiments of the present invention in different application scenarios. In addition, the doping concentration of the P-type doped semiconductor portion can also be selected to be greater than the conventional (generally the upper limit is 6E19 cm -3) doping concentration to improve the field passivation effect of the P-type doped semiconductor portion and have good contact performance with the conductive electrode, Rs can be reduced to improve FF, increase the wavelength range of light absorption, improve the bending of the battery and reduce the fragmentation rate. At the same time, even if the doping concentration of the P-type doped semiconductor portion is relatively high, in the manufacturing process of the back-contact battery provided by the embodiment of the present invention, by changing the composition of the alkaline etching solution and parameters such as the etching time and etching temperature, on the premise of reducing the etching rate difference between the P-type doped semiconductor portion and the semiconductor substrate, ensure that the length of the portion of the P-type doped semiconductor portion suspended on the groove is small, reducing the risk of leakage; and, the surface height difference between the corresponding first region and the second region of the semiconductor substrate is also relatively small, preventing the portion of the semiconductor substrate corresponding to the isolation region and the second region from being over-etched, reducing the risk of the battery being bent and fragmented, and improving the ability of the component to resist mechanical loads.

[0107] Optionally, the difference in the etching rates of the alkali on the P-type doped semiconductor portion and the semiconductor substrate is reduced through a one-step etching process, such as reducing the etching rate of the alkali on the semiconductor substrate and / or increasing the etching rate of the alkali on the P-type doped semiconductor portion, and cooperatively controlling the height difference between the surface of the first region and the surface of the second region, the doping concentration of the P-type doped semiconductor portion, and the length of the portion of the P-type doped semiconductor portion suspended above the groove within the above ranges.

[0108] As for the thickness of the P-type doped semiconductor portion, it can be set according to actual requirements. Exemplarily, the thickness of the P-type doped semiconductor portion can be greater than or equal to 60 nm and less than or equal to 350 nm. For example, the thickness of the P-type doped semiconductor portion can be 60 nm, 80 nm, 100 nm, 120 nm, 150 nm, 180 nm, 200 nm, 220 nm, 240 nm, 260 nm, 280 nm, 300 nm, 320 nm, or 350 nm, etc. In this case, the P-type doped semiconductor portion has a relatively large thickness, and when the P-type doped semiconductor portion has a relatively large doping concentration, it is beneficial to make the P-type doped semiconductor portion have a high field passivation effect and good contact performance with the conductive electrode. At the same time, although in the back contact battery provided by the embodiments of the present invention, the P-type doped semiconductor portion can have a large doping concentration and a relatively large thickness, increasing the etching difficulty and etching rate corresponding to the P-type doped semiconductor portion, as described above, in the actual manufacturing process, the length of the portion of the P-type doped semiconductor portion suspended on the groove can be made smaller by changing the composition of the alkaline etching solution and the parameter ranges such as the etching time and etching temperature, reducing the leakage risk, and further having a suitable height difference between the surface of the first region 12 and the surface of the second region 13 to interrupt the leakage path. It can be seen that the back contact battery provided by the embodiments of the present invention can take into account the high field passivation effect and contact performance of the P-type doped semiconductor portion, as well as the low leakage risk.

[0109] In terms of the formation position, as Figure 5 shown, the P-type doped semiconductor portion 16 can be directly disposed on the first region 12. Alternatively, as Figure 6 shown, the above-mentioned back contact battery may further include a first interface passivation layer 21 located between the P-type doped semiconductor portion 16 and the semiconductor substrate 11. In this case, the passivation contact structure composed of the first interface passivation layer 21 and the P-type doped semiconductor portion 16 has an excellent interface passivation effect and can realize the selective collection of carriers, reducing the carrier recombination rate of the first region 12 on the first surface of the semiconductor substrate 11 and further improving the photoelectric conversion efficiency of the back contact battery. The material and thickness of the first interface passivation layer 21 can be set according to the material of the P-type doped semiconductor portion 16 and actual requirements, and will not be specifically limited here. For example, when the material of the P-type doped semiconductor portion 16 is doped polysilicon, the first interface passivation layer is a tunneling passivation layer.

[0110] For the N-type doped semiconductor portion, in terms of the setting position, as Figure 2 shown, the N-type doped semiconductor portion 17 may include a doped region disposed in the second region 13; and / or, as Figure 6 shown, the N-type doped semiconductor portion 17 may also include a doped semiconductor layer disposed on the second region 13.

[0111] When the N-type doped semiconductor portion includes a doped semiconductor layer provided on the second region, the material of the doped semiconductor layer included in the N-type doped semiconductor portion may include any one of semiconductor materials such as silicon, silicon-germanium, germanium, or gallium arsenide. In terms of the arrangement form of substances, the crystal phase of the doped semiconductor layer included in the N-type doped semiconductor portion may be amorphous, microcrystalline, nanocrystalline, single crystal, or polycrystalline, etc. Among them, the material of the doped semiconductor layer included in the N-type doped semiconductor portion may be the same as or different from that of the P-type doped semiconductor portion.

[0112] Exemplarily, as Figure 7 and Figure 8 shown, the N-type doped semiconductor portion 17 may include an N-type doped crystalline silicon layer 18 provided on the second region 13. Among them, the material of the N-type doped crystalline silicon layer 18 may be at least one of microcrystalline silicon, nanocrystalline silicon, single crystal silicon, and polycrystalline silicon.

[0113] In addition, when the N-type doped semiconductor portion includes a doped semiconductor layer provided on the second region, as Figure 6 shown, the doped semiconductor layer included in the N-type doped semiconductor portion 17 may be directly provided on the second region 13 of the first surface. Or, as Figure 7 shown, the back contact battery may further include a second interface passivation layer 22 located between the doped semiconductor layer included in the N-type doped semiconductor portion 17 and the semiconductor substrate 11 to improve the passivation effect and achieve selective collection of carriers. The material of the second interface passivation layer 22 may be determined according to the material of the doped semiconductor layer included in the N-type doped semiconductor portion 17, and no specific limitation is made here. For example: when the material of the doped semiconductor layer included in the N-type doped semiconductor portion is doped polysilicon, the second interface passivation layer is a tunneling passivation layer. Another example: when the material of the doped semiconductor layer included in the N-type doped semiconductor portion includes doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon, the second interface passivation layer is an intrinsic amorphous silicon layer, an intrinsic microcrystalline silicon layer, an intrinsic nanocrystalline silicon layer, or a mixed layer of the above three.

[0114] When the back contact battery includes both the first interface passivation layer and the second interface passivation layer, the materials of the first interface passivation layer and the second interface passivation layer may be the same or different.

[0115] When the N-type doped semiconductor portion includes an N-type doped crystalline silicon layer provided on the second region, the thickness of the N-type doped crystalline silicon layer may be set according to actual needs, and no specific limitation is made here.

[0116] Exemplarily, the thickness of the N-type doped crystalline silicon layer included in the N-type doped semiconductor portion can be greater than or equal to 30 nm and less than or equal to 250 nm. For example, the thickness of the N-type doped crystalline silicon layer can be 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 100 nm, 120 nm, 150 nm, 180 nm, 200 nm, 220 nm, 250 nm, etc. With such a setting, on the premise of enabling the N-type doped crystalline silicon layer to have a good passivation effect, it is possible to prevent the light parasitic absorption of itself from being too high due to the excessive thickness of the N-type doped crystalline silicon layer, which is beneficial to improving the conversion efficiency of the back-contact battery.

[0117] In terms of the formation range, as Figure 1 shown, along the direction from the first region 12 to the second region 13, the side wall of the N-type doped crystalline silicon layer 18 can be aligned with the adjacent side walls in the groove 15. At this time, the N-type doped crystalline silicon layer 18 is disposed on the entire second region 13.

[0118] Alternatively, as Figure 7 and Figure 8 shown, along the direction from the first region 12 to the second region 13, the side wall of the N-type doped crystalline silicon layer 18 can also be indented inward relative to the adjacent side walls in the groove 15. It can be understood that when the N-type doped crystalline silicon layer 18 is doped with phosphorus, the presence of the phosphorus doping element causes the alkaline etchant used to pattern the N-type doped crystalline silicon layer 18 to have a relatively fast etching rate for the N-type doped crystalline silicon layer 18, and the etching rate of the alkaline etchant for the semiconductor substrate 11 is relatively slow. Based on this, when the side wall of the N-type doped crystalline silicon layer 18 is indented inward relative to the adjacent side walls in the groove 15, it can be ensured that after patterning the N-type doped crystalline silicon layer 18 with the alkaline etchant, the corresponding part of the semiconductor substrate 11 in the isolation region 14 has a longer etching time, which is beneficial to completely removing the corresponding inner diffusion doping region of the N-type doped crystalline silicon layer 18 formed in the isolation region 14 and reducing the leakage risk.

[0119] As for the distance by which the side wall of the N-type doped crystalline silicon layer indents inward relative to the adjacent side walls in the groove, and the height difference between the bottom of the groove and the surface of the second region, they can be determined according to the requirements for the leakage risk in the actual application scenario and the requirements for the etching degree of the corresponding part of the semiconductor substrate in the isolation region, and no specific limitation is made here.

[0120] Exemplarily, along the direction from the first region to the second region, the distance by which the sidewall of the N-type doped crystalline silicon layer indents inward relative to the adjacent sidewall in the groove can be less than or equal to 100 nm. For example, the distance by which the sidewall of the N-type doped crystalline silicon layer indents inward relative to the adjacent sidewall in the groove can be 1 nm, 10 nm, 20 nm, 40 nm, 60 nm, 80 nm, or 100 nm, etc. As described above, after patterning the N-type doped semiconductor portion, it may be necessary to remove the inwardly diffused doped region formed at least in the isolation region during the manufacture of the N-type doped semiconductor portion to reduce leakage current. In this case, the height difference between the surface of the second region and the bottom surface of the groove is set within a reasonable range (for example, 3 μm and less than or equal to 4 μm). To reduce the leakage current risk and increase the light absorption wavelength range of the N region, the distance by which the sidewall of the N-type doped crystalline silicon layer indents inward relative to the adjacent sidewall in the groove is less than or equal to 100 nm, such that the formation range of the N-type doped crystalline silicon layer on the second region is larger, which is conducive to the N-type doped crystalline silicon layer having a higher field passivation effect, reducing the carrier recombination rate, and facilitating the extraction and utilization of more current.

[0121] Exemplarily, the height difference between the bottom surface of the groove and the surface of the second region can be greater than or equal to 3 μm and less than or equal to 4 μm. For example, the height difference between the bottom surface of the groove and the surface of the second region can be 3 μm, 3.2 μm, 3.4 μm, 3.6 μm, 3.8 μm, or 4 μm, etc. With such a setting, the height difference between the bottom surface of the groove and the surface of the second region is within the above range, which is conducive to preventing the inwardly diffused doped region formed in the isolation region during the manufacture of the N-type doped crystalline silicon layer from not being completely removed due to the too small height difference, resulting in easy conduction and leakage between the P-type doped semiconductor portion and the N-type doped crystalline silicon layer through the inwardly diffused doped region remaining in the isolation region, and further reducing the leakage risk between the two; secondly, it can also prevent the partial etching of the semiconductor substrate in the isolation region from being excessive due to the too large height difference, such that the partial semiconductor substrate in the isolation region has a larger light absorption depth, improving the light utilization rate of the semiconductor substrate; at the same time, it can also enable the partial semiconductor substrate corresponding to the isolation region to have a higher resistance to mechanical load, reducing the risk of problems such as bending and fragmentation of the back contact battery.

[0122] It should be noted that the height difference between the bottom surface of the groove and the surface of the second region being greater than or equal to 3 μm and less than or equal to 4 μm is the height difference between the bottom surface of the groove and the surface of the second region when the surface of the first region is higher than the surface of the second region along the direction from the second surface to the first surface.

[0123] When the surface of the second region is higher than the surface of the first region along the direction from the second surface to the first surface, then the height difference between the bottom surface of the groove and the surface of the first region can be greater than or equal to 3 μm and less than or equal to 4 μm.

[0124] In a second aspect, embodiments of the present invention provide a photovoltaic module comprising: a cell string and an encapsulation layer. The cell string is formed by electrically connecting a plurality of back-contact cells as provided in the first aspect and various implementations thereof. The encapsulation layer covers a surface of the cell string.

[0125] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0126] In the third aspect, the present invention provides a method for manufacturing a back contact battery. Figures 9 to 13 The manufacturing process is described in detail with reference to the cross-sectional view of the operation shown. Specifically, the manufacturing method of the back contact battery includes the following steps:

[0127] First, a semiconductor substrate is provided. The semiconductor substrate includes a first surface and a second surface opposite to each other. The first surface includes a first region and a second region spaced apart from each other, and an isolation region located between the first region and the second region.

[0128] Next, if Figure 9 As shown, a P-type doped semiconductor portion 16 and a mask layer located on a portion of the P-type doped semiconductor portion 16 corresponding to the first region 12 and a portion of the isolation region 14 are formed on the first surface of the semiconductor substrate 11 .

[0129] Next, if Figure 10 As shown, under the protection of a mask layer, an alkaline etching solution containing an etching additive is used to pattern the P-type doped semiconductor portion 16 and etch a portion of the thickness of the semiconductor substrate 11. The etching additive is used to increase the ratio between the etching rate of the alkaline etching solution on the P-type doped crystalline silicon layer and the etching rate of the alkaline etching solution on the semiconductor substrate 11 to be greater than or equal to 0.5 and less than or equal to 1.5. After etching with the alkaline etching solution, the surface of the second region 13 and the surface of the first region 12 are offset along the thickness direction of the semiconductor substrate 11, and the height difference between the surface of the first region 12 and the surface of the second region 13 is less than or equal to 1.5 μm. Furthermore, the remaining P-type doped semiconductor portion 16 is disposed on the first region 12, extending in a direction close to the second region 13 and overhanging the isolation region 14. Along the arrangement direction of the first and second regions 12, 13, the length of the portion of the P-type doped semiconductor portion 16 overhanging the isolation region 14 is less than or equal to 0.2 μm.

[0130] Next, if Figure 11 and Figure 12 As shown, an N-type doped semiconductor portion 17 is formed in or on the second region 13 .

[0131] Next, if Figure 13As shown, the portion of the semiconductor substrate 11 corresponding to the isolation region 14 is etched so that the surface of the isolation region 14 is lower than the surfaces of the first region 12 and the second region 13, forming a groove 15.

[0132] The structure of the back contact battery manufactured by using the manufacturing method provided in the third aspect in the embodiments of the present invention is the same as the structure of the back contact battery manufactured in the first aspect. Therefore, for the beneficial effects of the third aspect and its various implementation manners in the embodiments of the present invention, reference can be made to the analysis of the beneficial effects in the first aspect and its various implementation manners, which will not be elaborated here. In addition, the embodiments of the present invention do not specifically limit the manufacturing sequence of the P-type doped semiconductor portion and the N-type doped semiconductor portion. It may be to first form the P-type doped semiconductor portion and then form the N-type doped semiconductor portion. Alternatively, the manufacturing sequence of the N-type doped semiconductor portion may also be before the P-type doped semiconductor portion.

[0133] In the actual manufacturing process, taking the example of first manufacturing the P-type doped semiconductor portion, the manufacturing process of the back contact battery will be described in detail below:

[0134] Processes such as chemical vapor deposition can be used to first form a first intrinsic silicon layer for manufacturing the P-type doped semiconductor portion on the first surface of the semiconductor substrate. Then, as Figure 9 shown, processes such as diffusion, ion implantation, or dopant source coating can be used to dope the first intrinsic silicon layer to form the P-type doped semiconductor portion 16.

[0135] It should be noted that if the manufactured back contact battery further includes a first interface passivation layer, before forming the first intrinsic silicon layer, processes such as thermal oxidation or chemical vapor deposition can be used to first form the first interface passivation layer on the first surface.

[0136] In addition, if the diffusion process is used to dope the first intrinsic silicon layer, a doped silicon glass layer will also be formed on the side of the P-type doped semiconductor portion facing away from the semiconductor substrate while forming the P-type doped semiconductor portion. In this case, if the mask layer is the doped silicon glass layer, there is no need to additionally use a deposition process to form the mask layer subsequently; processes such as laser heat treatment can be directly used to process the doped silicon glass layer so that the unprocessed part of the doped silicon glass layer forms the mask layer. Or, if the mask layer includes not only the doped silicon glass layer but also other film layers provided on the doped silicon glass layer, after the doping process, a deposition process can be used to form the other film layers included in the mask layer on the doped silicon glass layer, and then processes such as laser etching can be used to pattern the doped silicon glass layer and the film layers thereon to form the mask layer. Or, if the mask layer does not include the doped silicon glass layer, the doped silicon glass layer needs to be removed, and then deposition and etching processes are used in sequence to form the mask layer (such as a silicon nitride layer and / or an aluminum oxide layer, etc.).

[0137] Next, as Figure 10 shown, under the protection of the mask layer, a P-type doped semiconductor portion 16 is patterned using an alkaline etching solution containing an etching additive, and a portion of the semiconductor substrate 11 is etched. It can be understood that the patterning of the P-type doped semiconductor portion 16 and the etching operation of the portion of the semiconductor substrate 11 exposed outside the remaining P-type doped semiconductor portion 16 are carried out in the same step and achieved by the same alkaline etching solution containing an etching additive, which is beneficial to improving the manufacturing efficiency of the back-contact battery.

[0138] The types and concentrations of the base, the types and concentrations of the etching additive, and the etching parameters such as the etching time and etching temperature in the above-mentioned alkaline etching solution containing an etching additive can be determined according to the requirements for the height difference between the surfaces of the first region and the second region in the back-contact battery to be manufactured and the length of the portion of the P-type doped semiconductor portion suspended above the isolation region in the actual application scenario, and no specific limitation is made here.

[0139] Exemplarily, in the alkaline etching solution, the types of the base may include sodium hydroxide and / or potassium hydroxide, etc.

[0140] Exemplarily, in the alkaline etching solution, the volume ratio of the concentration of the base may be 2%.

[0141] Exemplarily, the etching temperature of the alkaline etching solution may be greater than or equal to 70 °C and less than or equal to 75 °C. For example: the etching temperature of the alkaline etching solution may be 70 °C, 71 °C, 72 °C, 73 °C, 74 °C or 75 °C, etc.

[0142] Exemplarily, in the alkaline etching solution, the volume ratio of the concentration of the etching additive may be 0.5%.

[0143] Exemplarily, the etching additive may include: a polishing agent, a first corrosion inhibitor, a cleaning agent, and an antifoaming agent. The first corrosion inhibitor is used to reduce the etching rate of the alkaline etching solution on the semiconductor substrate.

[0144] Among them, the polishing agent is used to enhance the isotropic etching of the alkaline etching solution containing the etching additive on the semiconductor substrate. For example: the polishing agent may include benzotriazole, etc.

[0145] The first corrosion inhibitor is used to reduce the etching rate of the alkaline etching solution on the semiconductor substrate to achieve that the height difference between the surfaces of the first region and the second region in the back-contact battery is less than or equal to 1.5 μm and the length of the portion of the P-type doped semiconductor portion suspended above the isolation region is less than or equal to 0.2 μm. For example: the first corrosion inhibitor may include sodium saccharin, etc.

[0146] As for the specific etching rates of the alkaline etching solution containing the etching additive on the P-type doped semiconductor portion and the semiconductor substrate, they can be determined according to the height difference between the surfaces of the first region and the second region in the back contact battery and the length of the portion of the P-type doped semiconductor portion suspended above the isolation region in the actual application scenario.

[0147] Exemplarily, the etching rate of the alkaline etching solution on the P-type doped crystalline silicon layer can be greater than or equal to 0.0008 μm / s and less than or equal to 0.00177 μm / s. For example: the etching rate of the alkaline etching solution on the P-type doped crystalline silicon layer can be 0.0008 μm / s, 0.0010 μm / s, 0.0012 μm / s, 0.0014 μm / s, 0.0016 μm / s, 0.0017 μm / s or 0.00177 μm / s, etc.

[0148] Exemplarily, the etching rate of the alkaline etching solution on the semiconductor substrate can be greater than or equal to 0.0004 μm / s and less than or equal to 0.002655 μm / s. For example: the etching rate of the alkaline etching solution on the semiconductor substrate can be 0.0004 μm / s, 0.00042 μm / s, 0.00045 μm / s, 0.0005 μm / s, 0.0008 μm / s, 0.001 μm / s, 0.0015 μm / s, 0.002 μm / s or 0.002655 μm / s, etc.

[0149] The above cleaning agent is used to improve the etching and cleaning effects. For example: the cleaning agent can include sodium citrate, etc.

[0150] The above defoaming agent is used to enhance the defoaming effect on the surface of the semiconductor substrate and improve the etching uniformity. For example: the defoaming agent can include siloxanes, etc.

[0151] Wherein, in the case where the mask layer includes a doped silicon glass layer, the etching additive can further include a second inhibitor, and the second inhibitor is used to reduce the etching rate of the alkaline etching solution on the doped silicon glass layer, improve the corrosion resistance of the mask layer, and facilitate improving the accuracy of the patterning process.

[0152] As for the specific etching rate of the alkaline etching solution on the doped silicon glass layer, it can be set according to actual requirements. For example: the ratio between the etching rate of the alkaline etching solution on the doped silicon glass layer and the etching rate of the alkaline etching solution on the P-type doped semiconductor portion can be greater than or equal to 1:35 and less than or equal to 1:40.

[0153] Exemplarily, in the case where the back contact battery further includes a first interface passivation layer and the first interface passivation layer includes a tunneling oxide layer, the alkaline etching solution containing an etching additive is further used to slow down the etching rate of the alkaline etching solution on the tunneling oxide layer, so as to improve the etching uniformity and at the same time facilitate the complete removal of the portion of the P-type doped semiconductor portion located on the second region and the isolation region. In this case, after the P-type doped crystalline silicon layer is patterned, before etching a semiconductor substrate with a certain thickness, the etching rate of the alkaline etching solution containing an etching additive on the tunneling oxide layer can be set according to actual requirements. For example, the ratio between the etching rate of the alkaline etching solution on the tunneling oxide layer and the etching rate of the alkaline etching solution on the P-type doped semiconductor portion can be greater than or equal to 1:35 and less than or equal to 1:40.

[0154] After etching the P-type doped semiconductor portion and the semiconductor substrate, the specific manufacturing process of the N-type doped semiconductor portion can be determined according to the formation position of the N-type doped semiconductor portion.

[0155] If the N-type doped semiconductor portion is a doped region disposed in the second region, then under the masking action of a corresponding mask layer, processes such as ion implantation or diffusion can be used to dope a portion of the semiconductor substrate corresponding to the second region to form the N-type doped semiconductor portion.

[0156] If the N-type doped semiconductor portion includes a doped semiconductor layer disposed on the second region, then a second intrinsic semiconductor layer covering the first surface can be formed by a deposition process. Then, processes such as ion implantation or diffusion are used to dope the second intrinsic semiconductor layer to form the N-type doped semiconductor portion. Then, under the protection of a corresponding mask layer, the N-type doped semiconductor portion is patterned so that the remaining N-type doped semiconductor portion is only located on the second region. [[ID=ll]]

[0157] It should be noted that if the doped semiconductor layer included in the manufactured N-type doped semiconductor portion includes a doped amorphous silicon layer, the N-type doped semiconductor portion can be formed by an in-situ doping method. There is no need to form the N-type doped semiconductor portion by a doping process after forming the first intrinsic semiconductor layer.

[0158] If the manufactured back contact battery further includes a second interface passivation layer, then before forming the N-type doped semiconductor portion, a second interface passivation layer needs to be formed by a deposition process. The patterning operation of the second interface passivation layer can be implemented together with the patterning operation of the N-type doped semiconductor portion, or can be performed before forming the N-type doped semiconductor portion.

[0159] In the above description, no detailed explanations are made for the technical details such as the composition and etching of each layer. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of the required shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as the methods described above. Additionally, although the embodiments are described separately above, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0160] The embodiments of the present invention have been described above. However, these embodiments are only for clearer illustration and not for limiting the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present invention.

Claims

1. A back-contact battery, characterized in that, Comprising: A semiconductor substrate including opposite first and second surfaces; the first surface includes a first region and a second region disposed at intervals, and an isolation region between the first region and the second region; along the direction from the second surface to the first surface, the surface of the isolation region is lower than the surfaces of the first region and the second region to form a groove; the surface of the second region is offset from the surface of the first region in the thickness direction of the semiconductor substrate, and the height difference between the surface of the first region and the surface of the second region is greater than or equal to 1 μm; A P-type doped semiconductor portion disposed on the first region, extending along the direction close to the second region and suspended above the groove; along the arrangement direction of the first region and the second region, the length of the portion of the P-type doped semiconductor portion suspended above the groove is less than or equal to 0.2 μm; An N-type doped semiconductor portion disposed in or on the second region.

2. The back-contact battery according to claim 1, wherein The height difference between the surface of the first region and the surface of the second region is less than or equal to 1.5 μm; And / or, the ratio of the length of the portion of the P-type doped semiconductor portion suspended above the groove to the height difference between the surface of the first region and the surface of the second region is greater than or equal to 0 and less than or equal to 20%.

3. The back-contact battery according to claim 1, wherein The doping concentration of the P-type doped semiconductor part is greater than or equal to 5E19 cm -3 and less than or equal to 1E20 cm -3 ; And / or, the P-type doped semiconductor portion includes a P-type doped polysilicon layer.

4. The back contact battery according to claim 3, characterized in that, The thickness of the P-type doped semiconductor portion is greater than or equal to 60 nm and less than or equal to 350 nm.

5. The back-contact battery according to claim 1, characterized in that, The N-type doped semiconductor portion includes an N-type doped crystalline silicon layer disposed on the second region; Wherein, the thickness of the N-type doped crystalline silicon layer is greater than or equal to 30 nm and less than or equal to 250 nm; and / or, along the direction from the first region to the second region, the distance by which the sidewall of the N-type doped crystalline silicon layer indents inward relative to the adjacent sidewall in the groove is less than or equal to 100 nm; and / or, the height difference between the bottom surface of the groove and the surface of the second region is greater than or equal to 3 μm and less than or equal to 4 μm.

6. The back contact battery according to any one of claims 1 to 5, characterized in that, The first surface has a first tower-base-like texture structure; the first tower-base-like texture structure includes a plurality of first sub-structures, and the bottom surface of the first sub-structure indents into the semiconductor substrate relative to the surface of the second region; the first tower-base-like texture structure is at least distributed on the surface of the second region; In the first tower-base-like texture structure, the first sub-structure with a complete bottom surface is defined as a target sub-structure; the one-dimensional dimension of at least one of the target sub-structures is greater than or equal to 12 μm and less than or equal to 35 μm.

7. The back-contact battery according to claim 6, wherein, The surface of the second region also has a second tower-base-like texture structure; The second tower-base-like texture structure includes a plurality of second sub-structures disposed in the first sub-structure, and the bottom surface of the second sub-structure indents into the semiconductor substrate relative to the surface of the first sub-structure; Wherein, the one-dimensional dimension of at least one of the second sub-structures is greater than or equal to 0.03 times and less than or equal to 0.1 times the one-dimensional dimension of the target sub-structure; and / or, the number of the second sub-structures provided in at least one of the target sub-structures is greater than or equal to 10 and less than or equal to 30.

8. The back-contact battery according to claim 7, characterized in that, The first tower-base-shaped texture structure and the second tower-base-shaped texture structure are also distributed on the surface of the first region, and the distribution density of the second tower-base-shaped texture structure in the first region is less than the distribution density of the second tower-base-shaped texture structure in the second region; Alternatively, the first tower-base-shaped texture structure is also distributed on the surface of the first region, and the second tower-base-shaped texture structure is not provided on the surface of the first region.

9. The back-contact battery according to any one of claims 1 to 5, characterized in that, The surface of the groove has a suede structure; and / or, along the direction from the second surface to the first surface, the surface of the second region is lower than the surface of the first region.

10. The back-contact battery according to any one of claims 1 to 5, characterized in that, Along the direction from the second surface to the first surface, the surface of the second region is lower than the surface of the first region, and the sum of the height difference between the surface of the first region and the bottom surface of the groove and the height difference between the surface of the second region and the bottom surface of the groove is less than or equal to 20 μm.

11. A photovoltaic module, characterized in that, Comprising: a battery string formed by electrically connecting a plurality of back-contact batteries according to any one of claims 1 to 10; and an encapsulation layer covering the surface of the battery string.

Images