Solar cell, preparation method thereof and photovoltaic module

Abstract

The invention discloses a solar cell, a preparation method thereof and a photovoltaic module, the solar cell comprises a silicon wafer, the silicon wafer comprises a first surface and a second surface which are opposite to each other, the first surface and / or the second surface are / is provided with a doped structure and a transparent conductive layer, the transparent conductive layer is provided with an electrode, and the electrode is arranged on the doped structure. The electrode comprises a conductive base layer and a first metal layer, the conductive base layer is in contact with the transparent conductive layer, the first metal layer at least covers the surface of the conductive base layer, and the conductive base layer comprises metal particles and non-metal particles which are not densely distributed. According to the invention, the electrode adopts the shell layer electrode of the conductive base layer and the metal layer, so that the resistivity of the electrode can be effectively reduced, the design of finer grid lines is realized, and the battery efficiency and the assembly power are improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of solar cells, and particularly relates to a solar cell, a preparation method thereof, and a photovoltaic module. Background Art

[0002] A heterojunction cell (HJT) is a hybrid solar cell made of a crystalline silicon wafer and an amorphous silicon thin film, which has many advantages such as a simple preparation process, a low process temperature, a high open-circuit voltage, a high photoelectric conversion efficiency, and a low temperature coefficient. It is one of the most widely used high-efficiency crystalline silicon solar technologies at present.

[0003] Copper electroplated cell grid lines are the ultimate route for silver removal in the existing photovoltaic industry. The copper interconnection technology can effectively reduce the BOM cost of heterojunction cells and improve the competitiveness of heterojunction cell products. However, the existing copper interconnection technology requires semiconductor yellow light area equipment and photosensitive ink for the patterning preparation of electroplating masks. The patterned electroplating mask requires a separate window opening process, and the grid line quality is closely related to the properties of the ink. The cell efficiency and module power are limited by the photosensitive ink.

[0004] Therefore, in view of the above technical problems, it is necessary to provide a solar cell, a preparation method thereof, and a photovoltaic module. Summary of the Invention

[0005] The purpose of the present invention is to provide a heterojunction cell, a preparation method thereof, and a photovoltaic module to obtain a metallization structure with excellent electrical properties and fine grid lines.

[0006] To achieve the above purpose, the technical solutions provided by an embodiment of the present invention are as follows: A solar cell includes a silicon wafer, the silicon wafer includes opposite first and second surfaces, a doping structure and a transparent conductive layer are provided on the first surface and / or the second surface, an electrode is provided on the transparent conductive layer, the electrode includes a conductive base layer and a first metal layer, the conductive base layer is in contact with the transparent conductive layer, the first metal layer covers at least the surface of the conductive base layer, and the conductive base layer includes non-densely distributed metal particles and non-metal particles.

[0007] In one or more embodiments of the present invention, the metal particles include one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, Sn particles; and / or, The non-metal particles include one or more of thermoplastic polymer resin particles, diluent particles, curing agent particles, thickening agent particles, coupling agent particles, organic solvent particles, and the thermoplastic polymer resin particles include one or more of acrylate resin particles and epoxy resin particles.

[0008] In one or more embodiments of the present invention, the volume ratio of metal particles in the conductive base layer is greater than or equal to 3%; and / or, the area ratio of metal particles in the cross-section of the conductive base layer is greater than or equal to 3%.

[0009] In one or more embodiments of the present invention, the volume ratio of metal particles in the conductive base layer is 85% - 95%; and / or, the area ratio of metal particles in the cross-section of the conductive base layer is 85% - 95%.

[0010] In one or more embodiments of the present invention, the maximum distance H1 between the conductive base layer and the surface of the transparent conductive layer facing the conductive base layer and the maximum distance H2 between the first metal layer and the surface of the transparent conductive layer facing the conductive base layer satisfy: 1.15 ≤ H2 / H1 ≤ 1.65 or 1.25 ≤ H2 / H1 ≤ 1.55.

[0011] In one or more embodiments of the present invention, the maximum distance H1 between the conductive base layer and the surface of the transparent conductive layer facing the conductive base layer is 100 nm - 15 μm; and / or, the maximum distance H2 between the first metal layer and the surface of the transparent conductive layer facing the conductive base layer is 116 nm - 30 μm; and / or, the maximum distance H1 between the conductive base layer and the surface of the transparent conductive layer facing the conductive base layer and the maximum distance H2 between the first metal layer and the surface of the transparent conductive layer facing the conductive base layer satisfy: 1.2 μm ≤ H2 - H1 ≤ 5.2 μm or 2 μm ≤ H2 - H1 ≤ 4.4 μm.

[0012] In one or more embodiments of the present invention, the surface of the transparent conductive layer facing the conductive base layer is a flat surface or a pyramidal structure matte surface, the maximum distance H1 is the maximum distance between the conductive base layer and the bottom of the flat surface or the pyramidal structure matte surface, and the maximum distance H2 is the maximum distance between the first metal layer and the bottom of the flat surface or the pyramidal structure matte surface.

[0013] In one or more embodiments of the present invention, the cross-sectional area S1 of the conductive base layer and the cross-sectional area S2 of the first metal layer satisfy: 0.28 ≤ S2 / S1 ≤ 0.95 or 0.46 ≤ S2 / S1 ≤ 0.85.

[0014] In one or more embodiments of the present invention, the cross-sectional area S1 of the conductive base layer is 0.5 μm 2 ~200 μm 2 ; and / or, The cross-sectional area S2 of the first metal layer is 0.25 μm 2 ~200 μm 2 。

[0015] In one or more embodiments of the present invention, the line width L2 of the first metal layer is greater than the line width L1 of the conductive base layer; and / or, The first metal layer extends to cover the surface of the transparent conductive layer.

[0016] In one or more embodiments of the present invention, the line width L1 of the conductive base layer is 5 μm to 20 μm; and / or, The height of the conductive base layer is 50 nm to 10 μm or 2 μm to 10 μm; and / or, The center distance between two adjacent conductive base layers is 1 mm to 5 mm or 2 mm to 3 mm.

[0017] In one or more embodiments of the present invention, the material of the first metal layer is one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, Sn.

[0018] In one or more embodiments of the present invention, the electrode further includes at least one second metal layer located at least outside a part of the first metal layer, and the material of the second metal layer is one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, Sn.

[0019] In one or more embodiments of the present invention, the doping structure includes at least one intrinsic layer and at least one doped layer stacked in sequence on the surface of the silicon wafer; and / or, The thickness of the transparent conductive layer is 15 nm to 150 nm; and / or, The transparent conductive layer is a combination of one or more of ITO, VTTO, IWO, HITO, VTZO, AMTO, TTO.

[0020] The technical solution provided by another embodiment of the present invention is as follows: A method for manufacturing a solar cell, the manufacturing method includes the following steps: Provide a silicon wafer; Form a doping structure and a transparent conductive layer in sequence on the surface of the silicon wafer; Prepare a conductive base layer on the transparent conductive layer, and the conductive base layer includes non-compactly distributed metal particles and non-metal particles; Prepare a first metal layer on the conductive base layer, and the first metal layer at least covers the surface of the conductive base layer.

[0021] In one or more embodiments of the present invention, the conductive base layer is prepared by a screen printing process or a laser transfer process; and / or, The first metal layer is prepared by electroplating or chemical plating.

[0022] In one or more embodiments of the present invention, the preparation method further comprises: At least one second metal layer is formed on the outer side of the first metal layer by using an electroplating or chemical plating process.

[0023] Another embodiment of the present invention provides the following technical solutions: A photovoltaic assembly comprises the above-mentioned solar cell.

[0024] Compared with the prior art, the present invention has the following beneficial effects: The electrode of the present invention adopts a shell electrode with a conductive base layer and a metal layer, which can effectively reduce the resistivity of the electrode and realize a finer grid line design, thereby improving the battery efficiency and component power. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0026] Figure 1 Schematic diagram of the structure of the heterojunction battery in Comparative Example 1 of the present invention; Figure 2 Schematic diagram of the structure of the heterojunction battery in Example 1 of the present invention; Figure 3 for Figure 2 A partial enlarged schematic diagram of point A in the middle; Figures 4a to 4d 1 is a process flow chart of the method for preparing a heterojunction battery in Example 1 of the present invention; Figure 5 Schematic diagram of the structure of the heterojunction battery in Example 2 of the present invention; Figure 6 for Figure 5 A partial enlarged schematic diagram of point B in the middle; Figure 7 Schematic diagram of the structure of the heterojunction battery in Example 3 of the present invention; Figure 8 for Figure 7 A partial enlarged schematic diagram of point C in the middle.

[0027] Description of main reference numerals: 10'-silicon wafer, 21'-first intrinsic layer, 22'-second intrinsic layer, 31'-first doped layer, 32'-second doped layer, 41'-first transparent conductive layer, 42'-second transparent conductive layer, 61'-first electrode, 62'-second electrode; 10-silicon wafer, 21-first intrinsic layer, 22-second intrinsic layer, 31-first doped layer, 32-second doped layer, 41-first transparent conductive layer, 42-second transparent conductive layer, 61-first electrode, 611-conductive base layer, 612-first metal layer, 613-second metal layer, 62-second electrode. Detailed implementation mode

[0028] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0029] In the present invention, unless otherwise clearly defined and limited, the first feature being "on" or "under" the second feature may be that the first and second features are in direct contact, or the first and second features are indirectly in contact through an intermediate medium. Moreover, the first feature being "above", "over" and "on" the second feature may be that the first feature is directly above or obliquely above the second feature, or merely indicates that the first feature has a higher horizontal height than the second feature. The first feature being "under", "beneath" and "under" the second feature may be that the first feature is directly below or obliquely below the second feature, or merely indicates that the first feature has a lower horizontal height than the second feature.

[0030] A solar cell includes a silicon wafer, the silicon wafer includes opposite first and second surfaces, a doping structure and a transparent conductive layer are provided on the first surface and / or the second surface, an electrode is provided on the transparent conductive layer, the electrode includes a conductive base layer and a first metal layer, the conductive base layer is in contact with the transparent conductive layer, the first metal layer at least covers the surface of the conductive base layer, and the conductive base layer includes non-densely distributed metal particles and non-metal particles.

[0031] The present invention also discloses a preparation method of a heterojunction cell, including the following steps: Provide a silicon wafer; Form a doping structure and a transparent conductive layer on the surface of the silicon wafer in sequence; Prepare a conductive base layer on the transparent conductive layer, and the conductive base layer includes non-densely distributed metal particles and non-metal particles; A first metal layer is prepared on a conductive base layer, and the first metal layer covers at least the surface of the conductive base layer.

[0032] Preferably, the maximum distance H1 between the conductive base layer and the surface of the transparent conductive layer facing the conductive base layer and the maximum distance H2 between the first metal layer and the surface of the transparent conductive layer facing the conductive base layer satisfy: 1.15 ≤ H2 / H1 ≤ 1.65, more preferably 1.25 ≤ H2 / H1 ≤ 1.55.

[0033] Preferably, the cross-sectional area S1 of the conductive base layer and the cross-sectional area S2 of the first metal layer satisfy: 0.28 ≤ S2 / S1 ≤ 0.95, more preferably 0.46 ≤ S2 / S1 ≤ 0.85.

[0034] In addition, the present invention also discloses a photovoltaic module, including the above-mentioned solar cell.

[0035] The electrode of the present invention adopts a shell electrode of a conductive base layer and a metal layer, which can effectively reduce the resistivity of the electrode, realize a finer grid line design, thereby improving the cell efficiency and module power; at the same time, expensive photosensitive ink is not required, and the process cost is greatly reduced.

[0036] Furthermore, by optimizing the height and cross-sectional area of the conductive base layer and the first metal layer, the present invention can effectively improve the cell efficiency.

[0037] The following further illustrates the present invention with specific examples.

[0038] Comparative Example 1: Refer Figure 1 The following shows a schematic structural diagram of the heterojunction cell in this comparative example. The heterojunction cell includes: A silicon wafer 10', which includes a front surface (i.e., the light-receiving surface) and a back surface (i.e., the light-shielding surface) arranged opposite to each other; A first intrinsic layer 21', a first doped layer 31' and a first transparent conductive layer 41' stacked in sequence on the front surface; A second intrinsic layer 22', a second doped layer 32' and a second transparent conductive layer 42' stacked in sequence on the back surface; A first electrode 61', which is in contact with the first transparent conductive layer 41'; A second electrode 62', which is in contact with the second transparent conductive layer 42'.

[0039] Exemplarily, the silicon wafer 10’ is N-type doped; the first intrinsic layer 21’ is an intrinsic amorphous silicon layer or an intrinsic microcrystalline silicon layer, and the first doped layer 31’ is an N-type doped amorphous silicon layer or microcrystalline silicon layer; the second intrinsic layer 22’ is an intrinsic amorphous silicon layer or an intrinsic microcrystalline silicon layer, and the second doped layer 32’ is a P-type doped amorphous silicon layer or microcrystalline silicon layer; the first transparent conductive layer 41’ and the second transparent conductive layer 42’ can be one or a combination of transparent conductive layers such as ITO, VTTO, IWO, HITO, VTZO, AMTO, TTO, etc.; the first electrode 61’ and the second electrode 62’ are both grid line electrodes.

[0040] Example 1: Refer Figure 2 And in combination with Figure 3 As shown, the solar cell in this embodiment is a heterojunction cell, which includes: A silicon wafer 10, which includes a front side (i.e., the light-receiving side) and a back side (i.e., the backlight side) that are oppositely arranged, and the front side and the back side respectively include a metal region and a non-metal region; The first intrinsic layer 21, the first doped layer 31, and the first transparent conductive layer 41 that are sequentially stacked on the front side; The second intrinsic layer 22, the second doped layer 32, and the second transparent conductive layer 42 that are sequentially stacked on the back side; The first electrode 61, the first electrode 61 is located in the metal region on the front side of the silicon wafer 10 and is spaced apart along the first direction (X direction), and it includes a conductive base layer 611 and a first metal layer 612. The conductive base layer 611 is in contact with the first transparent conductive layer 41, and the first metal layer 612 covers the surface of the conductive base layer 611 and extends to cover the surface of the first transparent conductive layer 41.

[0041] The second electrode 62, the structure of the second electrode 62 is exactly the same as that of the first electrode 61, and will not be elaborated here.

[0042] In this embodiment, the silicon wafer 10 is an N-type single-crystal silicon wafer, with a resistivity of 0.5 Ω·m to 3 Ω·m, a thickness of 90 μm to 120 μm, a size of 210 mm, and both the front side and the back side of the silicon wafer 10 are polished surfaces.

[0043] In this embodiment, the first intrinsic layer 21 and the second intrinsic layer 22 are intrinsic amorphous silicon layers or intrinsic microcrystalline silicon layers, the first doped layer 31 is an N-type doped (such as phosphorus doped) amorphous silicon layer or microcrystalline silicon layer, and the second doped layer 32 is a P-type doped (such as boron doped) amorphous silicon layer or microcrystalline silicon layer.

[0044] In this embodiment, the first transparent conductive layer 41 and the second transparent conductive layer 42 can be one or a combination of transparent conductive layers such as ITO, VTTO, IWO, HITO, VTZO, AMTO, TTO, etc., preferably an ITO transparent conductive layer, with a thickness of 15 nm to 150 nm, preferably 50 nm.

[0045] The silicon wafer, the intrinsic layer, the doped layer, and the transparent conductive layer in this embodiment are exactly the same as those in Comparative Example 1 and will not be elaborated here. Different from Comparative Example 1, the structures of the first electrode 61 and the second electrode 62 in this embodiment are different from those in Comparative Example 1.

[0046] The second electrode 62 is exactly the same as the first electrode 61. Refer Figure 2 and in combination with Figure 3 as shown, the first electrode 61 on the front side of the silicon wafer will be described in detail below as an example.

[0047] The first electrode 61 in the present invention adopts a shell electrode of a conductive base layer and a first metal layer (such as a metal plating layer), which can effectively reduce the resistivity of the electrode and has electrical advantages compared with the existing slurry system batteries. The first electrode 61 is a grid line electrode. When the size of the silicon wafer is 210 mm, the number of grid line electrodes is preferably 70 to 90.

[0048] Specifically, the conductive base layer 611 in the first electrode 61 is in direct contact with the first transparent conductive layer 41. The line width L1 of the conductive base layer 611 is the width of the conductive base layer 611 along the first direction (X direction), and its value is 5 μm to 20 μm, and the height along the second direction (Z direction) is 50 nm to 10 μm, preferably 2 μm to 10 μm. The center distance between two adjacent conductive base layers 611 is 1 mm to 5 mm, preferably 2 mm to 3 mm.

[0049] The conductive base layer 611 in the first electrode 61 in the present invention is a non-dense structure, which is prepared by screen printing process or laser transfer printing (PTP) process. A relatively inexpensive and simple deposition process can be used to prepare a patterned conductive base layer with a micron-level height.

[0050] Specifically, the conductive base layer 611 includes non-densely distributed metal particles and non-metal particles, which can also be called metal particles or non-metal particles. The metal particles include one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, Sn particles, etc. The non-metal particles include one or more of thermoplastic polymer resin particles, diluent particles, curing agent particles, thickening agent particles, coupling agent particles, organic solvent particles, etc. Among them, the thermoplastic polymer resin particles include one or more of acrylate resin particles, epoxy resin particles, etc. The conductive base layer 611 can be prepared from electrode paste, and the electrode paste is a mixture of metal materials and non-metal materials, and a non-dense structure can be formed after drying.

[0051] Preferably, the volume ratio of metal particles in the conductive base layer 611 of this embodiment is greater than or equal to 3%. When the metal particles and non-metal particles are evenly distributed, that is, the area ratio of metal particles in the cross-section of the conductive base layer 611 is greater than or equal to 3%.

[0052] More preferably, the conductive base layer 611 can be prepared using conventional electrode paste. After the electrode paste is dried, the volume ratio of metal particles in the conductive base layer 611 is 85% - 95%. When the metal particles and non-metal particles are evenly distributed, that is, the area ratio of metal particles in the cross-section of the conductive base layer 611 is 85% - 95%.

[0053] In addition, the first metal layer 612 in the first electrode 61 covers the surface of the conductive base layer 611 and extends to cover the surface of the first transparent conductive layer 41. Without preparing a dielectric layer and without opening a window in the dielectric layer, electrical contact between the first metal layer 612 and the conductive base layer 611 can be achieved. The line width L2 of the first metal layer 612, that is, the width of the first metal layer 612 along the first direction (X direction), is greater than the line width L1 of the conductive base layer 611, and full coverage of the conductive base layer 611 can be achieved.

[0054] The material of the first metal layer 612 is one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, Sn, etc. It is prepared using electroplating or electroless plating processes, preferably the electroplating process.

[0055] Refer Figure 3 As shown, the surface of the silicon wafer 10 is a polished surface (i.e., a flat surface), and the surface of the first transparent conductive layer 41 facing away from the silicon wafer is a flat surface. The maximum distance between the conductive base layer 611 and the surface of the first transparent conductive layer 41 facing the conductive base layer 611 is H1, that is, the height of the top of the conductive base layer 611 from the front surface (flat surface) of the first transparent conductive layer 41 in the second direction (Z direction); the maximum distance between the first metal layer 612 and the surface of the first transparent conductive layer 41 facing the conductive base layer 611 is H2, that is, the height of the top of the first metal layer 612 from the front surface (flat surface) of the first transparent conductive layer 41 in the second direction (Z direction).

[0056] In the present invention, H1 and H2 satisfy: 1.15 ≤ H2 / H1 ≤ 1.65, preferably: 1.25 ≤ H2 / H1 ≤ 1.55; where H1 is 100 nm - 15 μm and H2 is 116 nm - 30 μm.

[0057] In addition, H1 and H2 further satisfy: 1.2 μm ≤ H2 - H1 ≤ 5.2 μm, preferably: 2 μm ≤ H2 - H1 ≤ 4.4 μm.

[0058] Continue to refer to Figure 3As shown, the cross-sectional area S1 of the conductive base layer 611 is the cross-sectional area of the conductive base layer 611 in the plane perpendicular to the extension direction of the conductive base layer 611, and the cross-sectional area S2 of the first metal layer 612 is the cross-sectional area of the first metal layer 612 in the plane perpendicular to the extension direction of the first metal layer 612.

[0059] In the present invention, S1 and S2 satisfy: 0.28 ≤ S2 / S1 ≤ 0.95, preferably: 0.46 ≤ S2 / S1 ≤ 0.85; wherein, S1 is 0.5 μm 2 ~200 μm 2 , and S2 is 0.25 μm 2 ~200 μm 2 .

[0060] In this embodiment, the outer surfaces of the conductive base layer 611 and the first metal layer 612 away from the silicon wafer 10 are both curved surfaces. The cross-section of the conductive base layer 611 is generally semicircular. The distance between the conductive base layer and the front surface of the first transparent conductive layer gradually decreases from the middle to both sides. In other embodiments, the cross-section of the conductive base layer can also be rectangular, triangular, trapezoidal, etc. The outer surfaces of the conductive base layer 611 and the first metal layer 612 can be curved surfaces, flat surfaces or combinations thereof, or can be irregular surfaces, and no further examples will be given here for illustration.

[0061] The above has described in detail the first electrode 61 on the front side of the silicon wafer in this embodiment. The second electrode 62 on the back side of the silicon wafer is exactly the same as the first electrode 61 on the front side of the silicon wafer, and no further description will be given here.

[0062] The preparation method of the solar cell in this embodiment is specifically as follows: 1. Refer Figure 4a to the figure, and provide a silicon wafer.

[0063] The silicon wafer 10 in this embodiment is an N-type single-crystalline silicon wafer with a resistivity of 0.5 Ω·m to 3 Ω·m, a thickness of 90 μm to 120 μm, and a size of 210 mm. The front and back sides of the silicon wafer 10 are both polished with a polishing liquid to form polished surfaces.

[0064] 2. Refer Figure 4b to the figure, and sequentially form a first intrinsic layer 21, a first doped layer 31, and a first transparent conductive layer 41 on the front side of the silicon wafer 10, and sequentially form a second intrinsic layer 22, a second doped layer 32, and a second transparent conductive layer 42 on the back side of the silicon wafer 10.

[0065] Preferably, in this embodiment, the intrinsic layer and the doped layer are deposited by plasma enhanced chemical vapor deposition (PECVD) process, and the transparent conductive layer is deposited by reactive plasma deposition (RPD) process or magnetron sputtering process. Specifically as follows: First, introduce SiH4 (silane) gas into the vacuum chamber, and form an intrinsic amorphous silicon layer on the entire front area of the silicon wafer 10 through the PECVD process. Then, introduce SiH4 gas, H2 gas, and PH3 (phosphine) gas into the vacuum chamber, and form an N-type doped amorphous silicon layer on the intrinsic amorphous silicon layer through the PECVD process; Then turn it over, change the tray, introduce SiH4 (silane) gas into the vacuum chamber, and form an intrinsic amorphous silicon layer on the entire back area of the silicon wafer 10 through the PECVD process. Then, introduce SiH4 gas, H2 gas, and B2H6 (diborane) gas into the vacuum chamber, and form a P-type doped amorphous silicon layer on the intrinsic amorphous silicon layer through the PECVD process; Finally, on the N-type doped amorphous silicon layer and the P-type doped amorphous silicon layer, perform film coating using the reactive plasma deposition (RPD) process or the magnetron sputtering process; the back is shielded at the edge through the carrier plate design (shielded through a mask), the specific shielding area around is 0.5 mm to 0.8 mm, the transparent conductive layer is ITO (99.5%:0.5%) wt, the thickness is 50 nm, and the carrier concentration is 2E20 cm -3 ~3.5E20 cm -3 , and the mobility is 70 cm 2 / Vs~100 cm 2 / Vs.

[0066] In this embodiment, the carrier concentration of the first transparent conductive layer 41 and the second transparent conductive layer 42 is 2E20 cm -3 ~3.5E20 cm -3 , preferably 3E20 cm -3 , the mobility is 70 cm 2 / Vs~100 cm 2 / Vs, preferably 80 cm 2 / Vs, the contact resistivity is 0.8 mΩ·cm 2~ 4 mΩ·cm 2 , preferably 2 mΩ·cm 2 , and the refractive index is 2.0~2.1.

[0067] 3. Refer Figure 4c As shown, prepare a conductive base layer on the transparent conductive layer.

[0068] Specifically, a patterned conductive base layer is prepared by screen printing or laser transfer printing (PTP) process. The line width L1 is 5 μm to 20 μm, and the height is 50 nm to 10 μm, preferably 2 μm to 10 μm. A low-temperature electrode paste is used. The electrode paste is a mixture of a metal material and a non-metal material. The metal materials in the electrode paste include one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, Sn, etc. The non-metal materials include one or more of thermoplastic polymer resins, diluents, curing agents, thickeners, coupling agents, organic solvents, etc. The thermoplastic polymer resins include acrylate resins, epoxy resins, etc.

[0069] Then, sintering and curing are carried out at 150 °C to 220 °C to form a good ohmic contact. In this embodiment, the volume ratio of metal particles in the cured conductive base layer is about 90%.

[0070] 4. Refer Figure 4d As shown, a first metal layer is prepared on the conductive base layer.

[0071] Specifically, a patterned first metal layer is prepared on the conductive base layer by electroplating or electroless plating process. The line width L2 of the first metal layer is greater than the line width L1 of the conductive base layer. The material is one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, Sn, etc. The prepared first metal layer can achieve full coverage of the conductive base layer.

[0072] Exemplarily, taking electroplated copper as the first metal layer, the electroplated copper solution includes copper sulfate, sulfuric acid, copper balls, and additives that can optimize the crystal structure of the copper layer. The concentration of Cu 2+ in the electroplated copper solution is 50 g / L, and the concentration of sulfuric acid is 40 g / L.

[0073] 5. Finally, the heterojunction battery is alkali-washed, and the prepared heterojunction battery is subjected to light injection treatment. The temperature of the light injection treatment is 210 °C, and the time of the light injection treatment is 90 s.

[0074] Example 2: Refer Figure 5 And in combination with Figure 6 As shown, the solar cell in this embodiment is a heterojunction battery, and its structure and preparation method are basically the same as those in Example 1. The difference is that the front and back surfaces of the silicon wafer 10 in Example 1 are both polished surfaces, while in this embodiment, they are pyramid-structured matte surfaces.

[0075] The silicon wafer 10 in this embodiment is subjected to double-sided texturing by an alkali texturing process before depositing the intrinsic layer. Specifically: The surface oxide layer is removed using an HF solution with a mass fraction of 1% - 4%. Solutions such as KOH or NaOH with a mass fraction of 1% - 3% are used, and anisotropic etching of single-crystalline silicon is employed to form a pyramidal texture on the silicon wafer surface. Preferably, the size of the pyramidal structure is preferably 0.5 μm - 5 μm.

[0076] As shown Figure 6 in FIG. 5, the surface of the first transparent conductive layer 41 deposited on the surface of the silicon wafer 10 is a pyramidal texture.

[0077] The maximum distance between the conductive base layer 611 and the surface of the first transparent conductive layer 41 facing the conductive base layer 611 is H1, that is, the height from the top of the conductive base layer 611 to the bottom of the pyramidal texture of the first transparent conductive layer 41; the maximum distance between the first metal layer 612 and the surface of the first transparent conductive layer 41 facing the conductive base layer 611 is H2, that is, the height from the top of the first metal layer 612 to the bottom of the pyramidal texture of the first transparent conductive layer 41.

[0078] Example 3: As shown Figure 7 and in combination with Figure 8 FIG. 6, the solar cell in this example is a heterojunction cell, and its structure and preparation method are basically the same as those in Example 1. The difference is that in addition to the conductive base layer 611 and the first metal layer 612, the heterojunction cell in this example further includes at least one second metal layer 613 outside the first metal layer 612.

[0079] Specifically, a patterned second metal layer 613 is prepared on the outside of the first metal layer 612 by electroplating or electroless plating. The line width L3 of the second metal layer 613, that is, the width of the second metal layer 613 along the first direction (X direction), is greater than the line width L2 of the first metal layer 612, and the material is one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, Sn, etc.

[0080] Exemplarily, taking electroplated tin as an example for the second metal layer, the electroplated tin solution includes stannous methanesulfonate and a tin plating additive, and the concentration of Sn 2+ in the electroplated tin solution is 30 g / L, and the concentration of stannous methanesulfonate is 200 g / L.

[0081] IV performance tests were conducted on different heterojunction cells, and the test data are as follows in the table:

[0082]

[0083] Among them, Control Group 1 is the heterojunction cell in Comparative Example 1, and the grid line electrodes on the front and back are both prepared by screen printing with low-temperature silver paste. The grid line width is 25 μm, and the number is 60. Experimental groups 1 to 5 are the heterojunction batteries in Example 1, and the number of grid electrodes on the front and back is 80. It can be seen that compared with Control Group 1, Experimental groups 1 to 5 can fabricate finer grid electrodes with smaller line widths and spacings.

[0084] Through physical bonding and chemical adsorption, the conductive base layer can enhance the adhesion between the subsequent metal layer and the transparent conductive layer, reduce the contact resistivity, and the metal layer can replace the low-temperature silver paste.

[0085] Since the linear resistivity of the metal layer is significantly better than that of the conductive base layer, the larger the height ratio H2 / H1 and cross-sectional area ratio S2 / S1 of the conductive base layer and the metal layer, the more effectively the series resistance Rs can be reduced and the fill factor FF can be improved. However, with the increase of the height ratio H2 / H1 and cross-sectional area ratio S2 / S1, the lateral light enhancement will increase, resulting in a decrease in the short-circuit current Isc. By optimizing the height ratio H2 / H1 and cross-sectional area ratio S2 / S1 of the conductive base layer and the metal layer, within the range of 1.15 ≤ H2 / H1 ≤ 1.65 and 0.28 ≤ S2 / S1 ≤ 0.95, the battery efficiency Eta can be effectively improved. Especially within the range of 1.25 ≤ H2 / H1 ≤ 1.55 and 0.46 ≤ S2 / S1 ≤ 0.85, the battery efficiency Eta can be increased by 0.06% - 0.08%.

[0086] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or basic characteristics of the present invention. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the present invention. Any reference signs in the claims should not be regarded as limiting the claims involved.

[0087] In addition, it should be understood that although this specification is described according to embodiments, not every embodiment only contains an independent technical solution. This narrative way of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A solar cell, characterized in that, It includes a silicon wafer, the silicon wafer includes opposite first and second surfaces, a doping structure and a transparent conductive layer are provided on the first surface and / or the second surface, an electrode is provided on the transparent conductive layer, the electrode includes a conductive base layer and a first metal layer, the conductive base layer is in contact with the transparent conductive layer, the first metal layer covers at least the surface of the conductive base layer, and the conductive base layer includes non-densely distributed metal particles and non-metal particles.

2. The solar cell according to claim 1, characterized in that, The metal particles include one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, Sn particles; and / or, The non-metal particles include one or more of thermoplastic polymer resin particles, diluent particles, curing agent particles, thickener particles, coupling agent particles, organic solvent particles, and the thermoplastic polymer resin particles include one or more of acrylate resin particles and epoxy resin particles.

3. The solar cell according to claim 1, wherein The volume ratio of the metal particles in the conductive base layer is greater than or equal to 3%; and / or, The area ratio of the metal particles in the cross-section of the conductive base layer is greater than or equal to 3%.

4. The solar cell according to claim 1, characterized in that, The volume ratio of the metal particles in the conductive base layer is 85% - 95%; and / or, The area ratio of the metal particles in the cross-section of the conductive base layer is 85% - 95%.

5. The solar cell according to claim 1, characterized in that, The maximum distance H1 between the conductive base layer and the surface of the transparent conductive layer facing the conductive base layer and the maximum distance H2 between the first metal layer and the surface of the transparent conductive layer facing the conductive base layer satisfy: 1.15 ≤ H2 / H1 ≤ 1.65 or 1.25 ≤ H2 / H1 ≤ 1.

55.

6. The solar cell according to claim 1, wherein The maximum distance H1 between the conductive base layer and the surface of the transparent conductive layer facing the conductive base layer is 100 nm - 15 μm; and / or, The maximum distance H2 between the first metal layer and the surface of the transparent conductive layer facing the conductive base layer is 116 nm - 30 μm; and / or, The maximum distance H1 between the conductive base layer and the surface of the transparent conductive layer facing the conductive base layer and the maximum distance H2 between the first metal layer and the surface of the transparent conductive layer facing the conductive base layer satisfy: 1.2 μm ≤ H2 - H1 ≤ 5.2 μm or 2 μm ≤ H2 - H1 ≤ 4.4 μm.

7. The solar cell according to claim 5 or 6, characterized in that, The surface of the transparent conductive layer facing the conductive base layer is a plane or a pyramidal structure matte surface, the maximum distance H1 is the maximum distance between the conductive base layer and the bottom of the plane or the pyramidal structure matte surface, and the maximum distance H2 is the maximum distance between the first metal layer and the bottom of the plane or the pyramidal structure matte surface.

8. The solar cell according to claim 1, wherein The cross-sectional area S1 of the conductive base layer and the cross-sectional area S2 of the first metal layer satisfy: 0.28 ≤ S2 / S1 ≤ 0.95 or 0.46 ≤ S2 / S1 ≤ 0.

85.

9. The solar cell according to claim 1, wherein The cross-sectional area S1 of the conductive base layer is 0.5 μm 2 ~200 μm 2 ; and / or, The cross-sectional area S2 of the first metal layer is 0.25 μm 2 ~200 μm 2 .

10. The solar cell according to claim 1, characterized in that, The line width L2 of the first metal layer is greater than the line width L1 of the conductive base layer; and / or, [[ID= 11. The solar cell according to claim 1, characterized in that, ​ The height of the conductive base layer is 50 nm to 10 μm or 2 μm to 10 μm; and / or, The center distance between two adjacent conductive base layers is 1 mm to 5 mm or 2 mm to 3 mm.

12. The solar cell according to claim 1, wherein The material of the first metal layer is one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, Sn.

13. The solar cell according to claim 12, characterized in that, The electrode further includes at least one second metal layer located at least outside a part of the first metal layer, and the material of the second metal layer is one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, Sn.

14. The solar cell according to claim 1, characterized in that, The doping structure includes at least one intrinsic layer and at least one doping layer stacked in sequence on the surface of the silicon wafer; and / or, The thickness of the transparent conductive layer is 15 nm to 150 nm; and / or, The transparent conductive layer is a combination of one or more of ITO, VTTO, IWO, HITO, VTZO, AMTO, TTO.

15. A method for preparing a solar cell, characterized in that, The preparation method includes the following steps: Provide a silicon wafer; Form a doping structure and a transparent conductive layer in sequence on the surface of the silicon wafer; Prepare a conductive base layer on the transparent conductive layer, and the conductive base layer includes non-densely distributed metal particles and non-metal particles; Prepare a first metal layer on the conductive base layer, and the first metal layer covers at least the surface of the conductive base layer.

16. The preparation method according to claim 15, wherein The conductive base layer is prepared by screen printing process or laser transfer printing process; and / or, The first metal layer is prepared by electroplating or electroless plating process.

17. The preparation method according to claim 15, characterized in that, The preparation method further includes: Prepare at least one second metal layer outside the first metal layer by electroplating or electroless plating process.

18. A photovoltaic module, characterized in that, The photovoltaic module includes the solar cell according to any one of claims 1 to 14 or the solar cell prepared by the preparation method according to any one of claims 15 to 17.

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