Solar cell, preparation method thereof and photovoltaic module

Abstract

The invention discloses a solar cell, a preparation method thereof and a photovoltaic module, the solar cell comprises a silicon wafer, the silicon wafer comprises a first surface and a second surface which are opposite to each other, the first surface and / or the second surface are / is provided with a doped structure and a transparent conductive layer, the transparent conductive layer is provided with a dielectric layer and an electrode, and the dielectric layer and the electrode are arranged on the silicon wafer. The electrode comprises a conductive base layer and a first metal layer, the conductive base layer is in contact with the transparent conductive layer, the dielectric layer covers the transparent conductive layer and the conductive base layer, and the dielectric layer discontinuously covers the surface of the conductive base layer and continuously covers the surface of the transparent conductive layer. And the first metal layer at least covers the dielectric layer on the surface of the conductive base layer. According to the invention, by introducing the dielectric layer, a finer grid line design can be realized, so that the cell efficiency and the module power are improved; meanwhile, expensive photosensitive ink does not need to be adopted, so that the process cost is greatly reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of solar cells, and particularly relates to a solar cell, a preparation method thereof, and a photovoltaic module. Background Art

[0002] A heterojunction cell (HJT) is a hybrid solar cell made of a crystalline silicon wafer and an amorphous silicon thin film, which has many advantages such as a simple preparation process, a low process temperature, a high open-circuit voltage, a high photoelectric conversion efficiency, and a low temperature coefficient. It is one of the most widely used high-efficiency crystalline silicon solar technologies at present.

[0003] Copper electroplated cell grid lines are the ultimate route for silver removal in the existing photovoltaic industry. The copper interconnection technology can effectively reduce the BOM cost of heterojunction cells and improve the competitiveness of heterojunction cell products. However, the existing copper interconnection technology requires semiconductor yellow light area equipment and photosensitive ink for the patterning preparation of electroplating masks. The patterned electroplating mask requires a separate window opening process, and the grid line quality is closely related to the properties of the ink. The cell efficiency and module power are limited by the photosensitive ink.

[0004] Therefore, in view of the above technical problems, it is necessary to provide a solar cell, a preparation method thereof, and a photovoltaic module. Summary of the Invention

[0005] The purpose of the present invention is to provide a heterojunction cell, a preparation method thereof, and a photovoltaic module to obtain a metallization structure with excellent electrical properties and fine grid lines.

[0006] To achieve the above purpose, the technical solution provided by an embodiment of the present invention is as follows: A solar cell includes a silicon wafer, the silicon wafer includes opposite first and second surfaces, a doping structure and a transparent conductive layer are provided on the first surface and / or the second surface, a dielectric layer and an electrode are provided on the transparent conductive layer, the electrode includes a conductive base layer and a first metal layer, the conductive base layer is in contact with the transparent conductive layer, the dielectric layer covers the transparent conductive layer and the conductive base layer, the dielectric layer is discontinuously covered on the surface of the conductive base layer and continuously covered on the surface of the transparent conductive layer, and the first metal layer covers at least the dielectric layer on the surface of the conductive base layer.

[0007] In one or more embodiments of the present invention, the dielectric layer includes SiN X , SiO X , SiNO X , Al2O3, ZrO2, MgF2 or a plurality of layers thereof; and / or, The thickness of the dielectric layer is 2 nm to 10 nm.

[0008] In one or more embodiments of the present invention, the maximum distance H1 between the conductive base layer and the surface of the transparent conductive layer facing the conductive base layer and the maximum distance H2 between the first metal layer and the surface of the transparent conductive layer facing the conductive base layer satisfy: 1.1 ≤ H2 / H1 ≤ 1.45.

[0009] In one or more embodiments of the present invention, the maximum distance H1 between the conductive base layer and the surface of the transparent conductive layer facing the conductive base layer is 100 nm to 15 μm; and / or, the maximum distance H2 between the first metal layer and the surface of the transparent conductive layer facing the conductive base layer is 116 nm to 30 μm; and / or, the maximum distance H1 between the conductive base layer and the surface of the transparent conductive layer facing the conductive base layer and the maximum distance H2 between the first metal layer and the surface of the transparent conductive layer facing the conductive base layer satisfy: 1.9 μm ≤ H2 - H1 ≤ 3.6 μm.

[0010] In one or more embodiments of the present invention, the surface of the transparent conductive layer facing the conductive base layer is a flat surface or a pyramidal texture surface, the maximum distance H1 is the maximum distance between the conductive base layer and the bottom of the flat surface or the pyramidal texture surface, and the maximum distance H2 is the maximum distance between the first metal layer and the bottom of the flat surface or the pyramidal texture surface.

[0011] In one or more embodiments of the present invention, the cross-sectional area S1 of the conductive base layer and the cross-sectional area S2 of the first metal layer satisfy: 0.25 ≤ S2 / S1 ≤ 0.75.

[0012] In one or more embodiments of the present invention, the cross-sectional area S1 of the conductive base layer is 0.5 μm 2 ~200 μm 2 ; and / or, the cross-sectional area S2 of the first metal layer is 0.25 μm 2 ~200 μm 2 .

[0013] In one or more embodiments of the present invention, the line width L2 of the first metal layer is greater than the line width L1 of the conductive base layer; and / or, the first metal layer extends to cover the dielectric layer continuously covered on the surface of the transparent conductive layer.

[0014] In one or more embodiments of the present invention, the line width L1 of the conductive base layer is 5 μm to 20 μm; and / or, The height of the conductive base layer is 50 nm to 10 μm or 2 μm to 10 μm; and / or, The center distance between two adjacent conductive base layers is 1 mm to 5 mm or 2 mm to 3 mm.

[0015] In one or more embodiments of the present invention, the material of the conductive base layer is a metal or a mixture of a metal and an organic polymer, and the metal includes one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, Sn; and / or, The material of the first metal layer is one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, Sn.

[0016] In one or more embodiments of the present invention, the electrode further includes at least one second metal layer located at least partially outside the first metal layer, and the material of the second metal layer is one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, Sn.

[0017] In one or more embodiments of the present invention, the doping structure includes at least one intrinsic layer and at least one doping layer stacked in sequence on the surface of the silicon wafer; and / or, The refractive index of the dielectric layer is less than or equal to the refractive index of the transparent conductive layer; and / or, The thickness of the transparent conductive layer is 15 nm to 150 nm; and / or, The transparent conductive layer is a combination of one or more of ITO, VTTO, IWO, HITO, VTZO, AMTO, TTO.

[0018] The technical solution provided by another embodiment of the present invention is as follows: A method for manufacturing a solar cell, the manufacturing method including the following steps: Provide a silicon wafer; Form a doping structure and a transparent conductive layer in sequence on the surface of the silicon wafer; Prepare a conductive base layer on the transparent conductive layer; Form a dielectric layer on the surface of the transparent conductive layer and the surface of the conductive base layer, the dielectric layer is discontinuously covered on the surface of the conductive base layer and continuously covered on the surface of the transparent conductive layer; Prepare a first metal layer on the dielectric layer, and the first metal layer covers at least the dielectric layer that is discontinuously covered on the surface of the conductive base layer.

[0019] In one or more embodiments of the present invention, the dielectric layer is deposited by PECVD or hot wire CVD process, and the dielectric layer includes SiN X 、SiO X 、SiNOX One or more layers of Al2O3, ZrO2, MgF2, with a deposition temperature of 20°C to 200°C and a deposition thickness of 2 nm to 10 nm.

[0020] In one or more embodiments of the present invention, after forming the dielectric layer on the surface of the transparent conductive layer and the surface of the conductive base layer, it further includes: Heat-treating the dielectric layer to densify the dielectric layer, with a heat-treatment temperature of 50°C to 220°C or 150°C to 220°C, and a heat-treatment time of 10 s to 25 min or 30 s to 5 min.

[0021] In one or more embodiments of the present invention, the conductive base layer is prepared by screen printing process or laser transfer printing process; and / or, The first metal layer is prepared by electroplating or electroless plating process.

[0022] In one or more embodiments of the present invention, the preparation method further includes: At least one second metal layer is prepared by electroplating or electroless plating process outside the first metal layer.

[0023] The technical solution provided by another embodiment of the present invention is as follows: A photovoltaic module, the photovoltaic module includes several of the above-mentioned solar cells.

[0024] Compared with the prior art, the present invention has the following beneficial effects: In the present invention, the dielectric layer continuously covered on the transparent conductive layer can effectively protect the transparent conductive layer as a mask layer, while the dielectric layer on the surface of the conductive base layer is discontinuously covered, eliminating the need for an additional windowing process for the dielectric layer, optimizing the process flow, and avoiding damage to the dielectric layer caused by the windowing process, effectively improving the battery efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments recorded in the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0026] Figure 1 Schematic structural diagram of the heterojunction battery in Comparative Example 1 of the present invention; Figure 2 Schematic structural diagram of the heterojunction battery in Embodiment 1 of the present invention; Figure 3 For Figure 2 Partial enlarged schematic diagram at A in Figures 4a to 4e It is the process flow chart of the preparation method of the heterojunction battery in Embodiment 1 of the present invention; Figure 5 It is the schematic structural diagram of the heterojunction battery in Embodiment 2 of the present invention; Figure 6 It is Figure 5 the partial enlarged schematic diagram at B in Figure 7 It is the schematic structural diagram of the heterojunction battery in Embodiment 4 of the present invention; Figure 8 It is Figure 7 the partial enlarged schematic diagram at C in

[0027] Main reference numeral description: 10'- silicon wafer, 21'- first intrinsic layer, 22'- second intrinsic layer, 31'- first doped layer, 32'- second doped layer, 41'- first transparent conductive layer, 42'- second transparent conductive layer, 61'- first electrode, 62'- second electrode; 10 - silicon wafer, 21 - first intrinsic layer, 22 - second intrinsic layer, 31 - first doped layer, 32 - second doped layer, 41 - first transparent conductive layer, 42 - second transparent conductive layer, 51 - first dielectric layer, 511 discontinuous segment dielectric layer, 512 continuous segment dielectric layer, 52 - second dielectric layer, 61 - first electrode, 611 - conductive base layer, 612 - first metal layer, 613 - second metal layer, 62 - second electrode. Detailed implementation manners

[0028] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0029] In the present invention, unless otherwise clearly defined and limited, the first feature being "on" or "under" the second feature may be that the first and second features are in direct contact, or the first and second features are indirectly in contact through an intermediate medium. Moreover, the first feature being "above", "over" and "on" the second feature may be that the first feature is directly above or obliquely above the second feature, or merely indicates that the first feature has a higher horizontal height than the second feature. The first feature being "under", "below" and "beneath" the second feature may be that the first feature is directly below or obliquely below the second feature, or merely indicates that the first feature has a lower horizontal height than the second feature.

[0030] A solar cell includes a silicon wafer, the silicon wafer includes opposite first and second surfaces, a doping structure and a transparent conductive layer are provided on the first surface and / or the second surface, a dielectric layer and an electrode are provided on the transparent conductive layer, the electrode includes a conductive base layer and a first metal layer, the conductive base layer is in contact with the transparent conductive layer, the dielectric layer covers the transparent conductive layer and the conductive base layer, the dielectric layer is discontinuously covered on the surface of the conductive base layer and continuously covered on the surface of the transparent conductive layer, and the first metal layer covers at least the dielectric layer on the surface of the conductive base layer.

[0031] The present invention also discloses a preparation method of a heterojunction cell, including the following steps: Provide a silicon wafer; Successively form a doping structure and a transparent conductive layer on the surface of the silicon wafer; Prepare a conductive base layer on the transparent conductive layer; Form a dielectric layer on the surface of the transparent conductive layer and the surface of the conductive base layer, the dielectric layer is discontinuously covered on the surface of the conductive base layer and continuously covered on the surface of the transparent conductive layer; Prepare a first metal layer on the dielectric layer, and the first metal layer covers at least the dielectric layer discontinuously covered on the surface of the conductive base layer.

[0032] Preferably, the maximum distance H1 between the conductive base layer and the surface of the transparent conductive layer facing the conductive base layer and the maximum distance H2 between the first metal layer and the surface of the transparent conductive layer facing the conductive base layer satisfy: 1.1 ≤ H2 / H1 ≤ 1.45.

[0033] Preferably, the cross-sectional area S1 of the conductive base layer and the cross-sectional area S2 of the first metal layer satisfy: 0.25 ≤ S2 / S1 ≤ 0.75.

[0034] In addition, the present invention also discloses a photovoltaic module, including the above-mentioned solar cell.

[0035] By introducing the dielectric layer, the present invention can achieve a finer grid line design, thereby improving the battery efficiency and the module power; at the same time, expensive photosensitive ink is not required, and the process cost is greatly reduced.

[0036] The dielectric layer continuously covered on the transparent conductive layer can effectively protect the transparent conductive layer as a mask layer, while the dielectric layer on the surface of the conductive base layer is discontinuously covered, and no additional window opening process is required for the dielectric layer, optimizing the process flow and avoiding damage to the dielectric layer caused by the window opening process.

[0037] Furthermore, by optimizing the height and cross-sectional area of the conductive base layer and the first metal layer, and heat-treating the dielectric layer, the present invention can effectively improve the battery efficiency.

[0038] The following further illustrates the present invention with specific examples.

[0039] Comparative Example 1: Refer to Figure 1 The following is a schematic diagram of the structure of the heterojunction battery in this comparative example. The heterojunction battery includes: A silicon wafer 10', which includes a front surface (i.e., the light-receiving surface) and a back surface (i.e., the light-blocking surface) that are oppositely arranged; A first intrinsic layer 21', a first doped layer 31', and a first transparent conductive layer 41' that are sequentially stacked on the front surface; A second intrinsic layer 22', a second doped layer 32', and a second transparent conductive layer 42' that are sequentially stacked on the back surface; A first electrode 61', which is in contact with the first transparent conductive layer 41'; A second electrode 62', which is in contact with the second transparent conductive layer 42'.

[0040] Exemplarily, the silicon wafer 10' is N-type doped; the first intrinsic layer 21' is an intrinsic amorphous silicon layer or an intrinsic microcrystalline silicon layer, and the first doped layer 31' is an N-type doped amorphous silicon layer or a microcrystalline silicon layer; the second intrinsic layer 22' is an intrinsic amorphous silicon layer or an intrinsic microcrystalline silicon layer, and the second doped layer 32' is a P-type doped amorphous silicon layer or a microcrystalline silicon layer; the first transparent conductive layer 41' and the second transparent conductive layer 42' can be one or a combination of multiple transparent conductive layers such as ITO, VTTO, IWO, HITO, VTZO, AMTO, TTO, etc.; the first electrode 61' and the second electrode 62' are both grid line electrodes.

[0041] Example 1: Refer to Figure 2 And in combination with Figure 3 As shown, the solar cell in this example is a heterojunction battery, which includes: A silicon wafer 10, which includes a front surface (i.e., the light-receiving surface) and a back surface (i.e., the light-blocking surface) that are oppositely arranged, and the front surface and the back surface respectively include a metal region and a non-metal region; A first intrinsic layer 21, a first doped layer 31, and a first transparent conductive layer 41 that are sequentially stacked on the front surface; A second intrinsic layer 22, a second doped layer 32, and a second transparent conductive layer 42 that are sequentially stacked on the back surface; A first dielectric layer 51 and a first electrode 61. The first electrode 61 is located in the metal region on the front surface of the silicon wafer 10 and is spaced apart along the first direction (X direction). It includes a conductive base layer 611 and a first metal layer 612. The conductive base layer 611 is in contact with the first transparent conductive layer 41. In the metal region, the first dielectric layer 51 covers the surface of the conductive base layer 611, and in the non-metal region, the first dielectric layer 51 covers the surface of the first transparent conductive layer 41.

[0042] Specifically, the first dielectric layer 51 is discontinuously covered on the surface of the conductive base layer 611 and continuously covered on the surface of the first transparent conductive layer 41. The first dielectric layer discontinuously covered on the surface of the conductive base layer 611 is the discontinuous segment dielectric layer 511, and the first dielectric layer continuously covered on the surface of the first transparent conductive layer 41 is the continuous segment dielectric layer 512. The first metal layer 612 covers at least the discontinuous segment dielectric layer 511 discontinuously covered on the surface of the conductive base layer 611 and extends to the continuous segment dielectric layer 512 on the surface of the first transparent conductive layer 41; The second dielectric layer 52 and the second electrode 62. The structures of the second dielectric layer 52 and the second electrode 62 are exactly the same as those of the first dielectric layer 51 and the first electrode 61, and will not be elaborated here.

[0043] In this embodiment, the silicon wafer 10 is an N-type single-crystalline silicon wafer, with a resistivity of 0.5 Ω·m to 3 Ω·m, a thickness of 90 μm to 120 μm, a size of 210 mm, and both the front and back surfaces of the silicon wafer 10 are polished surfaces.

[0044] In this embodiment, the first intrinsic layer 21 and the second intrinsic layer 22 are intrinsic amorphous silicon layers or intrinsic microcrystalline silicon layers, the first doped layer 31 is an N-type doped (such as phosphorus-doped) amorphous silicon layer or microcrystalline silicon layer, and the second doped layer 32 is a P-type doped (such as boron-doped) amorphous silicon layer or microcrystalline silicon layer.

[0045] In this embodiment, the first transparent conductive layer 41 and the second transparent conductive layer 42 can be one or a combination of transparent conductive layers such as ITO, VTTO, IWO, HITO, VTZO, AMTO, TTO, etc. Preferably, it is an ITO transparent conductive layer, with a thickness of 15 nm to 150 nm, and preferably 50 nm.

[0046] The silicon wafer, the intrinsic layer, the doped layer, and the transparent conductive layer in this embodiment are exactly the same as those in Comparative Example 1, and will not be elaborated here. Different from Comparative Example 1, in this embodiment, the first dielectric layer 51 and the second dielectric layer 52 are added, and the structures of the first electrode 61 and the second electrode 62 are also different from those in Comparative Example 1.

[0047] The second dielectric layer 52 and the second electrode 62 are exactly the same as the first dielectric layer 51 and the first electrode 61. Refer Figure 2 And in combination with Figure 3 As shown, the first dielectric layer 51 and the first electrode 61 on the front surface of the silicon wafer will be described in detail below as an example.

[0048] The first dielectric layer 51 in the present invention includes SiN X , SiO X , SiNO X, one layer of Al2O3, ZrO2, MgF2, etc., or it can also be a multi-layer composite film. The thickness of the first dielectric layer 51 is 2 nm to 10 nm. When the first dielectric layer 51 is a multi-layer composite film structure, it includes an outer dielectric layer and an inner dielectric layer. The thickness of the inner dielectric layer is less than that of the outer dielectric layer, and the refractive index of the inner dielectric layer is greater than or equal to that of the outer dielectric layer.

[0049] Preferably, SiN X layers are selected as the first dielectric layer 51 in this embodiment. The refractive index n of the SiN X layer is 2.0, and the thickness is 5 nm. The SiN X layer can be deposited on the first transparent conductive layer 41 and the conductive base layer 611 by using a low-temperature PECVD process or a hot-wire CVD process.

[0050] Furthermore, in this embodiment, the refractive index of the first dielectric layer 51 is less than or equal to that of the first transparent conductive layer 41. In this way, it is more conducive to the incidence of light, reduces light reflection, and increases the short-circuit current Isc. At the same time, the chemical properties of the first dielectric layer are relatively stable, and it can be used as a mask layer to effectively protect the first transparent conductive layer, reducing the risk of the battery being corroded by chemical liquids, which is beneficial to improving the reliability of the component.

[0051] The first electrode 61 in the present invention uses a shell electrode of a conductive base layer and a first metal layer (such as a metal plating layer), which can effectively reduce the resistivity of the electrode and has an electrical advantage compared with the batteries of the existing paste system. The first electrode 61 is a grid line electrode. When the size of the silicon wafer is 210 mm, the number of grid line electrodes is preferably 70 to 90.

[0052] Specifically, the conductive base layer 611 in the first electrode 61 is in direct contact with the first transparent conductive layer 41, and the first dielectric layer 51 is discontinuously covered on the surface of the conductive base layer 611. The line width L1 of the conductive base layer 611, that is, the width of the conductive base layer 611 along the first direction (X direction), has a value of 5 μm to 20 μm, and the height along the second direction (Z direction) is 50 nm to 10 μm, preferably 2 μm to 10 μm. The center distance between two adjacent conductive base layers 611 is 1 mm to 5 mm, preferably 2 mm to 3 mm.

[0053] The material of the conductive base layer 611 is a metal or a mixture of a metal and an organic polymer. The metal includes one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, Sn, etc. The organic polymer includes non-metal particles in the electrode paste. The conductive base layer is prepared by using a screen printing process or a laser transfer printing (PTP) process. A relatively inexpensive and simple deposition process can be used to prepare the patterned conductive base layer.

[0054] In addition, the first metal layer 612 in the first electrode 61 covers the discontinuous segment dielectric layer 511 that is discontinuously covered on the surface of the conductive base layer 611. Therefore, it is not necessary to open a window in the first dielectric layer 51 to achieve electrical contact between the first metal layer 612 and the conductive base layer 611. The line width L2 of the first metal layer 612, that is, the width of the first metal layer 612 along the first direction (X direction), is greater than the line width L1 of the conductive base layer 611, and can achieve full coverage of the conductive base layer 611 and the discontinuous segment dielectric layer 511.

[0055] The material of the first metal layer 612 is one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, Sn, etc., and it is prepared by electroplating or electroless plating processes, preferably the electroplating process.

[0056] Refer Figure 3 As shown, the surface of the silicon wafer 10 is a polished surface (i.e., a flat surface), and the surfaces of the first transparent conductive layer 41 and the continuous segment dielectric layer 512 facing away from the silicon wafer are flat surfaces. The maximum distance between the conductive base layer 611 and the surface of the first transparent conductive layer 41 facing the conductive base layer 611 is H1, that is, the height of the top of the conductive base layer 611 from the front (flat surface) of the first transparent conductive layer 41 in the second direction (Z direction); the maximum distance between the first metal layer 612 and the surface of the first transparent conductive layer 41 facing the conductive base layer 611 is H2, that is, the height of the top of the first metal layer 612 from the front (flat surface) of the first transparent conductive layer 41 in the second direction (Z direction).

[0057] In the present invention, H1 and H2 satisfy: 1.1 ≤ H2 / H1 ≤ 1.45; where H1 is 100 nm to 15 μm, and H2 is 116 nm to 30 μm.

[0058] In addition, H1 and H2 further satisfy: 1.9 μm ≤ H2 - H1 ≤ 3.6 μm.

[0059] Continue to refer to Figure 3 As shown, the cross-sectional area S1 of the conductive base layer 611 is the cross-sectional area of the conductive base layer 611 in the plane perpendicular to the extending direction of the conductive base layer 611, and the cross-sectional area S2 of the first metal layer 612 is the cross-sectional area of the first metal layer 612 in the plane perpendicular to the extending direction of the first metal layer 612.

[0060] In the present invention, S1 and S2 satisfy: 0.25 ≤ S2 / S1 ≤ 0.75, where S1 is 0.5 μm 2 ~200 μm 2 , S2 is 0.25 μm 2 ~200 μm 2 .

[0061] In this embodiment, the outer surfaces of the conductive base layer 611 and the first metal layer 612 away from the silicon wafer 10 are both curved surfaces. The cross-section of the conductive base layer 611 is approximately semi-circular. The distance between the conductive base layer and the front surface of the first transparent conductive layer gradually decreases from the middle to both sides. In other embodiments, the cross-section of the conductive base layer can also be rectangular, triangular, trapezoidal, etc. The outer surfaces of the conductive base layer 611 and the first metal layer 612 can be curved surfaces, flat surfaces or combinations thereof, or can be irregular surfaces, and no further examples will be given here.

[0062] The first dielectric layer 51 and the first electrode 61 on the front surface of the silicon wafer in this embodiment are described in detail above. The second dielectric layer 52 and the second electrode 62 on the back surface of the silicon wafer are exactly the same as the first dielectric layer 51 and the first electrode 61 on the front surface of the silicon wafer, and will not be elaborated here.

[0063] The preparation method of the solar cell in this embodiment is specifically as follows: 1. Refer Figure 4a as shown, provide a silicon wafer.

[0064] The silicon wafer 10 in this embodiment is an N-type single-crystalline silicon wafer with a resistivity of 0.5 Ω·m - 3 Ω·m, a thickness of 90 μm - 120 μm, and a size of 210 mm. The front and back surfaces of the silicon wafer 10 are polished with a polishing solution to form polished surfaces.

[0065] 2. Refer Figure 4b as shown, sequentially form a first intrinsic layer 21, a first doped layer 31, and a first transparent conductive layer 41 on the front surface of the silicon wafer 10, and sequentially form a second intrinsic layer 22, a second doped layer 32, and a second transparent conductive layer 42 on the back surface of the silicon wafer 10.

[0066] Preferably, in this embodiment, the intrinsic layer and the doped layer are deposited by a plasma enhanced chemical vapor deposition (PECVD) process, and the transparent conductive layer is deposited by a reactive plasma deposition (RPD) process or a magnetron sputtering process. Specifically as follows: First, introduce SiH4 (silane) gas into the vacuum chamber, and form an intrinsic amorphous silicon layer on the entire front surface area of the silicon wafer 10 through the PECVD process. Then, introduce SiH4 gas, H2 gas, and PH3 (phosphine) gas into the vacuum chamber, and form an N-type doped amorphous silicon layer on the intrinsic amorphous silicon layer through the PECVD process; Then turn it over, change the tray, introduce SiH4 (silane) gas into the vacuum chamber, and form an intrinsic amorphous silicon layer on the entire back surface area of the silicon wafer 10 through the PECVD process. Then, introduce SiH4 gas, H2 gas, and B2H6 (diborane) gas into the vacuum chamber, and form a P-type doped amorphous silicon layer on the intrinsic amorphous silicon layer through the PECVD process; Finally, a film is deposited on the N-type doped amorphous silicon layer and the P-type doped amorphous silicon layer by using a reactive plasma deposition (RPD) process or a magnetron sputtering process; the back surface is shielded at the edge through a carrier plate design (shielded through a mask), the specific shielding area around is 0.5 mm to 0.8 mm, the transparent conductive layer is ITO (99.5%: 0.5%) wt, the thickness is 50 nm, and the carrier concentration is 2E20 cm -3 ~3.5E20 cm -3 and the mobility is 70 cm 2 / Vs ~ 100 cm 2 / Vs.

[0067] In this embodiment, the carrier concentration of the first transparent conductive layer 41 and the second transparent conductive layer 42 is 2E20 cm -3 ~3.5E20 cm -3 and preferably 3E20 cm -3 , the mobility is 70 cm 2 / Vs ~ 100 cm 2 / Vs, preferably 80 cm 2 / Vs, the contact resistivity is 0.8 mΩ·cm 2 4 mΩ·cm 2 and preferably 2 mΩ·cm 2 , and the refractive index is 2.0 to 2.1.

[0068] 3. As shown in Figure 4c , a conductive base layer is prepared on the transparent conductive layer.

[0069] Specifically, a patterned conductive base layer is prepared by using a screen printing process or a laser transfer printing (PTP) process, the line width is 5 μm to 20 μm, the height is 50 nm to 10 μm, preferably 2 μm to 10 μm, and the paste uses a low-temperature electrode paste. The electrode paste can be a metal or a mixture of a metal and an organic polymer. The conductive materials in the electrode paste include one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, Sn, etc.

[0070] Then, sintering and curing are carried out at 150 °C to 220 °C to form a good ohmic contact.

[0071] 4. As shown in Figure 4d , a dielectric layer is formed on the surface of the transparent conductive layer and the surface of the conductive base layer.

[0072] Taking the front surface of the silicon wafer 10 as an example, it is deposited on the first transparent conductive layer 41 and the conductive base layer 611 by using a low-temperature PECVD process or a hot-wire CVD process. A first dielectric layer 51 is formed on the surfaces of the first transparent conductive layer 41 and the conductive base layer 611. The first dielectric layer 51 includes SiN X , SiOX 、SiNO X 、one or more of Al2O3, ZrO2, MgF2, the deposition temperature is 20°C to 200°C, and the deposition thickness is 2nm to 10nm.

[0073] Preferably, SiN X layers are respectively used as the first dielectric layer 51, and the refractive index n of the SiN X layer is 2.0 and the thickness is 5nm.

[0074] Since the thickness of the conductive base layer 611 is in the micron range, while the thickness of the deposited first dielectric layer 51 is in the nanometer range, due to the difference in film layer height, the first dielectric layer 51 cannot form a closed coverage on the surface of the conductive base layer 611. Eventually, the first dielectric layer 51 is discontinuously covered on the surface of the conductive base layer 611, while being continuously covered on the surface of the first transparent conductive layer 41. The first dielectric layer continuously covered on the surface of the first transparent conductive layer 41 can act as a mask for the non-metal region.

[0075] 5. Heat-treat the dielectric layer.

[0076] Specifically, heat-treat the first dielectric layer 51 and the second dielectric layer 52 in an annealing furnace. The heat-treatment temperature is 50°C to 220°C, preferably 150°C to 220°C, and the heat-treatment time is 10s to 25min, preferably 30s to 5min. Exemplarily, in this embodiment, the heat-treatment temperature is 100°C and the heat-treatment time is 1min.

[0077] In the present invention, in order to make the dielectric layer on the surface of the conductive base layer discontinuously distributed, the thickness of the dielectric layer needs to be controlled within 2nm to 10nm. However, the relatively thin thickness of the dielectric layer is easily corroded during subsequent electroplating or electroless plating processes, affecting the passivation performance. This step can densify the dielectric layer on the transparent conductive layer by heat-treating the dielectric layer, enabling the dielectric layer in the non-metal region to have better corrosion resistance and maintaining the obtained good passivation performance during subsequent electroplating or electroless plating processes.

[0078] 6. Refer Figure 4e as shown, prepare the first metal layer on the dielectric layer.

[0079] Specifically, use electroplating or electroless plating process to prepare a patterned first metal layer on the dielectric layer. The line width L2 of the first metal layer is greater than the line width L1 of the conductive base layer, and the material is one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, Sn, etc. The prepared first metal layer can achieve full coverage of the conductive base layer.

[0080] Exemplarily, the first metal layer is electroplated copper. The electroplated copper solution includes copper sulfate, sulfuric acid, copper balls, and additives that can optimize the crystal structure of the copper layer. The concentration of Cu in the electroplated copper solution 2+ is 50 g / L, and the concentration of sulfuric acid is 40 g / L.

[0081] In the present invention, the thickness of the dielectric layer is 2 nm to 10 nm, and the height of the conductive base layer is 50 nm to 10 μm, preferably 2 μm to 10 μm. The height of the conductive base layer is much greater than the thickness of the dielectric layer. Therefore, the deposited dielectric layer is discontinuously covered on the surface of the conductive base layer. Subsequently, electroplating can be directly performed on the discontinuously covered dielectric layer, thereby achieving electrical contact between the first metal layer and the conductive base layer without the need for an additional window opening process for the dielectric layer, optimizing the process flow and avoiding damage to the dielectric layer caused by the window opening process.

[0082] 7. Finally, the heterojunction battery is subjected to alkali washing, and the prepared heterojunction battery is subjected to photo-injection treatment. The temperature of the photo-injection treatment is 210 °C, and the time of the photo-injection treatment is 90 s.

[0083] Example 2: Refer Figure 5 and combine with Figure 6 as shown. The solar cell in this embodiment is a heterojunction battery, and its structure and preparation method are basically the same as those in Example 1. The difference is that in Example 1, both the front and back surfaces of the silicon wafer 10 are polished surfaces, while in this embodiment, they are pyramid-structured matte surfaces.

[0084] The silicon wafer 10 in this embodiment is subjected to double-sided texturing through an alkali texturing process before depositing the intrinsic layer. Specifically: Use an HF solution with a mass fraction of 1% to 4% to remove the surface oxide layer, and use a solution such as KOH or NaOH with a mass fraction of 1% to 3%. Utilize the anisotropic etching of single-crystalline silicon to form a pyramid-structured matte surface on the surface of the silicon wafer. Preferably, the size of the pyramid structure is preferably 0.5 μm - 5 μm.

[0085] Refer Figure 6 as shown. The surface of the first transparent conductive layer 41 deposited on the surface of the silicon wafer 10 is a pyramid-structured matte surface, and the surface of the continuous segment dielectric layer 512 deposited thereon is also a pyramid-structured matte surface.

[0086] The maximum distance between the conductive base layer 611 and the surface of the first transparent conductive layer 41 facing the conductive base layer 611 is H1, that is, the height from the top of the conductive base layer 611 to the bottom of the pyramid-structured matte surface of the first transparent conductive layer 41; the maximum distance between the first metal layer 612 and the surface of the first transparent conductive layer 41 facing the conductive base layer 611 is H2, that is, the height from the top of the first metal layer 612 to the bottom of the pyramid-structured matte surface of the first transparent conductive layer 41.

[0087] Example 3: The solar cell in this example is a heterojunction cell, and its structure is exactly the same as that in Example 2. The difference is that in the preparation method of the solar cell in this example, the dielectric layer is not heat-treated.

[0088] Example 4: Refer to Figure 7 and in combination with Figure 8 As shown, the solar cell in this example is a heterojunction cell, and its structure and preparation method are basically the same as those in Example 1. The difference is that in addition to the conductive base layer 611 and the first metal layer 612, the heterojunction cell in this example further includes at least one second metal layer 613 outside the first metal layer 612.

[0089] Specifically, a patterned second metal layer 613 is prepared on the outside of the first metal layer 612 by electroplating or electroless plating processes. The line width L3 of the second metal layer 613, that is, the width of the second metal layer 613 along the first direction (X direction), is greater than the line width L2 of the first metal layer 612, and the material is one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, Sn, etc.

[0090] Exemplarily, taking electroplated tin as an example for the second metal layer, the electroplated tin solution includes stannous methyl sulfonate and tin plating additives, and the concentration of Sn 2+ in the electroplated tin solution is 30 g / L, and the concentration of stannous methyl sulfonate is 200 g / L.

[0091] IV performance tests were carried out on different heterojunction cells, and the test data are shown in the following table:

[0092] Among them, Control Group 1 is the heterojunction cell in Comparative Example 1, and the grid line electrodes on the front and back are both prepared by screen printing with low-temperature silver paste. The grid line width is 25 μm, and the number is 60; Experimental Groups 1-5 are the heterojunction cells in Example 2, and the number of grid line electrodes on the front and back is 80. It can be seen that compared with Control Group 1, Experimental Groups 1-5 can prepare finer grid line electrodes with smaller line width and spacing.

[0093] By introducing the dielectric layer in Experimental Groups 1-5, it is beneficial to the incidence of light, improves the optical advantage, and can effectively protect the transparent conductive layer and reduce the risk of being corroded by chemical liquids; in addition, the dielectric layer is discontinuously covered on the surface of the conductive base layer, and there is no need to adopt an additional windowing process for the dielectric layer, avoiding damage to the dielectric layer by the conventional windowing process, improving the passivation performance, and finally being able to effectively improve the cell efficiency Eta.

[0094] Through physical bonding and chemical adsorption, the conductive base layer can enhance the adhesion between the subsequent metal layer and the transparent conductive layer, reduce the contact resistivity, and the metal layer can replace the low-temperature silver paste.

[0095] Since the linear resistivity of the metal layer is significantly better than that of the conductive base layer, the larger the height ratio H2 / H1 and cross-sectional area ratio S2 / S1 of the conductive base layer and the metal layer, the more effectively the series resistance Rs can be reduced and the fill factor FF can be improved. However, with the increase of the height ratio H2 / H1 and cross-sectional area ratio S2 / S1, the lateral light enhancement will increase, resulting in a decrease in the short-circuit current Isc. By optimizing the height ratio H2 / H1 and cross-sectional area ratio S2 / S1 of the metal layer, within the range of 1.1 ≤ H2 / H1 ≤ 1.45 and 0.25 ≤ S2 / S1 ≤ 0.75, the cell efficiency Eta can be increased by 0.06% - 0.08%.

[0096] In experimental groups 2 - 5, the dielectric layer was heat-treated, while in experimental groups 6 - 9, the dielectric layer was not heat-treated. Heat treatment can densify the dielectric layer on the transparent conductive layer, enable the dielectric layer to have better corrosion resistance, endow the dielectric layer with good passivation performance, and further improve the cell efficiency Eta.

[0097] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or basic characteristics of the present invention. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be encompassed within the present invention. Any reference signs in the claims should not be regarded as limiting the claims involved.

[0098] In addition, it should be understood that although this specification is described according to embodiments, not every embodiment only contains an independent technical solution. This narrative way of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A solar cell, characterized in that, It includes a silicon wafer, the silicon wafer includes opposite first and second surfaces, a doping structure and a transparent conductive layer are provided on the first surface and / or the second surface, a dielectric layer and an electrode are provided on the transparent conductive layer, the electrode includes a conductive base layer and a first metal layer, the conductive base layer is in contact with the transparent conductive layer, the dielectric layer covers the transparent conductive layer and the conductive base layer, the dielectric layer is discontinuously covered on the surface of the conductive base layer and continuously covered on the surface of the transparent conductive layer, and the first metal layer covers at least the dielectric layer on the surface of the conductive base layer.

2. The solar cell according to claim 1, wherein The dielectric layer includes SiN X , SiO X , SiNO X , one or more of Al2O3, ZrO2, MgF2; and / or, The thickness of the dielectric layer is 2 nm to 10 nm.

3. The solar cell according to claim 1, characterized in that, The maximum distance H1 between the conductive base layer and the surface of the transparent conductive layer facing the conductive base layer and the maximum distance H2 between the first metal layer and the surface of the transparent conductive layer facing the conductive base layer satisfy: 1.1 ≤ H2 / H1 ≤ 1.

45.

4. The solar cell according to claim 1, wherein The maximum distance H1 between the conductive base layer and the surface of the transparent conductive layer facing the conductive base layer is 100 nm to 15 μm; and / or, The maximum distance H2 between the first metal layer and the surface of the transparent conductive layer facing the conductive base layer is 116 nm to 30 μm; and / or, The maximum distance H1 between the conductive base layer and the surface of the transparent conductive layer facing the conductive base layer and the maximum distance H2 between the first metal layer and the surface of the transparent conductive layer facing the conductive base layer satisfy: 1.9 μm ≤ H2 - H1 ≤ 3.6 μm.

5. The solar cell according to claim 3 or 4, characterized in that, The surface of the transparent conductive layer facing the conductive base layer is a flat surface or a pyramidal textured surface, the maximum distance H1 is the maximum distance between the conductive base layer and the bottom of the flat surface or the pyramidal textured surface, and the maximum distance H2 is the maximum distance between the first metal layer and the bottom of the flat surface or the pyramidal textured surface.

6. The solar cell according to claim 1, characterized in that, The cross-sectional area S1 of the conductive base layer and the cross-sectional area S2 of the first metal layer satisfy: 0.25 ≤ S2 / S1 ≤ 0.

75.

7. The solar cell according to claim 1, characterized in that, The cross-sectional area S1 of the conductive base layer is 0.5 μm 2 ~200 μm 2 ; and / or, The cross-sectional area S2 of the first metal layer is 0.25 μm 2 ~200 μm 2 .

8. The solar cell according to claim 1, characterized in that, The line width L2 of the first metal layer is greater than the line width L1 of the conductive base layer; and / or, The first metal layer extends and covers the dielectric layer on the surface of the transparent conductive layer.

9. The solar cell according to claim 1, characterized in that, The line width L1 of the conductive base layer is 5 μm to 20 μm; and / or, The height of the conductive base layer is 50 nm to 10 μm or 2 μm to 10 μm; and / or, The center distance between two adjacent conductive base layers is 1 mm to 5 mm or 1.3 mm to 2.1 mm or 0.6 mm to 1 mm.

10. The solar cell according to claim 1, wherein The material of the conductive base layer is a metal or a mixture of a metal and an organic polymer, and the metal includes one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, Sn; and / or, The material of the first metal layer is one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, Sn.

11. The solar cell according to claim 10, characterized in that, The electrode further includes at least one second metal layer located at least outside a part of the first metal layer, and the material of the second metal layer is one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, and Sn.

12. The solar cell according to claim 1, characterized in that, The doping structure includes at least one intrinsic layer and at least one doped layer stacked in sequence on the surface of the silicon wafer; and / or, The refractive index of the dielectric layer is less than or equal to the refractive index of the transparent conductive layer; and / or, The thickness of the transparent conductive layer is 15 nm - 150 nm; and / or, The transparent conductive layer is a combination of one or more of ITO, VTTO, IWO, HITO, VTZO, AMTO, and TTO.

13. A method for preparing a solar cell, characterized in that, The preparation method includes the following steps: Providing a silicon wafer; Successively forming a doping structure and a transparent conductive layer on the surface of the silicon wafer; Preparing a conductive base layer on the transparent conductive layer; Forming a dielectric layer on the surface of the transparent conductive layer and the surface of the conductive base layer, the dielectric layer is discontinuously covered on the surface of the conductive base layer and continuously covered on the surface of the transparent conductive layer; Preparing a first metal layer on the dielectric layer, and the first metal layer covers at least the dielectric layer that is discontinuously covered on the surface of the conductive base layer.

14. The preparation method according to claim 13, wherein, The dielectric layer is deposited by PECVD or hot-wire CVD process, and the dielectric layer includes SiN X , SiO X , SiNO X , one or more of Al2O3, ZrO2, and MgF2. The deposition temperature is 20°C to 200°C, and the deposition thickness is 2 nm to 10 nm.

15. The preparation method according to claim 13, wherein, After forming the dielectric layer on the surface of the transparent conductive layer and the surface of the conductive base layer, it further includes: Performing heat treatment on the dielectric layer to densify the dielectric layer, the heat treatment temperature is 50°C - 220°C or 150°C - 220°C, and the heat treatment time is 10 s - 25 min or 30 s - 5 min.

16. The preparation method according to claim 13, characterized in that, [[ID= ​ 17. The preparation method according to claim 13, wherein ​ ​ 18. A photovoltaic module, characterized in that, ​

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