Novel unijunction heterojunction battery and production process thereof

Abstract

The invention discloses a novel single-junction heterojunction battery and a production process thereof. The novel single-junction heterojunction battery comprises a substrate layer; a front electrode assembly and a back electrode assembly; a front conductive film; a back conductive film; the solar cell further comprises a buffer layer which is stacked between the front electrode assembly and the front conductive film and / or between the back electrode assembly and the back conductive film so as to reduce the potential barrier and improve the carrier mobility. According to the novel unijunction heterojunction cell, the buffer layer is stacked at at least one position between the front conductive film and the front electrode assembly and between the back conductive film and the back electrode assembly, so that the potential barrier is reduced, the loss of carriers on a transmission cross section is reduced, the carrier mobility is improved, the short-circuit current and the filling factor are improved, and the photoelectric conversion efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of photovoltaic cells, and in particular to a novel single-junction heterojunction cell and its production process. Background Art

[0002] As countries around the world continue to deepen the layout of innovation in the entire photovoltaic power generation industry chain, as the main strategic measure to promote the development of emerging industries, covering all aspects of research and development of advanced materials, manufacturing, and system applications helps to reduce costs and enhance competitiveness.

[0003] Currently, the core components of photovoltaics are developing towards high efficiency, low energy consumption, and low cost. Among them, crystalline silicon cells have built a complete industrial chain and occupy the main share of photovoltaic cell production. In the prior art, n-type crystalline silicon cells have occupied the mainstream position in the photovoltaic market. Among them, heterojunction cells have become one of the directions with the greatest industrialization potential in the n-type technology route due to their advantages such as high open-circuit voltage, low temperature coefficient, and bifacial power generation.

[0004] However, there are still some losses in the carrier transport interface of traditional heterojunction cells, mainly due to the potential barriers and defects existing at the heterojunction interface. These potential barriers and defects will hinder the transport of carriers, resulting in energy loss and efficiency reduction. Specifically, it is manifested as follows: 1. The heterojunction is composed of different semiconductor materials, and the energy difference structure differences between these materials will form potential barriers at the interface. Carriers need to overcome these potential barriers during the transport process, thus consuming energy; 2. Various defects may exist at the heterojunction interface, such as vacancies, impurities, lattice mismatch, etc. These defects will become traps for carriers, capturing and restricting the transport of carriers; 3. In the heterojunction, carriers may recombine at the interface before reaching the target area, resulting in energy loss. At the same time, high-concentration carriers may also overflow from the active region to the confinement layer, further exacerbating energy loss.

[0005] Due to the above factors, significant losses exist in the carrier transport cross-section during the operation of traditional heterojunction cells.

[0006] Therefore, it is necessary to improve the heterojunction cells in the prior art and improve the production process of heterojunction cells. Summary of the Invention

[0007] The purpose of the present invention is to overcome the defects existing in the prior art, and provide a novel single-junction heterojunction cell and its production process that reduce carrier loss, reduce contact resistance, suppress recombination loss, further increase the open-circuit voltage and short-circuit current, thereby improving the power generation efficiency.

[0008] To solve the above technical problems, the present invention provides a novel single-junction heterojunction battery, comprising: A substrate layer having a light-receiving surface and a backlight surface; A front electrode assembly and a back electrode assembly, which are respectively stacked on the light-receiving surface and the backlight surface, and are both used to generate photo-generated carriers by forming a PN junction; A front conductive film, which is stacked on the side of the front electrode assembly facing away from the substrate layer and is connected to a front electrode; A back conductive film, which is stacked on the side of the back electrode assembly facing away from the substrate layer and is connected to a back electrode; It further comprises: A buffer layer, which is stacked between the front electrode assembly and the front conductive film and / or between the back electrode assembly and the back conductive film to reduce the potential barrier and improve the carrier mobility.

[0009] Preferably, in order to further improve the carrier mobility, reduce the loss, and thus improve the power generation efficiency, the buffer layer includes a front buffer layer and a back buffer layer. The front buffer layer is stacked between the front electrode assembly and the front conductive film, and the back buffer layer is stacked between the back electrode assembly and the back conductive film.

[0010] Preferably, in order to improve the carrier mobility, the front buffer layer and the back buffer layer both include at least one of a MoO2 layer, a TiO2 layer, a ZnO layer, a MoS2 layer, a WS2 layer, and a SnS2 layer.

[0011] Preferably, in order to further improve the carrier mobility, the front buffer layer includes a ZnO layer and a TiO2 layer stacked and connected or a MoS2 layer and a WS2 layer stacked and connected. The TiO2 layer and the ZnO layer are respectively connected to the front electrode assembly and the front conductive film, and the MoS2 layer and the WS2 layer are respectively connected to the front electrode assembly and the front conductive film; the back buffer layer includes a MoO2 layer and a SnS2 layer stacked and connected, and the MoO2 layer and the SnS2 layer are respectively connected to the back electrode assembly and the back conductive film.

[0012] Preferably, in order to avoid the adverse effects caused by pinhole defects due to too thin film layers and increased series resistance and reduced light transmittance due to too thick film layers, the thicknesses of the ZnO layer and the TiO2 layer, the MoO2 layer and the SnS2 layer are both 5-20 nm, and the thicknesses of the MoS2 layer and the WS2 layer are 1-3 nm and 2-5 nm respectively.

[0013] To solve the above technical problems, the present invention also provides a production process for a novel single-junction heterojunction battery, comprising the following steps: S100. Prepare a heterojunction composite layer: The heterojunction composite layer includes a front electrode assembly, a substrate layer, and a back electrode assembly that are sequentially stacked and connected; S200. Deposit a buffer layer: Deposit a buffer layer on at least one side of the heterojunction composite layer obtained in S100 to reduce the potential barrier and improve the carrier mobility; S300. Deposit a conductive film: Deposit a front conductive film and a back conductive film on both sides of the composite layer structure obtained in S200. The front conductive film is adjacent to the front electrode assembly, and the back conductive film is adjacent to the back electrode assembly; S400. Prepare electrodes: Prepare a front electrode and a back electrode on the front conductive film and the back conductive film obtained in S200, respectively.

[0014] Preferably, in order to further improve the carrier mobility, in step S200, a front buffer layer and a back buffer layer are deposited on the front electrode assembly and the back electrode assembly, respectively. The front buffer layer and the back buffer layer each include at least one of a MoO2 layer, a TiO2 layer, a ZnO layer, a MoS2 layer, a WS2 layer, and a SnS2 layer.

[0015] Preferably, in order to improve the carrier mobility, in step S200, the front buffer layer includes a ZnO layer and a TiO2 layer stacked and connected or a MoS2 layer and a WS2 layer stacked and connected. The ZnO layer and the TiO2 layer are connected to the front electrode assembly and the front conductive film, respectively. The MoS2 layer and the WS2 layer are connected to the front electrode assembly and the front conductive film, respectively. The back buffer layer includes a MoO2 layer and a SnS2 layer stacked and connected. The MoO2 layer and the SnS2 layer are connected to the back electrode assembly and the back conductive film, respectively.

[0016] Preferably, in order to improve the deposition quality of the front buffer layer and the back buffer layer and facilitate the combination of multi-source co-evaporation, thereby improving the carrier mobility, in step S200, the front buffer layer and the back buffer layer are both formed by evaporation coating.

[0017] Preferably, in order to ensure the deposition of a stable and reliable metal oxide buffer layer and sulfide buffer layer, in step S200, the evaporation coating temperature of the MoO2 layer, the TiO2 layer, and the ZnO layer is 1500 - 2000 °C, the evaporation coating time is greater than 100 s, and the evaporation distance is 20 - 40 cm; the evaporation coating temperature of the MoS2 layer, the WS2 layer, and the SnS2 layer is 600 - 800 °C, the evaporation coating time is less than 120 s, and the evaporation distance is 10 - 20 cm.

[0018] In summary, compared with the prior art, in the novel single-junction heterojunction battery and its production process of the present invention, by laminating a buffer layer at least at one place between the front conductive film and the front electrode assembly and between the back conductive film and the back electrode assembly, the potential barrier is reduced, the loss of carriers at the transmission cross-section is reduced to improve the carrier mobility, thereby increasing the short-circuit current and the fill factor, which helps to improve the photoelectric conversion efficiency. Description of the Drawings

[0019] Figure 1 is a schematic structural diagram of a heterojunction battery of the first comparative example; Figure 2 is a schematic structural diagram of a heterojunction battery of the first embodiment; Figure 3 is a schematic structural diagram of a heterojunction battery of the second embodiment; Figure 4 is a schematic structural diagram of a heterojunction battery of the third embodiment; Figure 5 is a schematic structural diagram of a heterojunction battery of the fourth embodiment; Figure 6 is a schematic structural diagram of a heterojunction battery of the fifth embodiment; Figure 7 is a schematic structural diagram of a heterojunction battery of the sixth embodiment; Figure 8 is a schematic structural diagram of a heterojunction battery of the seventh embodiment; Figure 9 is a schematic structural diagram of a heterojunction battery of the eighth embodiment; Figure 10 is a schematic structural diagram of a heterojunction battery of the ninth embodiment; Figure 11 is a relevant performance data table of a heterojunction battery of the first comparative example; Figure 12 is a relevant performance data table of a heterojunction battery of the first embodiment; Figure 13 is a relevant performance data table of a heterojunction battery of the second embodiment; Figure 14 is a relevant performance data table of a heterojunction battery of the third embodiment; Figure 15 is a relevant performance data table of a heterojunction battery of the fourth embodiment; Figure 16 is a relevant performance data table of a heterojunction battery of the fifth embodiment; Figure 17 is a relevant performance data table of a heterojunction battery of the sixth embodiment; Figure 18 is a relevant performance data table of a heterojunction battery of the seventh embodiment; Figure 19It is the relevant performance data sheet of the heterojunction battery of the eighth embodiment; Figure 20 It is the relevant performance data sheet of the heterojunction battery of the ninth embodiment; Figure 21 It is the production process flow chart of the ninth embodiment of the present invention; Figure 22 It is the production process flow chart of the heterojunction composite layer in the ninth embodiment of the present invention; In the figure: 1, substrate layer; 11, light-receiving surface; 12, backlight surface; 2, front electrode assembly; 21, front intrinsic hydrogenated amorphous silicon layer; 22, n-type hydrogenated amorphous silicon layer; 3, back electrode assembly; 31, back intrinsic hydrogenated amorphous silicon layer; 32, p-type hydrogenated amorphous silicon layer; 4, front conductive film; 41, front electrode; 5, back conductive film; 51, back electrode; 6, front buffer layer; 7, back buffer layer; 81, MoO2 layer; 82, TiO2 layer; 83, ZnO layer; 84, MoS2 layer; 85, WS2 layer; 86, SnS2 layer. Specific embodiments

[0020] The following combines the drawings and embodiments to further describe the specific embodiments of the present invention. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention and cannot be used to limit the protection scope of the present invention.

[0021] The first comparative example As Figure 1 shown, the first comparative example, which is also a heterojunction battery of the prior art, includes a front conductive film 4, an n-type hydrogenated amorphous silicon layer 22, a front intrinsic hydrogenated amorphous silicon layer 21, a substrate layer 1, a back intrinsic hydrogenated amorphous silicon layer 31, a p-type hydrogenated amorphous silicon layer 32, and a back conductive film 5 that are sequentially stacked and connected. A front electrode 41 is provided on the side of the front conductive film 4 facing away from the substrate layer 1, and a back electrode 51 is provided on the side of the back conductive film 5 facing away from the substrate layer 1.

[0022] Among them, the substrate layer 1 is an n-type crystalline silicon with a thickness of 120 um. The two sides of the substrate layer 1 are respectively a light-receiving surface 11 and a backlight surface 12. The light-receiving surface 11 and the backlight surface 12 are distributed along the thickness direction of the substrate layer 1 and are respectively connected to the front intrinsic hydrogenated amorphous silicon layer 21 and the back intrinsic hydrogenated amorphous silicon layer 31.

[0023] The n-type hydrogenated amorphous silicon layer 22 and the front intrinsic hydrogenated amorphous silicon layer 21 are combined to form a front electrode assembly 2. The n-type hydrogenated amorphous silicon layer 22 is an n+ layer with a thickness of 15 nm, and the front intrinsic hydrogenated amorphous silicon layer 21 has a thickness of 9 nm; the back intrinsic hydrogenated amorphous silicon layer 31 and the p-type hydrogenated amorphous silicon layer 32 are combined to form a back electrode assembly 3. The p-type hydrogenated amorphous silicon layer 32 is a p+ layer with a thickness of 10 nm, and the back intrinsic hydrogenated amorphous silicon layer 31 has a thickness of 13 nm.

[0024] Both the front electrode 41 and the back electrode 51 are silver electrodes, and both the front conductive film 4 and the back conductive film 5 are ITO conductive films, with a thickness of 100 nm each.

[0025] In this comparative example, the front intrinsic hydrogenated amorphous silicon layer 21 and the back intrinsic hydrogenated amorphous silicon layer 31 are respectively deposited on the light-receiving surface 11 and the backlight surface 12 of the substrate layer 1. Their main function is to provide excellent surface passivation effects. Since there are a large number of dangling bonds on both sides of the substrate layer 1, these dangling bonds will capture minority carriers excited by light, leading to carrier recombination, thereby reducing the battery efficiency. However, the front intrinsic hydrogenated amorphous silicon layer 21 and the back intrinsic hydrogenated amorphous silicon layer 31 can effectively passivate these dangling bonds through hydrogenation, reducing surface defects, thereby increasing the minority carrier lifetime to improve the battery efficiency; the n-type hydrogenated amorphous silicon layer 22 is deposited on the front intrinsic hydrogenated amorphous silicon layer 21. The main function of this layer is to form a part of the PN junction. Through the PN junction, photo-generated carriers, that is, electrons and holes generated by photo-excitation, can be separated, enabling them to move towards the positive and negative electrodes of the battery respectively, thereby generating current. Similarly, the p-type hydrogenated amorphous silicon layer 32 is deposited on the back intrinsic hydrogenated amorphous silicon layer 31, and it is also a key part of forming the PN junction. The p-type hydrogenated amorphous silicon layer 32 forms a p-type semiconductor by doping with boron elements, while the n-type hydrogenated amorphous silicon layer 22 forms an n-type semiconductor by doping with phosphorus elements. The two together constitute a complete PN junction structure. Moreover, the n-type hydrogenated amorphous silicon layer 22 and the p-type hydrogenated amorphous silicon layer 32 also have excellent passivation effects, further reducing surface defects and carrier recombination, improving the battery efficiency, and thus optimizing the optoelectronic performance of the battery.

[0026] To accurately measure the relevant performance of the photovoltaic cell based on this comparative example, 5 heterojunction cell wafers with the above comparative example structure were selected for testing. The 5 comparative example cells are comparative samples A1 to comparative sample A5, and the Figure 11 table data shown below was obtained, where the photoelectric conversion efficiency is EFF (unit: %), the open-circuit voltage is Voc (unit: V), the short-circuit current is Isc (unit: A), and the fill factor is FF (unit: %).

[0027] First Embodiment As Figure 2 shown, a heterojunction cell according to the first embodiment of the present invention, based on the first comparative example, is different in that it further includes a buffer layer. The buffer layer includes a front buffer layer 6 laminated between the front electrode assembly 2 and the front conductive film 4. Preferably, the front buffer layer 6 is a TiO2 layer 82 with a thickness of 15 nm.

[0028] In the actual production process, the thickness of the TiO2 layer 82 can be controlled within 10 - 30 nm to achieve the passivation effect and reduce the interface state density.

[0029] Select 5 heterojunction solar cells with the structure of the above comparative example for testing. The 5 solar cells of this embodiment are the first samples B1 to B5, and the tabular data as shown in Figure 12 is obtained.

[0030] Taking the average value as a representative, compared with the first comparative example, for the heterojunction solar cell of this embodiment, the fill factor increases by 1.065%, and the photoelectric conversion efficiency increases by 0.273%.

[0031] Compared with the first comparative example, the TiO2 layer 82 can further improve the performance of the heterojunction solar cell. The main reasons are as follows: Firstly, the TiO2 layer 82 has a high carrier mobility, which helps the photo-generated carriers to be quickly transported at the interface, thereby reducing the loss during the transport process; Secondly, the TiO2 layer 82 can modify the microstructure of the transport interface, reduce the defects and impurities at the transport cross-section, and further reduce the interface state density, thereby reducing the recombination and leakage of carriers at the interface; Thirdly, through the TiO2 layer 82, its work function can also be adjusted to match that of the adjacent layer, which helps to reduce the barrier height at the interface, promote the smooth transport of carriers, and the precise matching of the work function can significantly increase the open-circuit voltage and short-circuit current density of the solar cell, thereby improving the overall efficiency of the solar cell. In addition, it can also reduce the light-induced degradation phenomenon of the solar cell under light conditions and extend the service life of the solar cell.

[0032] Generally speaking, the work function of the n-type hydrogenated amorphous silicon layer 22 is about 4.0 - 4.2 eV, and the work function of the front conductive film 4 is about 4.7 - 4.9 eV. A 15-nm TiO2 layer 82 is laminated between the n-type hydrogenated amorphous silicon layer 22 and the front conductive film 4, and its work function is 4.2 - 4.4 eV, which is between the work functions of the n-type hydrogenated amorphous silicon layer 22 and the front conductive film 4. The bottom of the conduction band of the TiO2 layer 82 matches the bottom of the conduction band of the n-type hydrogenated amorphous silicon layer 22, promoting electron transport, and the TiO2 layer 82 can play a passivation effect, repair interface defects, and reduce the interface state density. Therefore, while reducing recombination, the barrier is also reduced, further increasing the carrier mobility, which helps to improve the performance of the heterojunction solar cell.

[0033] In summary, selecting the TiO2 layer 82 as the front buffer layer 6 can reduce the barrier, increase the carrier mobility, reduce the transport loss, reduce the interface state density, reduce recombination and leakage; achieve precise matching of the work function, optimize the performance of the solar cell; significantly improve the efficiency of the solar cell and extend the service life.

[0034] Second Embodiment As Figure 3As shown, a heterojunction battery according to the second embodiment of the present invention is based on the first embodiment, and the difference is that the front buffer layer 6 is a ZnO layer 83 with a thickness of 10 nm. It should be noted that the thickness of the ZnO layer 83 is less than the thickness of the TiO2 layer 82 in the first embodiment, mainly based on the consideration of reducing light absorption and reducing light loss.

[0035] Five heterojunction battery chips with the above comparative structure were selected for testing. Five batteries of this embodiment are the second samples C5 to C5, and the tabular data as shown in Figure 13 was obtained.

[0036] Taking the average value as a representative, compared with the first comparative example, for the heterojunction battery of this embodiment, the open-circuit voltage increases by 0.396%, the short-circuit current increases by 0.755%, the fill factor increases by 1.065%, and the photoelectric conversion efficiency increases by 0.287%.

[0037] The overall improvement effect is similar to that of the first embodiment. The main reason is that the work function of the ZnO layer 83 is approximately 4.5 - 5.2 ev, and electrons can be transmitted at high speed in the ZnO layer 83, enabling it to match the n-type hydrogenated amorphous silicon layer 22, further improving the carrier mobility, so that the ZnO layer 83 can replace the TiO2 layer 82 in the first embodiment with a similar effect.

[0038] Third Embodiment As Figure 4 shown, a heterojunction battery according to the third embodiment of the present invention is based on the second embodiment, and the difference is that the front buffer layer 6 includes a ZnO layer 83 and a TiO2 layer 82 connected in a stacked manner, where the thickness of the ZnO layer 83 is 10 nm and the thickness of the TiO2 layer 82 is 15 nm. The TiO2 layer 82 and the ZnO layer 83 are respectively connected to the front electrode assembly 2 and the front conductive film 4.

[0039] Five heterojunction battery chips with the above comparative structure were selected for testing. Five batteries of this embodiment are the third samples D5 to D5, and the tabular data as shown in Figure 14 was obtained.

[0040] Taking the average value as a representative, compared with the second embodiment, for the heterojunction battery of this embodiment, the open-circuit voltage increases by 0.263%, the fill factor increases by 1.812%, and the photoelectric conversion efficiency increases by 0.207%.

[0041] Compared with the second embodiment, a ZnO layer 82 is stacked on the surface of the TiO2 layer 82 adjacent to the front conductive film 4. That is, the ZnO layer 82 and the TiO2 layer 82 together form the front buffer layer 6. In this stacked structure, the work functions of the n+ layer, the TiO2 layer 82, the ZnO layer 83, and the front conductive film 4 increase gradually, reducing the carrier transport barrier. In addition, this stacked structure takes into account high carrier mobility, light transmittance, and interface passivation, further improving the battery conversion efficiency.

[0042] Fourth Embodiment As Figure 5 shown, a heterojunction battery according to the fourth embodiment of the present invention is based on the first embodiment and the third embodiment. The difference is that the front buffer layer 6 includes a stacked and connected MoS2 layer 84 and WS2 layer 85, where the thickness of the MoS2 layer 84 is 2 nm and the thickness of the WS2 layer 85 is 2.5 nm. The MoS2 layer 84 and the WS2 layer 85 are respectively connected to the front electrode assembly 2 and the front conductive film 4.

[0043] It should be noted that in the above structure, if the MoS2 layer 84 is too thick, it will increase the series resistance, and the light absorption loss may cause a decrease in the short-circuit current. After the WS2 layer 85 adopts the above smaller thickness, it can accelerate the electron transfer to the front conductive film 4. The sum of the film layer thicknesses of the two is less than 5 nm, so that the light transmittance in the visible light band is greater than 95%, and the light loss can be ignored.

[0044] Select 5 heterojunction battery wafers with the above comparative structure for testing. The 5 batteries of this embodiment are the fourth samples E1 to E5, and the tabular data as Figure 15 shown is obtained.

[0045] Taking the average value as a representative, compared with the first comparative example, for the heterojunction battery of this embodiment, the open-circuit voltage increases by 0.528%, the short-circuit current increases by 0.092%, the fill factor increases by 0.229%, and the photoelectric conversion efficiency increases by 0.2%.

[0046] Compared with the first comparative example, the front buffer layer 6 composed of the double-layer sulfide buffer layer can also increase the photoelectric conversion efficiency of the heterojunction battery. The reason is as follows: The two-dimensional layered structure of the MoS2 layer 84 and the WS2 layer 85 can effectively passivate the dangling bonds and defect states at the interface, reducing the interface non-radiative recombination. In addition, this stacked structure has a high light transmittance, allowing more photons to penetrate to the silicon substrate. On the other hand, the MoS2 layer 84 and the WS2 layer 85 themselves have a high carrier mobility. Generally speaking, it can effectively optimize the performance of the solar cell.

[0047] Fifth Embodiment As Figure 6As shown in the figure, a heterojunction battery according to the fifth embodiment of the present invention is based on the first embodiment and the first comparative example, and is different in that the buffer layer includes a back buffer layer 7 stacked between the back electrode assembly 3 and the back conductive film 5, and the back buffer layer 7 is a MoO2 layer 81 with a thickness of 10 nm.

[0048] It should be noted that in the actual production process, the MoO2 layer 81 can also be controlled within 5 - 15 nm. The main reason is that when the MoO2 layer 81 is too thin, pinhole defects will occur, and when it is too thick, the series resistance will increase, reducing the battery performance.

[0049] Five heterojunction battery wafers with the above - mentioned comparative - example structure were selected for testing. Five batteries of this embodiment are the fifth samples F1 to F5, and the following ​ shown tabular data were obtained.

[0050] Taking the average value as a representative, compared with the first comparative example, for the heterojunction battery of this embodiment, the open - circuit voltage increases by 0.132%, the short - circuit current increases by 0.240%, the fill factor increases by 1.249%, and the photoelectric conversion efficiency increases by 0.392%.

[0051] Compared with the first comparative example, the back buffer layer 7 can also further improve the performance of the heterojunction battery. The main reasons are as follows: Firstly, the back buffer layer 7 has good electrical conductivity and carrier - transport performance. When used as a transport - layer material, it can improve the carrier - transport efficiency, effectively help the photoelectrons to be quickly transported, and thus improve the photoelectric conversion efficiency. Secondly, the back buffer layer 7 can modify the microstructure of the transport interface, reduce the defects and impurities at the transport cross - section, and further reduce the interface - state density, thereby reducing the recombination and leakage of carriers at the interface, and improving the chemical stability and thermal stability of the interface, preventing the interface from degrading during long - term use. Thirdly, the back buffer layer 7 adjusts its work function to match that of the adjacent layer, which helps to reduce the barrier height at the interface, improve the carrier - transport efficiency, thereby significantly increasing the open - circuit voltage and short - circuit current density of the battery, realizing the improvement of the overall efficiency of the battery. In addition, it also reduces the light - induced degradation phenomenon of the battery under light illumination conditions and extends the service life of the battery.

[0052] Using a 10-nm-thick MoO2 layer 81 as the back buffer layer 7, the work function of the p-type hydrogenated amorphous silicon layer 32 is 5.0 - 5.2 eV, and the work function of the MoO2 layer 81 is 5.3 - 5.7 eV. A hole-selective contact is formed through band bending, reducing recombination and improving carrier mobility. The MoO2 layer 81 is significantly effective as a hole transport layer in the organic / inorganic heterojunction. Therefore, by laminating the MoO2 layer 81 as the back buffer layer 7 between the p-type hydrogenated amorphous silicon layer 32 and the back conductive film 5, the potential barrier can be reduced and the carrier mobility can be enhanced, thereby improving the photoelectric conversion efficiency.

[0053] In summary, selecting the MoO2 layer 81 as the back buffer layer 7 can reduce the loss during carrier transport, reduce carrier recombination, improve carrier transport efficiency, and optimize the battery performance through precise matching of the work functions, extending the battery life while improving the photoelectric conversion efficiency of the battery.

[0054] Sixth Embodiment As ​ shown, a heterojunction battery according to the sixth embodiment of the present invention is based on the fifth embodiment, and the difference lies in that the back buffer layer 7 is a laminated connection of the MoO2 layer 81 and the SnS2 layer 86, where the thickness of the MoO2 layer 81 is 10 nm and the thickness of the SnS2 layer 86 is 5 nm. The MoO2 layer 81 and the SnS2 layer 86 are respectively connected to the back electrode assembly 3 and the back conductive film 5.

[0055] Five heterojunction battery cells with the above comparative structure were selected for testing. Five such cells of this embodiment were the sixth samples G1 to G5, and the tabular data as ​ shown was obtained.

[0056] Taking the average value as a representative, compared with the fifth embodiment, for the heterojunction battery of this embodiment, the open-circuit voltage remains basically unchanged, the short-circuit current increases by 0.103%, the fill factor increases by 0.509%, and the photoelectric conversion efficiency increases by 0.108%.

[0057] Compared with the fifth embodiment, the SnS2 layer 86 is laminated on the side of the MoO2 layer 81 adjacent to the back conductive film 5. Through the SnS2 layer 86, a transition can be achieved, gradually reducing the work function and the potential barrier. Its crystallinity is better than that of the fifth embodiment, and it can provide a higher carrier mobility channel, making the mobility improvement in this embodiment more obvious, and thus contributing to improving the performance of the heterojunction battery.

[0058] Seventh Embodiment As ​As shown in the figure, a heterojunction cell according to the seventh embodiment of the present invention is based on the fourth embodiment, and is different in that the buffer layer includes a front buffer layer 6 and a back buffer layer 7. The front buffer layer 6 includes a stacked MoS2 layer 84 and WS2 layer 85. The thickness of the MoS2 layer 84 is 2 nm, and the thickness of the WS2 layer 85 is 2.5 nm. The MoS2 layer 84 and the WS2 layer 85 are respectively connected to the front electrode assembly 2 and the front conductive film 4. The back buffer layer 7 is a MoO2 layer 81 with a thickness of 10 nm.

[0059] Five heterojunction cell wafers with the above comparative structure were selected for testing. Five cells of this embodiment are the seventh samples H1 to H5, and the tabular data as shown in ​ the following were obtained.

[0060] Taking the average value as a representative, compared with the fourth embodiment, the heterojunction cell of this embodiment has a fill factor increase of 0.719% and a photoelectric conversion efficiency increase of 0.181%.

[0061] Compared with the fourth embodiment, on the basis of the same structure of the front buffer layer 6, due to the addition of the back buffer layer 7, the MoO2 layer 8 within the back buffer layer 7 can not only reduce the potential barrier, but also help improve the carrier mobility, thereby improving the performance of the heterojunction cell.

[0062] Eighth Embodiment As shown in ​ the figure, a heterojunction cell according to the eighth embodiment of the present invention is based on the fifth embodiment, and is different in that the buffer layer includes a front buffer layer 6 and a back buffer layer 7. The front buffer layer 6 is a TiO2 layer 82 with a thickness of 15 nm, and the back buffer layer 7 is a MoO2 layer 81 with a thickness of 10 nm.

[0063] Five heterojunction cell wafers with the above comparative structure were selected for testing. Five cells of this embodiment are the eighth samples I1 to I5, and the tabular data as shown in ​ the following were obtained.

[0064] Taking the average value as a representative, compared with the fifth embodiment, the heterojunction cell of this embodiment has an open circuit voltage increase of 0.132%, a fill factor increase of 0.613%, and a photoelectric conversion efficiency increase of 0.205%.

[0065] Compared with the fifth embodiment, on the basis of the same structure of the back buffer layer 7, due to the addition of the front buffer layer 6, the conduction band bottom of the TiO2 layer 82 can match the conduction band bottom of the n-type hydrogenated amorphous silicon layer 22, thereby promoting electron transport, reducing the potential barrier, and having a passivation effect to reduce the interface state density, thereby improving the performance of the heterojunction cell.

[0066] Ninth Embodiment As shown in ​As shown in the figure, a heterojunction battery according to the ninth embodiment of the present invention is based on the third and eighth embodiments. The difference lies in that the buffer layer includes a front buffer layer 6 and a back buffer layer 7. The front buffer layer 6 includes a ZnO layer 83 and a TiO2 layer 82 connected in a stacked manner. The thickness of the ZnO layer 83 is 10 nm, and the thickness of the TiO2 layer 82 is 15 nm. The TiO2 layer 82 and the ZnO layer 83 are respectively connected to the front electrode assembly 2 and the front conductive film 4. The back buffer layer 7 includes a MoO2 layer 81 and a SnS2 layer 86 connected in a stacked manner. The thickness of the MoO2 layer 81 is 10 nm, and the thickness of the SnS2 layer 86 is 5 nm. The MoO2 layer 81 and the SnS2 layer 86 are respectively connected to the back electrode assembly 3 and the back conductive film 5.

[0067] Five heterojunction battery wafers with the above comparative structure were selected for testing. Five such batteries in this embodiment were the ninth samples J1 to J5, and the tabular data as shown in ​ was obtained.

[0068] Taking the average value as a representative, compared with the eighth embodiment, for the heterojunction battery in this embodiment, the open-circuit voltage increased by 0.263%, the short-circuit current increased by 0.011%, the fill factor increased by 0.410%, and the photoelectric conversion efficiency increased by 0.157%.

[0069] Both the front buffer layer 6 and the back buffer layer 7 adopt a double-layer structure. Compared with the eighth embodiment where both the front buffer layer 6 and the back buffer layer 7 adopt a single-layer structure, the technical effects of further reducing the potential barrier, repairing cross-sectional defects, and improving the carrier mobility are achieved, so that the performance indicators of the heterojunction battery in this embodiment are all improved.

[0070] As shown in ​ , the present invention also provides a production process for producing the novel single-junction heterojunction battery according to the ninth embodiment, including the following steps: S100. Prepare a heterojunction composite layer: The heterojunction composite layer includes a front electrode assembly 2, a substrate layer 1, and a back electrode assembly 3 connected in a stacked manner in sequence; S200. Deposit a buffer layer: Deposit a buffer layer on at least one side of the heterojunction composite layer obtained in S100 to improve the carrier mobility; S300. Deposit conductive films: Deposit a front conductive film 4 and a back conductive film 5 on both sides of the composite layer structure obtained in S200 respectively. The front conductive film 4 is adjacent to the front electrode assembly 2, and the back conductive film 5 is adjacent to the back electrode assembly 3; S400. Prepare electrodes: Prepare a front electrode 41 and a back electrode 51 on the front conductive film 4 and the back conductive film 5 obtained in S200 respectively.

[0071] As shown in ​ , step S100 includes the following steps: S101, cleaning and texturing the substrate layer 1, wherein the substrate layer 1 is n-type crystalline silicon, has a thickness of 120 μm, and has a light-receiving surface 11 and a backlight surface 12 distributed along its thickness direction; S102, depositing a front intrinsic hydrogenated amorphous silicon layer 21 and a back intrinsic hydrogenated amorphous silicon layer 31 on the light-receiving surface 11 and the backlight-receiving surface 12 of the substrate layer 1 obtained in S101, respectively, wherein the deposition thickness of the front intrinsic hydrogenated amorphous silicon layer 21 is 9 nm, and the deposition thickness of the back intrinsic hydrogenated amorphous silicon layer 31 is 13 nm; S103, depositing an n-type hydrogenated amorphous silicon layer 22, i.e., an n+ layer, on the front intrinsic hydrogenated amorphous silicon layer 21 obtained in S102, so that the front intrinsic hydrogenated amorphous silicon layer 21 and the n-type hydrogenated amorphous silicon layer 22 are combined to form a front electrode assembly 2, and depositing a p-type hydrogenated amorphous silicon layer 32, i.e., a p+ layer, on the back intrinsic hydrogenated amorphous silicon layer 31, so that the back intrinsic hydrogenated amorphous silicon layer 31 and the p-type hydrogenated amorphous silicon layer 32 are combined to form a back electrode assembly 3, wherein the deposition thickness of the n-type hydrogenated amorphous silicon layer 22 is 15 nm, and the deposition thickness of the p-type hydrogenated amorphous silicon layer 32 is 10 nm; In step S200, a front buffer layer 6 and a back buffer layer 7 are deposited on the front electrode assembly 2 and the back electrode assembly 3, respectively. The front buffer layer 6 and the back buffer layer 7 each include at least one of a MoO2 layer 81, a TiO2 layer 82, a ZnO layer 83, a MoS2 layer 84, a WS2 layer 85 and a SnS2 layer 86.

[0072] Specifically, the front buffer layer 6 includes a ZnO layer 83 and a TiO2 layer 82 connected in a stacked manner, wherein the thickness of the ZnO layer 83 is 10 nm, the thickness of the TiO2 layer 82 is 15 nm, and the TiO2 layer 82 and the ZnO layer 83 are respectively connected to the front electrode assembly 2 and the front conductive film 4; the back buffer layer 7 includes a MoO2 layer 81 and a SnS2 layer 86 connected in a stacked manner, wherein the thickness of the MoO2 layer 81 is 10 nm, the thickness of the SnS2 layer 86 is 5 nm, and the MoO2 layer 81 and the SnS2 layer 86 are respectively connected to the back electrode assembly 3 and the back conductive film 5.

[0073] In step S300 , the front conductive film 4 and the back conductive film 5 are both ITO conductive films, and the deposition thickness of the front conductive film 4 and the back conductive film 5 are both 100 nm.

[0074] In step S400 , the front electrode 41 and the back electrode 51 are both formed by metal grid line printing, and both the front electrode 41 and the back electrode 51 are silver electrodes.

[0075] A further improvement is that in step S200 , the front buffer layer 6 and the back buffer layer 7 are both formed by evaporation.

[0076] Compared with other deposition methods, the use of evaporation deposition to form the front buffer layer 6 and the back buffer layer 7 has the following advantages: First, high deposition speed and efficiency: During the evaporation process, by heating the bulk metal in the crucible in a vacuum to reach its vapor pressure and volatilize particles, these particles can be rapidly deposited on the surfaces of the front electrode assembly 2 and the back electrode assembly 3 to form a thin film. This method can significantly increase the deposition speed and shorten the production cycle. Second, high quality of the deposited thin film: The thin film formed by evaporation deposition has good directionality, uniform and dense thickness. Especially in electron beam evaporation, since the heated metal area is very small and the temperature at the place where the metal contacts the crucible is not high, the quality and performance of the front buffer layer 6 and the back buffer layer 7 can be more effectively controlled. Third, wide application range: The evaporation method is applicable to a variety of materials, including transition metal oxides and sulfides with high melting points. And by adjusting the evaporation parameters, the front buffer layer 6 and the back buffer layer 7 with different physical and chemical properties can be prepared. Fourth, good process controllability: The process parameters during the evaporation process, such as temperature, pressure, deposition rate, etc., can be precisely controlled, which helps to deposit and form the front buffer layer 6 and the back buffer layer 7 with specific structures and properties to meet different application requirements.

[0077] In addition, during the evaporation process, the material only undergoes physical phase changes (solid state → gaseous state → solid state), avoiding the introduction of impurities due to chemical reactions (such as Ar embedding in sputtering). The kinetic energy of the evaporated particles is relatively low. Compared with magnetron sputtering, it reduces substrate damage and interface defects (such as dangling bonds on the amorphous silicon surface). At the same time, the evaporation process is applicable to materials that are easy to decompose, such as SnS2, and sulfur volatilization is avoided through low-temperature evaporation. In terms of process flexibility, the evaporation process can combine multi-source co-evaporation (such as Mo + SnS2 stack) to achieve gradient composition design.

[0078] By depositing the front buffer layer 6 and the back buffer layer 7 on the front electrode assembly 2 and the back electrode assembly 3 respectively, the front buffer layer 6 includes a ZnO layer 83 and a TiO2 layer 82 connected in layers, and the back buffer layer 7 includes a MoO2 layer 81 and a SnS2 layer 86 connected in layers, which can effectively improve the carrier transport cross-section characteristics in the heterojunction battery, improve the electrical conductivity, heat resistance of the photovoltaic cell, and also enhance the mechanical strength, thereby improving the overall performance of the heterojunction battery; moreover, the front buffer layer 6 and the back buffer layer 7 formed by evaporation deposition have good adhesion with the front electrode assembly 2 and the back electrode assembly 3 respectively, ensuring that the front buffer layer 6 and the back buffer layer 7 will not fall off or peel off during the subsequent battery production and processing, resulting in a reduction in battery quality; in addition, compared with other equipment technologies (such as sputtering coating, ion coating, etc.), the evaporation method has relatively simple equipment and convenient operation, which helps to reduce production costs and improve production efficiency.

[0079] Through the front buffer layer 6 and the back buffer layer 7, the carrier loss in the transmission cross-section can be effectively reduced, the carrier mobility can be improved, thereby reducing the contact resistance, and reducing the barrier in the transmission cross-section, repairing some defects in the transmission interface, thereby reducing the carrier recombination, further increasing the open-circuit voltage and short-circuit current, and finally improving the power generation efficiency of the heterojunction battery.

[0080] A further improvement is that in step S200, the evaporation temperature of the MoO2 layer 81, the TiO2 layer 82, and the ZnO layer 83 is 1500 - 2000 °C, the evaporation time is greater than 100 s, and the evaporation distance is 20 - 40 cm; the evaporation temperature of the SnS2 layer 86 is 600 - 800 °C, the evaporation time is less than 120 s, and the evaporation distance is 10 - 20 cm.

[0081] During the evaporation process, the vacuum pressure is controlled between 1x10 -4 -5x10 -6 Torr. The evaporation temperature, pressure, time, etc. need to be determined according to the physical properties of the source material. For example, the evaporation temperature of metal oxides is relatively high, between 1500 - 2000 °C, the evaporation time is more than 100 s, and the evaporation distance is about 20 - 40 cm. Metal oxides are not easily decomposed at high temperatures, and the evaporation rate is slow. It takes a longer time to reach the target thickness and can be stably evaporated for a long time. The evaporation distance is mainly because the evaporation particles of high-melting-point materials have low kinetic energy and are prone to cooling and condensation during long-distance transmission, so the evaporation distance needs to be shortened to improve the deposition efficiency; the evaporation temperature of metal sulfides is relatively low, about 600 - 800 °C, the evaporation time is within 120 s, and the evaporation distance is 10 - 20 cm. Sulfides have a low melting point and sulfur elements are volatile. Sulfides are easily decomposed at high temperatures. It is necessary to control the evaporation temperature and time and shorten the evaporation distance at the same time to avoid composition deviation, usually by shortening the evaporation time or introducing sulfur vapor compensation.

[0082] ​

Claims

1. A novel single-junction heterojunction battery, comprising: A substrate layer having a light-receiving surface and a backlight surface; A front electrode assembly and a back electrode assembly, respectively laminated on the light-receiving surface and the backlight surface, and both are used to generate photo-generated carriers by forming a PN junction; A front conductive film, laminated on the side of the front electrode assembly facing away from the substrate layer and connected to a front electrode; A back conductive film, laminated on the side of the back electrode assembly facing away from the substrate layer and connected to a back electrode; It is characterized in that it further comprises: A buffer layer, laminated between the front electrode assembly and the front conductive film, and / or between the back electrode assembly and the back conductive film, to reduce the potential barrier and improve the carrier mobility.

2. The novel single-junction heterojunction battery according to claim 1, wherein: The buffer layer includes a front buffer layer and a back buffer layer. The front buffer layer is laminated between the front electrode assembly and the front conductive film, and the back buffer layer is laminated between the back electrode assembly and the back conductive film.

3. The novel single-junction heterojunction cell according to claim 2, wherein: Both the front buffer layer and the back buffer layer include at least one of a MoO2 layer, a TiO2 layer, a ZnO layer, a MoS2 layer, a WS2 layer, and a SnS2 layer.

4. The novel single-junction heterojunction cell according to claim 3, wherein: The front buffer layer includes a ZnO layer and a TiO2 layer laminated and connected, or a MoS2 layer and a WS2 layer laminated and connected. The TiO2 layer and the ZnO layer are respectively connected to the front electrode assembly and the front conductive film, and the MoS2 layer and the WS2 layer are respectively connected to the front electrode assembly and the front conductive film; The back buffer layer includes a MoO2 layer and a SnS2 layer laminated and connected. The MoO2 layer and the SnS2 layer are respectively connected to the back electrode assembly and the back conductive film.

5. The novel single-junction heterojunction cell according to claim 4, characterized in that: The thicknesses of the ZnO layer and the TiO2 layer, the MoO2 layer and the SnS2 layer are both 5 - 20 nm, and the thicknesses of the MoS2 layer and the WS2 layer are respectively 1 - 3 nm and 2 - 5 nm.

6. A production process of a novel single-junction heterojunction battery, characterized in that, Including the following steps: S100. Prepare a heterojunction composite layer: The heterojunction composite layer includes a front electrode assembly, a substrate layer, and a back electrode assembly laminated and connected in sequence; S200. Deposit a buffer layer: Deposit a buffer layer on at least one surface of the heterojunction composite layer obtained in S100 to reduce the potential barrier and improve the carrier mobility; S300. Deposit a conductive film: Deposit a front conductive film and a back conductive film on both sides of the composite layer structure obtained in S200. The front conductive film is adjacent to the front electrode assembly, and the back conductive film is adjacent to the back electrode assembly; S400. Prepare electrodes: Prepare a front electrode and a back electrode on the front conductive film and the back conductive film obtained in S200 respectively.

7. The production process of the single-junction heterojunction cell according to claim 6, characterized in that: In step S200, a front buffer layer and a back buffer layer are respectively deposited on the front electrode assembly and the back electrode assembly. Both the front buffer layer and the back buffer layer include at least one of a MoO2 layer, a TiO2 layer, a ZnO layer, a MoS2 layer, a WS2 layer, and a SnS2 layer.

8. The production process of the single-junction heterojunction cell according to claim 7, characterized in that: In the step S200, the front buffer layer includes a ZnO layer and a TiO2 layer connected in a stacked manner or a MoS2 layer and a WS2 layer connected in a stacked manner. The ZnO layer and the TiO2 layer are respectively connected to the front electrode assembly and the front conductive film, and the MoS2 layer and the WS2 layer are respectively connected to the front electrode assembly and the front conductive film; The back buffer layer includes a MoO₂ layer and a SnS₂ layer connected in a stacked manner. The MoO₂ layer and the SnS₂ layer are respectively connected to the back electrode assembly and the back conductive film.

9. The production process of the single-junction heterojunction cell according to claim 7, characterized in that: In the step S200, both the front buffer layer and the back buffer layer are formed by evaporation coating.

10. The production process of the single-junction heterojunction cell according to claim 9, characterized in that: In the step S200, the evaporation coating temperature of the MoO₂ layer, the TiO₂ layer, and the ZnO layer is 1500 - 2000 °C, the evaporation coating time is greater than 100 s, and the evaporation coating distance is 20 - 40 cm; the evaporation coating temperature of the MoS₂ layer, the WS₂ layer, and the SnS₂ layer is 600 - 800 °C, the evaporation coating time is less than 120 s, and the evaporation coating distance is 10 - 20 cm.

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