Embedded electrode gallium nitride photoconductive switch and preparation method thereof

Abstract

The invention belongs to the technical field of solid-state narrow-spectrum high-power microwaves, and particularly relates to an embedded electrode gallium nitride photoconductive switch and a preparation method thereof. Comprising a substrate, the upper surface of which is provided with an anode groove and a cathode groove with the same structure at intervals; along the thickness direction of the substrate, an anode doped gallium nitride layer, an anode ohmic contact layer and an anode packaging layer are sequentially arranged in the anode groove from bottom to top. A cathode doped gallium nitride layer, a cathode ohmic contact layer and a cathode packaging layer which are in one-to-one correspondence with the interiors of the anode grooves are sequentially arranged in the cathode groove from bottom to top along the thickness direction of the substrate; the dielectric passivation layer is arranged on the upper surface of the substrate, and the upper surface of the anode packaging layer and the upper surface of the cathode packaging layer are both in contact with the lower surface of the dielectric passivation layer; and the light-triggered antireflection layer is arranged on the lower surface of the substrate. The gallium nitride photoconductive switch is innovatively designed on the basis of a gallium nitride photoconductive switch structure, and the problem of balance between high-power output and high-frequency photoelectric response of an existing gallium nitride photoconductive switch can be solved.

Description

Technical Field

[0001] The present invention belongs to the technical field of solid-state narrow-spectrum high-power microwave, and particularly relates to an embedded electrode gallium nitride photoconductive switch and a preparation method thereof. Background Art

[0002] As an "invisible sharp weapon" on the high-tech battlefield, high-power microwave can instantaneously disable or permanently damage electronic devices, showing great value in information confrontation and other aspects. The damage effect of high-power microwave on the target is mainly determined by factors such as the microwave power density reaching the target, microwave frequency, and the coupling characteristics of the target. Narrow-spectrum high-power microwave can concentrate energy in a specific frequency range compared with wide-spectrum, so as to achieve high-power density output, and has characteristics such as strong penetration ability and long-distance transmission.

[0003] The advantage of traditional microwave technology based on vacuum electronic devices lies in high peak power, which can reach the gigawatt level, but it is difficult to adaptively adjust the output microwave frequency. Microwave technology based on microelectronic power amplifiers can achieve high-frequency output in the millimeter wave band, but the single-chip peak power is low (< kilowatt), and usually higher power output is achieved through multi-channel synthesis. The complexity and cost of the system will face major challenges. Therefore, integrating photoconductive switch technology, high-repetition-rate pulsed laser technology, and pulsed power technology, and using pulsed carrier-frequency laser to control photoconductive switch can generate high-power microwave, which is a brand-new technical route.

[0004] Wide-bandgap gallium nitride is relatively new in material technology, and the output power of its photoconductive switch is temporarily inferior to that of SiC devices. However, gallium nitride has higher electron mobility and saturated electron drift velocity than silicon carbide, its photoconductive device has a faster switching speed, and gallium nitride has a higher photoelectric conversion efficiency than silicon carbide, showing advantages in the field of narrow-spectrum high-power microwave. In addition, semi-insulating gallium nitride is mainly achieved through doping. Without affecting the high-resistance characteristics, its doping solubility is much higher than that of silicon carbide. Composite centers can be introduced into gallium nitride through deep-level doping to regulate the carrier lifetime, so that the device can obtain more excellent high-frequency photoelectric response. These characteristics provide strong support for constructing a narrow-spectrum high-power microwave system based on gallium nitride photoconductive switch.

[0005] However, due to the relatively late start of the crystal growth technology development of gallium nitride photoconductive switch compared with silicon carbide, there are still technical bottlenecks in high-power output and high-frequency photoelectric response. Therefore, it is of great significance to study gallium nitride photoconductive switches with improved high-power output and high-frequency photoelectric response to meet the application requirements of narrow-spectrum high-power microwave systems. Summary of the Invention

[0006] To solve the above problems, the present invention provides an embedded electrode gallium nitride photoconductive switch and a preparation method thereof. The present invention innovatively designs based on the structure of the gallium nitride photoconductive switch, which can solve the balance problem between high-power output and high-frequency photoresponse of the existing gallium nitride photoconductive switch, and helps to promote the development of photoconductive narrow-spectrum microwave technology.

[0007] The present invention solves the above technical problems through the following technical solutions.

[0008] On the one hand, the present invention provides an embedded electrode gallium nitride photoconductive switch, including: A substrate, on the upper surface of which an anode groove and a cathode groove with the same structure are provided at intervals; Along the thickness direction of the substrate, an anodic doped gallium nitride layer, an anodic ohmic contact adhesion layer, an anodic ohmic contact barrier layer, an anodic ohmic contact blocking layer, an anodic ohmic contact antioxidant layer and an anodic encapsulation layer are sequentially arranged in the anode groove from bottom to top; Along the thickness direction of the substrate, a cathodic doped gallium nitride layer, a cathodic ohmic contact adhesion layer, a cathodic ohmic contact barrier layer, a cathodic ohmic contact blocking layer, a cathodic ohmic contact antioxidant layer and a cathodic encapsulation layer corresponding to those in the anode groove one by one are sequentially arranged in the cathode groove from bottom to top; the upper surfaces of the anodic encapsulation layer, the cathodic encapsulation layer and the upper surface of the substrate are in the same horizontal plane; A dielectric passivation layer, which is arranged on the upper surface of the substrate, and the upper surfaces of the anodic encapsulation layer and the cathodic encapsulation layer are both in contact with the lower surface of the dielectric passivation layer; A light-triggered antireflection layer, which is arranged on the lower surface of the substrate.

[0009] Further, the substrate is a semi-insulating gallium nitride layer with a thickness of 100 μm to 150 μm.

[0010] Further, the depths of the anode groove and the cathode groove are both 2 μm to 2.5 μm.

[0011] Further, both the anodic doped gallium nitride layer and the cathodic doped gallium nitride layer are doped gallium nitride layers with a thickness of 0.5 μm to 1.0 μm.

[0012] Further, the anodic ohmic contact adhesion layer is a first titanium metal layer with a thickness of 10 nm to 20 nm; the anodic ohmic contact barrier layer is a first aluminum metal layer with a thickness of 110 nm to 120 nm; the anodic ohmic contact blocking layer is a first palladium metal layer with a thickness of 45 nm to 55 nm; the anodic ohmic contact antioxidant layer is a first gold metal layer with a thickness of 40 nm to 50 nm.

[0013] Further, the cathode ohmic contact adhesion layer is a second titanium metal layer with a thickness of 10 nm to 20 nm; the cathode ohmic contact barrier layer is a second aluminum metal layer with a thickness of 110 nm to 120 nm; the cathode ohmic contact blocking layer is a second palladium metal layer with a thickness of 45 nm to 55 nm; the cathode ohmic contact antioxidant layer is a second gold metal layer with a thickness of 40 nm to 50 nm.

[0014] Further, the anode encapsulation layer includes an anode encapsulation adhesion layer and an anode encapsulation welding layer sequentially arranged from bottom to top along the thickness direction of the substrate, and the cathode encapsulation layer includes a cathode encapsulation adhesion layer and a cathode encapsulation welding layer sequentially arranged from bottom to top along the thickness direction of the substrate; both the anode encapsulation adhesion layer and the cathode encapsulation adhesion layer are nickel metal layers with a thickness of 20 nm to 30 nm; both the anode encapsulation welding layer and the cathode encapsulation welding layer are third gold metal layers with a thickness of 500 nm to 800 nm.

[0015] Further, the dielectric passivation layer is a silicon nitride layer with a thickness of 220 nm to 250 nm; the optical trigger antireflection layer is a first silicon oxide layer with a thickness of 90 nm to 100 nm.

[0016] On the other hand, the present invention provides a method for manufacturing the above-mentioned embedded electrode gallium nitride photoconductive switch, including the following steps: Step 1, provide a substrate.

[0017] Step 2, deposit a protective layer on the upper surface of the substrate.

[0018] Step 3, partially etch the protective layer to expose the etched areas of the anode groove and the cathode groove on the upper surface of the substrate.

[0019] Step 4, etch the etched area again to obtain the anode groove and the cathode groove.

[0020] Step 5, deposit an anodic doped gallium nitride layer and a cathodic doped gallium nitride layer on the anode groove and the cathode groove respectively.

[0021] Step 6, remove the protective layer on the upper surface of the substrate.

[0022] Step 7, sequentially deposit an anode ohmic contact adhesion layer, an anode ohmic contact barrier layer, an anode ohmic contact blocking layer, and an anode ohmic contact antioxidant layer on the upper surface of the anodic doped gallium nitride layer, and sequentially deposit a cathode ohmic contact adhesion layer, a cathode ohmic contact barrier layer, a cathode ohmic contact blocking layer, and a cathode ohmic contact antioxidant layer on the upper surface of the cathodic doped gallium nitride layer; then perform an alloying treatment.

[0023] Step 8, deposit an anode encapsulation layer and a cathode encapsulation layer on the upper surface of the anode ohmic contact antioxidant layer and the upper surface of the cathode ohmic contact antioxidant layer respectively.

[0024] Step 9: Deposit a silicon nitride layer on the upper surface of the substrate, the upper surface of the anode encapsulation layer, and the upper surface of the cathode encapsulation layer.

[0025] Step 10: Partially etch the silicon nitride layer to expose the anode encapsulation layer and the cathode encapsulation layer, forming a dielectric passivation layer. Among them, the upper surface of the anode encapsulation layer is in contact with the lower surface of the dielectric passivation layer, and the upper surface of the cathode encapsulation layer is in contact with the lower surface of the dielectric passivation layer.

[0026] Step 11: Grind and thin the lower surface of the substrate to form a substrate.

[0027] Step 12: Deposit a light-triggered antireflection layer on the lower surface of the substrate; form an embedded electrode gallium nitride photoconductive switch.

[0028] Furthermore, the substrate is a semi-insulating gallium nitride single crystal with a thickness of 325 μm to 350 μm; the protective layer is a second silicon oxide layer with a thickness of 90 nm to 110 nm, the temperature of the alloying treatment is 750 °C to 850 °C, and the time is 40 s to 60 s; after depositing the light-triggered antireflection layer on the lower surface of the substrate, annealing is performed to repair the interface defects to obtain an embedded electrode gallium nitride photoconductive switch. The temperature for annealing and repairing the interface defects is 110 °C to 130 °C, and the gas used is carbon dioxide.

[0029] The present invention has the following beneficial effects compared with the prior art: The embedded electrode gallium nitride photoconductive switch provided by the present invention constructs anode grooves and cathode grooves with specific morphologies on the gallium nitride surface, and deposits an embedded doped gallium nitride layer, an ohmic contact layer, and an encapsulation layer on the anode grooves and cathode grooves respectively. The ohmic contact layer is successively an ohmic contact adhesion layer, an ohmic contact barrier layer, an ohmic contact blocking layer, and an ohmic contact antioxidant layer. By reconstructing the traditional lateral current path into a three-dimensional distribution, this structural design makes the current channel embedded in the material body region rather than on the surface, effectively suppressing the surface flashover phenomenon, and the breakdown voltage is greatly improved compared with the traditional planar structure; by optimizing the groove depth and distribution density, the parasitic capacitance of the device itself can be significantly reduced, further improving the high-frequency response of the device. The doped gallium nitride layer and the multi-layer metal electrode act synergistically to further reduce the contact resistivity and achieve low-loss ohmic contact. The encapsulation metal layer helps with reliable electrical connection to the external circuit. Description of the Drawings

[0030] Figure 1 It is a structural schematic diagram of the embedded electrode gallium nitride photoconductive switch of the present invention.

[0031] Figure 2 It is an overall structural schematic diagram of the embedded electrode gallium nitride photoconductive switch of the present invention.

[0032] Figure 3 This is a schematic process flow diagram of the embedded electrode gallium nitride photoconductive switch of the present invention. Specific embodiments

[0033] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0034] The present invention provides an embedded electrode gallium nitride photoconductive switch, as Figure 1 shown, including: A substrate 1, on the upper surface of which there are anode grooves and cathode grooves with the same structure at intervals; along the thickness direction of the substrate 1, an anode-doped gallium nitride layer 2, an anode ohmic contact adhesion layer 3, an anode ohmic contact barrier layer 4, an anode ohmic contact blocking layer 5, an anode ohmic contact antioxidant layer 6, and an anode encapsulation layer 7 are sequentially arranged from bottom to top in the anode groove; along the thickness direction of the substrate 1, a cathode-doped gallium nitride layer 8, a cathode ohmic contact adhesion layer 9, a cathode ohmic contact barrier layer 10, a cathode ohmic contact blocking layer 11, a cathode ohmic contact antioxidant layer 12, and a cathode encapsulation layer 13 that correspond one by one to those in the anode groove are sequentially arranged from bottom to top in the cathode groove; a dielectric passivation layer 14, which is arranged on the upper surface of the substrate 1, and the upper surfaces of the anode encapsulation layer 7 and the cathode encapsulation layer 13 are in contact with the lower surface of the dielectric passivation layer 14; a light-triggered antireflection layer 15, which is arranged on the lower surface of the substrate 1.

[0035] It should be noted that the impulse response photocurrent of the photoconductive switch device is related to the damping angular frequency and the neper frequency, and the damping angular frequency is inversely proportional to the square root of the capacitance parameter. Therefore, the self-structural capacitance of the photoconductive switch device has a great influence on its high-frequency response ability. Although the traditional vertical structure device has a high breakdown voltage, due to its large parasitic capacitance, it is not conducive to the high-frequency photoelectric response of the device. The coplanar device structure has a small parasitic capacitance. However, considering that the current channel of the coplanar device is on the surface layer of the material, surface flashover and electric breakdown are likely to occur, thus affecting high-power output and high-frequency photoelectric response. Therefore, the embedded electrode gallium nitride photoconductive switch provided by the present invention is innovatively designed based on the gallium nitride photoconductive switch structure, and the high-power output and high-frequency photoelectric response ability of the device are further improved through structural optimization, aiming to solve the balance problem between the high-power output and high-frequency photoelectric response of the existing gallium nitride photoconductive switch. An anode groove and a cathode groove with the same structure are provided at intervals on the substrate 1, and an anodic doped gallium nitride layer 2 and a cathodic doped gallium nitride layer 8 are respectively deposited in the anode groove and the cathode groove. An anodic ohmic contact adhesion layer 3, an anodic ohmic contact barrier layer 4, an anodic ohmic contact blocking layer 5, an anodic ohmic contact antioxidant layer 6 and an anodic encapsulation layer 7 are sequentially deposited on the anodic doped gallium nitride layer 2. A cathodic ohmic contact adhesion layer 9, a cathodic ohmic contact barrier layer 10, a cathodic ohmic contact blocking layer 11, a cathodic ohmic contact antioxidant layer 12 and a cathodic encapsulation layer 13 are sequentially deposited on the cathodic doped gallium nitride layer 8. The anodic ohmic contact adhesion layer 3, the anodic ohmic contact barrier layer 4, the anodic ohmic contact blocking layer 5, the anodic ohmic contact antioxidant layer 6, the anodic encapsulation layer 7 and the corresponding cathodic ohmic contact adhesion layer 9, the cathodic ohmic contact barrier layer 10, the cathodic ohmic contact blocking layer 11, the cathodic ohmic contact antioxidant layer 12, the cathodic encapsulation layer 13 all have the same thickness.

[0036] The present invention constructs anodic grooves and cathodic grooves with specific morphologies on the surface of gallium nitride, and respectively deposits embedded doped gallium nitride layers, ohmic contact layers and encapsulation layers in the anodic grooves and the cathodic grooves. The ohmic contact layers are sequentially an ohmic contact adhesion layer, an ohmic contact barrier layer, an ohmic contact blocking layer and an ohmic contact antioxidant layer. By reconstructing the traditional lateral current path into a three-dimensional distribution, this structural design embeds the current channel in the bulk region of the material rather than on the surface, effectively suppressing the surface flashover phenomenon, and the breakdown voltage is greatly improved compared with the traditional planar structure. By optimizing the groove depth and distribution density, the self-parasitic capacitance of the device can be significantly reduced, and the high-frequency response of the device is further improved. The doped gallium nitride layer and the multi-layer metal electrodes act synergistically to further reduce the contact resistivity and achieve low-loss ohmic contact. The encapsulation metal layer helps with reliable electrical connection to the external circuit.

[0037] The upper surface of the anode encapsulation layer 7 and the upper surface of the cathode encapsulation layer 13 are both in contact with the lower surface of the dielectric passivation layer 14. That is, the anode encapsulation layer 7 locally wraps the boundaries of the anode encapsulation layer 7 and the cathode encapsulation layer 13, suppressing the peak electric field at the "metal-semiconductor-dielectric" triple junction, thereby improving the reliability of the gallium nitride photoconductive switch under high voltage.

[0038] In a specific embodiment, the substrate 1 is a semi-insulating gallium nitride layer with a thickness of 100 μm to 150 μm. It should be noted that the semi-insulating gallium nitride layer used in the present invention can reduce the equivalent impedance of the device under backlight triggering and increase the conduction current.

[0039] In a specific embodiment, the depths of both the anode groove and the cathode groove are 2 μm to 2.5 μm. It should be noted that the purpose of the anode groove and the cathode groove provided in the present invention is to deposit and embed a doped gallium nitride layer, an ohmic contact metal layer, and a packaging metal layer in the anode groove and the cathode groove respectively. The depths of the anode groove and the cathode groove are the total thickness of the doped gallium nitride layer, the ohmic contact metal layer, and the packaging metal layer. That is, the upper surface of the anode encapsulation layer 7, the upper surface of the anode encapsulation layer 7, and the upper surface of the substrate 1 are on the same horizontal plane.

[0040] In a specific embodiment, both the anode doped gallium nitride layer 2 and the cathode doped gallium nitride layer 8 are doped gallium nitride layers with a thickness of 0.5 μm to 1.0 μm. It should be noted that the doped gallium nitride layer is doped with silicon (Si), and the doping amount is 1×10 17 cm -3 to 1×10 19 cm -3 。

[0041] In a specific embodiment, the anode ohmic contact adhesion layer 3 is a first titanium metal layer with a thickness of 10 nm to 20 nm; the anode ohmic contact barrier layer 4 is a first aluminum metal layer with a thickness of 110 nm to 120 nm; the anode ohmic contact blocking layer 5 is a first palladium metal layer with a thickness of 45 nm to 55 nm; the anode ohmic contact antioxidant layer is a first gold metal layer with a thickness of 40 nm to 50 nm.

[0042] In a specific embodiment, the cathode ohmic contact adhesion layer 9 is a second titanium metal layer with a thickness of 10 nm to 20 nm; the cathode ohmic contact barrier layer 10 is a second aluminum metal layer with a thickness of 110 nm to 120 nm; the cathode ohmic contact blocking layer 11 is a second palladium metal layer with a thickness of 45 nm to 55 nm; the cathode ohmic contact antioxidant layer 12 is a second gold metal layer with a thickness of 40 nm to 50 nm.

[0043] It should be noted that in the present invention, titanium, aluminum, palladium, and gold are sequentially deposited on the doped gallium nitride layer to form an ohmic contact metal layer, and the ohmic contact metal layer can form good contact characteristics with the doped gallium nitride layer under high-temperature rapid annealing.

[0044] In a specific embodiment, as Figure 2 shown, the anode encapsulation layer 7 includes an anode encapsulation adhesion layer 16 and an anode encapsulation welding layer 17 sequentially arranged from bottom to top along the thickness direction of the substrate 1. The lower surface of the anode encapsulation adhesion layer 16 is in contact with the upper surface of the anode ohmic contact antioxidant layer 6. The cathode encapsulation layer 13 includes a cathode encapsulation adhesion layer 18 and a cathode encapsulation welding layer 19 sequentially arranged from bottom to top along the thickness direction of the substrate 1. The lower surface of the cathode encapsulation adhesion layer 18 is in contact with the upper surface of the cathode ohmic contact antioxidant layer 12. Both the anode encapsulation adhesion layer 16 and the cathode encapsulation adhesion layer 18 are nickel metal layers with a thickness of 20 nm to 30 nm. Both the anode encapsulation welding layer 17 and the cathode encapsulation welding layer 19 are third gold metal layers with a thickness of 1 μm to 2 μm. It should be noted that the purpose of the encapsulation layer designed in the present invention is to effectively achieve the electrical reliable connection between the device and the external circuit.

[0045] In a specific embodiment, the dielectric passivation layer 14 is a silicon nitride layer with a thickness of 220 nm to 250 nm. The light-triggered antireflection layer 15 is a first silicon oxide layer with a thickness of 90 nm to 100 nm. It should be noted that the purpose of the light-triggered antireflection layer adopted in the present invention is to satisfy the incidence of the trigger laser reaching more than 90%.

[0046] The present invention also provides a preparation method for the above-mentioned embedded electrode gallium nitride photoconductive switch, as Figure 3 shown, including the following steps: Step 1, provide a substrate.

[0047] It should be noted that the substrate is a semi-insulating gallium nitride single crystal with a thickness of 300 μm to 4,000 μm. In order to avoid the possible impurities on the surface of the substrate affecting the quality and performance of the subsequent formed device, the substrate needs to be pretreated. It is cleaned with a hydrochloric acid solution with a concentration of 35% for 40 s and rinsed with deionized water for 5 min. It is ultrasonically cleaned with acetone, isopropyl alcohol, and absolute ethanol in sequence for 3 min. It is rinsed with deionized water for 5 min and dried with nitrogen N2.

[0048] Step 2, deposit a protective layer on the upper surface of the substrate.

[0049] It should be noted that in order to etch anodic grooves and cathodic grooves on the upper surface of the substrate, it is necessary to first deposit a protective layer on the upper surface of the substrate. The deposition methods include, but are not limited to, plasma-enhanced chemical vapor deposition technology, and it is only necessary to ensure that the protective layer reaches the required thickness. In a preferred embodiment, the protective layer is a second silicon oxide (SiO2) layer with a thickness of 90 nm to 110 nm.

[0050] Step 3: Partially etch the protective layer to expose the etching regions of the anodic grooves and cathodic grooves on the upper surface of the substrate.

[0051] It should be noted that during the etching process of the protective layer, photoresist needs to be spin-coated on the surface of the protective layer. To enhance the adhesion of the photoresist and prevent the developer from penetrating the photoresist in subsequent steps, thereby ensuring the accuracy and integrity of the photolithographic pattern, before etching, the surface hydroxyl groups on the surface of the protective layer are removed using hexamethyldisilazane (HMDS) to form a hydrophobic layer, and then the photoresist is spin-coated; in some preferred embodiments of the present invention, in order to facilitate the formation of anodic grooves and cathodic grooves on the protective layer, the mask method is adopted, that is, according to actual needs, the anodic and cathodic mask plates corresponding to the actual requirements are selected to form the required anodic and cathodic patterns, and then the protective layer is partially etched using photolithography technology so that the etching regions form anodic grooves and cathodic grooves. In some preferred embodiments of the present invention, it is achieved through the following steps: (1) Photoresist rotation: Dropwise apply the photoresist, and the spin coater is maintained at 500 r / min for 10 s, and then at 2000 r / min for 30 s. (2) Soft bake: Maintain on a hot plate at 110 °C for 1 min. (3) Alignment exposure: The exposure time is 5.5 s. (4) Post-bake: Maintain on a baking plate at 120 °C for 2 min. (5) Bare exposure: The exposure time is 65 s. (6) Development: Immerse the single crystal in the developer for 45 s. (7) Hard bake: Maintain on a hot plate at 120 °C for 5 min.

[0052] During the partial etching process of the protective layer, the substrate needs to be placed in the etching solution for etching. Therefore, it is necessary to protect the lower surface of the substrate. Specifically: Use photoresist for protection: (1) Photoresist rotation: Dropwise apply the photoresist, and the spin coater is maintained at 500 r / min for 10 s, and then at 1500 r / min for 30 s. (2) Hard bake: Maintain on a hot plate at 120 °C for 5 min.

[0053] The etching solution used for etching is a buffered hydrofluoric acid (BHF) solution composed of hydrofluoric acid (HF) and ammonium fluoride (NH4F). In a preferred embodiment, the volume ratio of HF to NH4F is 1:6. The protective layer is etched at room temperature, and the etching rate is about 80 nm / min to 100 nm / min, and the etching depth is 100 nm, exposing the etched area of semi-insulating gallium nitride (SI-GaN), that is, the etching area exposing the anode groove and the cathode groove.

[0054] Step 4: Etch the etched area again to obtain the anode groove and the cathode groove.

[0055] It should be noted that the etching again is carried out by means including but not limited to plasma etching, which is a conventional process. An inductively coupled plasma (ICP) device is used for etching, with a chlorine (Cl2) flow rate of 20 sccm, an argon (Ar) flow rate of 10 sccm, an etching power of 600 W, a pressure of 4.5 mTorr, an etching rate of 300 nm / min, and an etching depth of 2 μm to 2.5 μm to obtain the anode groove and the cathode groove.

[0056] Step 5: Deposit an anodic doped gallium nitride layer 2 and a cathodic doped gallium nitride layer 8 on the anode groove and the cathode groove respectively.

[0057] It should be noted that the methods for depositing the anodic doped gallium nitride layer 2 and the cathodic doped gallium nitride layer 8 include but are not limited to chemical vapor deposition. The present invention does not limit the specific process of radio frequency magnetron sputtering, which is a conventional process. As long as the thicknesses of the anodic doped gallium nitride layer 2 and the cathodic doped gallium nitride layer 8 are 0.5 μm to 1.0 μm, metalorganic chemical vapor deposition (MOCVD) equipment is used for chemical vapor deposition.

[0058] Step 6: Remove the protective layer on the upper surface of the substrate.

[0059] It should be noted that after etching the anode groove and the cathode groove on the substrate, it is necessary to remove the remaining protective layer on the upper surface of the substrate. A buffered hydrofluoric acid (BHF) solution composed of hydrofluoric acid (HF) and ammonium fluoride (NH4F) is used to remove all the protective layers on the surface.

[0060] Step 7: Deposit an anodic ohmic contact adhesion layer 3, an anodic ohmic contact barrier layer 4, an anodic ohmic contact blocking layer 5, and an anodic ohmic contact antioxidant layer 6 on the upper surface of the anodic doped gallium nitride layer 2 in sequence, and deposit a cathodic ohmic contact adhesion layer 9, a cathodic ohmic contact barrier layer 10, a cathodic ohmic contact blocking layer 11, and a cathodic ohmic contact antioxidant layer 12 on the upper surface of the cathodic doped gallium nitride layer 8 in sequence; then alloying treatment is carried out.

[0061] It should be noted that during the deposition of the ohmic contact multilayer on the anodic doped gallium nitride layer 2 and the cathodic doped gallium nitride layer 8, the mask method needs to be adopted. That is, according to actual requirements, a contact electrode mask plate for lithography that meets the actual needs is selected to form the required contact electrode pattern, and then the ohmic contact multilayer is deposited. During the process of lithographing the contact electrode pattern, photoresist needs to be spin-coated on the upper surface of the device obtained in step 6 to enhance the adhesion of the photoresist and prevent the developer from penetrating the photoresist in subsequent steps, so as to ensure the accuracy and integrity of the lithography pattern. Before etching, hexamethyldisilazane (HMDS) is used to remove the surface hydroxyl groups on the surface of the protective layer to form a hydrophobic layer, and then photoresist is spin-coated. In some preferred embodiments of the present invention, the lithographing of the contact electrode pattern is achieved through the following steps: (1) Photoresist rotation: Drop the photoresist, and the spin coater is maintained at 1000 r / min for 10 s, and then at 3000 r / min for 30 s. (2) Soft bake: Maintain on a hot plate at 110 °C for 1 min. (3) Alignment exposure: The exposure time is 5.5 s. (4) Post-bake: Maintain on a baking plate at 120 °C for 2 min. (5) Bare exposure: The exposure time is 65 s. (6) Development: Immerse the single crystal in the developer for 45 s. (6) Hard bake: Maintain on a hot plate at 120 °C for 5 min.

[0062] After the lithographing of the contact electrode pattern is completed, the remaining photoresist needs to be removed. The residual photoresist is treated with oxygen plasma for 2 min and a power of 20 W. Then, an anodic ohmic contact adhesion layer 3, an anodic ohmic contact barrier layer 4, an anodic ohmic contact blocking layer 5, and an anodic ohmic contact antioxidant layer 6 are sequentially deposited on the upper surface of the anodic doped gallium nitride layer 2. A cathodic ohmic contact adhesion layer 9, a cathodic ohmic contact barrier layer 10, a cathodic ohmic contact blocking layer 11, and a cathodic ohmic contact antioxidant layer 12 are sequentially deposited on the upper surface of the cathodic doped gallium nitride layer 8. The deposition methods include, but are not limited to, electron beam evaporation. The present invention does not limit the specific process of radio frequency magnetron sputtering, which is a conventional process, as long as the anodic ohmic contact adhesion layer 3, the anodic ohmic contact barrier layer 4, the anodic ohmic contact blocking layer 5, and the anodic ohmic contact antioxidant layer 6, as well as the cathodic ohmic contact adhesion layer 9, the cathodic ohmic contact barrier layer 10, the cathodic ohmic contact blocking layer 11, and the cathodic ohmic contact antioxidant layer 12 reach the required thickness.

[0063] After the deposition is completed, in order to avoid the possible impurities on the surface affecting the quality and performance of the subsequent formed device, the surface of the device obtained in step 6 needs to be cleaned. It is ultrasonically cleaned with acetone, isopropyl alcohol, and absolute ethanol in sequence for 3 min, rinsed with deionized water for 5 min, dried with high-purity N2, and subjected to alloying treatment. The alloying treatment is carried out in a high-temperature vacuum rapid annealing furnace at a temperature of 800 °C for 40 s.

[0064] Step 8: An anode encapsulation layer 7 and a cathode encapsulation layer 13 are respectively deposited on the upper surfaces of the anti-oxidation layer 6 of the anode ohmic contact and the anti-oxidation layer 12 of the cathode ohmic contact.

[0065] It should be noted that during the process of depositing the anode encapsulation layer 7 and the cathode encapsulation layer 13 on the upper surfaces of the anti-oxidation layer 6 of the anode ohmic contact and the anti-oxidation layer 12 of the cathode ohmic contact respectively, the mask method also needs to be adopted. That is, according to actual requirements, an electrode window mask plate corresponding to the actually required photolithography is selected to form the required electrode window pattern, and then the encapsulation metal layer is deposited. During the process of lithographing the electrode window pattern, photoresist needs to be spin-coated on the upper surface of the device obtained in Step 7, and the method of lithographing the electrode window pattern is the same as that of lithographing the contact electrode pattern.

[0066] The methods of depositing the anode encapsulation layer 7 and the cathode encapsulation layer 13 include but are not limited to the method of radio frequency magnetron sputtering. The present invention does not limit the specific process of radio frequency magnetron sputtering, which is a conventional process, as long as the formation of the anode encapsulation layer 7 and the cathode encapsulation layer 13 reaches the required thickness.

[0067] Step 9: A silicon nitride layer is deposited on the upper surface of the substrate, the upper surface of the anode encapsulation layer 7, and the upper surface of the cathode encapsulation layer 13.

[0068] When depositing the silicon nitride layer, in order to avoid the influence of possible impurities on the surface on the quality and performance of the subsequent formed device, it is necessary to clean the surface of the device obtained in Step 8. Acetone, isopropyl alcohol, and absolute ethanol are successively used for ultrasonic cleaning for 3 minutes, rinsed with deionized water for 5 minutes, dried with high-purity N2, and subjected to alloying treatment. The alloying treatment is carried out in a high-temperature vacuum rapid annealing furnace at a temperature of 800 °C for 40 seconds.

[0069] The methods of depositing the silicon nitride layer include but are not limited to the method of plasma-enhanced chemical vapor deposition, which is a conventional process, as long as the thickness of the silicon nitride layer is ensured to be within 220 nm to 250 nm. In a preferred embodiment, the silicon nitride layer is deposited by plasma-enhanced chemical vapor deposition. The deposition temperature is 350 °C, the pressure is 130 Pa, the power is 30 W, the flow rate of ammonia (NH3) is 15 sccm, the flow rate of silane (SiH4) is 240 sccm, the flow rate of nitrogen N2 is 100 sccm, and the deposition rate is 3 Å / s.

[0070] Step 10: The silicon nitride layer is partially etched to expose the anode encapsulation layer 7 and the cathode encapsulation layer 13, forming a dielectric passivation layer 14. Among them, the upper surface of the anode encapsulation layer 7 is in contact with the lower surface of the dielectric passivation layer 14, and the upper surface of the cathode encapsulation layer 13 is in contact with the lower surface of the dielectric passivation layer 14.

[0071] It should be noted that partial etching includes, but is not limited to, plasma etching, which is a conventional process. As long as the anode encapsulation layer 7 and the cathode encapsulation layer 13 are exposed, in a preferred embodiment, inductively coupled plasma etching is used, with a gas pressure of 1000 Pa, a carbon tetrafluoride (CF4) flow rate of 50 sccm, a radio frequency power of 120 W, and an etching rate of 2 nm / s.

[0072] The upper surfaces of the anode encapsulation layer 7 and the cathode encapsulation layer 13 are both in contact with the lower surface of the dielectric passivation layer 14. That is, the anode encapsulation layer 7 locally wraps the boundaries of the anode encapsulation layer 7 and the cathode encapsulation layer 13, suppressing the peak electric field at the "metal-semiconductor-dielectric" triple junction, thereby improving the reliability of the gallium nitride photoconductive switch under high voltage.

[0073] Step 11: Grind and thin the lower surface of the substrate to form the substrate 1.

[0074] It should be noted that the method of grinding and thinning includes thinning by using a temporary bonding, grinding, debonding, and polishing process until the substrate 1 reaches the required thickness, which is 100 μm to 150 μm, and then depositing a light-triggered antireflection layer 15 to reduce the equivalent impedance under backlight triggering and improve light absorption.

[0075] Step 12: Deposit a silicon oxide layer with a thickness of 90 nm to 100 nm on the lower surface of the substrate 1 to obtain the light-triggered antireflection layer 15; form an embedded electrode gallium nitride photoconductive switch. It should be noted that the deposition method includes, but is not limited to, the deposition method of plasma-enhanced chemical vapor deposition technology, which is a conventional process. As long as the thickness is guaranteed to be 90 nm to 100 nm. After depositing the light-triggered antireflection layer 15 on the lower surface of the substrate 1, annealing is performed to repair interface defects to obtain an embedded electrode gallium nitride photoconductive switch. The temperature for annealing and repairing interface defects is 110 °C to 130 °C, and the gas used is carbon dioxide.

[0076] The following is further illustrated through specific examples.

[0077] Example 1 A method for preparing an embedded electrode gallium nitride photoconductive switch, as Figure 2 shown, includes the following steps: Step 1: Provide a semi-insulating gallium nitride (SI-GaN) single crystal substrate with a thickness of 350 μm. Clean the semi-insulating gallium nitride (1) (SI-GaN) single crystal substrate with a hydrochloric acid solution with a concentration of 35% for 40 s, and rinse with deionized water for 5 min; successively ultrasonically clean with acetone, isopropyl alcohol, and absolute ethanol for 3 min; rinse with deionized water for 5 min, and dry with nitrogen N2.

[0078] Step 2: Deposit a protective layer on the upper surface of the substrate. Using plasma-enhanced chemical vapor deposition technology, deposit silicon dioxide (SiO2) with a thickness of 100 nm on the SI-GaN single crystal substrate to form a protective layer.

[0079] Step 3: First, perform surface hydroxyl removal treatment on the protective layer with hexamethyldisilazane (HMDS) to form a hydrophobic layer, enhance adhesion, and prevent the developer from penetrating the photoresist in subsequent steps, thereby ensuring the accuracy and integrity of the lithography pattern. Second, perform lithography to form the anode and cathode patterns. Specifically: (1) Photoresist rotation: Drop the photoresist, and the spin coater maintains at 500 r / min for 10 s, and then at 2000 r / min for 30 s; (2) Soft bake: Maintain on a hot plate at 110 °C for 1 min. (3) Alignment exposure: The exposure time is 5.5 s; (4) Post-bake: Maintain on a baking plate at 120 °C for 2 min. (5) Bare exposure: The exposure time is 65 s; (6) Development: Immerse the single crystal in the developer for 45 s; (7) Hard bake: Maintain on a hot plate at 120 °C for 5 min. Then, it is necessary to protect the lower surface of the semi-insulating gallium nitride (SI-GaN) single crystal substrate. Specifically: Use photoresist protection: (1) Photoresist rotation: Drop the photoresist, and the spin coater maintains at 500 r / min for 10 s, and then at 1500 r / min for 30 s. (2) Hard bake: Maintain on a hot plate at 120 °C for 5 min; Finally, perform partial etching on the protective layer, immerse it in a buffered hydrofluoric acid (BHF) solution composed of hydrofluoric acid (HF) and ammonium fluoride (NH4F), etch silicon dioxide (SiO2) at room temperature, the etching rate is about 100 nm / min, and the etching depth is 100 nm, exposing the etched area of the semi-insulating gallium nitride (SI-GaN), that is, the etched areas of the anode groove and the cathode groove are exposed on the upper surface of the semi-insulating gallium nitride single crystal substrate.

[0080] Step 4: Etch the etched area again, that is, etch the etched area of the semi-insulating gallium nitride single crystal substrate. Use an inductively coupled plasma equipment for etching, with a Cl2 flow rate of 20 sccm, an Ar flow rate of 10 sccm, an etching power of 600 W, a pressure of 4.5 mTorr, an etching rate of 300 nm / min, and an etching depth of 2 μm to obtain the anode groove and the cathode groove.

[0081] Step 5: Use a metal-organic chemical vapor deposition equipment to deposit anodic-doped gallium nitride and cathodic-doped gallium nitride on the anode groove and the cathode groove respectively. The thickness of the doped gallium nitride is 1 μm, the doped gallium nitride is silicon-doped gallium nitride, and the doping amount is 1×10 18 cm -3 to obtain the anodic-doped gallium nitride layer 2 and the cathodic-doped gallium nitride layer 8.

[0082] Step 6: Use a buffered BHF solution composed of HF and NH4F to remove the protective layer on the upper surface of the semi-insulating gallium nitride single crystal substrate.

[0083] Step 7: First, perform surface hydroxyl removal treatment on the device obtained in Step 6 using hexamethyldisilazane (HMDS) to form a hydrophobic layer, enhance adhesion, and prevent the developer from penetrating the photoresist in subsequent steps, thereby ensuring the accuracy and integrity of the photolithography pattern.

[0084] Secondly, perform photolithography of the contact electrode pattern, including the following steps: (1) Photoresist rotation: Drop the photoresist, and the spin coater maintains at 1000 r / min for 10 s, then at 3000 r / min for 30 s. (2) Soft bake: Maintain on a hot plate at 110 °C for 1 min. (3) Alignment exposure: The exposure time is 5.5 s. (4) Post-bake: Maintain on a baking plate at 120 °C for 2 min. (5) Bare exposure: The exposure time is 65 s. (6) Development: Immerse the single crystal in the developer for 45 s. (6) Hard bake: Maintain on a hot plate at 120 °C for 5 min. Then use oxygen plasma to treat the residual photoresist for 2 min with a power of 20 W.

[0085] Finally, use electron beam evaporation to sequentially deposit titanium, aluminum, palladium, and gold on the upper surface of the anodic doped gallium nitride layer 2. The thickness of the titanium metal is 10 nm, the thickness of the aluminum is 110 nm, the thickness of the palladium is 55 nm, and the thickness of the gold is 45 nm to obtain the anodic ohmic contact adhesion layer 3, the anodic ohmic contact barrier layer 4, the anodic ohmic contact blocking layer 5, and the anodic ohmic contact antioxidant layer 6; sequentially deposit titanium, aluminum, palladium, and gold on the upper surface of the cathodic doped gallium nitride layer 8. The thickness of the titanium is 10 nm, the thickness of the aluminum is 110 nm, the thickness of the palladium is 55 nm, and the thickness of the gold is 45 nm to obtain the cathodic ohmic contact adhesion layer 9, the cathodic ohmic contact barrier layer 10, the cathodic ohmic contact blocking layer 11, and the cathodic ohmic contact antioxidant layer 12; and sequentially perform ultrasonic cleaning in acetone, isopropyl alcohol, and absolute ethanol for 3 min; rinse with deionized water for 5 min, dry with nitrogen N2, and perform alloying treatment in a high-temperature vacuum rapid annealing furnace at a temperature of 800 °C for 40 s.

[0086] Step 8: First, perform surface hydroxyl removal treatment on the device obtained in Step 7 using HMDS to form a hydrophobic layer, enhance adhesion, and prevent the developer from penetrating the photoresist in subsequent steps, thereby ensuring the accuracy and integrity of the photolithography pattern.

[0087] Secondly, perform photolithography on the electrode window pattern, including the following steps: (1) Photoresist rotation: Drop and coat the photoresist, and the spin coater keeps at 1000 r / min for 10 s, then at 3000 r / min for 30 s. (2) Soft bake: Keep on a hot plate at 110 °C for 1 min. (3) Alignment exposure: The exposure time is 5.5 s. (4) Post-bake: Keep on a baking plate at 120 °C for 2 min. (5) Naked exposure: The exposure time is 65 s. (6) Development: Immerse the single crystal in the developer for 45 s. (6) Hard bake: Keep on a hot plate at 120 °C for 5 min. Then use oxygen plasma to treat the residual photoresist for 2 min with a power of 20 W.

[0088] Finally, adopt the method of radio frequency magnetron sputtering to sequentially deposit nickel and gold on the upper surface of the anodic ohmic contact antioxidant layer 6. The thickness of nickel is 20 nm, and the thickness of gold is 500 nm, obtaining the anodic encapsulation adhesion layer 16 and the anodic encapsulation welding layer 17, which is the anodic encapsulation layer 7; sequentially deposit nickel and gold on the upper surface of the cathodic ohmic contact antioxidant layer 12. The thickness of nickel is 20 nm, and the thickness of gold is 500 nm, obtaining the cathodic encapsulation adhesion layer 18 and the cathodic encapsulation welding layer 19, which is the cathodic encapsulation layer 13.

[0089] Step 9: Clean the surface of the device obtained in Step 8. Ultrasonically clean with acetone, isopropyl alcohol, and absolute ethanol for 3 min in sequence, rinse with deionized water for 5 min, and dry with high-purity N2. Then deposit a silicon nitride layer by plasma-enhanced chemical vapor deposition. The deposition temperature is 350 °C, the pressure is 130 Pa, the power is 30 W, the NH3 flow rate is 15 sccm, the SiH4 flow rate is 240 sccm, the nitrogen N2 flow rate is 100 sccm, the deposition rate is 3 Å / s, and the thickness of the silicon nitride layer is 250 nm.

[0090] Step 10: Partially etch the silicon nitride layer to expose the anodic encapsulation welding layer 17 and the cathodic encapsulation welding layer 19, forming the dielectric passivation layer 14. Adopt inductively coupled plasma etching with a gas pressure of 1000 Pa, a CF4 flow rate of 50 sccm, a radio frequency power of 120 W, and an etching rate of 2 nm / s.

[0091] Among them, the upper surface of the anodic encapsulation layer 7 is in contact with the lower surface of the dielectric passivation layer 14, and the upper surface of the cathodic encapsulation layer 13 is in contact with the lower surface of the dielectric passivation layer 14.

[0092]

[0093] ​Step 12: Using plasma-enhanced chemical vapor deposition technology, deposit a silicon oxide layer with a thickness of 90 nm on the lower surface of the substrate 1 to obtain the light-triggered antireflection layer 15; and perform supercritical cryogenic fluid annealing to repair interface defects at a temperature of 120 °C with CO2 as the gas; obtain the embedded electrode gallium nitride photoconductive switch. Conduct dark-state and high-frequency modulated laser pulse trigger tests on the embedded electrode gallium nitride photoconductive switch, with laser wavelengths of 355 nm and 532 nm and trigger modes of front and back triggers.

[0094] Example 2 A preparation method of an embedded electrode gallium nitride photoconductive switch, as Figure 2 shown, includes the following steps: Step 1: Provide a semi-insulating gallium nitride (SI-GaN) single crystal substrate with a thickness of 325 μm. Clean the semi-insulating gallium nitride (1) (SI-GaN) single crystal substrate with a hydrochloric acid solution with a concentration of 35% for 40 s, and rinse with deionized water for 5 min; ultrasonically clean with acetone, isopropyl alcohol, and absolute ethanol in sequence for 3 min; rinse with deionized water for 5 min, and dry with nitrogen N2.

[0095] Step 2: Deposit a protective layer on the upper surface of the substrate. Using plasma-enhanced chemical vapor deposition technology, deposit silicon dioxide (SiO2) with a thickness of 90 nm on the SI-GaN single crystal substrate to form a protective layer.

[0096] Step 3: First, the surface hydroxyl groups of the protective layer are removed by hexamethyldisilazane (HMDS) to form a hydrophobic layer, enhancing adhesion and preventing the developer from penetrating the photoresist in subsequent steps, thereby ensuring the accuracy and integrity of the lithography pattern. Secondly, lithography is performed to form the anode and cathode patterns. Specifically: (1) Photoresist rotation: The photoresist is drop-coated, and the spin coater is maintained at 500 r / min for 10 s and then at 2000 r / min for 30 s. (2) Soft bake: It is maintained on a hot plate at 110 °C for 1 min. (3) Alignment exposure: The exposure time is 5.5 s. (4) Post-bake: It is maintained on a baking plate at 120 °C for 2 min. (5) Bare exposure: The exposure time is 65 s. (6) Development: The single crystal is immersed in the developer for 45 s. (7) Hard bake: It is maintained on a hot plate at 120 °C for 5 min. Then, the lower surface of the semi-insulating gallium nitride (SI-GaN) single crystal substrate needs to be protected. Specifically: Photoresist protection is adopted: (1) Photoresist rotation: The photoresist is drop-coated, and the spin coater is maintained at 500 r / min for 10 s and then at 1500 r / min for 30 s. (2) Hard bake: It is maintained on a hot plate at 120 °C for 5 min; Finally, the protective layer is partially etched by immersing it in a buffered hydrofluoric acid (BHF) solution composed of hydrofluoric acid (HF) and ammonium fluoride (NH4F) to etch silicon dioxide (SiO2) at room temperature. The etching rate is about 100 nm / min, and the etching depth is 100 nm, exposing the etched area of the semi-insulating gallium nitride (SI-GaN), that is, the etched area where the anode groove and the cathode groove are exposed on the upper surface of the semi-insulating gallium nitride single crystal substrate.

[0097] Step 4: The etched area is etched again, that is, the etched area of the semi-insulating gallium nitride single crystal substrate is etched using an inductively coupled plasma equipment. The Cl2 flow rate is 20 sccm, the Ar flow rate is 10 sccm, the etching power is 600 W, the pressure is 4.5 mTorr, the etching rate is 30 nm / min, and the etching depth is 2.5 μm to obtain the anode groove and the cathode groove.

[0098] Step, 5: Using a metal-organic chemical vapor deposition equipment, anodically doped gallium nitride and cathodically doped gallium nitride are respectively deposited on the anode groove and the cathode groove. The thickness of the doped gallium nitride is 1 μm, and the doped gallium nitride is silicon-doped gallium nitride with a doping amount of 1×10 18 cm -3 , obtaining the anodically doped gallium nitride layer 2 and the cathodically doped gallium nitride layer 8.

[0099] Step 6: Use a buffered BHF solution composed of HF and NH4F to remove the protective layer on the upper surface of the semi-insulating gallium nitride single crystal substrate.

[0100] Step 7: First, the device obtained in Step 6 is subjected to surface hydroxyl removal treatment with hexamethyldisilazane (HMDS) to form a hydrophobic layer, enhance adhesion, and prevent the developer from penetrating the photoresist in subsequent steps, thereby ensuring the accuracy and integrity of the lithography pattern.

[0101] Second, perform lithography for the contact electrode pattern, including the following steps: (1) Photoresist rotation: Drop the photoresist, and the spin coater maintains at 1000 r / min for 10 s, and then at 3000 r / min for 30 s. (2) Soft bake: Maintain on a hot plate at 110 °C for 1 min. (3) Alignment exposure: The exposure time is 5.5 s. (4) Post-bake: Maintain on a baking plate at 120 °C for 2 min. (5) Bare exposure: The exposure time is 65 s. (6) Development: Immerse the single crystal in the developer for 45 s. (6) Hard bake: Maintain on a hot plate at 120 °C for 5 min. Then treat the residual photoresist with oxygen plasma for 2 min at a power of 20 W.

[0102] Finally, by means of electron beam evaporation, titanium, aluminum, palladium, and gold are sequentially deposited on the upper surface of the anodic doped gallium nitride layer 2, with the thickness of the titanium metal being 20 nm, the thickness of the aluminum being 120 nm, the thickness of the palladium being 55 nm, and the thickness of the gold being 50 nm, to obtain the anodic ohmic contact adhesion layer 3, the anodic ohmic contact barrier layer 4, the anodic ohmic contact blocking layer 5, and the anodic ohmic contact antioxidant layer 6; on the upper surface of the cathodic doped gallium nitride layer 8, titanium, aluminum, palladium, and gold are sequentially deposited, with the thickness of the titanium metal being 15 nm, the thickness of the aluminum being 120 nm, the thickness of the palladium being 55 nm, and the thickness of the gold being 50 nm, to obtain the cathodic ohmic contact adhesion layer 9, the cathodic ohmic contact barrier layer 10, the cathodic ohmic contact blocking layer 11, and the cathodic ohmic contact antioxidant layer 12; and sequentially perform ultrasonic cleaning with acetone, isopropyl alcohol, and absolute ethanol for 3 min; rinse with deionized water for 5 min, dry with nitrogen N2, and perform alloying treatment in a high-temperature vacuum rapid annealing furnace at a temperature of 800 °C for 40 s.

[0103] Step 8: First, the device obtained in Step 7 is subjected to surface hydroxyl removal treatment with HMDS to form a hydrophobic layer, enhance adhesion, and prevent the developer from penetrating the photoresist in subsequent steps, thereby ensuring the accuracy and integrity of the lithography pattern.

[0104] Secondly, perform photolithography on the electrode window pattern, including the following steps: (1) Photoresist rotation: Drop and coat the photoresist, and the spin coater maintains at 1000 r / min for 10 s, then at 3000 r / min for 30 s. (2) Soft bake: Maintain on a hot plate at 110 °C for 1 min. (3) Alignment exposure: The exposure time is 5.5 s. (4) Post-bake: Maintain on a baking plate at 120 °C for 2 min. (5) Bare exposure: The exposure time is 65 s. (6) Development: Immerse the single crystal in the developer for 45 s. (6) Hard bake: Maintain on a hot plate at 120 °C for 5 min. Then use oxygen plasma to treat the residual photoresist for 2 min with a power of 20 W.

[0105] Finally, in the way of radio frequency magnetron sputtering, deposit nickel and gold successively on the upper surface of the anodic ohmic contact antioxidant layer 6. The thickness of nickel is 30 nm and the thickness of gold is 800 nm, obtaining the anodic encapsulation adhesion layer 16 and the anodic encapsulation welding layer 17, which is the anodic encapsulation layer 7; deposit nickel and gold successively on the upper surface of the cathodic ohmic contact antioxidant layer 12. The thickness of nickel is 30 nm and the thickness of gold is 800 nm, obtaining the cathodic encapsulation adhesion layer 18 and the cathodic encapsulation welding layer 19, which is the cathodic encapsulation layer 13.

[0106] Step 9, clean the surface of the device obtained in Step 8, ultrasonically clean with acetone, isopropyl alcohol, and absolute ethanol for 3 min successively, rinse with deionized water for 5 min, dry with high-purity N2, and then deposit a silicon nitride layer by plasma enhanced chemical vapor deposition. The deposition temperature is 350 °C, the pressure is 130 Pa, the power is 30 W, the NH3 flow rate is 15 sccm, the SiH4 flow rate is 240 sccm, the nitrogen N2 flow rate is 100 sccm, and the deposition rate is 3 Å / s. The thickness of the silicon nitride layer is 230 nm.

[0107] Step 10, partially etch the silicon nitride layer to expose the anodic encapsulation welding layer 17 and the cathodic encapsulation welding layer 19, forming the dielectric passivation layer 14. Use inductively coupled plasma etching with a gas pressure of 1000 Pa, a CF4 flow rate of 50 sccm, a radio frequency power of 120 W, and an etching rate of 2 nm / s.

[0108] Among them, the upper surface of the anodic encapsulation layer 7 is in contact with the lower surface of the dielectric passivation layer 14, and the upper surface of the cathodic encapsulation layer 13 is in contact with the lower surface of the dielectric passivation layer 14.

[0109] Step 11, ultrasonically clean with acetone, isopropyl alcohol, and absolute ethanol for 3 min successively, rinse with deionized water for 5 min, dry with high-purity nitrogen N2, and then perform thinning using the processes of temporary bonding, grinding, debonding, and polishing to form the substrate 1 with a thickness of 100 μm.

[0110] Step 12: Using plasma-enhanced chemical vapor deposition technology, deposit a silicon oxide layer with a thickness of 100 nm on the lower surface of the substrate 1 to obtain the photo-triggered antireflection layer 15; and perform supercritical low-temperature fluid annealing to repair the interface defects at a temperature of 120 °C with CO2 as the gas; obtain the embedded electrode gallium nitride photoconductive switch. Conduct dark-state and high-frequency modulated laser pulse trigger tests on the embedded electrode gallium nitride photoconductive switch, with laser wavelengths of 355 nm and 532 nm, and trigger modes of front and back triggering.

[0111] Example 3 A preparation method of an embedded electrode gallium nitride photoconductive switch, as Figure 2 shown, includes the following steps: Step 1: Provide a semi-insulating gallium nitride (SI-GaN) single crystal substrate with a thickness of 340 μm. Clean the semi-insulating gallium nitride (1) (SI-GaN) single crystal substrate with a hydrochloric acid solution with a concentration of 35% for 40 s, and rinse it with deionized water for 5 min; ultrasonically clean it with acetone, isopropyl alcohol, and absolute ethanol in sequence for 3 min; rinse it with deionized water for 5 min, and dry it with nitrogen N2.

[0112] Step 2: Deposit a protective layer on the upper surface of the substrate. Using plasma-enhanced chemical vapor deposition technology, deposit silicon dioxide (SiO2) with a thickness of 110 nm on the SI-GaN single crystal substrate to form a protective layer.

[0113] Step 3: First, the surface hydroxyl groups of the protective layer are removed by hexamethyldisilazane (HMDS) to form a hydrophobic layer, enhancing adhesion and preventing the developer from penetrating the photoresist in subsequent steps, thereby ensuring the accuracy and integrity of the lithography pattern. Secondly, lithography is performed to form the anode and cathode patterns. Specifically: (1) Photoresist rotation: The photoresist is drop-coated, and the spin coater is maintained at 500 r / min for 10 s, and then at 2000 r / min for 30 s. (2) Soft bake: It is maintained on a hot plate at 110 °C for 1 min. (3) Alignment exposure: The exposure time is 5.5 s. (4) Post-bake: It is maintained on a baking plate at 120 °C for 2 min. (5) Bare exposure: The exposure time is 65 s. (6) Development: The single crystal is immersed in the developer for 45 s. (7) Hard bake: It is maintained on a hot plate at 120 °C for 5 min. Then, the lower surface of the semi-insulating gallium nitride (SI-GaN) single crystal substrate needs to be protected. Specifically: Photoresist protection is adopted: (1) Photoresist rotation: The photoresist is drop-coated, and the spin coater is maintained at 500 r / min for 10 s, and then at 1500 r / min for 30 s. (2) Hard bake: It is maintained on a hot plate at 120 °C for 5 min; Finally, the protective layer is partially etched. It is immersed in a buffered hydrofluoric acid (BHF) solution composed of hydrofluoric acid (HF) and ammonium fluoride (NH4F) to etch silicon dioxide (SiO2) at room temperature. The etching rate is about 100 nm / min, and the etching depth is 100 nm, exposing the etched area of the semi-insulating gallium nitride (SI-GaN), that is, the etched areas of the anode groove and the cathode groove are exposed on the upper surface of the semi-insulating gallium nitride single crystal substrate.

[0114] Step 4: The etched area is etched again, that is, the etched area of the semi-insulating gallium nitride single crystal substrate is etched. Inductively coupled plasma equipment is used for etching. The Cl2 flow rate is 20 sccm, the Ar flow rate is 10 sccm, the etching power is 600 W, the pressure is 4.5 mTorr, the etching rate is 300 nm / min, and the etching depth is 2 μm to obtain the anode groove and the cathode groove.

[0115] Step 5: Using a metal-organic chemical vapor deposition equipment, anodic-doped gallium nitride and cathodic-doped gallium nitride are respectively deposited on the anode groove and the cathode groove. The thickness of the doped gallium nitride is 0.5 μm, and the doped gallium nitride is silicon-doped gallium nitride with a doping amount of 1×10 18 cm -3 , obtaining the anodic-doped gallium nitride layer 2 and the cathodic-doped gallium nitride layer 8.

[0116] Step 6: Use a buffered BHF solution composed of HF and NH4F to remove the protective layer on the upper surface of the semi-insulating gallium nitride single crystal substrate.

[0117] Step 7: First, the device obtained in Step 6 is treated with hexamethyldisilazane (HMDS) to remove surface hydroxyl groups, form a hydrophobic layer, enhance adhesion, and prevent the developer from penetrating the photoresist in subsequent steps, thereby ensuring the accuracy and integrity of the lithography pattern.

[0118] Second, perform lithography of the contact electrode pattern, including the following steps: (1) Photoresist rotation: Drop the photoresist, and the spin coater is maintained at 1000 r / min for 10 s, and then at 3000 r / min for 30 s. (2) Soft bake: Maintain on a hot plate at 110 °C for 1 min. (3) Alignment exposure: The exposure time is 5.5 s. (4) Post-bake: Maintain on a baking plate at 120 °C for 2 min. (5) Bare exposure: The exposure time is 65 s. (6) Development: Immerse the single crystal in the developer for 45 s. (6) Hard bake: Maintain on a hot plate at 120 °C for 5 min. Then treat the residual photoresist with oxygen plasma for 2 min at a power of 20 W.

[0119] Finally, by means of electron beam evaporation, titanium, aluminum, palladium, and gold are sequentially deposited on the upper surface of the anodic doped gallium nitride layer 2, with the thickness of the titanium metal being 15 nm, the thickness of the aluminum being 115 nm, the thickness of the palladium being 45 nm, and the thickness of the gold being 40 nm, to obtain the anodic ohmic contact adhesion layer 3, the anodic ohmic contact barrier layer 4, the anodic ohmic contact blocking layer 5, and the anodic ohmic contact antioxidant layer 6; titanium, aluminum, palladium, and gold are sequentially deposited on the upper surface of the cathodic doped gallium nitride layer 8, with the thickness of the titanium metal being 15 nm, the thickness of the aluminum being 115 nm, the thickness of the palladium being 45 nm, and the thickness of the gold being 40 nm, to obtain the cathodic ohmic contact adhesion layer 9, the cathodic ohmic contact barrier layer 10, the cathodic ohmic contact blocking layer 11, and the cathodic ohmic contact antioxidant layer 12; and then ultrasonic cleaning is performed with acetone, isopropyl alcohol, and absolute ethanol for 3 min in sequence; rinsing is carried out with deionized water for 5 min, dried with nitrogen N2, and alloying treatment is performed in a high-temperature vacuum rapid annealing furnace at a temperature of 800 °C for 40 s.

[0120] Step 8: First, the device obtained in Step 7 is treated with HMDS to remove surface hydroxyl groups, form a hydrophobic layer, enhance adhesion, and prevent the developer from penetrating the photoresist in subsequent steps, thereby ensuring the accuracy and integrity of the lithography pattern.

[0121] Secondly, perform photolithography on the electrode window pattern, including the following steps: (1) Photoresist rotation: Drop the photoresist, and the spin coater is maintained at 1000 r / min for 10 s, and then at 3000 r / min for 30 s. (2) Soft bake: Maintain on a hot plate at 110 °C for 1 min. (3) Alignment exposure: The exposure time is 5.5 s. (4) Post-bake: Maintain on a baking plate at 120 °C for 2 min. (5) Bare exposure: The exposure time is 65 s. (6) Development: Immerse the single crystal in the developer for 45 s. (6) Hard bake: Maintain on a hot plate at 120 °C for 5 min. Then use oxygen plasma to treat the residual photoresist for 2 min with a power of 20 W.

[0122] Finally, by means of radio frequency magnetron sputtering, nickel and gold are sequentially deposited on the upper surface of the anodic ohmic contact antioxidant layer 6. The thickness of nickel is 25 nm, and the thickness of gold is 700 nm, obtaining the anodic encapsulation adhesion layer 16 and the anodic encapsulation welding layer 17, which is the anodic encapsulation layer 7; on the upper surface of the cathodic ohmic contact antioxidant layer 12, nickel and gold are sequentially deposited. The thickness of nickel is 25 nm, and the thickness of gold is 700 nm, obtaining the cathodic encapsulation adhesion layer 18 and the cathodic encapsulation welding layer 19, which is the cathodic encapsulation layer 13.

[0123] Step 9: Clean the surface of the device obtained in step 8. Ultrasonically clean with acetone, isopropyl alcohol, and absolute ethanol for 3 min in sequence, rinse with deionized water for 5 min, and dry with high-purity N2. Then deposit a silicon nitride layer by plasma-enhanced chemical vapor deposition. The deposition temperature is 350 °C, the pressure is 130 Pa, the power is 30 W, the NH3 flow rate is 15 sccm, the SiH4 flow rate is 240 sccm, the nitrogen N2 flow rate is 100 sccm, the deposition rate is 3 Å / s, and the thickness of the silicon nitride layer is 220 nm.

[0124] Step 10: Partially etch the silicon nitride layer to expose the anodic encapsulation welding layer 17 and the cathodic encapsulation welding layer 19, forming the dielectric passivation layer 14. Use inductively coupled plasma etching with a gas pressure of 1000 Pa, a CF4 flow rate of 50 sccm, a radio frequency power of 120 W, and an etching rate of 2 nm / s.

[0125] Among them, the upper surface of the anodic encapsulation layer 7 is in contact with the lower surface of the dielectric passivation layer 14, and the upper surface of the cathodic encapsulation layer 13 is in contact with the lower surface of the dielectric passivation layer 14.

[0126] Step 11: Ultrasonically clean with acetone, isopropyl alcohol, and absolute ethanol for 3 min, rinse with deionized water for 5 min, and dry with high-purity nitrogen N2. Then perform thinning using the processes of temporary bonding, grinding, debonding, and polishing to form the substrate 1 with a thickness of 100 μm.

[0127] Step 12: Using plasma enhanced chemical vapor deposition technology, deposit a silicon oxide layer with a thickness of 90 nm on the lower surface of the substrate 1 to obtain the photo-triggered antireflection layer 15; and perform supercritical low-temperature fluid annealing to repair the interface defects at a temperature of 120 °C with CO2 as the gas; obtain the embedded electrode gallium nitride photoconductive switch. Perform dark state and high-frequency modulated laser pulse trigger tests on the embedded electrode gallium nitride photoconductive switch with laser wavelengths of 355 nm and 532 nm, and the trigger modes are front and back triggers.

[0128] It should be noted that when the present invention involves numerical ranges, it should be understood that any value between the two endpoints of each numerical range and the two endpoints can be selected. Since the adopted step methods are the same as those in the embodiments, in order to prevent repetition, the present invention describes the preferred embodiments. Although the preferred embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications to these embodiments once they know the basic creative concept. Therefore, the appended claims are intended to be construed as including the preferred embodiments and all changes and modifications falling within the scope of the present invention.

[0129] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention also intends to include these modifications and variations.

Claims

1. An embedded electrode gallium nitride photoconductive switch, characterized in that, Comprising: A substrate (1), on the upper surface of which anodic grooves and cathodic grooves with the same structure are provided at intervals; Along the thickness direction of the substrate (1), an anodic doped gallium nitride layer (2), an anodic ohmic contact adhesion layer (3), an anodic ohmic contact barrier layer (4), an anodic ohmic contact blocking layer (5), an anodic ohmic contact antioxidant layer (6) and an anodic encapsulation layer (7) are sequentially arranged from bottom to top in the anodic groove; Along the thickness direction of the substrate (1), a cathodic doped gallium nitride layer (8), a cathodic ohmic contact adhesion layer (9), a cathodic ohmic contact barrier layer (10), a cathodic ohmic contact blocking layer (11), a cathodic ohmic contact antioxidant layer (12) and a cathodic encapsulation layer (13) which correspond one by one to those in the anodic groove are sequentially arranged from bottom to top in the cathodic groove; A dielectric passivation layer (14), which is arranged on the upper surface of the substrate (1), and the upper surfaces of the anodic encapsulation layer (7) and the cathodic encapsulation layer (13) are all in contact with the lower surface of the dielectric passivation layer (14); A light-triggered antireflection layer (15), which is arranged on the lower surface of the substrate (1).

2. The embedded electrode gallium nitride photoconductive switch according to claim 1, wherein, The substrate (1) is a semi-insulating gallium nitride layer with a thickness of 100 μm to 150 μm.

3. The embedded electrode gallium nitride photoconductive switch according to claim 1, wherein The depths of both the anodic groove and the cathodic groove are 2 μm to 2.5 μm.

4. The embedded electrode gallium nitride photoconductive switch according to claim 1, wherein Both the anodic doped gallium nitride layer (2) and the cathodic doped gallium nitride layer (8) are doped gallium nitride layers with a thickness of 0.5 μm to 1.0 μm.

5. The embedded electrode gallium nitride photoconductive switch according to claim 1, wherein The anodic ohmic contact adhesion layer (3) is a first titanium metal layer with a thickness of 10 nm to 20 nm; the anodic ohmic contact barrier layer (4) is a first aluminum metal layer with a thickness of 110 nm to 120 nm; the anodic ohmic contact blocking layer (5) is a first palladium metal layer with a thickness of 45 nm to 55 nm; the anodic ohmic contact antioxidant layer is a first gold metal layer with a thickness of 40 nm to 50 nm.

6. The embedded electrode gallium nitride photoconductive switch according to claim 1, wherein The cathodic ohmic contact adhesion layer (9) is a second titanium metal layer with a thickness of 10 nm to 20 nm; the cathodic ohmic contact barrier layer (10) is a second aluminum metal layer with a thickness of 110 nm to 120 nm; the cathodic ohmic contact blocking layer (11) is a second palladium metal layer with a thickness of 45 nm to 55 nm; the cathodic ohmic contact antioxidant layer (12) is a second gold metal layer with a thickness of 40 nm to 50 nm.

7. The embedded electrode gallium nitride photoconductive switch according to claim 1, wherein The anodic encapsulation layer (7) includes an anodic encapsulation adhesion layer (16) and an anodic encapsulation welding layer (17) which are sequentially arranged from bottom to top along the thickness direction of the substrate (1), and the cathodic encapsulation layer (13) includes a cathodic encapsulation adhesion layer (18) and a cathodic encapsulation welding layer (19) which are sequentially arranged from bottom to top along the thickness direction of the substrate (1); both the anodic encapsulation adhesion layer (16) and the cathodic encapsulation adhesion layer (18) are nickel metal layers with a thickness of 20 nm to 30 nm; both the anodic encapsulation welding layer (17) and the cathodic encapsulation welding layer (19) are third gold metal layers with a thickness of 500 nm to 800 nm.

8. The embedded electrode gallium nitride photoconductive switch according to claim 1, characterized in that, The dielectric passivation layer (14) is a silicon nitride layer with a thickness of 220 nm to 250 nm; the light-triggered antireflection layer (15) is a first silicon oxide layer with a thickness of 90 nm to 100 nm.

9. A method for preparing an embedded electrode gallium nitride photoconductive switch according to any one of claims 1 to 8, characterized in that, Including the following steps: Providing a substrate; Depositing a protective layer on the upper surface of the substrate; Partially etch the protective layer to expose the etched areas of the anode groove and the cathode groove on the upper surface of the substrate; Etch the etched areas again to obtain the anode groove and the cathode groove; Correspondingly deposit an anodic doped gallium nitride layer (2) and a cathodic doped gallium nitride layer (8) on the anode groove and the cathode groove respectively; Remove the protective layer on the upper surface of the substrate; Sequentially deposit an anodic ohmic contact adhesion layer (3), an anodic ohmic contact barrier layer (4), an anodic ohmic contact blocking layer (5) and an anodic ohmic contact antioxidation layer (6) on the upper surface of the anodic doped gallium nitride layer (2), and sequentially deposit a cathodic ohmic contact adhesion layer (9), a cathodic ohmic contact barrier layer (10), a cathodic ohmic contact blocking layer (11), a cathodic ohmic contact antioxidation layer (12) on the upper surface of the cathodic doped gallium nitride layer (8); then perform alloying treatment; Correspondingly deposit an anodic encapsulation layer (7) and a cathodic encapsulation layer (13) on the upper surfaces of the anodic ohmic contact antioxidation layer (6) and the cathodic ohmic contact antioxidation layer (12) respectively; Deposit a silicon nitride layer on the upper surface of the substrate, the upper surface of the anodic encapsulation layer (7) and the upper surface of the cathodic encapsulation layer (13); Partially etch the silicon nitride layer to expose the anodic encapsulation layer (7) and the cathodic encapsulation layer (13), forming a dielectric passivation layer (14), wherein the upper surface of the anodic encapsulation layer (7) is in contact with the lower surface of the dielectric passivation layer (14), and the upper surface of the cathodic encapsulation layer (13) is in contact with the lower surface of the dielectric passivation layer (14); Grind and thin the lower surface of the substrate to form a substrate (1); Deposit a light-triggered antireflection layer (15) on the lower surface of the substrate (1); forming an embedded electrode gallium nitride photoconductive switch.

10. The preparation method of the embedded electrode gallium nitride photoconductive switch according to claim 9, characterized in that, The substrate is a semi-insulating gallium nitride single crystal with a thickness of 325 μm to 350 μm; the protective layer is a second silicon oxide layer with a thickness of 90 nm to 110 nm, the temperature of the alloying treatment is 750 °C to 850 °C, and the time is 40 s to 60 s; after depositing the light-triggered antireflection layer (15) on the lower surface of the substrate (1), annealing is performed to repair the interface defects to obtain an embedded electrode gallium nitride photoconductive switch, the temperature of annealing to repair the interface defects is 110 °C to 130 °C, and the gas used is carbon dioxide.

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