Display device

Abstract

A display device includes: a first display area around a second display area; a first opening in the first display area and the second display area, and a light emitting element disposed in the first opening; a second opening and a third opening in the second display area, the light emitting element being not positioned in the second opening and the third opening, and each of the second opening and the third opening having a size smaller than a size of each of the first openings; a light blocking layer including a light blocking pattern, a first hole overlapping the first opening, a second hole overlapping the second opening, and a third hole around the light blocking pattern, the third hole overlapping a third opening among the third openings; and a plurality of color filters in the first display area and the second display area and overlapping the first holes, in which a number of the first holes in the second display area among the first holes is greater than each of a number of the second holes and a number of the third holes.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10-2024-0015875, filed with the Korean Intellectual Property Office on February 1, 2024, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Aspects of some embodiments of the present disclosure relate to a display device. Background Art

[0004] With the progress of the information society, more and more requirements can be put forward for display devices that display images in various ways. For example, display devices can be adopted in various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, and smart televisions. The display device can be a flat panel display device such as a liquid crystal display device, a field emission display device, and an organic light emitting display device. Among flat panel display devices, in a self-emitting display device, since each of the pixels of the display panel includes a light emitting element capable of emitting light by itself, an image can be displayed without a backlight unit that supplies light to the display panel.

[0005] The above information disclosed in this background art section is only for enhancing the understanding of the background art, and thus the information discussed in this background art section does not necessarily constitute the prior art. Summary of the Invention

[0006] Aspects of some embodiments of the present disclosure include a display device having relatively improved performance in sensing light incident from the side of the display device.

[0007] However, aspects of the present disclosure are not limited to the aspects specifically set forth herein. Through reference to the detailed description given below of the present disclosure, the above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains.

[0008] According to some embodiments of the present disclosure, a display device is provided. The display device includes: a first display area and a second display area, the first display area being positioned around the second display area; a plurality of first openings located in the first display area and the second display area, and light-emitting elements being positioned in the plurality of first openings; a plurality of second openings and a plurality of third openings located in the second display area, the light-emitting elements not being positioned in the plurality of second openings and the plurality of third openings, and each of the plurality of second openings and the plurality of third openings having a size smaller than that of each of the plurality of first openings; a light-blocking layer including a light-blocking pattern, a plurality of first holes overlapping with the plurality of first openings, a plurality of second holes overlapping with the plurality of second openings, and a plurality of third holes around the light-blocking pattern and partially overlapping with third openings among the plurality of third openings; and a plurality of color filters located in the first display area and the second display area and overlapping with the plurality of first holes, wherein the number of first holes among the plurality of first holes in the second display area is greater than each of the number of the plurality of second holes and the number of the plurality of third holes.

[0009] According to some embodiments, each of the plurality of third holes is arranged to surround the light-blocking pattern.

[0010] According to some embodiments, the light-blocking pattern has a circular shape in a plan view, and each of the plurality of third holes has a quadrilateral edge in the plan view.

[0011] According to some embodiments, each of the plurality of second holes has an oval shape in a plan view, and the plurality of third holes are respectively located on both sides of the light-blocking pattern.

[0012] According to some embodiments, each of the plurality of third holes does not overlap with a corresponding one of the plurality of third openings.

[0013] According to some embodiments, the light-blocking pattern has an oval shape in a plan view, and both ends of the light-blocking pattern in the major axis direction are in contact with a portion of the light-blocking layer other than the plurality of first holes, the plurality of second holes, and the plurality of third holes, and third holes among the plurality of third holes are formed between the light-blocking pattern and the portion of the light-blocking layer other than the plurality of first holes, the plurality of second holes, and the plurality of third holes.

[0014] According to some embodiments, the third holes have a width that varies in the major axis direction of the light-blocking pattern.

[0015] According to some embodiments, the number of the plurality of second holes in the second display region is less than the number of the plurality of third holes.

[0016] According to some embodiments, the number of the plurality of second holes in the second display region is greater than or equal to the number of the plurality of third holes.

[0017] According to some embodiments, the plurality of color filters do not overlap with the plurality of second holes and the plurality of third holes.

[0018] According to some embodiments, the plurality of color filters do not overlap with the plurality of second openings and the plurality of third openings.

[0019] According to some embodiments, the display device may further include a plurality of signal lines extending in one direction in the first display region and the second display region, wherein a first opening among the plurality of first openings partially overlaps with the plurality of signal lines, and the plurality of second openings and the plurality of third openings do not overlap with the plurality of signal lines.

[0020] According to some embodiments, the center line between a pair of adjacent signal lines among the plurality of signal lines is not parallel to the center line of each of the plurality of third openings.

[0021] According to some embodiments, the light blocking pattern is integrated with a portion of the light blocking layer other than the plurality of first holes, the plurality of second holes, and the plurality of third holes to cover the plurality of third openings, and a third hole among the plurality of third holes does not overlap with a corresponding one of the plurality of third openings.

[0022] According to some embodiments, some of the plurality of signal lines partially overlap with the light blocking pattern.

[0023] According to some embodiments of the present disclosure, a display device is provided. The display device includes: a substrate including a first display area and a second display area, the first display area being positioned around the second display area; a plurality of pixel electrodes located on the substrate and spaced apart from each other in the first display area and the second display area; a pixel defining layer including a plurality of first openings, a plurality of second openings, and a plurality of third openings, the plurality of first openings being located on the substrate and the plurality of pixel electrodes and overlapping with the plurality of pixel electrodes, the plurality of second openings and the plurality of third openings not overlapping with the plurality of pixel electrodes in the second display area; a encapsulation layer located on the pixel defining layer; a light blocking layer including a light blocking pattern, a plurality of first holes, a plurality of second holes, and a plurality of third holes, the plurality of first holes being located on the encapsulation layer and overlapping with the plurality of first openings, the plurality of second holes overlapping with the plurality of second openings, the plurality of third holes being around the light blocking pattern and overlapping with the plurality of third openings; and a plurality of color filters located on the light blocking layer and overlapping with the plurality of first holes and not overlapping with the plurality of second holes and the plurality of third holes.

[0024] According to some embodiments, the plurality of third holes are defined as a region between the light blocking pattern and a portion of the light blocking layer other than the plurality of first holes, the plurality of second holes, and the plurality of third holes, and a diameter of the light blocking pattern is the same as a diameter of each of the plurality of third openings, and a width of each of the plurality of third holes is the same as a separation distance between each of the plurality of third openings and the light blocking layer.

[0025] According to some embodiments, a diameter of the light blocking pattern is different from a diameter of each of the plurality of third openings.

[0026] According to some embodiments, the light blocking pattern is integrated with a portion of the light blocking layer other than the plurality of first holes, the plurality of second holes, and the plurality of third holes to overlap with the plurality of third openings, and the plurality of third holes do not overlap with the plurality of third openings.

[0027] According to some embodiments, the display device may further include a plurality of signal lines located on the substrate and arranged not to overlap with the plurality of second holes and the plurality of third holes, wherein a center line of a pair of adjacent signal lines among the plurality of signal lines is not parallel to a center line of each of the plurality of third openings.

[0028] The display device according to some embodiments may include a transmissive portion having different opening shapes in a light sensing area. In the display device, the performance of sensing light incident from the side and the performance of sensing light incident from the front may be relatively improved.

[0029] However, the features of the embodiments of the present disclosure are not limited to the above features, and various other features are incorporated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Aspects of some embodiments of the present disclosure will become more apparent by describing the aspects in more detail with reference to the accompanying drawings, in which:

[0031] Figure 1 is a schematic perspective view of an electronic device according to some embodiments;

[0032] Figure 2 is a perspective view showing a display device included in an electronic device according to some embodiments;

[0033] Figure 3 is Figure 2 a cross-sectional view of the display device taken from a side view;

[0034] Figure 4 is Figure 2 a plan view of the display device;

[0035] Figure 5 is a plan view showing the arrangement of holes and emission regions of a light blocking layer in a first display region of a display device according to some embodiments;

[0036] Figure 6 is a plan view showing the arrangement of color filters in a first display region of a display device according to some embodiments;

[0037] Figure 7 is along Figure 5 and Figure 6 a cross-sectional view taken along line X1-X1';

[0038] Figure 8 is a plan view showing the arrangement of emission regions and light transmission regions in a second display region of a display device according to some embodiments;

[0039] Figure 9 is along Figure 8 a cross-sectional view taken along line X2-X2';

[0040] Figure 10 is showing Figure 8 the relative arrangement of emission regions, light transmission regions, and signal lines in the second display region;

[0041] Figure 11 is a plan view showing a second light transmission region of a display device according to some embodiments;

[0042] Figure 12 is showingFigure 11 Cross-sectional view of the second light-transmitting region;

[0043] Figure 13 and Figure 14 is a schematic cross-sectional view of the second light-transmitting region of a display device according to some embodiments;

[0044] Figures 15 to 17 is a plan view showing the second light-transmitting region of a display device according to some embodiments;

[0045] Figure 18 is a plan view showing the first and second light-transmitting regions of a display device according to some embodiments;

[0046] Figure 19 is a plan view showing the second light-transmitting region of a display device according to some embodiments;

[0047] Figure 20 shows Figure 19 Cross-sectional view of the second light-transmitting region;

[0048] Figure 21 is a cross-sectional view showing the second light-transmitting region of a display device according to some embodiments;

[0049] Figure 22 is a cross-sectional view showing the second light-transmitting region of a display device according to some embodiments;

[0050] Figures 23 to 25 is a plan view showing the arrangement of the light-transmitting regions in the second display region of a display device according to some embodiments; and

[0051] Figure 26 and Figure 27 is a cross-sectional view of a display device according to some embodiments. DETAILED DESCRIPTION

[0052] Aspects of some embodiments of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which aspects of some embodiments of the invention are shown. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0053] It will also be understood that when a layer or substrate is referred to as being "on" another layer or substrate, the layer or substrate may be directly on the other layer or substrate, or an intervening layer may also be present. Throughout the specification, the same reference numerals indicate the same components.

[0054] Hereinafter, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0055] Hereinafter, aspects of some embodiments will be described in more detail with reference to the accompanying drawings.

[0056] Figure 1 is a schematic perspective view of an electronic device according to some embodiments.

[0057] Referring to Figure 1 , the electronic device 1 displays moving images (e.g., video images) or still images (e.g., static images). The electronic device 1 may refer to any electronic device that provides a display screen. Examples of the electronic device 1 may include a television, a laptop computer, a monitor, a billboard, an Internet of Things device, a mobile phone, a smartphone, a tablet personal computer (PC), an electronic watch, a smart watch, a watch phone, a head-mounted display, a mobile communication terminal, an electronic notebook, an e-book, a portable multimedia player (PMP), a navigation device, a game console, a digital camera, and a video camera, etc., that provide a display screen.

[0058] The electronic device 1 may include Figure 2 a display device 10 that provides a display screen among . Examples of the display device 10 may include an inorganic light-emitting diode display device, an organic light-emitting display device, a quantum dot light-emitting display device, a plasma display device, and a field emission display device. In the following description, a case where an organic light-emitting diode display device is applied as the display device will be described, but the embodiments of the present disclosure are not limited thereto, and other display devices may be applied within the spirit and scope of the embodiments of the present disclosure.

[0059] The shape of the electronic device 1 may be variously modified. For example, in a plan view, the electronic device 1 may have a shape such as a rectangular shape elongated in the horizontal direction, a rectangular shape elongated in the vertical direction, a square shape, a quadrilateral shape with rounded corners (vertices), other polygonal shapes, and a circular shape. In a plan view, the shape of the display area DA of the electronic device 1 may also be similar to the overall shape of the electronic device 1. Figure 1 shows an electronic device 1 having a rectangular shape elongated in the second direction DR2.

[0060] The electronic device 1 may include a display area DA and a non-display area NDA surrounding the display area DA (outside the periphery of the display area DA or outside the occupied area of the display area DA). The display area DA is an area where an image can be displayed, and the non-display area NDA is an area where an image is not displayed. The display area DA may also be referred to as an effective area, and the non-display area NDA may also be referred to as a non-effective area. The display area DA may occupy the center of the electronic device 1.

[0061] The display area DA may include a first display area DA1, a second display area DA2, and a third display area DA3. The second display area DA2 and the third display area DA3 are areas where components for attaching various functions to the electronic device 1 are located, and the second display area DA2 and the third display area DA3 may correspond to the component area.

[0062] Figure 2 is a perspective view showing a display device included in an electronic device according to some embodiments.

[0063] Referring to Figure 2 , the electronic device 1 according to some embodiments may include a display device 10. The display device 10 may display an image displayed by the electronic device 1. The display device 10 may have a planar shape similar to the shape of the electronic device 1. For example, the display device 10 may have a shape similar to a rectangular shape having a short side in a first direction DR1 and a long side in a second direction DR2. The edge where the short side in the first direction DR1 and the long side in the second direction DR2 meet may be rounded to have a curvature, but the embodiments are not limited thereto and may be formed at a right angle. The planar shape of the display device 10 is not limited to a quadrilateral shape and may be formed in a shape similar to another polygonal shape, a circular shape, or an elliptical shape.

[0064] The display device 10 may include a display panel 100, a display driver 200, a circuit board 300, and a touch driver 400.

[0065] The display panel 100 may include a main area MA and a sub-area SBA.

[0066] The main area MA may include a display area DA and a non-display area NDA. The display area DA includes pixels PX for displaying an image (see Figure 4 ), and the non-display area NDA is arranged around the display area DA. The display area DA may be located at the center of the main area MA, and the non-display area NDA may surround the display area DA. The display area DA may include a first display area DA1, a second display area DA2, and a third display area DA3. The display area DA may emit light from a plurality of emission areas or a plurality of opening areas. For example, the display panel 100 may include a pixel circuit including a switching element, a pixel defining layer defining an emission area or an opening area, and a self-luminous element.

[0067] For example, the self-luminous element may include at least one of an organic light-emitting diode (LED) including an organic light-emitting layer, a quantum dot LED including a quantum dot light-emitting layer, an inorganic LED including an inorganic semiconductor, and a micro LED, but the embodiments are not limited thereto.

[0068] The non-display area NDA can be an area outside the display area DA (e.g., at the periphery of the display area DA or outside the occupied area of the display area DA). The non-display area NDA can be defined as the edge area of the main area MA of the display panel 100. The non-display area NDA can include a gate driver that supplies gate signals to the gate lines and fan-out lines that connect the display driver 200 to the display area DA.

[0069] The sub-area SBA can be an area extending from one side of the main area MA. The sub-area SBA can include flexible materials that can be bent, folded, or curled. For example, when the sub-area SBA is bent, the sub-area SBA can overlap with the main area MA in the thickness direction (the third direction DR3). The sub-area SBA can include the display driver 200 and a pad portion connected to the circuit board 300. According to some embodiments, the sub-area SBA can be omitted, and the display driver 200 and the pad portion can be arranged in the non-display area NDA.

[0070] The display driver 200 can output signals and voltages for driving the display panel 100. The display driver 200 can supply data voltages to the data lines. The display driver 200 can supply power voltages to the power lines and can supply gate control signals to the gate driver. The display driver 200 can be formed as an integrated circuit (IC) and mounted on the display panel 100 by a chip-on-glass (COG) method, a chip-on-plastic (COP) method, or an ultrasonic bonding method. For example, the display driver 200 can be positioned in the sub-area SBA and can overlap with the main area MA in the thickness direction by bending the sub-area SBA. For another example, the display driver 200 can be mounted on the circuit board 300.

[0071] The circuit board 300 can be attached to the pad portion of the display panel 100 by using an anisotropic conductive film (ACF). The leads of the circuit board 300 can be electrically connected to the pad portion of the display panel 100. The circuit board 300 can be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip-on-film.

[0072] The touch driver 400 can be mounted on the circuit board 300. The touch driver 400 can be connected to the touch sensing unit of the display panel 1OO. The touch driver 400 can supply touch drive signals to a plurality of touch electrodes of the touch sensing unit and can sense the amount of change in capacitance between the plurality of touch electrodes. For example, the touch drive signal can be a pulse signal having a frequency (e.g., a set frequency or a predetermined frequency). The touch driver 400 can calculate whether an input has been made and the input coordinates based on the amount of change in capacitance between the plurality of touch electrodes. The touch driver 400 can be formed as an integrated circuit (IC).

[0073] Figure 3Yes Figure 2 Cross-sectional view of the display device as viewed from the side. Figure 3 Shows Figure 2 Sub-region SBA of the display panel 100 in the display device 10 is in a folded state.

[0074] Referring to Figure 3 , the display panel 100 may include a display layer DU, a touch sensing layer TSU, and a color filter layer CFL. The display layer DU may include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML, and a packaging layer TFEL.

[0075] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, or curled. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but is not limited thereto. According to some embodiments, the substrate SUB may include a glass material or a metal material.

[0076] The thin film transistor layer TFTL may be positioned on the substrate SUB. The thin film transistor layer TFTL may include a plurality of thin film transistors that constitute a pixel circuit of a pixel. The thin film transistor layer TFTL may further include a gate line, a data line, a power line, a gate control line, a fan-out line that connects the display driver 200 to the data line, and a lead that connects the display driver 200 to the pad portion. Each of the thin film transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, when the gate driver is formed on one side of the non-display region NDA of the display panel 100, the gate driver may include thin film transistors.

[0077] The thin film transistor layer TFTL may be positioned in the display region DA, the non-display region NDA, and the sub-region SBA. The thin film transistors, gate lines, data lines, and power lines of the thin film transistor layer TFTL may be positioned in the display region DA. The gate control line and the fan-out line of the thin film transistor layer TFTL may be positioned in the non-display region NDA. The leads of the thin film transistor layer TFTL may be positioned in the sub-region SBA.

[0078] The light emitting element layer EML may be positioned on the thin film transistor layer TFTL. The light emitting element layer EML may include a plurality of light emitting elements and a pixel defining layer that defines a pixel. Each of the plurality of light emitting elements includes a first electrode, a second electrode, and a light emitting layer for emitting light. The plurality of light emitting elements of the light emitting element layer EML may be positioned in the display region DA.

[0079] According to some embodiments, the light-emitting layer may be an organic light-emitting layer including an organic material. The light-emitting layer may include a hole transport layer, an organic light-emitting layer, and an electron transport layer. When the first electrode of the light-emitting element receives an anode voltage through the thin-film transistor of the thin-film transistor layer TFTL and the second electrode of the light-emitting element receives a cathode voltage, holes and electrons may be respectively transmitted to the organic light-emitting layer through the hole transport layer and the electron transport layer, and may be recombined with each other to emit light in the organic light-emitting layer.

[0080] According to some embodiments, the light-emitting element may include a quantum dot light-emitting diode including a quantum dot light-emitting layer, an inorganic light-emitting diode including an inorganic semiconductor, or a micro light-emitting diode.

[0081] The encapsulation layer TFEL may cover the top surface and the side surface of the light-emitting element layer EML, and may protect the light-emitting element layer EML. The encapsulation layer TFEL may include at least one inorganic layer and at least one organic layer for encapsulating the light-emitting element layer EML.

[0082] The touch sensing layer TSU may be positioned on the encapsulation layer TFEL. The touch sensing layer TSU may include a plurality of touch electrodes for capacitively sensing a user's touch and touch lines connecting the plurality of touch electrodes to the touch driver 400. For example, the touch sensing layer TSU may sense a user's touch by using a mutual capacitance method or a self-capacitance method.

[0083] According to some embodiments, the touch sensing layer TSU may be positioned on a separate substrate positioned on the display layer DU. In this case, the substrate supporting the touch sensing layer TSU may be a matrix member encapsulating the display layer DU.

[0084] The plurality of touch electrodes of the touch sensing layer TSU may be positioned in a touch sensor area overlapping with the display area DA. The touch lines of the touch sensing layer TSU may be positioned in a touch peripheral area overlapping with the non-display area NDA.

[0085] The color filter layer CFL may be positioned on the touch sensing layer TSU. The color filter layer CFL may include a plurality of color filters respectively corresponding to a plurality of emission areas. Each of the plurality of color filters may selectively transmit light of a specific wavelength and may block or absorb light of different wavelengths. The color filter layer CFL may absorb a part of the light from the outside of the display device 10 to reduce the reflected light caused by the external light. Therefore, the color filter layer CFL may prevent or reduce color distortion caused by the reflection of the external light.

[0086] Since the color filter layer CFL is directly positioned on the touch sensing layer TSU, the display device 10 may not require a separate substrate for the color filter layer CFL. Therefore, the thickness of the display device 10 may be relatively small.

[0087] According to some embodiments, the display device 10 may further include an optical device 500. The optical device 500 may be positioned in the second display area DA2 or the third display area DA3. The optical device 500 may emit or receive light in the infrared band, ultraviolet band, and visible light band. For example, the optical device 500 may be an optical sensor that detects light incident on the display device 10, such as a proximity sensor, an illuminance sensor, and a camera sensor or an image sensor. In the display device 10, the light transmission area where the optical device 500 senses incident light may be positioned in the second display area DA2 and / or the third display area DA3.

[0088] Figure 4 is Figure 2 a plan view of the display device. Figure 4 shows the display device 10 in an unbent state and an unfolded state (see Figure 2 ).

[0089] Referring to Figure 4 , the display device 10 may include a main area MA and a sub area SBA. The main area MA may include a display area DA and a non-display area NDA, and the sub area SBA may include a bank area BNKA, a driving circuit mounting area ICA, and a pad area PA.

[0090] The display area DA may be an area where a plurality of pixels PX are positioned. The pixels PX and the wirings (or some of the wirings) connected to the pixels PX may be positioned in the display area DA.

[0091] The pixels PX may be provided in the thin film transistor layer TFTL (see Figure 3 ) and the light emitting element layer EML (see Figure 3 ) of the display device 10. For example, each pixel PX may include a pixel circuit including circuit elements positioned in the thin film transistor layer TFTL and a light emitting element (e.g., Figure 7 the light emitting element ED) positioned in the light emitting element layer EML.

[0092] The pixel PX may include at least two color emission areas EA that emit light of different colors. For example, the pixel PX may include a first color emission area that emits light of a first color (e.g., red light), a second color emission area that emits light of a second color (e.g., green light), and a third color emission area that emits light of a third color (e.g., blue light).

[0093] At least one first color emission region, at least one second color emission region, and at least one third color emission region adjacent to each other can form a unit pixel (denoted by the same reference numeral PX as the pixel in this text). For example, one first color emission region, two second color emission regions, and one third color emission region adjacent to each other can form a unit pixel PX. Each unit pixel PX can emit various colors of light including white light through color mixing of the light emitted from the emission regions constituting the unit pixel PX. According to some embodiments, the first color emission region and the third color emission region can be alternately arranged in the first direction DR1 and / or the second direction DR2, and the second color emission region can be continuously arranged and / or sequentially arranged in the first direction DR1. The type, shape, and / or arrangement structure of the emission regions can be variously changed according to the embodiments. In addition, the type, number, ratio, and / or arrangement structure of the emission regions constituting each unit pixel PX can also be variously changed according to the embodiments.

[0094] The encapsulation layer TFEL can be positioned on the pixel PX. For example, the encapsulation layer TFEL can be provided at least in the display area DA to cover the pixel PX, and a part of the encapsulation layer TFEL can extend into the non-display area NDA.

[0095] Multiple wirings can be provided in the thin film transistor layer TFTL and can be positioned in the display area DA and the non-display area NDA. In addition, the wirings can also be located in the sub-area SBA. For example, the wirings can extend from the sub-area SBA to the display area DA through the non-display area NDA.

[0096] The non-display area NDA can be positioned around the display area DA (e.g., positioned at the periphery of the display area DA or outside the occupied area of the display area DA). For example, the non-display area NDA can be the edge area of the main area MA located outside the display area DA.

[0097] The non-display area NDA can include a dam area DAMA spaced apart from the display area DA, a first non-display area NDA1 between the display area DA and the dam area DAMA, and a second non-display area NDA2 outside the dam area DAMA. The dam area DAMA can be the area where the dam surrounding the display area DA is positioned. The second non-display area NDA2 can include an inorganic encapsulation area IEA (also referred to as a "bonding area") where the inorganic encapsulation layers of the encapsulation layer TFEL are bonded to each other.

[0098] The sub-region SBA may include a bank region BNKA, a driving circuit mounting region ICA, and a pad region PA that are sequentially arranged on one side of the main region MA. Wiring (or portions of the wiring), banks, and pads PD may be positioned in the sub-region SBA. At least some of the wiring may extend into the main region MA and be connected to the pixels PX.

[0099] The bank region BNKA may be a region in which at least one bank is positioned. According to some embodiments, the bank region BNKA may overlap with the bending region BA. For example, the bank region BNKA may include a bending region BA spaced apart from the main region MA and first and second edge regions BEA1 and BEA2 located on both sides of the bending region BA in the second direction DR2. Banks may be provided in the bending region BA and the peripheral region of the bending region BA (e.g., the first and second edge regions BEA1 and BEA2 of the bank region BNKA) to cover the wiring passing through the bending region BA. The display panel 100 may be bent in the bending region BA such that a part of the sub-region SBA may be located behind the main region MA.

[0100] The driving circuit mounting region ICA may be a region in which the display driver 200 is positioned. Pads for connecting at least some of the wiring to the display driver 200 may be positioned in the driving circuit mounting region ICA. For example, in the driving circuit mounting region ICA, input pads for connecting the display driver 200 to specific pads (e.g., data input pads) in the pad region PA and output pads for connecting the display driver 200 to the pixels PX may be positioned.

[0101] According to some embodiments, the display driver 200 may not be positioned on the display panel 100. In this case, the display device 10 may not include the driving circuit mounting region ICA, and only the wiring may be positioned in the region between the bank region BNKA and the pad region PA.

[0102] The pad region PA may be a region in which pads PD for connecting the display device 10 and / or the display driver 200 to a circuit board 300 or the like are positioned. The circuit board 300 may be positioned or bonded on the pad region PA.

[0103] A plurality of pads PD including power pads and signal pads connected to the pixels PX, the display driver 200, and / or the embedded circuit may be positioned in the pad region PA. A power voltage for driving the pixels PX, the display driver 200, and / or the embedded circuit or the like may be supplied to the power pads. Driving signals and / or image data for driving the pixels PX, the display driver 200, and / or the embedded circuit or the like may be supplied to the signal pads. The type, position, arrangement order, and / or number of the pads PD may be variously changed according to the embodiments.

[0104] Figure 5 is a plan view showing the arrangement of holes and emission regions of a light-blocking layer in a first display area of a display device according to some embodiments. Figure 6 is a plan view showing the arrangement of color filters in a first display area of a display device according to some embodiments. Figure 5 and Figure 6 show the arrangement of a first hole OPT1, a second hole OPT2, and a third hole OPT3 of a light-blocking layer BM (see Figure 7 ) positioned in a first display area DA1 and emission regions EA1, EA2, and EA3. Figure 7 is a cross-sectional view taken along line X1-X1' of Figure 5 and Figure 6 . Figure 7 shows a cross-section across a first pixel electrode AE1, a second pixel electrode AE2, and a third pixel electrode AE3 in a unit pixel PX (see Figure 4 ) of a first display area DA1.

[0105] Referring to ​ , ​ and ​ , the display device 10 may include a plurality of emission regions EA1, EA2, and EA3 positioned in a first display area DA1. The plurality of emission regions EA1, EA2, and EA3 may be arranged in a type (e.g., diamond type). For example, the plurality of emission regions EA1, EA2, and EA3 may be arranged in a fourth direction DR4 and a fifth direction DR5, which are diagonal directions between a first direction DR1 and a second direction DR2. The first emission region EA1 and the second emission region EA2 may be positioned adjacent to each other in the fifth direction DR5 or the fourth direction DR4, and the second emission region EA2 and the third emission region EA3 may be positioned adjacent to each other in the fourth direction DR4 or the fifth direction DR5. The first emission region EA1 and the third emission region EA3 may be arranged to be spaced apart from each other in the second direction DR2 or the first direction DR1. In the arrangement of the emission regions EA1, EA2, and EA3, the first emission region EA1 and the third emission region EA3 may be alternately arranged in the first direction DR1 in a first row R1 and a third row R3. In a first column C1 and a third column C3, the first emission region EA1 and the third emission region EA3 may be alternately arranged in the second direction DR2. The second emission region EA2 may be repeatedly arranged in the first direction DR1 in a second row R2 and a fourth row R4, and the second emission region EA2 may be repeatedly arranged in the second direction DR2 in a second column C2 and a fourth column C4.

[0106] According to some embodiments, in the display device 10, the plurality of pixel electrodes AE1, AE2, and AE3 may be repeatedly arranged throughout the entire first display area DA1 in a ​ layout. For example, one pixel PX (see ​ ) may include one first pixel electrode AE1, two second pixel electrodes AE2, and one third pixel electrode AE3. The first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be arranged similarly to the layout of the emission areas EA1, EA2, and EA3. However, the embodiments according to the present disclosure are not limited thereto. The number and layout of the pixel electrodes AE1, AE2, and AE3 positioned in the pixel PX may be variously modified.

[0107] Each of the pixel electrodes AE1, AE2, and AE3 may be an anode electrode of a light-emitting element ED included in the pixel PX (see ​ ). One pixel PX may include one or more light-emitting elements ED (see ​ ), and the light-emitting element ED may be a light-emitting element that emits light of different colors. For example, the light-emitting element ED including the first pixel electrode AE1 may emit first light of red color. The light-emitting element ED including the second pixel electrode AE2 may emit second light of green color, and the light-emitting element ED including the third pixel electrode AE3 may emit third light of blue color. However, the embodiments according to the present disclosure are not limited thereto. One first pixel electrode AE1, two second pixel electrodes AE2, and one third pixel electrode AE3 may form one pixel PX, and may emit light of different colors and exhibit a white gray level. However, the embodiments according to the present disclosure are not limited thereto, and the combination of the pixel electrodes AE1, AE2, and AE3 constituting one pixel PX may be variously modified according to the layout of the pixel electrodes AE1, AE2, and AE3 and the color of the light emitted by the light-emitting element ED, etc.

[0108] According to some embodiments, the emission areas EA1, EA2, and EA3 of the display device 10 may be areas overlapping with the pixel electrodes AE1, AE2, and AE3. For example, ​The openings OPE1, OPE2, and OPE3 of the pixel defining layer PDL shown in the figure may correspond to the emission regions EA1, EA2, and EA3, and the pixel electrodes AE1, AE2, and AE3 may overlap with the openings OPE1, OPE2, and OPE3, respectively. For example, the first pixel electrode AE1 may overlap with the first emission region EA1 that emits light of a first color, the second pixel electrode AE2 may overlap with the second emission region EA2 that emits light of a second color, and the third pixel electrode AE3 may overlap with the third emission region EA3 that emits light of a third color. The first emission region EA1 may be defined by the first opening OPE1 of the pixel defining layer PDL that overlaps with the first pixel electrode AE1, the second emission region EA2 may be defined by the second opening OPE2 of the pixel defining layer PDL that overlaps with the second pixel electrode AE2, and the third emission region EA3 may be defined by the third opening OPE3 of the pixel defining layer PDL that overlaps with the third pixel electrode AE3.

[0109] According to some embodiments, the areas or sizes of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may be different from each other. In addition, the areas or sizes of the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be different from each other. According to some embodiments shown in ​ the figure, the area of the third emission region EA3 may be greater than the areas of the first emission region EA1 and the second emission region EA2, and the area of the first emission region EA1 may be greater than the area of the second emission region EA2. The areas of the emission regions EA1, EA2, and EA3 may vary according to the sizes of the openings OPE1, OPE2, and OPE3 formed in the pixel defining layer PDL. In addition, the area of the third pixel electrode AE3 may be greater than the areas of the first pixel electrode AE1 and the second pixel electrode AE2, and the area of the first pixel electrode AE1 may be greater than the area of the second pixel electrode AE2. The brightness of the emitted light may vary according to the areas of the emission regions EA1, EA2, and EA3 that overlap with the pixel electrodes AE1, AE2, and AE3, and the areas of the emission regions EA1, EA2, and EA3 may be adjusted to control the color of the screen displayed in the electronic device 1 (see ​ ) or the display device 10. According to some embodiments shown in ​In some embodiments shown, the third emission region EA3 is shown to have the largest area, but is not limited thereto. The sizes and areas of the pixel electrodes AE1, AE2, and AE3 and the emission regions EA1, EA2, and EA3 can be freely adjusted according to the colors of the images required by the display device 10 and the electronic device 1. In addition, the areas of the pixel electrodes AE1, AE2, and AE3 can be related to the luminous efficiency and lifespan of the light-emitting element ED, and can have a trade-off relation with the reflection of external light. Considering the above factors, the areas of the pixel electrodes AE1, AE2, and AE3 can be adjusted.

[0110] The display device 10 may further include a light-blocking layer BM positioned on the pixel electrodes AE1, AE2, and AE3 and a plurality of color filters CF1, CF2, and CF3.

[0111] The light-blocking layer BM may be disposed throughout the display area DA (see ​ )(e.g., ​ the first display area DA1 in ​ ). The light-blocking layer BM may include a plurality of holes OPT1, OPT2, and OPT3 arranged to correspond to the pixel electrodes AE1, AE2, and AE3, respectively. The holes OPT1, OPT2, and OPT3 of the light-blocking layer BM may be arranged to correspond to the openings OPE1, OPE2, and OPE3 of the pixel defining layer PDL (see

[0112] ). The light-blocking layer BM may cover the remaining area of the display area DA except for the areas in the display area DA where the holes OPT1, OPT2, and OPT3 are located. The holes OPT1, OPT2, and OPT3 of the light-blocking layer BM may be regions where the light emitted from the light-emitting element ED including the pixel electrodes AE1, AE2, and AE3 is emitted. ​ ) occupied by one pixel PX (see

[0113] The plurality of holes OPT1, OPT2, and OPT3 may each have an area in a plan view that is larger than the area of the plurality of emission regions EA1, EA2, and EA3, or the plurality of openings OPE1, OPE2, and OPE3, and the plurality of pixel electrodes AE1, AE2, and AE3. For example, the first hole OPT1 may have an area in a plan view that is larger than the area of the first opening OPE1. The second hole OPT2 and the third hole OPT3 may also each have an area in a plan view that is larger than the area of the second opening OPE2 and the third opening OPE3, respectively. In addition, each of the holes OPT1, OPT2, and OPT3 in the light blocking layer BM may have a different area in a plan view. As described above, the plurality of emission regions EA1, EA2, and EA3, the plurality of openings OPE1, OPE2, and OPE3, and the plurality of pixel electrodes AE1, AE2, and AE3 may have different areas, such that the holes OPT1, OPT2, and OPT3 in the light blocking layer BM may also have different sizes. For example, the diameter or size of the third hole OPT3 may be greater than the diameter or size of the first hole OPT1 and the second hole OPT2, and the diameter or size of the first hole OPT1 may be greater than the diameter or size of the second hole OPT2. However, the embodiments according to the present disclosure are not limited thereto.

[0114] The plurality of color filters CF1, CF2, and CF3 may be arranged to correspond to the emission regions EA1, EA2, and EA3, respectively. For example, the color filters CF1, CF2, and CF3 may be positioned on the light blocking layer BM and may be arranged to correspond to the plurality of holes OPT1, OPT2, and OPT3 in the light blocking layer BM, respectively. The holes OPT1, OPT2, and OPT3 in the light blocking layer BM may be formed to overlap the openings OPE1, OPE2, and OPE3 of the pixel defining layer PDL (see ​ ) respectively, and may form light emission regions through which light emitted from the emission regions EA1, EA2, and EA3 passes. Each of the color filters CF1, CF2, and CF3 may have an area larger than the area of each of the holes OPT1, OPT2, and OPT3 in the light blocking layer BM, and the color filters CF1, CF2, and CF3 may completely cover the light emission regions formed by the holes OPT1, OPT2, and OPT3. Each of the color filters CF1, CF2, and CF3 may completely cover the corresponding one of the holes OPT1, OPT2, and OPT3 in the light blocking layer BM, and some of the color filters CF1, CF2, and CF may be directly positioned on the light blocking layer BM. However, according to some embodiments, the color filters CF1, CF2, and CF3 may be omitted.

[0115] The color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3 arranged to correspond to different emission regions EA1, EA2, and EA3, respectively. The color filters CF1, CF2, and CF3 may include colorants such as dyes or pigments that absorb light in a band different from that of light in a specific band, and may be arranged to correspond to the colors of light emitted by the light-emitting elements ED including the pixel electrodes AE1, AE2, and AE3. For example, the first color filter CF1 may be a red color filter arranged to overlap with the first emission region EA1 or the first opening OPE1 and transmit only the first light of red. The second color filter CF2 may be a green color filter arranged to overlap with the second emission region EA2 or the second opening OPE2 and transmit only the second light of green, and the third color filter CF3 may be a blue color filter arranged to overlap with the third emission region EA3 or the third opening OPE3 and transmit only the third light of blue.

[0116] Similar to the arrangement of the emission regions EA1, EA2, and EA3, the color filters CF1, CF2, and CF3 may be arranged to type (e.g., diamond type). For example, the first color filter CF1 and the third color filter CF3 may be alternately arranged in a first direction DR1 and a second direction DR2. The second color filter CF2 and another adjacent second color filter CF2 may be arranged in the first direction DR1 and the second direction DR2, and the second color filter CF2 and the adjacent first color filter CF1 and the adjacent third color filter CF3 may be arranged in a fourth direction DR4 or a fifth direction DR5. A plurality of second color filters CF2 may be repeatedly arranged along the first direction DR1 and the second direction DR2, and the second color filter CF2 and the first color filter CF1 or the second color filter CF2 and the third color filter CF3 may be alternately arranged along the fourth direction DR4 or the fifth direction DR5.

[0117] According to some embodiments, the plurality of color filters CF1, CF2, and CF3 may have different areas in a plan view. As described above, the areas of the plurality of emission regions EA1, EA2, and EA3 may be different from each other, and thus the sizes and areas of the holes OPT1, OPT2, and OPT3 of the light-blocking layer BM and the color filters CF1, CF2, and CF3 in the plan view may also be different from each other. For example, the area of the third color filter CF3 as a blue color filter may be larger than the area of the second color filter CF2 as a green color filter and the area of the first color filter CF1 as a red color filter. In addition, the area of the first color filter CF1 may be larger than the area of the second color filter CF2.

[0118] The color filters CF1, CF2, and CF3 may have a quadrilateral shape, a rectangular shape, or a rhombus shape including sides extending in a fourth direction DR4 and a fifth direction DR5. The first color filter CF1 and the third color filter CF3 may have sides of the same length extending in the fourth direction DR4 and the fifth direction DR5, and may have a quadrilateral shape or a rhombus shape in a plan view. The area of the third color filter CF3 in the plan view may be greater than the area of the first color filter CF1, and the second color filter CF2 adjacent to the first color filter CF1 and the third color filter CF3 may have sides of different lengths extending in the fourth direction DR4 and the fifth direction DR5 and may have a rectangular shape in the plan view. In other words, the extending sides of the first color filter CF1 and the third color filter CF3 have the same length, and thus may have a shape that is not affected by the position, while the extending sides of the second color filter CF2 have different lengths, and thus may have different extending directions of the long sides depending on the position. In the case of describing ​ the shape of the second color filter CF2 shown, for example, the second color filter CF2 positioned in the second column C2 of the second row R2 may have a shape in which the long side extends in the fifth direction DR5, and the second color filter CF2 positioned in the fourth column C4 of the second row R2 may have a shape in which the long side extends in the fourth direction DR4.

[0119] However, the embodiments according to the present disclosure are not limited thereto. According to some embodiments, the shapes of the color filters CF1, CF2, and CF3 in the plan view may be circular shapes similar to the shapes of the emission regions EA1, EA2, and EA3. The display device 10 according to some embodiments may be designed such that the planar shapes and areas of the color filters CF1, CF2, and CF3 allow the light emitted from the display device 10 to have a specific color.

[0120] According to some embodiments, the ratio of the planar area of the first color filter CF1 to the second color filter CF2 may be in the range of 1:0.3 to 1:0.7 (or approximately 1:0.3 to 1:0.7), and the ratio of the area of the first color filter CF1 to the third color filter CF3 may be in the range of 1:0.4 to 1:1 (or approximately 1:0.4 to 1:1). For example, the area ratio of the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be 1:0.59:0.52 or 1:0.59:1. However, the area ratio of the color filters CF1, CF2, and CF3 is not limited to the above area ratio, and the planar areas of the color filters CF1, CF2, and CF3 may be designed differently such that the reflected light in the display device 10 and the electronic device 1 (see ​ ) has desired color coordinates.

[0121] The display device 10 may include color filters CF1, CF2, and CF3 positioned on the display layer DU to reduce the intensity of reflected light caused by external light. In addition, the color of the reflected light caused by external light can be controlled by adjusting the arrangement, shape, and area of the color filters CF1, CF2, and CF3 in a plan view.

[0122] The touch electrode TL may be positioned between the emission regions EA1, EA2, and EA3 or between the holes OPT1, OPT2, and OPT3 of the light blocking layer BM. The touch electrode TL may be arranged to extend in the fourth direction DR4 and the fifth direction DR5 and may be spaced apart from the holes OPT1, OPT2, and OPT3 of the light blocking layer BM. The touch electrode TL may be arranged to overlap with the pixel defining layer PDL (see ​ ).) and the light blocking layer BM. Although the touch electrode TL is briefly shown in the drawings, the touch electrode TL may include a touch driving electrode and a sensing electrode.

[0123] Reference will be made to ​ to describe the cross-sectional structure of the display device 10. The display device 10 may include a display layer DU, a touch sensing layer TSU, a light blocking layer BM, a color filter layer CFL, and an outer coating OC. The display layer DU may include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML, and a packaging layer TFEL. The light blocking layer BM may be positioned on the touch sensing layer TSU of the display panel 100, and the color filters CF1, CF2, and CF3 of the color filter layer CFL may be positioned on the light blocking layer BM. The outer coating OC may be positioned on the color filter layer CFL and the light blocking layer BM.

[0124] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, or curled. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but is not limited thereto. For another example, the substrate SUB may include a glass material or a metal material.

[0125] The thin film transistor layer TFTL may include a first buffer layer BF1, a lower metal layer BML, a second buffer layer BF2, a thin film transistor TFT, a gate insulating layer GI, a first interlayer insulating layer ILD1, a capacitor electrode CPE, a second interlayer insulating layer ILD2, a first connection electrode CNE1, a first passivation layer PAS1, a second connection electrode CNE2, and a second passivation layer PAS2.

[0126] The first buffer layer BF1 may be positioned on the substrate SUB. The first buffer layer BF1 may include an inorganic layer capable of preventing or reducing the penetration of contaminants such as air or moisture. For example, the first buffer layer BF1 may include a plurality of inorganic layers stacked alternately.

[0127] The lower metal layer BML can be positioned on the first buffer layer BF1. For example, the lower metal layer BML can be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or their alloys.

[0128] The second buffer layer BF2 can cover the first buffer layer BF1 and the lower metal layer BML. The second buffer layer BF2 can include an inorganic layer capable of preventing or reducing the penetration of contaminants such as air or moisture. For example, the second buffer layer BF2 can include a plurality of inorganic layers stacked alternately.

[0129] The thin film transistor TFT can be positioned on the second buffer layer BF2 and can constitute the pixel circuit of each of the plurality of pixels. For example, the thin film transistor TFT can be a switching transistor or a driving transistor of the pixel circuit. The thin film transistor TFT can include a semiconductor layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0130] The semiconductor layer ACT can be positioned on the second buffer layer BF2. The semiconductor layer ACT can overlap with the lower metal layer BML and the gate electrode GE in the thickness direction and can be insulated from the gate electrode GE through a gate insulating layer GI. In a part of the semiconductor layer ACT, the material of the semiconductor layer ACT can be made into a conductor to form the source electrode SE and the drain electrode DE.

[0131] The gate electrode GE can be positioned on the gate insulating layer GI. The gate electrode GE can overlap with the semiconductor layer ACT and the gate insulating layer GI is interposed between the gate electrode GE and the semiconductor layer ACT.

[0132] The gate insulating layer GI can be positioned on the semiconductor layer ACT. For example, the gate insulating layer GI can cover the semiconductor layer ACT and the second buffer layer BF2 to insulate the gate electrode GE from the semiconductor layer ACT. The gate insulating layer GI can include a contact hole through which a first connection electrode CNE1 passes.

[0133] The first interlayer insulating layer ILD1 can cover the gate electrode GE and the gate insulating layer GI. The first interlayer insulating layer ILD1 can include a contact hole through which a first connection electrode CNE1 passes. The contact hole of the first interlayer insulating layer ILD1 can be connected to the contact hole of the gate insulating layer GI and the contact hole of the second interlayer insulating layer ILD2.

[0134] The capacitor electrode CPE can be positioned on the first interlayer insulating layer ILD1. The capacitor electrode CPE can overlap with the gate electrode GE in the thickness direction. The capacitor electrode CPE and the gate electrode GE can form a capacitance.

[0135] The second interlayer insulating layer ILD2 may cover the capacitor electrode CPE and the first interlayer insulating layer ILD1. The second interlayer insulating layer ILD2 may include contact holes through which the first connection electrode CNE1 passes. The contact holes of the second interlayer insulating layer ILD2 may be connected to the contact holes of the first interlayer insulating layer ILD1 and the contact holes of the gate insulating layer GI.

[0136] The first connection electrode CNE1 may be positioned on the second interlayer insulating layer ILD2. The first connection electrode CNE1 may electrically connect the drain electrode DE of the thin film transistor TFT to the second connection electrode CNE2. The first connection electrode CNE1 may be embedded in the contact holes provided in the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the gate insulating layer GI to contact the drain electrode DE of the thin film transistor TFT.

[0137] The first passivation layer PAS1 may cover the first connection electrode CNE1 and the second interlayer insulating layer ILD2. The first passivation layer PAS1 may protect the thin film transistor TFT. The first passivation layer PAS1 may include contact holes through which the second connection electrode CNE2 passes.

[0138] The second connection electrode CNE2 may be positioned on the first passivation layer PAS1. The second connection electrode CNE2 may electrically connect the first connection electrode CNE1 to the pixel electrode AE of the light emitting element ED. The second connection electrode CNE2 may be embedded in the contact holes formed in the first passivation layer PAS1 to contact the first connection electrode CNE1.

[0139] The second passivation layer PAS2 may cover the second connection electrode CNE2 and the first passivation layer PAS1. The second passivation layer PAS2 may include contact holes through which the pixel electrode AE of the light emitting element ED passes.

[0140] The light emitting element layer EML may be positioned on the thin film transistor layer TFTL. The light emitting element layer EML may include a light emitting element ED and a pixel defining layer PDL. The light emitting element ED may include pixel electrodes AE1, AE2, and AE3, a light emitting layer EL, and a common electrode CE.

[0141] The pixel electrodes AE1, AE2, and AE3 may be positioned on the second passivation layer PAS2. Each of the different pixel electrodes AE1, AE2, and AE3 may be arranged to overlap with one of the different openings OPE1, OPE2, and OPE3 of the pixel defining layer PDL. The pixel electrodes AE1, AE2, and AE3 may be electrically connected to the drain electrode DE of the thin film transistor TFT through the first connection electrode CNE1 and the second connection electrode CNE2.

[0142] The light-emitting layer EL can be positioned on the pixel electrodes AE1, AE2, and AE3. For example, the light-emitting layer EL can be an organic light-emitting layer made of an organic material, but is not limited thereto. In the case of using an organic light-emitting layer as the light-emitting layer EL, the thin-film transistor TFT applies a voltage (e.g., a set voltage or a predetermined voltage) to the pixel electrodes AE1, AE2, and AE3 of the light-emitting element ED, and if the common electrode CE of the light-emitting element ED receives a common voltage or a cathode voltage, holes and electrons can move through the hole transport layer and the electron transport layer to the light-emitting layer EL and recombine to generate light to be emitted by the light-emitting layer EL.

[0143] According to some embodiments, the light-emitting layer EL positioned on different pixel electrodes AE1, AE2, and AE3 can emit lights of different colors. For example, the light-emitting layer EL positioned on the first pixel electrode AE1 can emit red light of the first color, the light-emitting layer EL positioned on the second pixel electrode AE2 can emit green light of the second color, and the light-emitting layer EL positioned on the third pixel electrode AE3 can emit blue light of the third color. However, the present disclosure is not limited thereto. According to some embodiments, the light-emitting layer EL can be arranged as a common layer on different pixel electrodes AE1, AE2, and AE3 and the pixel defining layer PDL, or the light-emitting layer EL positioned on different pixel electrodes AE1, AE2, and AE3 can emit lights of the same color. In this case, the display device 10 can further include a color adjustment layer positioned on the light-emitting element ED.

[0144] The common electrode CE can be arranged on the light-emitting layer EL. For example, the common electrode CE can be formed in the form of an electrode common to all pixels PX (see ​ ) rather than an electrode specific to each of the pixels. The common electrode CE can be positioned on the light-emitting layer EL on the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3, and can be positioned on the pixel defining layer PDL in an area other than the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3.

[0145] The common electrode CE can receive a common voltage or a low-potential voltage. When the pixel electrode AE receives a voltage corresponding to a data voltage and the common electrode CE receives a low-potential voltage, a potential difference is formed between the pixel electrodes AE1, AE2, and AE3 and the common electrode CE, such that the light-emitting layer EL can emit light.

[0146] The pixel defining layer PDL can include a plurality of openings OPE1, OPE2, and OPE3 (see ​ and ​) and can be positioned on a part of the second passivation layer PAS2 and a part of the pixel electrodes AE1, AE2, and AE3. The openings OPE1, OPE2, and OPE3 of the pixel definition layer PDL can respectively expose a part of the pixel electrodes AE1, AE2, and AE3. As described above, each of the openings OPE1, OPE2, and OPE3 of the pixel definition layer PDL can define the corresponding one of the first emission region EA1, the second emission region EA2, and the third emission region EA3, and the areas or dimensions of the openings OPE1, OPE2, and OPE3 can be different. The pixel definition layer PDL can separate and insulate the pixel electrodes AE1, AE2, and AE3 of each of the plurality of light-emitting elements ED. The pixel definition layer PDL can include a light-absorbing material to prevent or reduce light reflection. For example, the pixel definition layer PDL can include a polyimide (PI)-type adhesive and a pigment in which red, green, and blue are mixed. Alternatively, the pixel definition layer PDL can include a Cardo-type adhesive resin and a mixture of a lactam black pigment and a blue pigment. Alternatively, the pixel definition layer PDL can include carbon black.

[0147] The encapsulation layer TFEL can be positioned on the common electrode CE to cover the plurality of light-emitting elements ED. The encapsulation layer TFEL can include at least one inorganic layer to prevent or reduce the penetration of contaminants such as oxygen or moisture into the light-emitting element layer EML. The encapsulation layer TFEL can include at least one organic layer to protect the light-emitting element layer EML from foreign substances such as dust.

[0148] According to some embodiments, the encapsulation layer TFEL can include a first encapsulation layer TFE1, a second encapsulation layer TFE2, and a third encapsulation layer TFE3. The first encapsulation layer TFE1 and the third encapsulation layer TFE3 can be inorganic encapsulation layers, and the second encapsulation layer TFE2 positioned between the first encapsulation layer TFE1 and the third encapsulation layer TFE3 can be an organic encapsulation layer.

[0149] Each of the first encapsulation layer TFE1 and the third encapsulation layer TFE3 can include one or more inorganic insulating materials. The inorganic insulating materials can include alumina, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0150] The second encapsulation layer TFE2 can include a polymer-type material. Examples of the polymer-type material can include acrylic resin, epoxy resin, polyimide, and polyethylene, etc. For example, the second encapsulation layer TFE2 can include an acrylic resin, for example, polymethyl methacrylate or polyacrylic acid, etc. The second encapsulation layer TFE2 can be formed by curing a monomer or coating a polymer.

[0151] The touch sensing layer TSU may be positioned on the encapsulation layer TFEL. The touch sensing layer TSU may include a first touch insulating layer SIL1, a second touch insulating layer SIL2, a touch electrode TL, and a third touch insulating layer SIL3.

[0152] The first touch insulating layer SIL1 may be positioned on the encapsulation layer TFEL. The first touch insulating layer SIL1 may have an insulating function and an optical function. The first touch insulating layer SIL1 may include at least one inorganic layer. Optionally, the first touch insulating layer SIL1 may be omitted.

[0153] The second touch insulating layer SIL2 may cover the first touch insulating layer SIL1. According to some embodiments, a touch electrode TL of another layer may be further positioned on the first touch insulating layer SIL1, and the second touch insulating layer SIL2 may cover the touch electrode TL of the said another layer. The second touch insulating layer SIL2 may have an insulating function and an optical function. For example, the second touch insulating layer SIL2 may be an inorganic layer including at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0154] A part of the touch electrode TL may be positioned on the second touch insulating layer SIL2. The touch electrode TL may not overlap with the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3. The touch electrode TL may be formed of a single layer including molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or indium tin oxide (ITO), or may be formed into a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an Ag-Pd-Cu (APC) alloy, or a stacked structure of an APC alloy and ITO (ITO / APC / ITO).

[0155] The touch electrode TL of the touch sensing layer TSU may have a constant line width and may be arranged to overlap with a light blocking layer BM to be described later. The light blocking layer BM may have a width sufficient to completely cover the touch electrode TL, and a gap between the edge of the light blocking layer BM and the touch electrode TL may be defined. According to some embodiments, the line width of the touch electrode TL may be in the range of 4 μm to 6 μm, and the gap between the edge of the touch electrode TL and the light blocking layer BM may be in the range of 5 μm to 7 μm. The touch electrode TL may be arranged such that the center of the touch electrode TL is almost parallel to the center of the light blocking layer BM, and the gaps from both sides of the touch electrode TL to the edge of the light blocking layer BM may be constant (or substantially constant).

[0156] The third touch insulating layer SIL3 may cover the touch electrode TL and the second touch insulating layer SIL2. The third touch insulating layer SIL3 may have an insulating function and an optical function. The third touch insulating layer SIL3 may be made of a material described and characterized in connection with the second touch insulating layer SIL2.

[0157] The light blocking layer BM may be positioned on the third touch insulating layer SIL3 of the touch sensing layer TSU. The light blocking layer BM may be arranged to cover the wires of the touch electrode TL while including a plurality of holes OPT1, OPT2, and OPT3 that overlap with the pixel electrodes AE1, AE2, and AE3. For example, the first hole OPT1 may be arranged to overlap with the first pixel electrode AE1. The second hole OPT2 may be arranged to overlap with the second pixel electrode AE2, and the third hole OPT3 may be arranged to overlap with the third pixel electrode AE3. The area or size of the holes OPT1, OPT2, and OPT3 may be larger than the area or size of the pixel electrodes AE1, AE2, and AE3. In addition, the holes OPT1, OPT2, and OPT3 are formed to be larger in area or size than the openings OPE1, OPE2, and OPE3 of the pixel defining layer PDL, such that light emitted from the light emitting element ED can be visually recognized by the user not only from the front but also from the side of the display device 10.

[0158] The light blocking layer BM may include a light absorbing material. For example, the light blocking layer BM may include an inorganic black pigment or an organic black pigment. The inorganic black pigment may be carbon black, and the organic black pigment may include at least one of lactam black, perylene black, and aniline black, but the embodiments are not limited thereto. The light blocking layer BM may prevent or reduce visible light penetration and color mixing between the holes OPT1, OPT2, and OPT3, which may lead to an improvement in the color reproducibility of the display device 10. According to some embodiments, the light blocking layer BM may have a thickness of 1 μm to 3 μm or 1.5 μm (or approximately 1.5 μm).

[0159] The color filters CF1, CF2, and CF3 of the color filter layer CFL can be positioned on the light blocking layer BM. The different color filters CF1, CF2, and CF3 can be arranged to correspond to different pixel electrodes AE1, AE2, and AE3 and the holes OPT1, OPT2, and OPT3 of the light blocking layer BM, respectively. For example, the first color filter CF1 can be arranged to correspond to the first pixel electrode AE1, the second color filter CF2 can be arranged to correspond to the second pixel electrode AE2, and the third color filter CF3 can be arranged to correspond to the third pixel electrode AE3. The first color filter CF1 can be positioned in the first hole OPT1 of the light blocking layer BM, the second color filter CF2 can be positioned in the second hole OPT2 of the light blocking layer BM, and the third color filter CF3 can be positioned in the third hole OPT3 of the light blocking layer BM. Each of the color filters CF1, CF2, and CF3 can be formed to have an area larger than the area of the corresponding one of the holes OPT1, OPT2, and OPT3 of the light blocking layer BM in a plan view, and some of the color filters CF1, CF2, and CF3 can be directly positioned on the light blocking layer BM.

[0160] The areas of the plurality of color filters CF1, CF2, and CF3 can vary according to the sizes of the holes OPT1, OPT2, and OPT3 of the light blocking layer BM. For example, the first color filter CF1 can have an area larger than the area of the second color filter CF2 in a plan view, but can have an area smaller than the area of the third color filter CF3 in a plan view.

[0161] The outer coating OC can be positioned on the light blocking layer BM and the color filter layer CFL. The outer coating OC can be arranged throughout the entire display area DA (see ​ ) to flatten the top surface of the display device 10. The outer coating OC can be a colorless light-transmitting layer that does not have a color in the visible light band. For example, the outer coating OC can include a colorless light-transmitting organic material such as an acrylic resin.

[0162] ​ is a plan view showing the arrangement of the emission regions and the light transmission regions in the second display area of a display device according to some embodiments. ​ is a cross-sectional view taken along the line ​ X2-X2' of ​ is a view showing ​ the relative arrangement of the emission regions, the light transmission regions, and the signal lines in the second display area of

[0163] For example, ​ shows a plurality of light transmission regions TA1 and TA2 in the second display area DA2, but the description can be equivalently applied to the third display area DA3 (see ​ ).

[0164] Reference ​ , the display device 10 may include a plurality of light transmission regions TA1 and TA2 and a plurality of emission regions EA1, EA2, and EA3 located in the second display region DA2 and the third display region DA3 of the display region DA (see ​ ). The touch electrodes TL, color filters CF1, CF2, and CF3, and the light blocking layer BM may also be located in the second display region DA2. In addition, according to some embodiments, pixel electrodes AE1, AE2, and AE3 may be located in the second display region DA2 and the third display region DA3 to correspond to the emission regions EA1, EA2, and EA3, and light may be emitted from the light emitting element ED. The description is the same as that described above.

[0165] The plurality of light transmission regions TA1 and TA2 may be located between adjacent emission regions EA1, EA2, and EA3. For example, the plurality of light transmission regions TA1 and TA2 may be located between two second emission regions EA2 adjacent in the first direction DR1 and between two emission regions EA1 and EA3 adjacent in the second direction DR2. The plurality of light transmission regions TA1 and TA2 may be adjacent to the second emission region EA2 in the first direction DR1 and may be adjacent to the first emission region EA1 and the third emission region EA3 in the second direction DR2. The plurality of light transmission regions TA1 and TA2 may be located in the first column C1 and the third column C3 of the second row R2 and the fourth row R4. On the other hand, the light transmission regions TA1 and TA2 may not be located in the first row R1 and the third row R3. In addition, as shown in the drawings, the light transmission regions TA1 and TA2 may not be located in the first column C1 of the second row R2, but the present disclosure is not limited thereto.

[0166] According to some embodiments, in the second display region DA2 of the display device 10, the number of the first light transmission regions TA1 and the number of the second light transmission regions TA2 per unit region UTA may be different. For example, in the second display region DA2, a unit region UTA corresponding to four pixel regions may be defined. According to some embodiments in which one first emission region EA1, two second emission regions EA2, and one third emission region EA3 correspond to one pixel region, four first emission regions EA1, eight second emission regions EA2, and four third emission regions EA3 may be located in the unit region UTA of the second display region DA2.

[0167] The arrangement of the first light transmission regions TA1 and the second light transmission regions TA2 may be similar to or substantially similar to the arrangement of the second emission region EA2. That is, there may be a space for placing eight light transmission regions TA1 and TA2 in a unit region UTA. In the display device 10, the number of the first holes OPT1, the second holes OPT2, and the third holes OPT3 corresponding to the emission regions EA1, EA2, and EA3 in the second display region DA2 may be greater than the number of the fourth hole OPT4 and the fifth hole OPT5.

[0168] In the display device 10, the eight light transmission regions TA1 and TA2 do not necessarily have to be formed in the unit region UTA of the second display region DA2, but only some of the eight light transmission regions TA1 and TA2 may be formed in the unit region UTA of the second display region DA2. For example, in the display device 10, four first light transmission regions TA1 and two second light transmission regions TA2 may be formed in the unit region UTA of the second display region DA2. That is, the display device 10 may have an arrangement of "4 / 6 first light transmission regions TA1 + 2 / 6 second light transmission regions TA2". In the display device 10, the number of the first light transmission regions TA1 in the unit region UTA may be greater than the number of the second light transmission regions TA2. In addition, the arrangement of the number and space of the light transmission regions TA1 and TA2 that may be formed in the unit region UTA may be the same as the number and arrangement of the second holes OPT2 corresponding to the second emission region EA2, but the number of each of the first light transmission regions TA1 and the second light transmission regions TA2 in the second display region DA2 may be less than the number of the second holes OPT2. However, the present disclosure is not limited thereto, and the arrangement and number of the light transmission regions TA1 and TA2 may be variously modified.

[0169] The plurality of light transmission regions TA1 and TA2 may be defined by the fourth hole OPT4 and the fifth hole OPT5 of the light blocking layer BM. For example, the first light transmission region TA1 may be formed in the fourth hole OPT4 of the light blocking layer BM that overlaps with the fourth opening OPE4 of the pixel defining layer PDL. The plurality of color filters CF1, CF2, and CF3 may not be positioned in the first light transmission region TA1 and form a color filter opening CFO that overlaps with the fourth hole OPT4. In the thin film transistor layer TFTL, the wirings and electrodes may not be positioned at the portion overlapping with the first light transmission region TA1 and the fourth opening OPE4, and the light incident from the outside of the display device 10 may be transmitted to the rear surface of the substrate SUB in the first light transmission region TA1. The optical device 500 (see ​ ) positioned in the second display region DA2 may sense the light incident from the outside through the first light transmission region TA1.

[0170] The second light transmission region TA2 may be defined by the fifth hole OPT5 of the light blocking layer BM. According to some embodiments, the light blocking layer BM may include a light blocking pattern BMP arranged to overlap with the fifth opening OPE5 of the pixel defining layer PDL, and the fifth hole OPT5 may be arranged to surround the light blocking pattern BMP. The second light transmission region TA2 may also be formed to surround the light blocking pattern BMP. The plurality of color filters CF1, CF2, and CF3 may not be positioned in the second light transmission region TA2 and on the light blocking pattern BMP and form a color filter opening CFO overlapping with the fifth hole OPT5. In the thin film transistor layer TFTL, wirings and electrodes may not be positioned at portions overlapping with the second light transmission region TA2 and the fifth opening OPE5, and light incident from the outside of the display device 10 may be transmitted to the rear surface of the substrate SUB in the second light transmission region TA2. The optical device 500 positioned in the second display region DA2 may also sense light incident from the outside through the second light transmission region TA2.

[0171] The pixel defining layer PDL may include a fourth opening OPE4 and a fifth opening OPE5 positioned in the second display region DA2. The fourth opening OPE4 may overlap with the fourth hole OPT4 of the light blocking layer BM. The fifth opening OPE5 may overlap with the light blocking pattern BMP surrounded by the fifth hole OPT5 of the light blocking layer BM. The size or diameter of the fourth opening OPE4 and the fifth opening OPE5 may be smaller than the size or diameter of the first opening OPE1, the second opening OPE2, and the third opening OPE3, and the size or diameter of the light transmission regions TA1 and TA2 may be smaller than the size or diameter of the first hole OPT1, the second hole OPT2, and the third hole OPT3. Although the pixel defining layer PDL may include a light absorbing material, the pixel defining layer PDL is not positioned in the first light transmission region TA1 so that light can be smoothly incident on the optical device 500. In addition, the fifth opening OPE5 of the pixel defining layer PDL is positioned at the lower part of the second light transmission region TA2 so that light incident from the side can be incident on the optical device 500. The common electrode CE of the encapsulation layer TFEL and the light emitting element ED may be positioned at the fourth opening OPE4 and the fifth opening OPE5 of the pixel defining layer PDL.

[0172] As ​As shown, the display device 10 may include a plurality of signal lines SWR1 and SWR2 extending in a second direction DR2, and the plurality of signal lines SWR1 and SWR2 may be arranged across a plurality of emission regions EA1, EA2, and EA3. The signal lines SWR1 and SWR2 may be positioned on a first passivation layer PAS1 and may overlap with pixel electrodes AE1, AE2, and AE3. The pixel electrodes AE1, AE2, and AE3 may be positioned in the emission regions EA1, EA2, and EA3, and light incident from the outside may be reflected from the pixel electrodes AE1, AE2, and AE3 without reaching the substrate SUB. In addition, a light-emitting layer EL is positioned on the pixel electrodes AE1, AE2, and AE3 to emit light, such that the signal lines SWR1 and SWR2 may be positioned in the emission regions EA1, EA2, and EA3.

[0173] However, a first light-transmissive region TA1 overlaps with a fourth opening OPE4 of a pixel defining layer PDL and transmits light, such that the signal lines SWR1 and SWR2 may not overlap with the first light-transmissive region TA1 and the fourth opening OPE4 of the pixel defining layer PDL. A pair of a first signal line SWR1 and a second signal line SWR2 may extend side by side in the second direction DR2 and then may be bent around the first light-transmissive region TA1 so as not to overlap with the first light-transmissive region TA1.

[0174] Similarly, in the case of a second light-transmissive region TA2, light is transmitted through a fifth opening OPE5 of the pixel defining layer PDL, such that the signal lines SWR1 and SWR2 may not overlap with the second light-transmissive region TA2, a light-blocking pattern BMP, and the fifth opening OPE5 of the pixel defining layer PDL. A pair of a first signal line SWR1 and a second signal line SWR2 may extend side by side in the second direction DR2 and then may be bent around the second light-transmissive region TA2 so as not to overlap with the second light-transmissive region TA2. The first signal line SWR1 and the second signal line SWR2 may be arranged to overlap with the pixel defining layer PDL around the fourth opening OPE4 and the fifth opening OPE5 of the pixel defining layer PDL, respectively.

[0175] However, the present disclosure is not limited thereto. A region where light does not enter from both the front surface and the side surface of the display device 10 may be formed at a portion of the fifth opening OPE5 of the pixel defining layer PDL that overlaps with the light-blocking pattern BMP, and the signal lines SWR1 and SWR2 may be positioned in the corresponding region. In this case, the signal lines SWR1 and SWR2 may overlap with the light-blocking pattern BMP.

[0176] The touch electrode TL may also be positioned in the second display area DA2. The touch electrode TL may be arranged to extend in a fourth direction DR4 and a fifth direction DR5, and may extend while bypassing the light transmission areas TA1 and TA2. A part of the touch electrode TL may be bent near the light transmission areas TA1 and TA2. The touch electrode TL may be arranged not to overlap with the fourth opening OPE4 and the fifth opening OPE5 of the pixel defining layer PDL. As described above, the touch electrode TL may be arranged to bypass the light transmission areas TA1 and TA2 in a plan view, and may be arranged to be spaced apart from the fourth opening OPE4 and the fifth opening OPE5 in a cross-sectional view.

[0177] The light blocking layer BM may include a fourth hole OPT4 overlapping with the fourth opening OPE4, a light blocking pattern BMP overlapping with the fifth opening OPE5, and a fifth hole OPT5 arranged around the light blocking pattern BMP. The size or area of the fourth hole OPT4 may be larger than the size or area of the fourth opening OPE4. Since the fourth hole OPT4 of the light blocking layer BM is formed to be larger than the fourth opening OPE4 of the pixel defining layer PDL, the optical device 500 may sense light even if light entering from the outside is incident from a side surface of the display device 10 other than the front surface. The fifth hole OPT5 may have a width (e.g., a set width or a predetermined width), and may be positioned at the periphery of the light blocking pattern BMP (e.g., may be arranged to surround the periphery of the light blocking pattern BMP). Since the fifth hole OPT5 is positioned at the periphery of the light blocking pattern BMP overlapping with the fifth opening OPE5, the light incident from the side surface of the display device 10 may be transmitted through the fifth hole OPT5 and the fifth opening OPE5 and incident on the optical device 500. The size or area of the fifth hole OPT5 may be larger than the size or area of the fifth opening OPE5.

[0178] The color filters CF1, CF2, and CF3 of the color filter layer CFL may be positioned on the light blocking layer BM, and may be arranged not to cover the light transmission areas TA1 and TA2. The color filters CF1, CF2, and CF3 may be arranged to be spaced apart from the edges of the fourth hole OPT4 and the edges of the fifth hole OPT5 of the light blocking layer BM. Accordingly, the color filters CF1, CF2, and CF3 may not be arranged around the fourth hole OPT4 and the fifth hole OPT5 of the light blocking layer BM, such that a part of the light blocking layer BM may be exposed. In addition, on the light blocking layer BM, a color filter opening CFO may be formed in an area where the color filters CF1, CF2, and CF3 are not positioned, and the area is an area overlapping with the light transmission areas TA1 and TA2. The size or area of the color filter opening CFO may be formed to be larger than the size or area of the fourth hole OPT4 and the fifth hole OPT5, and a part of the top surface of the light blocking layer BM may not be covered by the color filters CF1, CF2, and CF3 in the second display area DA2.

[0179] According to some embodiments, in the display device 10, different types of light transmission regions TA1 and TA2 may be positioned in the second display region DA2. The first light transmission region TA1 overlaps with the fourth opening OPE4 of the pixel defining layer PDL, and thus may transmit most of the light incident from the front of the display device 10. In addition, light incident from the side of the display device 10 at a specific angle rather than from the front of the display device 10 may be partially transmitted through the first light transmission region TA1. Here, the transmittance of the light incident from the outside of the display device 10 may be affected by the sizes of the light transmission regions TA1 and TA2. As the sizes of the light transmission regions TA1 and TA2 become larger, the transmittance of the light incident on the second display region DA2 may increase.

[0180] Meanwhile, in the display device 10, in terms of the transmittance of the light in the second display region DA2, the field of view (FOV) angle may be defined as the angle of the incident light having a transmittance of 50% compared to the transmittance of the light incident from the front. As the light transmission regions TA1 and TA2 formed in the second display region DA2 easily transmit the light incident from the side and as the areas of the light transmission regions TA1 and TA2 increase, the FOV angle may increase. The display device 10 according to some embodiments includes, in addition to the first light transmission region TA1 overlapping with the opening (i.e., the fourth opening OPE4) of the pixel defining layer PDL, a second light transmission region TA2 having a shape surrounding a light blocking pattern BMP overlapping with the opening (i.e., the fifth opening OPE5) of the pixel defining layer PDL, such that the transmittance of the light incident from the side may be relatively improved. In addition, the display device 10 may have a characteristic of having a large number of pixels per inch (PPI) due to a large number of pixels arranged in a relatively small area. Accordingly, the empty space where the wiring of the thin film transistor layer TFTL is not arranged is reduced, and the sizes of the light transmission regions TA1 and TA2 are reduced. However, the display device 10 includes the second light transmission region TA2 such that the transmittance in the second display region DA2 may be high. For example, the lateral transmittance of the second light transmission region TA2 may be relatively improved.

[0181] Hereinafter, the second light transmission region TA2 will be described in more detail with reference to other drawings.

[0182] ​ is a plan view showing a second light transmission region of a display device according to some embodiments. ​ is a view showing ​ a cross-sectional view of the second light transmission region of

[0183] Referring to ​ and ​, the second light transmission region TA2 can be defined as the region between the light blocking layer BM and the light blocking pattern BMP. The light blocking pattern BMP can overlap with the fifth opening OPE5, and the second light transmission region TA2 can surround the light blocking pattern BMP. According to some embodiments, the light blocking pattern BMP and the fifth opening OPE5 of the pixel defining layer PDL can have a circular shape in a plan view, and the second light transmission region TA2 or the fifth hole OPT5 can have an annular shape surrounding the light blocking pattern BMP.

[0184] The width of the second light transmission region TA2 or the fifth hole OPT5 can vary according to the separation distance D2 between the end of the fifth opening OPE5 of the pixel defining layer PDL and the fifth hole OPT5 of the light blocking layer BM and the size of the light blocking pattern BMP. Here, the separation distance D2 between the pixel defining layer PDL and the light blocking layer BM can be set according to the above-mentioned FOV angle, the thickness T between the light blocking layer BM and the pixel defining layer PDL, and the refractive index of the material between the light blocking layer BM and the pixel defining layer PDL. For example, the light L incident at an incident angle θ1 can pass through the second light transmission region TA2 and be incident at a refraction angle θ2 due to the refractive index of the material between the light blocking layer BM and the pixel defining layer PDL. Here, in order for the incident light to be incident on at least the fifth opening OPE5 of the pixel defining layer PDL and pass through the display device 10, the separation distance D2 between the pixel defining layer PDL and the light blocking layer BM can have the relationship of the following equation (1).

[0185] Equation (1)

[0186] D2 = T × tan(θ2)

[0187] Here, "D2" is the separation distance in the plan view between the light blocking layer BM in the fifth hole OPT5 and the pixel defining layer PDL in the fifth opening OPE, "T" is the thickness between the light blocking layer BM and the pixel defining layer PDL, and "θ2", which is the refraction angle of the incident light, is a value set by the incident angle θ1 and the refractive index of the material between the light blocking layer BM and the pixel defining layer PDL.

[0188] The value of "T" is set according to the thickness specification and the materials used in the manufacturing process of the display device 10, and the refraction angle θ2 can also be set according to the FOV angle or the incident angle θ1. Therefore, the separation distance D2 between the light blocking layer BM in the fifth hole OPT5 and the pixel defining layer PDL in the fifth opening OPE5 can be fixed, and the width D3 of the second light transmission region TA2 can vary according to the size of the light blocking pattern BMP.

[0189] According to some embodiments, the size of the light-blocking pattern BMP may be the same as the width D1 of the fifth opening OPE5 of the pixel defining layer PDL, and the width D3 of the second light-transmitting region TA2 may be the same as the separation distance D2 between the light-blocking layer BM in the fifth hole OPT5 and the pixel defining layer PDL in the fifth opening OPE5. The width of the portion of the light-blocking layer BM penetrated by the fifth hole OPT5 and the light-blocking pattern BMP may have a value of "2×D2 + D1". However, the present disclosure is not limited thereto, and the width D3 of the second light-transmitting region TA2 may vary according to the size of the light-blocking pattern BMP.

[0190] ​ and ​ is a schematic cross-sectional view of a second light-transmitting region of a display device according to some embodiments.

[0191] Referring to ​ FIG. [Reference numeral], in the display device 10 according to some embodiments, the size of the light-blocking pattern BMP may be smaller than the width D1 of the fifth opening OPE5 of the pixel defining layer PDL, and the width D3 of the second light-transmitting region TA2 may be greater than the separation distance D2 between the light-blocking layer BM in the fifth hole OPT5 and the pixel defining layer PDL in the fifth opening OPE5. Referring to ​ FIG. [Reference numeral], in the display device 10 according to some embodiments, the size of the light-blocking pattern BMP may be greater than the width D1 of the fifth opening OPE5 of the pixel defining layer PDL, and the width D3 of the second light-transmitting region TA2 may be smaller than the separation distance D2 between the light-blocking layer BM in the fifth hole OPT5 and the pixel defining layer PDL in the fifth opening OPE5. According to some embodiments, the size of the light-blocking pattern BMP may have a deviation of 5 μm to 10 μm from the width D1 of the fifth opening OPE5, and the width D3 of the second light-transmitting region TA2 may have a deviation of 2.5 μm to 5 μm from the separation distance D2 between the light-blocking layer BM in the fifth hole OPT5 and the pixel defining layer PDL in the fifth opening OPE5. However, also in the case of the above embodiments, the diameter of the portion of the light-blocking layer BM penetrated by the fifth hole OPT5 and the light-blocking pattern BMP may have a value of "2×D2 + D1".

[0192] The display device 10 according to some embodiments includes a second light-transmitting region TA2 in addition to the first light-transmitting region TA1, and since the display device 10 has a specification with a large PPI value, even if the areas of the light-transmitting regions TA1 and TA2 become smaller, the lateral transmittance can be relatively improved.

[0193] Hereinafter, various embodiments of the display device 10 will be described with reference to other drawings.

[0194] ​It is a plan view showing a second light transmission region of a display device according to some embodiments.

[0195] Referring to ​ , according to some embodiments, in the display device 10 (see ​ ), the light blocking pattern BMP and the fifth hole OPT5 or the second light transmission region TA2 may have different shapes. For example, similar to the above embodiments, circular holes may be formed in the light blocking layer BM, and the fifth hole OPT5 and the light blocking pattern BMP may be positioned in the circular holes. However, differently, the light blocking pattern BMP may have an elliptical shape, and each of the upper and lower sides of the light blocking pattern BMP may be in contact with or connected to the light blocking layer BM, that is, both ends of the light blocking pattern BMP in the major axis direction are in contact with the light blocking layer BM. The fifth hole OPT5 or the second light transmission region TA2 may be formed on the left and right sides of the light blocking pattern BMP. The shape of the fifth opening OPE5 of the pixel defining layer PDL (see ​ ) may also have an elliptical shape to correspond to the change in the shape of the light blocking pattern BMP, that is, the fifth hole OPT5 has a width that varies in the major axis direction of the light blocking pattern BMP. However, the present disclosure is not limited thereto. The fifth opening OPE5 of the pixel defining layer PDL may not follow the shape of the light blocking pattern BMP.

[0196] The display device 10 according to some embodiments may be different from the above embodiments in that the light blocking pattern BMP and the fifth hole OPT5 or the second light transmission region TA2 have different shapes. The second light transmission region TA2 may have a shape that does not surround the light blocking pattern BMP and may have different widths according to the position. Due to the change in the shapes of the light blocking pattern BMP and the second light transmission region TA2, the display device 10 may have a structure that is favorable for the incidence of light incident from the left and right sides.

[0197] Referring to ​ and ​ , the shapes of the light blocking pattern BMP and the fifth hole OPT5 may be different from each other. For example, as in the embodiment of ​ , the light blocking pattern BMP may have a circular shape in a plan view, and the fifth hole OPT5 of the light blocking layer BM may have a quadrilateral edge. On the contrary, in the embodiment of ​ , the light blocking pattern BMP may have a quadrilateral shape in a plan view, and the fifth hole OPT5 of the light blocking layer BM may have a circular edge. The width of the second light transmission region TA2 between the light blocking layer BM and the light blocking pattern BMP may vary according to the position. As described above, the pixel defining layer PDL (see ​) The fifth opening OPE5 may follow the shape of the light blocking pattern BMP, or may not follow the shape of the light blocking pattern BMP.

[0198] ​ is a plan view showing a first light transmission region and a second light transmission region of a display device according to some embodiments.

[0199] Referring to ​ , in the display device 10 (see ​ ), the shape of the second light transmission region TA2 may be designed to be different from the shape of the first light transmission region TA1. If the shape of the first light transmission region TA1 is not conducive to the sensing of laterally incident light, the second light transmission region TA2 may have a corresponding shape that is conducive to the sensing of laterally incident light. For example, in the display device 10, the first light transmission region TA1 or the fourth hole OPT4 of the light blocking layer BM may have an elliptical shape in the plan view, and compared with a circular shape, the first light transmission region TA1 may have a low transmittance for laterally incident light incident from the left or right. In response to this, the fifth hole OPT5 of the light blocking layer BM or the second light transmission region TA2 may be formed on the left and right sides of the light blocking pattern BMP. The second light transmission region TA2, which is a light transmission region for compensating the lateral light transmittance of the first light transmission region TA1, may not have to surround the light blocking pattern BMP and may not have a uniform transmittance in all four directions. In ​ 's display device 10, the second light transmission region TA2 may be formed only on both sides of the light blocking pattern BMP to ensure the transmittance of laterally incident light.

[0200] ​ is a plan view showing a second light transmission region of a display device according to some embodiments. ​ is showing ​ 's cross-sectional view of the second light transmission region.

[0201] Referring to ​ and ​ , in the display device 10 according to some embodiments, the fifth opening OPE5 of the pixel defining layer PDL may not completely overlap with the second light transmission region TA2 or the fifth hole OPT5 of the light blocking layer BM. The fifth opening OPE5 of the pixel defining layer PDL may overlap with the light blocking layer BM and may be covered by the light blocking layer BM. The fifth hole OPT5 of the light blocking layer BM may form the second light transmission region TA2, and a separate light blocking pattern BMP may not be arranged. Since the second light transmission region TA2 and the fifth opening OPE5 are arranged to be misaligned and not aligned, the second light transmission region TA2 may have a shape for ensuring the transmittance of laterally incident light.

[0202] Even if the pixel defining layer PDL and the light blocking layer BM have ​ the arrangement as shown in ​ , the separation distance D2 between the end of the fifth opening OPE5 of the pixel defining layer PDL and the fifth hole OPT5 of the light blocking layer BM can also be set according to the above equation (1) based on the thickness T between the light blocking layer BM and the pixel defining layer PDL and the refractive index of the material between the light blocking layer BM and the pixel defining layer PDL.

[0203] According to some embodiments, the center of the fifth opening OPE5 of the pixel defining layer PDL may not be aligned with the center SMP between the signal lines SWR1 and SWR2 whose centers are not spaced apart from each other. The pixel defining layer PDL may be arranged to cover the signal lines SWR1 and SWR2 and may have an arrangement in which the light incident in the fifth opening OPE5 is not reflected by the signal lines SWR1 and SWR2. In the above embodiments, the center SMP (or center line) between the spaced-apart signal lines SWR1 and SWR2 is aligned with the center (or center line) of the fifth opening OPE5, but in the display device 10 according to some embodiments, the two centers (or center lines) may not be aligned with each other. In the case of a structure in which the incident light that has passed through the second light transmission region TA2 and the fifth opening OPE5 is not reflected by the signal lines SWR1 and SWR2, various designs can be made for the positions of the fifth hole OPT5 of the light blocking layer BM and the fifth opening OPE5 of the pixel defining layer PDL.

[0204] ​ FIG. 9 is a cross-sectional view showing a second light transmission region of a display device according to some embodiments.

[0205] Referring to ​ FIG. 9, the second color filter CF2 located in the second display region DA2 may be arranged not to overlap with the second light transmission region TA2 or the fifth hole OPT5 of the light blocking layer BM, and a color filter opening CFO may be formed. The second color filter CF2 may be arranged not to overlap with the light blocking pattern BMP, and a separate light blocking pattern BMP may not be arranged. Therefore, the fifth opening OPE5 of the pixel defining layer PDL may also overlap with the color filter opening CFO. On the other hand, in the display device 10 of ​ FIG. 9, the second light transmission region TA2 and the fifth opening OPE5 of the pixel defining layer PDL do not overlap and are not aligned, so that the second color filter CF2 may not overlap with the second light transmission region TA2 but may overlap with the fifth opening OPE5. Since the second light transmission region TA2 is a hole for transmitting the light incident from the side, even if the fifth opening OPE5 overlaps with the second color filter CF2, the light that has passed through the second light transmission region TA2 can be incident on the fifth opening OPE5.

[0206] ​It is a cross-sectional view showing a second light transmission region of a display device according to some embodiments.

[0207] Referring to ​ , according to some embodiments, in the display device 10, any one of the signal lines SWR1 and SWR2 may overlap with the fifth opening OPE5 of the pixel defining layer PDL. In addition, the light blocking pattern BMP surrounded by the second light transmission region TA2 may overlap with at least one of the signal lines SWR1 or SWR2 positioned below the light blocking pattern BMP.

[0208] Since the light blocking pattern BMP is arranged to overlap with the fifth opening OPE5, a region where light does not enter can be formed at a part of the fifth opening OPE5. Even if the light incident from the side of the display device 10 passes through the second light transmission region TA2 and enters the fifth opening OPE5, a region where a part of the fifth opening OPE5 is covered by the light blocking pattern BMP can be formed, and even if the signal lines SWR1 and SWR2 are positioned in the corresponding region, the light may not be reflected. In the display device 10, it may be advantageous that the signal lines SWR1 and SWR2 are not positioned in the fifth opening OPE5 in order to ensure the transmittance of external incident light. However, in the display device 10, the pixels per inch (PPI) can be increased by arranging a large number of pixels in a relatively small area, and the signal lines SWR1 and SWR2 may be positioned in the region of the fifth opening OPE5 covered by the light blocking pattern BMP to maximize the space utilization in the small area.

[0209] ​ It is a plan view showing the arrangement of the light transmission regions in the second display region of a display device according to some embodiments.

[0210] Referring to ​ , according to some embodiments, the number of the first light transmission regions TA1 and the number of the second light transmission regions TA2 per unit region UTA may be different in the second display region DA2 of the display device 10. As described above, in the second display region DA2, a unit region UTA corresponding to four pixel regions may be defined, and there may be a space in the unit region UTA where eight light transmission regions TA1 and TA2 can be positioned.

[0211] In ​ the display device 10, six first light transmission regions TA1 and two second light transmission regions TA2 may be positioned in the unit region UTA. In the unit region UTA, the number of the first light transmission regions TA1 may be greater than the number of the second light transmission regions TA2, and the display device 10 may have an arrangement of "6 / 8 first light transmission regions TA1 + 2 / 8 second light transmission regions TA^2".

[0212] In ​ In the display device 10 of ​ , four first light-transmitting regions TA1 and four second light-transmitting regions TA2 may be positioned in a unit region UTA. In the unit region UTA, the number of first light-transmitting regions TA1 may be the same as the number of second light-transmitting regions TA2, and the display device 10 may have an arrangement of "4 / 8 first light-transmitting regions TA1 + 4 / 8 second light-transmitting regions TA2".

[0213] In ​ In the display device 10 of ​ , two first light-transmitting regions TA1 and six second light-transmitting regions TA2 may be positioned in a unit region UTA. In the unit region UTA, the number of first light-transmitting regions TA1 may be less than the number of second light-transmitting regions TA2, and the display device 10 may have an arrangement of "2 / 8 first light-transmitting regions TA1 + 6 / 8 second light-transmitting regions TA2".

[0214] In the display device 10, the number and arrangement of the light-transmitting regions TA1 and TA2 may be variously designed according to the desired values of the transmittance of the laterally incident light or the FOV characteristics.

[0215] ​ And ​ are cross-sectional views of a display device according to some embodiments.

[0216] Referring to ​ In the display device 10 according to some embodiments, the color filters CF1, CF2, and CF3 may be arranged to partially overlap. The plurality of color filters CF1, CF2, and CF3 may overlap with different adjacent color filters on the light-blocking layer BM. For example, the second color filter CF2 may overlap with each of the adjacent first color filter CF1 and third color filter CF3 on the light-blocking layer BM. According to some embodiments, the first color filter CF1 may overlap with the third color filter CF3 on the light-blocking layer BM, and according to some embodiments, all the first color filters CF1, second color filters CF2, and third color filters CF3 may overlap.

[0217] Referring to ​ In the display device 10 according to some embodiments, the light-blocking layer BM may not be included, but rather may include color-blocking layers CFB1 and CFB2, which are made of the same material as the color filters CF1, CF2, and CF3. The color filters CF1, CF2, and CF3 and the color-blocking layers CFB1 and CFB2 may overlap with each other between the adjacent emission regions EA1, EA2, and EA3, and may serve the same function as the light-blocking layer BM.

[0218] For example, the first color filter CF1 may be arranged to overlap with the first pixel electrode AE1 and cover the peripheral region of the first pixel electrode AE1. The first color blocking layer CFB1 including the same material as the first color filter CF1 may be positioned at the boundary between the second emission region EA2 overlapping with the second pixel electrode AE2 and the third emission region EA3 overlapping with the third pixel electrode AE3.

[0219] The third color filter CF3 may be arranged to overlap with the third pixel electrode AE3 and cover the peripheral region of the third pixel electrode AE3. A part of the third color filter CF3 may be positioned on the first color filter CF1 and the first color blocking layer CFB1. A part of the first color filter CF1 may be positioned at the boundary between the first emission region EA1 overlapping with the first pixel electrode AE1 and the second emission region EA2 overlapping with the second pixel electrode AE2, and the second color blocking layer CFB2 including the same material as the third color filter CF3 may be positioned on this part of the first color filter CF1.

[0220] The second color filter CF2 may be arranged to overlap with the second pixel electrode AE2 and cover the peripheral region of the second pixel electrode AE2. A part of the second color filter CF2 may be positioned on the first color blocking layer CFB1 and the second color blocking layer CFB2.

[0221] The color filters CF1, CF2, and CF3 or the color blocking layers CFB1 and CFB2 including different color materials may overlap at the boundaries between the emission regions EA1, EA2, and EA3 overlapping with the corresponding pixel electrodes AE1, AE2, and AE3. Thus, they may serve the same function as the light blocking layer BM and may block the transmission of light. The holes OPT1, OPT2, and OPT3 through which light is transmitted may be formed in the regions of the color filters CF1, CF2, and CF3 that do not overlap with the color blocking layers CFB1 and CFB2 or the color filters CF1, CF2, and CF3 including different color materials.

[0222] At the end of the detailed description, those skilled in the art will appreciate that many changes and modifications can be made to the disclosed embodiments without departing from the spirit and scope of the embodiments according to the present disclosure. Therefore, the disclosed embodiments of the present invention are used only in a general and descriptive sense and not for purposes of limitation.

Claims

1. A display device, wherein, The display device includes: A first display area and a second display area, wherein the first display area is arranged around the second display area; A plurality of first openings, located in the first display area and the second display area, and light-emitting elements are arranged in the plurality of first openings; A plurality of second openings and a plurality of third openings, located in the second display area, the light-emitting elements are not positioned in the plurality of second openings and the plurality of third openings, and each of the plurality of second openings and the plurality of third openings has a size smaller than that of each of the plurality of first openings; A light-blocking layer, including a light-blocking pattern, a plurality of first holes, a plurality of second holes, and a plurality of third holes, the plurality of first holes overlap with the plurality of first openings, the plurality of second holes overlap with the plurality of second openings, the plurality of third holes are around the light-blocking pattern, and the plurality of third holes at least partially overlap with the third openings among the plurality of third openings; and A plurality of color filters, located in the first display area and the second display area and overlapping with the plurality of first holes, wherein, the number of the first holes among the plurality of first holes in the second display area is greater than each of the number of the plurality of second holes and the number of the plurality of third holes.

2. The display device according to claim 1, wherein, Each of the plurality of third holes is arranged to surround the light-blocking pattern.

3. The display device according to claim 2, wherein, The light-blocking pattern has a circular shape in a plan view, and Each of the plurality of third holes has a quadrilateral edge in the plan view.

4. The display device according to claim 1, wherein, Each of the plurality of second holes has an elliptical shape in a plan view, and the plurality of third holes are respectively arranged on both sides of the light-blocking pattern.

5. The display device according to claim 1, wherein, Each of the plurality of third holes does not overlap with a corresponding one of the plurality of third openings.

6. The display device according to claim 1, wherein, The light-blocking pattern has an elliptical shape in a plan view, and both ends of the light-blocking pattern in the major axis direction are in contact with the part of the light-blocking layer other than the plurality of first holes, the plurality of second holes, and the plurality of third holes, and The third holes among the plurality of third holes are formed between the light-blocking pattern and the part of the light-blocking layer other than the plurality of first holes, the plurality of second holes, and the plurality of third holes.

7. The display device according to claim 6, wherein, The third holes have a width that varies in the major axis direction of the light-blocking pattern.

8. The display device according to claim 1, wherein, The number of the plurality of second holes in the second display area is less than the number of the plurality of third holes.

9. The display device according to claim 1, wherein, The number of the plurality of second holes in the second display area is greater than or equal to the number of the plurality of third holes.

10. The display device according to claim 1, wherein, The plurality of color filters do not overlap with the plurality of second holes and the plurality of third holes.

11. The display device according to claim 10, wherein, The plurality of color filters do not overlap with the plurality of second openings and the plurality of third openings.

12. The display device according to claim 1, wherein, The display device further includes: a plurality of signal lines, located in the first display area and the second display area and extending in one direction, wherein, A first opening among the plurality of first openings partially overlaps with the plurality of signal lines, and The plurality of second openings and the plurality of third openings do not overlap with the plurality of signal lines.

13. The display device according to claim 12, wherein, The center line between a pair of adjacent signal lines among the plurality of signal lines is not parallel to the center line of each of the plurality of third openings.

14. The display device according to claim 12, wherein the light-blocking pattern is integrated with a portion of the light-blocking layer other than the plurality of first holes, the plurality of second holes, and the plurality of third holes to cover the plurality of third openings, and a third hole among the plurality of third holes does not overlap with a corresponding one of the plurality of third openings.

15. The display device according to claim 12, wherein, Some of the plurality of signal lines partially overlap with the light-blocking pattern.

16. A display device, wherein, The display device includes: a substrate including a first display area and a second display area, the first display area being disposed around the second display area; a plurality of pixel electrodes located on the substrate and spaced apart from each other in the first display area and the second display area; a pixel defining layer including a plurality of first openings, a plurality of second openings, and a plurality of third openings, the plurality of first openings being located on the substrate and the plurality of pixel electrodes and overlapping with the plurality of pixel electrodes, the plurality of second openings and the plurality of third openings not overlapping with the plurality of pixel electrodes in the second display area; a packaging layer located on the pixel defining layer; a light-blocking layer including a light-blocking pattern, a plurality of first holes, a plurality of second holes, and a plurality of third holes, the plurality of first holes being located on the packaging layer and overlapping with the plurality of first openings, the plurality of second holes overlapping with the plurality of second openings, the plurality of third holes being around the light-blocking pattern, and the plurality of third holes overlapping with the plurality of third openings; and a plurality of color filters located on the light-blocking layer and overlapping with the plurality of first holes and not overlapping with the plurality of second holes and the plurality of third holes.

17. The display device according to claim 16, wherein the plurality of third holes are defined as a region between the light-blocking pattern and a portion of the light-blocking layer other than the plurality of first holes, the plurality of second holes, and the plurality of third holes, and the diameter of the light-blocking pattern is equal to the diameter of each of the plurality of third openings, and the width of each of the plurality of third holes is equal to the separation distance between each of the plurality of third openings and the light-blocking layer.

18. The display device according to claim 16, wherein, The diameter of the light-blocking pattern is different from the diameter of each of the plurality of third openings.

19. The display device according to claim 16, wherein the light-blocking pattern is integrated with a portion of the light-blocking layer other than the plurality of first holes, the plurality of second holes, and the plurality of third holes to overlap with the plurality of third openings, and the plurality of third holes do not overlap with the plurality of third openings.

20. The display device according to claim 19, wherein, The display device further includes: a plurality of signal lines located on the substrate and arranged not to overlap with the plurality of second holes and the plurality of third holes, wherein the center line of a pair of adjacent signal lines among the plurality of signal lines is not parallel to the center line of each of the plurality of third openings.

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