Register array access method, electronic device and medium based on UVM RAL

Abstract

The present invention relates to the field of chip verification technology, and in particular to a register array access method, electronic device, and medium based on UVM RAL. The method comprises the following steps: step S1, generating an instantiated UVM RAL register array according to a register array template structure; step S2, establishing a correspondence between bits in a lineno field in a UVM method class function and matrix dimension parameters of the register array; step S3, obtaining a target address, a target lineno, and a target access parameter; step S4, determining a target UVM RAL register model array; step S5, determining a target UVM RAL register model in the target UVM RAL register model array; and step S6, calling a corresponding method function in the target UVM RAL register model according to the target access parameter to perform a target access operation. The present invention implements access to a register array based on UVM RAL.

Description

Technical Field

[0001] The present invention relates to the technical field of chip verification, and in particular to a register array access method, electronic equipment and medium based on UVM RAL. Background Art

[0002] Currently, chip verification requires the use of Universal Verification Methodology (UVM). A UVM RAL (Universal Verification Methodology) register model is generated within the verification environment, and the hardware register model in the device under test (DUT) is verified using the UVM RAL register model. In graphics processing unit (GPU) systems, a single address is often mapped to multiple registers. Multiple registers corresponding to a single address form a register array, and GPU systems need to use the same address to access multiple different register entities within the register array. However, existing register addressing methods all use address addressing, with a one-to-one correspondence between addresses and registers. Furthermore, in the UVM RAL, only one register entity exists for the same address. Therefore, register array access is not possible using the existing UVM RAL. Therefore, implementing register array access using the UVM RAL has become a pressing technical challenge. Summary of the Invention

[0003] The present invention aims to provide a register array access method, electronic equipment and medium based on UVM RAL, thereby realizing the access of the register array based on UVM RAL.

[0004] According to a first aspect of the present invention, a register array access method based on UVM RAL is provided, comprising:

[0005] Step S1, generate the register array of instantiated UVM RAL according to the register array template structure, the register array template structure is generated based on the class class declaration, the register array template structure inherits the properties and methods of all UVM RAL register models and sets the matrix dimension parameters {A1, A2, ..., A n ,...,A N}, where A n is the parameter of the nth dimension in the register array template structure, the value range of n is 1 to N, and N is the total number of register array template structures;

[0006] Step S2: Establish the corresponding relationship between the bit in the lineno field in the UVM method class function and the matrix dimension parameter of the register array, and generate {[B2 1 :B1 1 ],[B2 2 :B1 2 ],...,[B2 n :B1 n ],...,[B2 N :B1 N ]}, where [B1 n ,B2 n ] is the number of bits corresponding to the lineno field of the nth dimension, B1 1 =0,B1 2 =B2 1 +1, B2 N ≤L, where L is the parameter length defined by the lineno field;

[0007] Step S3, obtaining the target address, target lineno and target access parameters;

[0008] Step S4, determining the target UVM RAL register model array based on the address mapping information of UVM RAL and the target access address;

[0009] Step S5, determining the target UVM RAL register model in the target UVM RAL register model array based on the corresponding relationship between the lineno field corresponding to the target lineno and UVM RAL and the matrix dimension parameter of the register array;

[0010] Step S6: Call the corresponding method function in the target UVM RAL register model according to the target access parameter to perform the target access operation.

[0011] According to a second aspect of the present invention, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to execute the method described in the first aspect of the present invention.

[0012] According to a third aspect of the present invention, a computer-readable storage medium is provided, storing computer-executable instructions, wherein the computer instructions are used to execute the method according to the first aspect of the present invention.

[0013] The present invention has obvious advantages and beneficial effects compared with the prior art. By means of the above technical solution, a register array access method based on UVM RAL, an electronic device and a medium provided by the present invention can achieve considerable technological advancement and practicality, and has a wide range of industrial utilization value, which at least has the following beneficial effects:

[0014] The present invention provides a register array template structure and inherits the attribute and method of the UVM RAL register model, and reuses the attribute and method information of the UVM RAL register model. In addition, the present invention uses the lineno field as an auxiliary ID by setting up the corresponding relationship between the lineno field in the method class function of UVM and the matrix dimension parameter of the register array, addresses the register model in the register array by the auxiliary ID corresponding to the lineno field, and realizes the access of the register array based on UVM RAL. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0016] Figure 1 A flow chart of a register array access method based on UVM RAL is provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0017] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0018] GPU software is not usually only single thread at work during execution, GPU hardware usually supports the software work of multiple threads, and for the convenience of the development of upper-level software, the addresses corresponding to the multiple threads supported by GPU are identical, so in GPU system, the application scenario of multiple registers of an address correspondence often occurs.And in UVM RAL, same address has only one register entity, so existing UVM RAL cannot realize the access of multiple registers of an address correspondence.If all overturn the register model in existing UVM RAL, rebuild a set of systems that can realize register array access, need to expend a large amount of costs, realize difficulty height, and efficiency is low. Based on this, the present invention proposes a kind of mode realizing register array access method on the basis of existing UVM RAL.

[0019] The embodiment of the present invention provides a register array access method based on UVM RAL, such as Figure 1 As shown, including:

[0020] Step S1, generate the register array of instantiated UVM RAL according to the register array template structure, the register array template structure is generated based on the class class declaration, the register array template structure inherits the properties and methods of all UVM RAL register models and sets the matrix dimension parameters {A1, A2, ..., A n ,...,A N}, where A n is the parameter of the nth dimension in the register array template structure, the value range of n is 1 to N, and N is the total number of register array template structures.

[0021] It should be noted that based on the class declaration in UVM, all the properties and methods of the UVM RAL register model can be directly passed in for inheritance without reconstruction. In step S1, the matrix dimension parameters of the register array are also set. The matrix dimension parameters of the register array are exposed to the user. The user specifies the target register model in the register data by configuring the matrix dimension parameters of the register array. The register array of the instantiated UVM RAL consists of multiple UVM RAL register models with the same address. n The corresponding maximum value is the register depth of the nth dimension, A n The corresponding numerical value of the nth dimension id, all A n The numerical values ​​of can be combined to determine a unique register in the register array. The register array template structure inherits the properties of all UVM RAL register models including address mapping information, which is used to store the mapping relationship between the register model and the address.

[0022] Step S2: Establish the corresponding relationship between the bit in the lineno field in the UVM method class function and the matrix dimension parameter of the register array, and generate {[B2 1 :B1 1 ],[B2 2 :B1 2 ],...,[B2 n :B1 n ],...,[B2 N :B1 N ]}, where [B1 n ,B2 n ] is the number of bits corresponding to the lineno field of the nth dimension, B1 1 =0,B1 2 =B2 1 +1, B2 N ≤L, where L is the parameter length defined by the lineno field.

[0023] It should be noted that UVM is implemented based on the SystemVerilog language. While SystemVerilog can modify tasks within a class during inheritance, it cannot modify the original formal parameters within tasks and functions. Therefore, it is not possible to directly add parameters to assist in addressing IDs. The lineno field is an existing field in the corresponding method function in the UVM RAL register model, typically declared as an int type, corresponding to 32 bits. The lineno field is typically unused or used as a parameter to assist in debugging. This embodiment of the present invention selects the lineno field, establishes a correspondence between the bits in the lineno field in the UVM method class function and the matrix dimension parameters of the register array, and uses the lineno field as an aid in finding the ID of the register model in the register array.

[0024] Step S3: Obtain the target address, target lineno and target access parameters.

[0025] It should be noted that the target address is the address corresponding to a register array. The target address can only address the target register array, but cannot directly address the register model within the target register array. The target lineno refers to the target lineno field and the specific data set. The target lineno can be used to determine the register model within the target register array. The target access parameters include the target access type and access data. The access type is usually read or write. When the access type is write, the corresponding data to be written must be set in the access data. If the access type is read, the access data can be set to empty.

[0026] Step S4: determining a target UVM RAL register model array based on the address mapping information of the UVM RAL and the target access address.

[0027] It should be noted that the register array of the instantiated UVM RAL generated in step S1 can be regarded as a register model in the original UVMRAL, and also has an address. The mapping relationship between the address and the register model is stored in the address mapping information of UVM RAL. Through the steps in step S1, the mapping relationship between the register array and the address of the instantiated UVM RAL is also stored in the address mapping information of UVM RAL. Therefore, the address mapping information of UVM RAL is retrieved based on the target access address, and the target UVM RAL register model array can be determined.

[0028] Step S5: Determine the target UVM RAL register model in the target UVM RAL register model array based on the correspondence between the lineno field corresponding to the target lineno and UVM RAL and the matrix dimension parameter of the register array.

[0029] It should be noted that the {[B2 1 :B1 1 ],[B2 2 :B1 2 ],...,[B2 n :B1 n ],...,[B2 N :B1 N ]} clarifies the correspondence between the segment of the lineno field and the matrix dimension parameter of the register array, based on {[B2 1 :B1 1 ],[B2 2 :B1 2 ],...,[B2 n :B1 n ],...,[B2 N :B1 N ]} and target lineno can determine {A1,A2,...,A n ,...,A N} corresponding to the value based on {A1,A2,...,A n ,...,A N The value corresponding to} can determine the target UVM RAL register model in the target UVM RAL register model array.

[0030] It should be noted that, based on the operation of step S1-step S5, the register array access process can be divided into two addressing stages, the first stage will regard the register array as a UVM RAL register model, addressing is carried out based on the target address imported and the address mapping information of UVM RAL, and the target register array is first determined. The second stage, based on the corresponding relationship between the lineno field corresponding to target lineno and UVM RAL and the matrix dimension parameter of register array, determines the unique id of the register model array in the register array, determines the target UVM RAL register model in the target UVM RAL register model array based on unique id.

[0031] Step S6: Call the corresponding method function in the target UVM RAL register model according to the target access parameter to perform the target access operation.

[0032] It should be noted that a corresponding method function can be set in each UVM RAL register model. After the target UVM RAL register model is determined, the method function corresponding to the target access parameter in the target UVM RAL register model can be directly called to perform the target access operation.

[0033] As an embodiment, step S1 includes:

[0034] Step S11, based on the class class declaration, the register array template structure is inherited based on the extends keyword in UVM. The properties and methods of all UVM RAL register models are inherited and the matrix dimension parameters {A1, A2, ..., A n ,...,A N}.

[0035] It should be noted that by setting the class declaration and using the extends keyword in UVM, the register array template structure can be simply extended on the basis of the original UVMRAL, and all the properties and methods of the UVMRAL register model can be reused in subsequent processing.

[0036] Step S12: Setting the register array template structure based on UVM to override the register model in the original UVM RAL to generate a register array of an instantiated UVM RAL.

[0037] Override is an important concept in UVM that is used to replace or enhance the behavior of a class. It can change its behavior without modifying the original class. Specifically, the register array of the instantiated UVM RAL can be generated by setting the following statement:

[0038] set_type_override_by_type(mvt_reg_array_template#(ral_a,maxA1,maxA2,...,maxA n ,...,maxA N ), ral_a)

[0039] In the above statement, mvt_reg_array_template#(ral_a,maxA1,maxA2,...,maxA n ,...,maxA N ) represents a register array template structure, ral_a represents a UVM RAL register model, maxA n Indicates A n The maximum value of the register array template structure is overwritten by ral_a through the set_type_override_by_type function to generate an instantiated UVM RAL register array, and the register array of UVM RAL inherits the properties and methods of the ral_a register model.

[0040] It should be noted that N is set according to specific application requirements. Preferably, in step S2, N is set to 3. 1 :B1 1 ],[B2 2 :B1 2 ],...,[B2 n :B1 n ],...,[B2 N :B1 N ]} is set to {[9:0],[19:10],[29:20]}.

[0041] As an embodiment, step S5 includes:

[0042] Step S51, set [B2 n :B1 n The value of the data segment corresponding to the ] bit is determined as the target A n .

[0043] Step S52: All target A corresponding to the target lineno n Determine the target {A1,A2,...,A n ,...,A N}.

[0044] Step S53: Set the target UVM RAL register model array to {A1, A2, ..., A n ,...,AN The corresponding UVM RAL register model is determined as the target UVM RAL register model.

[0045] As an embodiment, the corresponding method functions in the UVM RAL register model include UVM set function, UVMget function, UVM get_mirrored value function, UVM write function, UVM read function, UVM poke function, UVM peek function, UVM update function, and UVM mirror function. It should be noted that all of the above functions are existing method functions in UVM, and each UVM RAL register model can directly call the above method functions to perform corresponding operations.

[0046] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the steps as sequential processes, many of the steps can be performed in parallel, concurrently, or simultaneously. In addition, the order of the steps can be rearranged. A process can be terminated when its operation is completed, but can also have additional steps not included in the accompanying drawings. A process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0047] An embodiment of the present invention also provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are configured to execute the method described in the embodiment of the present invention.

[0048] An embodiment of the present invention further provides a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the embodiment of the present invention.

[0049] The embodiment of the present invention provides a register array template structure and inherits the attribute and method of the UVM RAL register model, and reuses the attribute and method information of the UVM RAL register model. In addition, the present invention uses the lineno field as auxiliary id by setting up the corresponding relationship between the lineno field in the method class function of UVM and the matrix dimension parameter of the register array, addresses the register model in the register array by the auxiliary id corresponding to the lineno field, and realizes the access of the register array based on UVM RAL.

[0050] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Any technician familiar with the present profession can make slight changes or modifications to equivalent embodiments using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A register array access method based on UVM RAL, characterized in that, include: Step S1, generate the register array of instantiated UVM RAL according to the register array template structure, the register array template structure is generated based on the class class declaration, the register array template structure inherits the properties and methods of all UVM RAL register models and sets the matrix dimension parameters {A1, A2, ..., A n ,...,A N }, where A n is the parameter of the nth dimension in the register array template structure, the value range of n is 1 to N, and N is the total number of register array template structures; Step S2: Establish the corresponding relationship between the bit in the lineno field in the UVM method class function and the matrix dimension parameter of the register array, and generate {[B2 1 :B1 1 ],[B2 2 :B1 2 ],...,[B2 n :B1 n ],...,[B2 N :B1 N ]}, where [B1 n ,B2 n ] is the number of bits corresponding to the lineno field of the nth dimension, B1 1 =0,B1 2 =B2 1 +1, B2 N ≤L, where L is the parameter length defined by the lineno field; Step S3, obtaining the target address, target lineno and target access parameters; Step S4, determine the target UVM RAL register model array based on the address mapping information of UVM RAL and the target address; Step S5, determining the target UVM RAL register model in the target UVM RAL register model array based on the corresponding relationship between the lineno field corresponding to the target lineno and UVM RAL and the matrix dimension parameter of the register array; Step S6: Call the corresponding method function in the target UVM RAL register model according to the target access parameter to perform the target access operation; The step S1 comprises: Step S11, based on the class class declaration, the register array template structure is inherited based on the extends keyword in UVM. The properties and methods of all UVM RAL register models are inherited and the matrix dimension parameters {A1, A2, ..., A n ,...,A N }; Step S12, setting the register array template structure override the register model in the original UVM RAL based on UVM, and generating a register array of the instantiated UVM RAL; In step S2, N is set to 3, {[B2 1 :B1 1 ],[B2 2 :B1 2 ],...,[B2 n :B1 n ],...,[B2 N :B1 N ]} is set to {[9:0],[19:10],[29:20]}; The step S5 comprises: Step S51, set [B2 n :B1 n The value of the data segment corresponding to the ] bit is determined as the target A n ; Step S52: All target A corresponding to the target lineno n Determine the target {A1,A2,...,A n ,...,A N }; Step S53: Set the target UVM RAL register model array to {A1, A2, ..., A n ,...,A N The corresponding UVM RAL register model is determined as the target UVM RAL register model.

2. The method according to claim 1, characterized in that In step S3, the target access parameters include the target access type and access data.

3. The method according to claim 1, characterized in that The corresponding method functions in the UVM RAL register model include UVM set function, UVM get function, UVM get_mirrored value function, UVM write function, UVM read function, UVM poke function, UVM peek function, UVMupdate function, and UVM mirror function.

4. An electronic device, characterized in that: include: at least one processor; and, a memory communicatively coupled to the at least one processor; The memory stores instructions that can be executed by the at least one processor, and the instructions are configured to execute the method according to any one of claims 1 to 3.

5. A computer-readable storage medium, characterized in that The computer-executable instructions are stored, and the computer-executable instructions are used to execute the method according to any one of the preceding claims 1 to 3.

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