Hybrid key system and real-time optimization method thereof

Abstract

The embodiment of the invention provides a hybrid key system and a real-time optimization method thereof, the hybrid key system comprises a real-time operating system and a non-real-time operating system, and a first CPU core group and other CPU core groups in a processor of the hybrid key system have different L3 caches. The method comprises the following steps: closing a super thread in a BI OS of the hybrid key system, so that threads of different operating systems do not share the same CPU core of the processor; deploying the real-time operating system on the first CPU core group, and deploying the non-real-time operating system on the other CPU core groups; and closing the system management interruption of the hybrid key system. According to the technical scheme provided by the embodiment of the invention, the real-time optimization of the hybrid key system is carried out from four aspects of hardware, BI OS setting, CPU configuration strategy and system software, and the real-time performance of a real-time operating system in the hybrid key system is improved.

Description

Technical Field

[0001] The present application relates to the field of operating system technology, and in particular to a hybrid critical system and a real-time optimization method thereof. Background Art

[0002] Virtualization technology has now penetrated the core computing operations of key industries. The emergence of virtualization has transformed traditional single-computer architectures. Its high availability and rapid migration capabilities effectively ensure the continuity of computer operations in critical systems and minimize business interruptions caused by computer failures. Applying virtualization to industrial control effectively ensures the high availability of industrial computers (IPCs), reduces business interruptions caused by IPC failures, and helps customers consolidate multiple, distributed systems into a single machine for centralized management. This not only reduces production costs for industrial and automation design and manufacturing companies, but also helps them bring products to market faster and more efficiently, while increasing flexibility and reducing space requirements.

[0003] Since many industrial applications have high requirements for real-time performance and operational capabilities, the integration of related virtualization solutions poses a huge challenge. Existing technologies mainly rely on multiple virtual machines. Some virtual machines run real-time operating systems, which run real-time applications. Some virtual machines run non-real-time operating systems, which run non-real-time applications. In existing virtualization technologies, virtual machine management software (hereinafter referred to as VMM) generally creates a virtual hardware environment (including virtual network cards and virtual hard disks) independent of the actual hardware for use by virtual machines. This affects the real-time performance of real-time systems and cannot meet the requirements of industrial environments. Summary of the Invention

[0004] In view of this, an embodiment of the present application provides a hybrid criticality system and a real-time optimization method thereof, wherein a real-time operating system and a non-real-time operating system are set on the core of the hybrid criticality system. The technical solution of the embodiment of the present application configures an L3 cache channel different from the non-real-time operating system for the real-time operating system based on the CPU core resource division of the chip, and the real-time operating system and the non-real-time operating system do not share the CPU core in the BIOS setting, and the system management interrupt is turned off in the software so that it does not interrupt the operation of the real-time operating system. The real-time performance of the real-time operating system in the hybrid criticality system is improved through the above optimization.

[0005] In a first aspect, an embodiment of the present application provides a real-time optimization method for a hybrid critical system, wherein a real-time operating system and a non-real-time operating system are set on the core of the hybrid critical system, and the first CPU core group and other CPU core groups in the processor of the hybrid critical system have different L3 caches. The method includes: turning off hyperthreading in the BIOS of the hybrid critical system so that threads of different operating systems do not share the same CPU core of the processor; deploying the real-time operating system on the first CPU core group and deploying the non-real-time operating system on other CPU core groups; and turning off the system management interrupt of the hybrid critical system.

[0006] Based on the above, at the hardware level, chips with different L3 cache channels are selected. At the chip level, different L3 cache channels are configured for the real-time operating system and the non-real-time operating system in the division of CPU core resources. At the BIOS setting level, the real-time operating system and the non-real-time operating system do not share the CPU core. At the software level, system management interrupts are disabled so that they do not interrupt the operation of the real-time operating system. Through the above optimization, the real-time performance of the real-time operating system in the mixed-criticality system is improved.

[0007] In a possible implementation of the first aspect, the shutting down of the system management interrupt of the hybrid critical system includes: the real-time operating system shutting down the system management interrupt through the switch control bit of the system management interrupt when starting; and the non-real-time operating system setting the switch control bit to read-only space for the non-real-time operating system.

[0008] From the above, the kernel sets the switch control bit of the system management interrupt to read-only space for the non-real-time operating system, so that the non-real-time operating system will not turn on the system management interrupt when it starts, and the system management interrupt will remain closed, thereby improving the real-time performance of the real-time operating system.

[0009] In a possible implementation manner of the first aspect, the method further includes: disabling frequency and voltage regulation control of the processor in the BIOS of the hybrid criticality system.

[0010] From the above, by turning off the frequency and voltage regulation control of the processor in the BIOS, the processor can work stably, each CPU core can work stably, and the real-time operating system can maintain good real-time performance.

[0011] In a possible implementation manner of the first aspect, the method further includes: setting a GPU to a low-frequency mode in the BIOS of the hybrid criticality system.

[0012] As mentioned above, the GPU is set to low-frequency mode to reduce its impact on the CPU core. Especially when the built-in GPU and CPU share the LLC (Last Level Cache), a high-frequency GPU can seriously interfere with the CPU core running the real-time operating system. Furthermore, if the high-frequency built-in GPU is running too many tasks, it can cause high system temperatures, triggering hardware throttling of the CPU core.

[0013] In a possible implementation of the first aspect, when the processor is a Hygon 3350, the first CPU core group is the first four CPU cores, and the other CPU core groups are the last four CPU cores.

[0014] As described above, the first four CPU cores of Hygon 3350 are assigned to the real-time operating system, and the last four CPU cores are assigned to the non-real-time operating system, so that the real-time operating system and the non-real-time operating system are isolated on the L3 cache, reducing the interference of the non-real-time operating system on the real-time operating system and improving the real-time performance of the real-time operating system.

[0015] In a possible implementation manner of the first aspect, when the processor is an AMD system, disabling hyperthreading in the BIOS of the mixed-criticality system includes disabling SVM Control and SMT Control in the BIOS.

[0016] As described above, the SVM Control and SMT Control in the AMD system BIOS are disabled so that threads of different operating systems do not share the same CPU core of the processor, thereby improving the real-time performance of the real-time operating system.

[0017] In a possible implementation of the first aspect, when the processor is an Intel system, the frequency and voltage regulation control of the processor is turned off in the BIOS, specifically including: setting P-States to off mode; setting C-States to off mode; and setting Other power control to off mode.

[0018] As mentioned above, setting P-States, C-States, and Other power control to off mode prevents Intel processors from adjusting frequency and voltage under high load, idle, and high temperature conditions, allowing them to operate in a stable state and maintain the real-time performance of the real-time operating system.

[0019] In a possible implementation of the first aspect, when the processor is an AMD system, the regulation control of the CPU core frequency and voltage of the processor is turned off in the BIOS, specifically including: setting the Global C-state control to the shutdown mode; and setting the P-state control to the performance mode.

[0020] As shown above, turn off Global C-state control and set P-state control to performance mode. Under high load, idle and high temperature conditions, the AMD system processor will not adjust the frequency and voltage, and will work in a stable state to maintain the real-time performance of the real-time operating system.

[0021] In a possible implementation of the first aspect, when the processor is an AMD system, turning off the adjustment control of the CPU core frequency and voltage of the processor in the BIOS also includes: setting Core performance boost to off mode, and setting Fan profile and Determinism slider to performance mode.

[0022] As shown above, by turning off Core performance boost, setting the Fan profile and Determinism slider to performance mode, the AMD system processor will not adjust the frequency and voltage further under high load and high temperature, working in a stable state, maintaining the real-time performance of the real-time operating system.

[0023] In a possible implementation manner of the first aspect, when the processor is a Hygon processor, the switch control bit is an address of a setting bit of a system management interrupt register.

[0024] As described above, the system management interrupt is disabled by operating the corresponding bit of the system management interrupt register of the Hygon processor.

[0025] In a possible implementation manner of the first aspect, when the processor is an AMD system, the BIOS further performs one of the following settings: setting an L1 stream HW Prefetcher to AUTO mode; and setting an L2 stream HWPrefetcher to AUTO mode.

[0026] As mentioned above, by setting the L1 stream HW Prefetcher and L2 stream HW Prefetcher to AUTO mode, the prefetching strategy can be dynamically adjusted according to the load to predict the CPU's access pattern to the L1 cache, load data in advance to reduce memory access latency, and balance performance and power consumption. The combination of the two can achieve balanced memory access performance and power consumption.

[0027] In a possible implementation manner of the first aspect, when the processor is an AMD system, the BIOS further performs the following settings: setting a memory lock according to an access speed of DDR.

[0028] As shown above, disabling Network configuration disables the onboard network card or network boot function to improve system security or avoid network interference. Setting Memory lock according to the DDR access speed to match the industrial standard upper limit of DDR memory is the most cost-effective solution, which not only releases the hardware's nominal performance but also avoids the risk of aggressive overclocking.

[0029] In a possible implementation manner of the first aspect, when the processor is an AMD system, one of the following settings is further performed in the BIOS: Available PSP CCP VQ count is set to 0; SMEE Control is disabled; and Network configuration is disabled.

[0030] From the above, set Available PSP CCP VQ count to 0 and disable SMEE Control to save memory resources. Disable Networkconfig to disable the BIOS network function, so that the BIOS cannot be modified over the network.

[0031] In the second aspect, an embodiment of the present application provides a hybrid critical system, which includes: a processor, a BIOS, a real-time operating system, and a non-real-time operating system; the hardware layer includes a processor, the processor is provided with a first CPU core group and other CPU core groups, the first CPU core group and the other CPU core groups have different L3 caches, the real-time operating system is deployed on the first CPU core group, and the non-real-time operating system is deployed on the other CPU core groups; the BIOS turns off the processor's hyperthreading so that threads of different operating systems do not share the same CPU core of the processor; the real-time operating system turns off the system management interrupt through the switch control bit of the system management interrupt at startup; the kernel driver of the non-real-time operating system sets the switch control bit of the system management interrupt to read-only space.

[0032] Based on the above, at the hardware level, chips with different L3 cache channels are selected. At the chip level, different L3 cache channels are configured for the real-time operating system and the non-real-time operating system based on the chip's CPU core resource division. At the BIOS setting level, the real-time operating system and the non-real-time operating system do not share the CPU core. At the software level, system management interrupts are disabled so that they do not interrupt the operation of the real-time operating system. Through the above optimization, the real-time performance of the real-time operating system in the mixed-criticality system is improved.

[0033] In a possible implementation of the second aspect, frequency and voltage regulation control of the processor is disabled in the BIOS of the hybrid criticality system.

[0034] From the above, by turning off the frequency and voltage regulation control of the processor in the BIOS, the processor can work stably, each CPU core can work stably, and the real-time operating system can maintain good real-time performance.

[0035] In a possible implementation of the second aspect, a GPU is set to a low-frequency mode in the BIOS of the mixed-criticality system.

[0036] As mentioned above, the GPU is set to low-frequency mode to reduce its impact on the CPU core. Especially when the built-in GPU and CPU share the LLC (Last Level Cache), a high-frequency GPU can seriously interfere with the CPU core running the real-time operating system. Furthermore, if the high-frequency built-in GPU is running too many tasks, it can cause high system temperatures, triggering hardware throttling of the CPU core.

[0037] In a possible implementation of the second aspect, when the processor is Hygon 3350, the first CPU core group is the first four CPU cores, and the other CPU core groups are the last four CPU cores.

[0038] As described above, the first four CPU cores of Hygon 3350 are assigned to the real-time operating system, and the last four CPU cores are assigned to the non-real-time operating system, so that the real-time operating system and the non-real-time operating system are isolated on the L3 cache, reducing the interference of the non-real-time operating system on the real-time operating system and improving the real-time performance of the real-time operating system.

[0039] In a possible implementation of the second aspect, when the processor is an AMD system, SVM Control and SMT Control in the BIOS of the mixed-criticality system are disabled.

[0040] As described above, the SVM Control and SMT Control in the AMD system BIOS are disabled so that threads of different operating systems do not share the same CPU core of the processor, thereby improving the real-time performance of the real-time operating system.

[0041] In a possible implementation of the second aspect, when the processor is an Intel system, in the BIOS, P-States is set to a shutdown mode; C-States is set to a shutdown mode; and Other power control is set to a shutdown mode.

[0042] As mentioned above, setting P-States, C-States, and Other power control to off mode prevents Intel processors from adjusting frequency and voltage under high load, idle, and high temperature conditions, allowing them to operate in a stable state and maintain the real-time performance of the real-time operating system.

[0043] In a possible implementation of the second aspect, when the processor is an AMD system, Global C-state control is set to a shutdown mode in the BIOS; and P-state control is set to a performance mode.

[0044] As shown above, turn off Global C-state control and set P-state control to performance mode. Under high load, idle and high temperature conditions, the AMD system processor will not adjust the frequency and voltage, and will work in a stable state to maintain the real-time performance of the real-time operating system.

[0045] In a possible implementation of the second aspect, when the processor is an AMD system, turning off the regulation control of the CPU core frequency and voltage of the processor in the BIOS also includes: setting Core performance boost to off mode, and setting Fan profile and Determinism slider to performance mode.

[0046] As shown above, by turning off Core performance boost, setting the Fan profile and Determinism slider to performance mode, the AMD system processor will not adjust the frequency and voltage further under high load and high temperature, working in a stable state, maintaining the real-time performance of the real-time operating system.

[0047] In a possible implementation manner of the second aspect, when the processor is a Hygon processor, the switch control bit is an address of a setting bit of a system management interrupt register.

[0048] As described above, the system management interrupt is disabled by operating the corresponding bit of the system management interrupt register of the Hygon processor.

[0049] In a possible implementation of the second aspect, when the processor is an AMD system, the BIOS further performs one of the following settings: setting an L1 stream HW Prefetcher to AUTO mode; and setting an L2 stream HWPrefetcher to AUTO mode.

[0050] As mentioned above, by setting the L1 stream HW Prefetcher and L2 stream HW Prefetcher to AUTO mode, the prefetching strategy can be dynamically adjusted according to the load to predict the CPU's access pattern to the L1 cache, load data in advance to reduce memory access latency, and balance performance and power consumption. The combination of the two can achieve balanced memory access performance and power consumption.

[0051] In a possible implementation of the second aspect, when the processor is an AMD system, the BIOS further performs the following settings: setting a memory lock according to an access speed of DDR.

[0052] As shown above, disabling Network configuration disables the onboard network card or network boot function to improve system security or avoid network interference. Setting Memory lock according to the DDR access speed to match the industrial standard upper limit of DDR memory is the most cost-effective solution, which not only releases the hardware's nominal performance but also avoids the risk of aggressive overclocking.

[0053] In a possible implementation manner of the second aspect, when the processor is an AMD system, one of the following settings is further performed in the BIOS: Available PSP CCP VQ count is set to 0; SMEE Control is disabled; and Network configuration is disabled.

[0054] Based on the above, set Available PSP CCP VQ count to 0 and disable SMEE Control to save memory resources. Disable Networkconfig to disable the BIOS network function, making it impossible to modify the BIOS over the network and maintaining stable BIOS settings. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 This is a schematic diagram of the structure of the application scenarios of various embodiments of the present application;

[0056] Figure 2 Schematic diagrams of four aspects of an embodiment of a real-time optimization method for a hybrid critical system of the present application;

[0057] Figure 3This is a flow chart of a first embodiment of a real-time optimization method for a hybrid critical system of the present application;

[0058] Figure 4 This is a flow chart of a second embodiment of a real-time optimization method for a hybrid critical system of the present application;

[0059] Figure 5A Schematic diagram of four CPU cores sharing one L3 Cache;

[0060] Figure 5B This diagram shows how to achieve soft isolation of L3 Cache between real-time and non-real-time systems based on software-based L3 Cache segmentation.

[0061] Figure 5C This is a schematic diagram of the physical isolation method for the Hygon 3350's L3 Cache;

[0062] Figure 5D A diagram showing the register addresses of the system management interrupt of the Hygon processor;

[0063] Figure 6 This is a structural diagram of a hybrid key system embodiment of the present application. DETAILED DESCRIPTION

[0064] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0065] In the following description, the terms "first\second\third, etc." or module A, module B, module C, etc. are only used to distinguish similar objects, or to distinguish different embodiments, and do not represent a specific ordering of the objects. It can be understood that the specific order or sequence can be interchanged where permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0066] In the following description, the numbers representing the steps, such as S110, S120, etc., do not necessarily mean that the steps must be executed in this manner. If permitted, the order of the steps can be interchanged or they can be executed simultaneously.

[0067] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein are for the purpose of describing the embodiments of this application only and are not intended to limit this application.

[0068] An embodiment of the present application provides a hybrid criticality system and a real-time optimization method thereof, wherein the hybrid criticality system includes a real-time operating system and a non-real-time operating system, and a first CPU core group in a processor of the hybrid criticality system has a different L3 cache from other CPU core groups. The method includes: disabling hyperthreading in the BIOS of the hybrid criticality system so that threads of different operating systems do not share the same CPU core of the processor; deploying the real-time operating system on the first CPU core group and deploying the non-real-time operating system on other CPU core groups; and disabling system management interrupts of the hybrid criticality system.

[0069] The technical solution of the embodiment of the present application selects a chip with different L3 cache channels, configures different L3 cache channels for the real-time operating system and the non-real-time operating system based on the CPU core resource division of the chip, sets the BIOS so that the real-time operating system and the non-real-time operating system do not share the CPU core, and disables the system management interrupt in the software so that it does not interrupt the operation of the real-time operating system. Through the above optimization, the real-time performance of the real-time operating system in the mixed-criticality system is improved.

[0070] The following describes various embodiments of the present application in conjunction with the accompanying drawings. Figure 1 Introduce the application scenarios of each embodiment of this application.

[0071] In order to improve the real-time performance of real-time operating systems in virtualized systems, this application proposes a mixed-criticality system based on the AMP (Asymmetric Multi-Processing) operating mode. Different processing cores in the AMP architecture run multiple operating system environments, including Linux / Windows operating environments and RTOS real-time operating system (such as Intel system) operating environments. The two systems work together to achieve the design goal of industrial applications.

[0072] Figure 1 The structure of the application scenario of each embodiment of the present application is shown, which is used in an industrial control system and includes: a hardware layer, a system layer, and an application layer.

[0073] The hardware layer includes a processor, which includes multiple CPU cores, for example, including the CPU cores Core 1, Core 2, Core 3, and Core 4.

[0074] The system layer includes a real-time operating system (RTOS) and a non-real-time operating system. For example, the non-real-time operating system is a Windows system, but it can also be a Linux system. For example, the RTOS is an Intel system, but it can also be other RTOSs, with two or more RTOSs.

[0075] The application layer includes real-time tasks and non-real-time tasks. Real-time tasks run on an RTOS, while non-real-time tasks run non-real-time tasks. For example, real-time tasks include softPLC and EtherCAT-based motion control, each running on an RTOS. For example, non-real-time tasks include machine vision and other non-real-time applications.

[0076] The following combination Figure 2 and Figure 3 A first embodiment of a real-time optimization method for a hybrid critical system is introduced.

[0077] Figure 2 Four aspects of an embodiment of a real-time optimization method for a hybrid critical system of the present application are shown.

[0078] First, at the hardware level, select a processor with multiple L3 cache channels; then, configure real-time functionality in the BIOS to turn it into a real-time BIOS; then, in chip resource allocation, deploy the real-time operating system and non-real-time operating system on CPU core groups with different L3 cache channels; finally, at the software level, disable system management interrupts.

[0079] Figure 3 The flowchart of the first embodiment of a real-time optimization method for a hybrid critical system of the present application is shown, including steps S310 to S340.

[0080] S310: Selecting a processor with multiple L3 cache channels as a processor of a mixed criticality system.

[0081] The first CPU core group and the other CPU core groups of the processor of the hybrid critical system have different L3 caches. Each CPU core group includes several CPU cores of the processor.

[0082] Among them, three levels of cache are set inside the processor chip. The L1 cache and L2 cache correspond to specific CPU cores respectively, and the L3 cache corresponds to specific CPU core groups respectively. Each CPU core group includes several CPU cores.

[0083] In some implementations of this embodiment, when the processor of the hybrid critical system is Hygon 3350, the first CPU core group is the first four CPU cores, which have independent L3 cache channels; the other CPU core groups are the last four CPU cores, which also have independent L3 cache channels.

[0084] S320: Disable hyperthreading in the BIOS of the mixed-criticality system so that threads of different operating systems do not share the same CPU core of the processor.

[0085] The BIOS (Basic Input and Output System) stores the computer's most important basic input and output programs, post-boot self-test programs, and system startup programs, providing the lowest-level, most direct hardware configuration and control for the computer. This step configures the mixed-criticality system's BIOS to become a real-time BIOS, ensuring better real-time performance.

[0086] In some implementations of this embodiment, when the processor is an Intel architecture, disabling hyperthreading in the BIOS of the mixed-criticality system includes disabling the Hyper-Threading function in the BIOS so that threads of different operating systems do not share the same CPU core. The Intel architecture includes processors that are licensed to use Intel IP.

[0087] In some implementations of this embodiment, when the processor of the hybrid-criticality system is an AMD system, disabling hyperthreading in the BIOS of the hybrid-criticality system includes disabling SVM and SMT controls in the BIOS, disabling virtualization technology on the AMD platform, and not allowing a single CPU core to execute multiple threads concurrently. The AMD system includes processors licensed to use AMD IP, and the Hygon processor belongs to the AMD system.

[0088] In some implementations of this embodiment, when the processor is an Intel system, the CPU core frequency and voltage regulation control of the processor is also disabled in the BIOS of the mixed-criticality system to ensure that the processor operates stably in a state and maintain the real-time performance of the real-time operating system. Specifically, this includes:

[0089] ●P-States are set to off mode to prevent the CPU from reducing voltage and frequency due to different loads during operation, resulting in uncertain execution time of real-time tasks.

[0090] ●C-States is set to off mode to prevent the CPU from entering sleep mode or voltage and frequency reduction when idle, and to avoid inconsistent wake-up times in different CPU states, so that the CPU of the real-time system is in a fixed state.

[0091] ●Other power control is in shutdown mode. You need to turn off the Power Control function to ensure that the real-time CPU is in a stable state as much as possible.

[0092] In some implementations of this embodiment, the GPU is also set to low-frequency mode in the BIOS of the hybrid-critical system to reduce its impact on the CPU core. When the built-in GPU and CPU share the LLC (Last Level Cache), a high-frequency GPU can severely interfere with the CPU core running the real-time operating system. Furthermore, if the high-frequency built-in GPU is running too many tasks, it can cause high system temperatures, triggering hardware frequency reduction of the CPU core.

[0093] In some implementations of this embodiment, when the processor is an AMD system, the adjustment control of the CPU core frequency and voltage of the processor is turned off in the BIOS, specifically including: setting the Global C-state control to the shutdown mode; setting the P-state control to the performance mode, so that the AMD system processor does not adjust the frequency and voltage under high load, idle and high temperature conditions, operates in a stable state, and maintains the real-time performance of the real-time operating system.

[0094] In some implementations of this embodiment, when the processor is an AMD system, the adjustment control of the CPU core frequency and voltage of the processor is turned off in the BIOS, which also includes: setting the Core performance boost to off mode, setting the Fanprofile and Determinism slider to performance mode, so that the AMD system processor does not further adjust the frequency and voltage under high load and high temperature, operates in a stable state, and maintains the real-time performance of the real-time operating system.

[0095] In some implementations of this embodiment, when the processor of the mixed-criticality system is an AMD system, the L1 stream HW Prefetcher and the L2 stream HW Prefetcher are set to AUTO mode to achieve a balance between memory access performance and power.

[0096] In some implementations of this embodiment, when the processor of the hybrid critical system is of AMD architecture, the memory lock is set in the BIOS according to the access speed of DDR so that the processor can access the memory at the fastest speed.

[0097] In some implementations of this embodiment, when the processor of the hybrid critical system is an AMD system, the Available PSP CCP VQ count is set to 0 in the BIOS and the SMEE Control is disabled to save memory resources.

[0098] In some implementations of this embodiment, when the processor of the hybrid critical system is an AMD system, Network config is disabled in the BIOS to disable the network function of the BIOS, and the BIOS settings cannot be modified through the network.

[0099] S330: Deploy a real-time operating system on the first CPU core group, and deploy a non-real-time operating system on other CPU core groups, so that the real-time operating system and the non-real-time operating system use different L3 cache channels respectively.

[0100] Among them, non-real-time operating systems are often used for non-real-time processing of large amounts of data. If the two share L3 Cache, the non-real-time operating system will interfere with the real-time operating system. Deploying the two on a CPU core group with physically isolated L3 Cache improves the real-time performance of the real-time operating system.

[0101] In some implementations of this embodiment, when the processor of the hybrid critical system is Hygon 3350, a real-time operating system is deployed on the first four CPU core groups, and a non-real-time operating system is deployed on the last four CPU core groups, so that the real-time operating system and the non-real-time operating system use different L3 cache channels respectively.

[0102] S340: Disable the system management interrupt of the mixed criticality system so that the real-time operating system is not interrupted during operation.

[0103] System Management Interrupts (SMIs) are special interrupts with the highest priority. They cause the x86 CPU to enter System Management Mode (SMM), where it executes certain BIOS-implemented handlers. In this mode, all normal execution, including the real-time operating system, is suspended. SMIs can preempt real-time code at any time for an indeterminate amount of time and cannot be blocked or preempted by kernel software. Kernel software is unaware of ongoing SMI requests. The SMM handlers invoked by SMIs are implemented in the BIOS, are opaque, and incur a 300-microsecond delay.

[0104] In some implementations of this embodiment, disabling a system management interrupt (SMI) for a mixed-criticality system includes: a kernel driver of a non-real-time operating system sets a SMI switch control bit to read-only space for the non-real-time operating system; and a real-time operating system disables the SMI via the switch control bit during startup. In other examples, a kernel layer of the mixed-criticality system is set, and the SMI is disabled at the kernel layer.

[0105] In some implementations of this embodiment, when the processor of the hybrid critical system is a Hygon processor, the on / off control bit of the system management interrupt is an address corresponding to a set bit of a system management interrupt register. For example, the address of the system management interrupt register of the Hygon processor is 0xFED80298, and the set bit is bit 31.

[0106] In summary, a first embodiment of a real-time performance optimization method for a mixed-criticality system selects chips with different L3 cache channels at the hardware level, configures different L3 cache channels for a real-time operating system and a non-real-time operating system based on the CPU core resource division of the chip, sets the BIOS so that the real-time operating system and the non-real-time operating system do not share CPU cores, and disables system management interrupts in software so that they do not interrupt the operation of the real-time operating system, thereby improving the real-time performance of the real-time operating system in the mixed-criticality system.

[0107] The following is combined with Figures 4 to 5C A second embodiment of a real-time optimization method for a hybrid critical system is introduced.

[0108] A second embodiment of a real-time optimization method for a hybrid critical system is a specific implementation method of the first embodiment of a real-time optimization method for a hybrid critical system on a Hygon processor, and has all the advantages of the first embodiment of a real-time optimization method for a hybrid critical system.

[0109] Embodiment 2 of a real-time optimization method for a mixed-criticality system deploys a mixed-criticality system RTOS-Win system (such as Intewell-Win information) on a Hygon processor. The RTOS-Win system is a domestic operating system developed based on Windows that can support real-time applications. It can enable real-time and non-real-time applications to run simultaneously on the same hardware, and realize the parallel operation of Wi ndows applications and real-time applications based on a multi-core processor. The Windows system and the RTOS real-time operating system are securely isolated, which is compatible with the rich ecology of Windows and ensures the real-time and deterministic performance of real-time system tasks.

[0110] Domestic Haiguang processors are compatible with the x86 instruction set and are AMD systems. The processor performance parameters are comparable to international mainstream processor products of the same type. They support four platforms: mainstream domestic and foreign operating systems, databases, virtualization platforms or cloud computing. They can effectively be compatible with millions of existing system software and application software based on the x86 instruction set, and have excellent ecosystem advantages. However, Haiguang processors are mainly used in servers, and their real-time performance needs to be further optimized, especially in mixed-criticality system environments. Due to the influence of Window or Linux non-real-time systems, the real-time performance of real-time systems is poor. Therefore, it is necessary to integrate mixed-criticality systems based on the characteristics of Haiguang CPUs to solve real-time problems.

[0111] The following describes a second embodiment of a real-time optimization method for a mixed-criticality system using the Haiguang 3350 processor as an example.

[0112] Figure 4 The flowchart of the second embodiment of a real-time optimization method for a hybrid critical system is shown, including steps S410 to S440.

[0113] S410: Plan the CPU core resources of the Hygon 3350, allocate the first four CPU cores to the real-time operating system, and allocate the last four CPU cores to the non-real-time operating system.

[0114] Among them, the first four CPU cores and the last four CPU cores of Hygon 3350 use different L3 cache channels respectively to achieve physical isolation of the L3 cache of the real-time operating system and the non-real-time operating system.

[0115] Figure 5A This diagram shows four CPU cores sharing a single L3 cache. Each CPU core has its own L1 cache and L2 cache. The L1 cache includes the L1 I cache for instruction caching and the L1 D cache for data caching. Sharing a single L3 cache among four CPU cores can lead to mutual interference between the CPU cores and real-time performance issues caused by cache competition between different operating systems.

[0116] Figure 5B The figure shows a schematic diagram of L3 Cache isolation between real-time and non-real-time systems based on L3 Cache software partitioning. Although Core0 and Core1 share L3 Cache, different CPU cores use different L3 Caches through software partitioning. This is the implementation method of the Intel system, which is based on proportional partitioning.

[0117] Figure 5C The L3 Cache physical isolation method of the Haiguang 3350 of this application is shown. The first 4 CPU cores (upper 4 Cores) share 8M L3 Cache, and the last 4 CPU cores (lower 4 Cores) share another 8M L3 Cache, realizing the physical isolation of the L3 Cache of different CPU core groups. The non-real-time operating system and the real-time operating system do not share the L3 Cache. Figure 5B The software segmentation method further improves the real-time performance of the real-time operating system.

[0118] S420: Configuring the BIOS of the mixed criticality system as a real-time BIOS.

[0119] The following settings are made to the BIOS of the mixed-criticality system, including: disabling hyperthreading and ensuring that the CPU core runs in a stable working state.

[0120]

[0121] Among them, SVM Control is set to disabled mode (off mode) to turn off hardware virtualization, and SMTControl is set to disabled mode to disable CPU simultaneous multi-threading technology. The combination of the two is equivalent to turning off hyper-threading mode.

[0122] Among them, Core performance boost is set to disabled mode to prohibit the CPU core from dynamically increasing the frequency to the turbo state according to the load, Global C-state control is set to disabled mode to prohibit adjusting the CPU sleep depth, P-state control is set to performance mode (performance mode) to prohibit dynamic adjustment of the CPU core voltage and frequency according to the load to maintain a high response speed, Determinism slider is set to performance mode to prioritize the maximum performance output of the CPU core and limit the adjustment of frequency and voltage, Fan profile is set to performance mode to increase the fan speed to prioritize heat dissipation performance, which is suitable for maintaining stable operation of the CPU / GPU in high-load scenarios. The combination of the above settings is equivalent to the CPU core working in a stable state.

[0123] The Prefetcher settings (L2 stream HW Prefetcher) are set to AUTO mode to dynamically enable or disable the prediction of CPU access patterns to memory based on load, preloading data into the cache to reduce memory access latency. The Prefetcher settings (L1 stream HW Prefetcher) are set to AUTO mode to dynamically adjust the prefetching strategy based on load to predict CPU access patterns to the L1 cache, preloading data to reduce memory access latency, and balance performance and power consumption. The combination of the two achieves balanced memory access performance and power consumption.

[0124] Among them, the Memory lock is set to 3200MT / S. 3200MT / S is the industrial standard upper limit of DDR4 memory. It is the optimal cost-effective solution for DDR4 memory, which not only releases the nominal performance of the hardware but also avoids the risk of aggressive overclocking.

[0125] Among them, Available PSP CCP VQ count is set to 0 to disable hardware-accelerated SSL cryptography technology, without allocating resources for the confidential computing virtual queue (VQ) of the CPU core, and SMEE Control is set to Disabled mode to turn off the memory encryption function.

[0126] Among them, Networkconfig is set to Disabled mode to turn off the onboard network card or network boot function, improve system security or avoid network interference, and prevent BIOS settings from being changed by the network.

[0127] S430: Start the real-time operating system on the first four CPU core groups through the core of the mixed critical system. When the real-time operating system is started, the system management interrupt is disabled through a switch control bit.

[0128] Among them, the switch of the system management interrupt of the Hygon processor is controlled by a register. The register address is 0xFED80298, and the 31st bit is the switch control bit of the system management interrupt.

[0129] Figure 5D The figure shows the register address of the system management interrupt of the Hygon processor, where SMI=FED80200h represents the base address of the register and SMI x098 represents the offset address of the register.

[0130] Among them, when the real-time operating system turns off the system management interrupt, because the switch control bit of the system management interrupt has been set to read-only space, the non-real-time operating system cannot initialize the switch control bit of the system management interrupt when it starts, and the system management interrupt remains in the off state.

[0131] S440: A non-real-time operating system is deployed on the last four CPU core groups. The kernel driver of the non-real-time operating system sets the switch control bit of the system management interrupt to a read-only space for the non-real-time operating system.

[0132] Among them, the switch of the system management interrupt of the Hygon processor is a global register. Windows or Linux will also initialize this register, which will cause the register set by the real-time system to be modified. Therefore, by modifying the kernel driver to set this space as read-only memory, the non-real-time system cannot modify the register. The non-real-time operating system cannot initialize the switch control bit of the system management interrupt when it starts, and the system management interrupt remains in the off state.

[0133] In summary, Example 2 of a real-time optimization method for a hybrid critical system selects a Hygon 3350 processor with dual L3 Cache channels, disables hyperthreading through BIOS settings, and ensures that the processor operates in a stable state, regardless of temperature and load changes. The L1 and L2 Cache hit rates are high, the memory access speed is fast, and the system management interrupt is disabled. In this hybrid critical system based on the Hygon 3350 processor, the real-time performance of the real-time operating system is optimized from hundreds of microseconds to less than 5 microseconds.

[0134] The following combination Figure 6 A mixed-criticality system embodiment is introduced.

[0135] A hybrid critical system embodiment is optimized by the method described in the first embodiment of a real-time optimization method for a hybrid critical system, and has all the advantages of the first embodiment of a real-time optimization method for a hybrid critical system.

[0136] Figure 6 The structure of an embodiment of a mixed-criticality system is introduced, including: a hardware layer 610, a BIOS layer 620, a system layer 630, and an application layer 640.

[0137] Hardware layer 610 includes a processor. The processor's first CPU core group and other CPU core groups have different L3 caches. The first CPU core group and other CPU core groups have different L3 caches. The real-time operating system of system layer 630 runs on the first CPU core group of the processor in hardware layer 610, while the non-real-time operating system of system layer 630 runs on the other CPU core groups of the processor in hardware layer 610, achieving physical isolation of the L3 caches of the two.

[0138] For example, Core3 and Core4 are a first CPU core group, sharing one L3 cache; Core1 and Core2 are another CPU core group, sharing another L3 cache.

[0139] The BIOS in the BIOS layer 620 is a real-time BIOS that disables hyperthreading so that threads of different operating systems do not share the CPU core of the processor, thereby reducing the impact of non-real-time operating systems on real-time operating systems and improving the performance of real-time operating systems.

[0140] The real-time operating system (RTOS) of the system layer 630 runs the real-time applications of the application layer 640 and disables system management interrupts (SMIs) during startup to eliminate their impact on the RTOS. The non-RTOS of the system layer 630 runs the non-real-time applications of the application layer 640 and sets the SMI on / off control bit to read-only for the non-RTOS during startup, preventing write access.

[0141] When the hardware layer 610 includes a Hygon processor, this embodiment is also optimized by the method described in the second embodiment of a real-time optimization method for a mixed-criticality system, and has all the advantages of the second embodiment of a real-time optimization method for a mixed-criticality system.

[0142] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will appreciate that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the scope of protection of the present invention.

Claims

1. A real-time optimization method for a mixed-criticality system, characterized in that: The hybrid criticality system includes a real-time operating system and a non-real-time operating system, and a first CPU core group in a processor of the hybrid criticality system has different L3 caches from other CPU core groups. The method includes: disabling hyperthreading in the BIOS of the mixed-criticality system; Deploy the real-time operating system on the first CPU core group, and deploy the non-real-time operating system on the other CPU core groups; Disable system management interrupts for the mixed-criticality system.

2. The method according to claim 1, characterized in that The disabling of the system management interruption of the hybrid critical system includes: The real-time operating system turns off the system management interrupt through the switch control bit of the system management interrupt when starting; The kernel driver of the non-real-time operating system sets the switch control bit to a read-only space.

3. The method according to claim 1, characterized in that Also includes: The processor frequency and voltage scaling controls are disabled in the BIOS of the mixed-criticality system.

4. The method according to claim 1, characterized in that Also includes: Set the GPU to underclocking mode in the BIOS of the mixed-criticality system.

5. The method according to claim 1, characterized in that: When the processor is of AMD system, disabling hyperthreading in the BIOS of the mixed-criticality system includes: setting SVM Control and SMT Control in the BIOS to a disable mode.

6. The method according to claim 3, characterized in that: When the processor is an AMD system, disabling frequency and voltage regulation control of the processor in the BIOS includes: Global C-state control is set to shutdown mode, and P-state control is set to performance mode.

7. The method according to claim 6, characterized in that When the processor is an AMD system, disabling frequency and voltage regulation control of the processor in the BIOS further includes: Core performance boos is set to off mode, and Fan profile and Determinism slider are set to performance mode.

8. The method according to claim 1, characterized in that: When the processor is an AMD system, the following settings are also performed in the BIOS: Set L1 stream HW Prefetcher and L2 stream HW Prefetcher to AUTO mode.

9. The method according to claim 1, characterized in that: When the processor is an AMD system, the following settings are also performed in the BIOS: Set the Memory lock according to the DDR access speed.

10. A mixed key system, characterized in that, include: Processor, BIOS, real-time operating system, non-real-time operating system; The processor is provided with a first CPU core group and other CPU core groups, the first CPU core group and the other CPU core groups have different L3 caches, the real-time operating system is deployed on the first CPU core group, and the non-real-time operating system is deployed on the other CPU core groups; The BIOS disables hyperthreading so that threads of different operating systems do not share the same CPU core of the processor; The real-time operating system turns off the system management interrupt through the switch control bit of the system management interrupt when starting; The kernel driver of the non-real-time operating system sets the switch control bit to a read-only space.

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