Circuit diagram-based fault diagnosis method, terminal equipment and storage medium

Abstract

The invention relates to the technical field of circuit diagnosis, and discloses a circuit diagram-based fault diagnosis method, terminal equipment and a storage medium, and the method comprises the steps: obtaining element information and a lead connection relation in a to-be-detected circuit diagram after image preprocessing; constructing a topological relation graph based on the element information of the circuit diagram to be tested and the wire connection relation, and generating a circuit digital model; obtaining fault information, and performing circuit logic analysis on the fault information based on the circuit digital model to generate a fault list; and matching all fault types in the fault list with a maintenance database to obtain maintenance recommendation information. The circuit diagram to be tested is automatically processed, the recognition and fault diagnosis efficiency is greatly improved, detailed maintenance suggestions and steps are generated, a user is guided to quickly repair faults, and the method is suitable for analysis of the circuit diagrams to be tested in different design stages.

Description

Technical Field

[0001] The present application relates to the technical field of circuit diagnosis, and in particular to a fault diagnosis method based on a circuit diagram, a terminal device, and a storage medium. Background Art

[0002] Analysis and fault diagnosis of circuit diagrams under test primarily rely on manual labor, such as engineers manually examining paper diagrams to locate problems. This approach has the following drawbacks: digitizing paper diagrams is time-consuming and error-prone; fault diagnosis often relies on engineers' experience and lacks a systematic and standardized process; and potential design flaws cannot be discovered promptly during the circuit design phase. Even if the fault point is identified, repair recommendations are often insufficiently specific, making the repair process complex and time-consuming. Summary of the Invention

[0003] In view of this, the embodiments of the present application provide a circuit diagram-based fault diagnosis method, terminal device and storage medium, which can effectively solve the problems of traditional circuit diagnosis being time-consuming and lacking real-time analysis.

[0004] In a first aspect, an embodiment of the present application provides a circuit diagram-based fault diagnosis method, comprising: Obtaining component information and wire connection relationships in the circuit diagram to be tested after image preprocessing; Constructing a topology diagram based on the component information and the wire connection relationship of the circuit diagram to be tested, and generating a circuit digital model; Acquire fault information described by the user, and perform circuit logic analysis on the fault information based on the circuit digital model to generate a fault list; All fault types in the fault list are matched with the maintenance database to obtain maintenance recommendation information.

[0005] In a first possible embodiment of the first aspect, the circuit diagram-based fault diagnosis method further includes: Constructing a circuit logic model according to the component information of the circuit diagram to be tested; Analyzing the signal flow direction of the circuit to be tested and the functional relationship between various components based on the topological relationship diagram of the circuit to be tested and the circuit logic model; The design defects of the circuit to be tested are detected through a rule engine and topology analysis, and a defect report is generated.

[0006] In a second possible embodiment of the first aspect, the component information includes component types and component parameters, and acquiring the component information and wire connection relationships in the circuit diagram to be tested after image preprocessing includes: Inputting the circuit diagram to be tested into a pre-trained component recognition model to identify the component types in the circuit diagram to be tested; Performing text recognition on the text area of the circuit diagram to be tested to obtain the component parameters; The wires in the circuit diagram to be tested are used as detection targets to identify the connection relationship of the wires in the circuit diagram to be tested.

[0007] In a third possible embodiment of the first aspect, the constructing a topology relationship diagram based on the component information and the wire connection relationship of the circuit diagram to be tested includes: Constructing a topology diagram based on the component types and the wire connection relationships, and marking the component parameters to the corresponding components in the topology diagram; The topological relationship diagram after parameter annotation is used as the circuit digital model.

[0008] In a fourth possible embodiment of the first aspect, the fault information includes a faulty component and a fault phenomenon, and performing circuit logic analysis on the fault information based on the circuit digital model to generate a fault list includes: Taking the faulty component as a starting point, searching and identifying a portion of circuit elements related to the fault information in the topology diagram; Performing logical reasoning on the searched circuit elements to determine the fault point; Determine the fault type corresponding to the fault point according to the fault database; The fault types are sorted according to the fault probabilities to generate the fault list.

[0009] In a fifth possible embodiment of the first aspect, the maintenance recommendation information includes a maintenance suggestion, a maintenance process, and a maintenance time, and obtaining the maintenance recommendation information includes: Obtaining the maintenance suggestion and the maintenance process corresponding to the fault type based on a maintenance database; The total operation time of the maintenance process is determined based on a time weight library, and the total operation time is adjusted based on preset constraints to determine the maintenance time.

[0010] In a sixth possible embodiment of the first aspect, the analyzing the signal flow direction of the circuit to be tested and the functional relationship between components based on the topological relationship diagram and the circuit logic model of the circuit diagram to be tested includes: Starting from the analog signal at the input end of the circuit to be tested, sequentially determining the level change of each circuit node in the circuit to be tested; Starting from a target circuit node, an upstream signal source affecting the target circuit node is determined.

[0011] In a seventh possible embodiment of the first aspect, detecting design defects of the circuit under test by using a rule engine and topology analysis and generating a defect report includes: Performing short circuit and overload detection on the circuit to be tested using predefined circuit detection rules; Determine a signal loop path of the circuit to be tested by topological analysis, and perform loop detection on the circuit to be tested; The isolation node of the circuit to be tested is determined through topological analysis, and an isolation check is performed on the circuit to be tested.

[0012] In a second aspect, an embodiment of the present application provides a terminal device, which includes a processor and a memory, wherein the memory stores a computer program, and the processor is used to execute the computer program to implement the above-mentioned circuit diagram-based fault diagnosis method.

[0013] In a third aspect, an embodiment of the present application provides a computer-readable storage medium storing a computer program. When the computer program is executed on a processor, the computer program implements the above-mentioned circuit diagram-based fault diagnosis method.

[0014] The embodiments of the present application have the following beneficial effects: The present embodiment provides a circuit diagram-based fault diagnosis method, comprising: obtaining component information and wire connection relationships in the circuit diagram to be tested after image preprocessing; constructing a topological relationship diagram based on the component information and wire connection relationships in the circuit diagram to be tested, and generating a circuit digital model; obtaining fault information, and performing circuit logic analysis on the fault information based on the circuit digital model to generate a fault list; matching all fault types in the fault list with a maintenance database to obtain maintenance recommendation information. This application realizes automated processing of circuit diagrams to be tested, significantly improving recognition and diagnosis efficiency, utilizing circuit digital models and logical reasoning to ensure the accuracy of fault point inference, generating detailed maintenance suggestions and steps, and guiding users to quickly repair faults. It is suitable for analyzing circuit diagrams to be tested at different design stages. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0016] Figure 1 A first flow chart of a circuit diagram-based fault diagnosis method according to an embodiment of the present application is shown; Figure 2 A second flow chart of the circuit diagram-based fault diagnosis method according to an embodiment of the present application is shown; Figure 3A third flow chart of the circuit diagram-based fault diagnosis method according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0017] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0018] The components of the embodiments of the present application generally described and illustrated in the drawings herein may be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed application, but rather merely represents selected embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort are within the scope of protection of the present application.

[0019] Hereinafter, the terms "including", "having" and their cognates used in various embodiments of the present application are intended only to indicate specific features, numbers, steps, operations, elements, components or combinations of the aforementioned items, and should not be understood as excluding the existence of one or more other features, numbers, steps, operations, elements, components or combinations of the aforementioned items or adding the possibility of one or more features, numbers, steps, operations, elements, components or combinations of the aforementioned items. In addition, the terms "first", "second", "third" and the like are only used to distinguish descriptions and should not be understood as indicating or implying relative importance.

[0020] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which the various embodiments of the present application belong. Terms (such as those defined in generally used dictionaries) will be interpreted as having the same meaning as in the context of the relevant technical field and will not be interpreted as having an idealized meaning or an overly formal meaning unless clearly defined in the various embodiments of the present application.

[0021] The following describes some embodiments of the present application in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments may be combined with each other.

[0022] The circuit diagram-based fault diagnosis method is described below with reference to some specific embodiments.

[0023] Figure 1 A flow chart of a circuit diagram-based fault diagnosis method according to an embodiment of the present application is shown. Exemplarily, the circuit diagram-based fault diagnosis method includes the following steps: S110, obtaining component information and wire connection relationship in the circuit diagram to be tested after image preprocessing.

[0024] In this embodiment, the present application imports the circuit diagram to be tested through a scanner or image file, and performs image preprocessing on the circuit diagram to be tested. Demonstratively, the present application improves clarity and reduces noise interference through image enhancement processing, and then uses an edge detection algorithm to identify areas in the image where brightness changes significantly. In the present application, the area usually corresponds to the boundary or outline of the circuit diagram to be tested, which helps to locate components such as resistors and capacitors.

[0025] In one embodiment, image enhancement processing includes grayscale processing, binarization processing, and denoising processing. Grayscale processing is used to convert a color image into a grayscale image, reducing redundant information while retaining key features. Binarization processing is used to further simplify the grayscale image into a black and white image to facilitate subsequent contour extraction or region segmentation. Denoising processing is used to eliminate random noise in the image and retain useful signals. For example, a Gaussian filter is used to perform a convolution operation on the image to reduce the impact of high-frequency noise.

[0026] In another embodiment, the present application performs edge detection on the circuit diagram to be tested using the Canny edge detection algorithm. The Canny edge detection algorithm is based on computer vision technology and is used to extract clear and accurate edges from images. In the present application, the circuit diagram to be tested, after image enhancement processing, is input, and the edge detection of the circuit diagram to be tested is performed using the Canny edge detection algorithm, and an edge map containing the outlines of the circuit components is output.

[0027] In one embodiment, component information includes component type and component parameters. This application inputs the circuit diagram to be tested into a pre-trained component recognition model to identify the component types in the circuit diagram to be tested. The component recognition model is a deep learning-based target detection algorithm used to automatically identify and classify various electronic components (such as power supplies, motors, sensors, resistors, capacitors, etc.) in the circuit diagram to be tested. By training the model to learn the characteristic representations of different components in the circuit diagram to be tested, the model can output the location of each component and its category label with high accuracy.

[0028] In one embodiment, the component recognition model is pre-trained, including: in the data preparation phase, images of circuit diagrams to be tested containing components such as power supplies, motors, sensors, resistors, and capacitors are collected and annotated, such as by using the LabelImg tool to mark component categories and bounding boxes. In the model selection phase, the component recognition model is trained based on YOLO or Faster R-CNN, using pre-trained weights for transfer learning. In the training optimization phase, the pre-processed image is input, a loss function (classification loss + bounding box regression loss) is defined, and the model parameters are optimized through backpropagation until the validation set accuracy converges.

[0029] In another embodiment, the component recognition model's recognition mechanism involves inputting an edge map containing circuit component outlines into the component recognition model. The model then extracts image features using a convolutional neural network (CNN) to generate candidate regions (e.g., Faster R-CNN's RPN network or YOLO's grid partitioning). Each candidate region is then classified to identify components such as power supplies, motors, sensors, resistors, and capacitors. Simultaneously, the model accurately locates the components and adjusts the bounding box coordinates (x, y, width, height) to ensure the most accurate range of detected components. The final output of the component recognition model is a structured list including component category, confidence score, and location coordinates. The confidence score represents the model's confidence in the component's recognition result, typically expressed as a value between 0 and 1 (1 indicating complete confidence). The location coordinates represent the component's specific location within the circuit diagram under test, represented by the bounding box coordinates (x, y, width, height).

[0030] In one embodiment, the present application further refines the component type through template matching or feature extraction algorithms. The feature matching algorithm can be a local feature description algorithm and an algorithm for local shape features of the image. Template matching is to determine the specific type by comparing the known component template with the detected component outline. The feature extraction algorithm is used to extract SIFT (Scale-Invariant Feature Transform) or HOG (Histogram of Oriented Gradients) features for each bounding box area output by the deep learning model, match the extracted features with a predefined feature library, and determine the specific type of the component.

[0031] It's understandable that while deep learning models can provide preliminary classification results, some subcategories (such as different types of resistors or capacitors) may require more precise feature descriptions. This is where traditional computer vision algorithms, such as template matching or feature extraction, can be introduced for further refinement.

[0032] In one embodiment, the present application performs text recognition on a text area of a circuit diagram to be tested to obtain component parameters, wherein the component parameters include but are not limited to the resistance value, capacitance value, model number, etc. of the component. In this embodiment, the present application extracts component parameters from the circuit diagram to be tested through an OCR (Optical Character Recognition) engine. The OCR engine is used to convert text content in an image into editable and searchable data. In this application, the OCR engine can be used to read the labeled information on the component (such as "1kΩ", "10uF", "BC547", etc.), thereby realizing automatic recognition and classification.

[0033] In one embodiment, the OCR engine may be Tesseract, which is an open source optical character recognition (OCR) engine used to extract text information from images.

[0034] In another embodiment, the present application uses the wires in the circuit diagram to be tested as the detection target to identify the connection relationship of the wires in the circuit diagram to be tested. In this embodiment, the present application uses Hough transform or deep learning segmentation model (such as U-Net) to extract the connection relationship of the wires in the circuit.

[0035] Among them, the Hough transform is used to detect specific shapes (such as straight lines, circles, etc.) from an image. In the present application, the Hough transform can be used to detect the geometric characteristics of the wires (such as direction and position), thereby identifying the connection relationship of the wires. The deep learning segmentation model is an image segmentation technology based on the Convolutional Neural Network (CNN), which can identify the target area in the image with pixel-level accuracy. In the present application, the deep learning segmentation model is used to accurately extract the pixel distribution of the wires and further identify their connection relationships. It can be understood that the present application further determines the wires connected between the components under the condition of determining the component type, thereby determining the wire connection relationship between the components.

[0036] S120 , constructing a topology diagram based on the component information and wire connection relationship of the circuit diagram to be tested, and generating a circuit digital model.

[0037] In one embodiment, the present application constructs a topology diagram based on component types and wire connection relationships, annotates component parameters to corresponding components in the topology diagram, and uses the parameter-annotated topology diagram as the digital model of the circuit. A topology diagram is a mathematical model used to represent the electrical connection relationships between components in a circuit. The present application automatically annotates component functions and parameters in the topology diagram using a component database (containing standard component parameters), and uses the annotated topology diagram as the digital model of the circuit.

[0038] Optionally, the digital circuit model of the present application is stored as structured data. The format of the structured data includes, but is not limited to, JSON format, XML format, etc., which is not limited here. The digital circuit model can be displayed in the form of a visual circuit diagram to be tested. The visual circuit diagram to be tested can be in the form of SVG, PNG format, etc., for user viewing.

[0039] In this embodiment, the topology graph consists of nodes and edges. Nodes represent components, and their attributes include component type, parameters, and location coordinates. Edges represent wire connections, and their attributes include line width and signal type (power / ground / signal). The topology graph structure can be stored using an adjacency list or a Neo4j graph database, supporting fast path queries (e.g., the shortest path from power source to load).

[0040] S130 , obtaining the fault information described by the user, and performing circuit logic analysis on the fault information based on the circuit digital model to generate a fault list.

[0041] In this embodiment, the application obtains user-generated fault information, such as "window cannot be raised or lowered," and uses natural language processing (NLP) to parse the user-entered fault description and extract fault information, including the faulty component and fault phenomenon. Natural language processing focuses on the interaction between computers and human language. Its core goal is to enable computers to understand, interpret, generate, and respond to natural language. In this application, NLP is used to parse the user-entered fault description, converting the user's unstructured language input into a structured data format for subsequent fault diagnosis.

[0042] In one embodiment, if Figure 2 As shown, this application performs circuit logic analysis on fault information, including the following steps: S131 , starting from the faulty component, searching and identifying some circuit elements related to the fault information in the topology diagram.

[0043] In one embodiment, the present application identifies circuit components associated with the fault information based on a digital circuit model. These components may include, but are not limited to, control units, motors, and power paths. Starting with the faulty component, the present application performs a breadth-first search (BFS) to traverse a topological graph in a graph database.

[0044] In one embodiment, the present application uses a breadth-first search to trace back upstream from the faulty component to the control unit and power supply path. This involves initializing a queue, adding the faulty component to the queue, sequentially removing nodes from the queue, checking their predecessors (i.e., all nodes pointing to that node), adding those predecessors to the queue, and continuing the traversal until the power supply or control unit is reached. For example, if the faulty component is a car window, the upstream path includes relays, switches, and batteries, and the control unit is a microcontroller control pin.

[0045] In another embodiment, the present application uses a breadth-first search to expand downstream from the faulty component to locate controlled loads. A queue is initialized, the faulty component is added to the queue, and nodes are sequentially removed from the queue. Successor nodes (i.e., all nodes pointed to by the node) are checked, and the successor nodes are added to the queue. The search continues until the terminal load is reached. For example, if the faulty component is a car window, the downstream controlled load may include a motor.

[0046] S132, performing logical reasoning on the searched circuit elements to determine the fault point.

[0047] In this embodiment, the present application establishes a Boolean logic model, represents the searched circuit element nodes as Boolean variables (such as relay status, motor operating status, etc.), and establishes a Boolean expression to describe the logical relationship between each node.

[0048] In one embodiment, the circuit element nodes found in this application are represented as Boolean variables (True / False or 1 / 0), including input signals such as MCU_GPIO outputs (1 for high level, 0 for low level); intermediate nodes such as relay status (1 for closed, 0 for open); and output loads such as motor operating status (1 for running, 0 for stopped). Boolean expressions are created to describe the logical relationships between these nodes. For example, relay status: R = (MCU_GPIO AND Switch), motor operating status: M = R. Here, R represents the relay state, MCU_GPIO represents the controller output pin level, Switch represents the external input switch state, and M represents the motor operating status.

[0049] Assuming the states of some nodes are known (such as MCU_GPIO outputting a high level and a switch being closed), the states of other nodes can be deduced using Boolean algebra. For example, if the input conditions are: MCU_GPIO = 1, Switch = 1, then the relay state can be deduced based on the logical relationship: R = 1 AND 1 = 1; the motor running state: M = R = 1.

[0050] If the actual measured data doesn't match the inferred result, there may be a fault. Combined with the logical reasoning results, list all candidate points that may cause the fault. For example, if the relay is not working properly (R = 0), while MCU_GPIO = 1 and Switch = 1, the relay itself may be at fault. If the motor does not start (M = 0, while R = 1), there may be an internal problem with the motor.

[0051] S133: Determine the fault type corresponding to the fault point according to the fault database.

[0052] S134: Sort the fault types according to the fault probability and generate a fault list. In this embodiment, the fault database contains various components (such as relays, motors, transistors, etc.) and their fault types. Based on the results of logical reasoning analysis and combined with the fault database, this application determines the fault type corresponding to the fault point and labels each fault point with the corresponding fault type. For example, when determining a fault in the relay itself, the corresponding fault types include open circuit fault, short circuit fault, and parameter drift. Based on common component fault types and historical data statistics, this application can rank possible fault types by probability and provide priority recommendations, prioritizing high-probability fault points to improve diagnostic efficiency.

[0053] S140: Match all fault types in the fault list with the maintenance database to obtain maintenance recommendation information.

[0054] In one embodiment, the recommended repair information includes repair suggestions, repair procedures, and repair time. This application obtains the repair procedures corresponding to the fault type based on a maintenance database. In this embodiment, the database should include, but is not limited to, the following information: recommended repair methods corresponding to different fault point types (e.g., "Replace relay model XYZ") and recommended procedures corresponding to the repair methods. This application determines the repair method corresponding to the fault type based on the maintenance database and generates a repair procedure based on the circuit diagram to be tested and the maintenance database. For example, the repair procedure may include: disconnecting the power supply, removing the relay, installing a new relay, and testing the circuit.

[0055] In another embodiment, the present application also determines the total operation time of the maintenance process based on a time weight library, adjusts the total operation time based on preset constraints, and determines the maintenance time. In this embodiment, the maintenance process is decomposed: the maintenance process is broken down into multiple atomic operations, for example, removing 4 M3 screws and soldering 2 pins. Among them, the maintenance process refers to the overall process of completing a maintenance task from start to finish. Atomic operations refer to the basic operation units in the maintenance process that cannot be further subdivided.

[0056] In one embodiment, the present application establishes a time weight library containing atomic operations and their basic time consumption, and determines the total operation time of the maintenance process based on the atomic operation time consumption in the time weight library, for example: it takes 0.5 minutes to remove each screw; it takes 1 minute to solder each pin. The present application introduces a variety of preset constraints to reflect the additional difficulty in actual operation. The present application introduces a space constraint correction. When the operation area is narrow, the basic time consumption is increased by 20%. The narrow operation area means that when performing maintenance tasks, due to the limitation of physical space, the operator cannot complete certain atomic operations conveniently and efficiently. If there is a narrow operation range when removing a screw, the time consumption of the operation after correction is minute.

[0057] This application introduces a tool-dependency correction condition. If a specialized tool is not available, the base time is increased by 30%. For example, if the base time to remove a screw is 0.5 minutes, the corrected time is 0.5 (1 + 30%) = 0.65 minutes if a specialized tool is not available. In this application, specialized tools are high-efficiency tools designed for specific repair tasks (such as electric screwdrivers and specialized wrenches). If specialized tools are not available, general-purpose tools (such as ordinary screwdrivers and pliers) may be required.

[0058] This application also introduces a historical calibration correction condition. By analyzing past maintenance logs (e.g., the average duration of the past 100 "relay replacements" was 28 minutes), the application dynamically adjusts the duration of atomic operations within the maintenance process. Historical calibration correction involves analyzing actual duration data from past maintenance logs and dynamically adjusting the parameter values in the time weighting library to make the estimate more accurate. For example, if historical data shows that the average duration of a maintenance process over the past 100 times was 28 minutes, this application can adjust the duration of atomic operations accordingly, resulting in an estimated duration closer to 28 minutes.

[0059] In one embodiment, the present application can also analyze the circuit to be tested to determine whether there are potential design defects in the circuit design of the circuit to be tested, such as short circuit risk, component overload, etc. Figure 3 As shown, the analytical analysis method may include the following steps: S141: Construct a circuit logic model according to the component information of the circuit diagram to be tested.

[0060] In this embodiment, the circuit diagram to be tested can be input as a circuit design file in CAD format (e.g., Altium Designer or Eagle). This application uses a CAD file parsing library (e.g., a DXF or Gerber parser) to extract circuit design information, including but not limited to component layout and wire connections. Similar to establishing the circuit topology diagram described above, a topology diagram of the circuit to be tested is obtained.

[0061] In one embodiment, the present application also classifies and models the components based on the component information, constructs a circuit logic model, and divides the circuit components into passive components and active components. Passive components may include resistors and capacitors. The circuit logic model of passive components refers to describing the behavioral characteristics of active components in the circuit through mathematical or logical methods. For example, resistance R=V / I, and the resistance value of the resistor is determined by the voltage V and the current I.

[0062] Active components are components in a circuit whose operating state can be controlled by external signals, such as gain or switching functions. Active components include, but are not limited to, transistors, diodes, and operational amplifiers. A circuit logic model for an active component describes its behavior in a circuit through mathematical, physical, or logical means.

[0063] In one embodiment, active component modeling can be achieved using two primary approaches: SPICE models and state machines. SPICE (Simulation Program with Integrated Circuit Emphasis) models are physics-based mathematical models that reproduce the actual electrical characteristics of active components, including non-ideal effects (such as parasitic capacitance and temperature dependence), through a set of parameterized equations. For MOSFETs (metal oxide semiconductor field effect transistors), SPICE models can accurately simulate their on, off, and saturation states.

[0064] A state machine model is a modeling method based on logic functions, primarily used to describe the switching behavior or logical state of active components. In this application, the state machine model abstracts the operating state of a transistor into discrete states (such as "on" and "off") and defines the state switching relationship through input conditions. For example, a transistor state machine model can be represented by two states: on (ON) and off (OFF).

[0065] In this embodiment, the circuit logic model of the passive component analyzes the signal flow and the interactions between components in the circuit under test. When resistance exists in the signal path, an impedance effect is introduced, which affects voltage transmission. When voltage and capacitance exist in the signal path, an RC time constant is established. The RC time constant (τ) is a core parameter used to measure the speed of capacitor charge and discharge in a resistor-capacitor (RC) circuit. Its value is equal to the product of the resistance and capacitance (τ = R × C). The circuit logic model of the active component analyzes the signal flow and the interactions between components in the circuit under test to determine whether the device is in an active state (e.g., a transistor forms a path when it is turned on).

[0066] S142 , analyzing the signal flow direction of the circuit to be tested and the functional relationship between various components based on the topological relationship diagram of the circuit to be tested and the circuit logic model.

[0067] In one embodiment, the present application converts the topology graph into a directed acyclic graph (DAG), where nodes represent signal states (high / low level) and edges represent logic gates (AND / OR / NOT). In this embodiment, the DAG is constructed based on the circuit topology graph and the signal transmission order, with the input signal as the starting node, the output signal as the ending node, and the intermediate nodes representing the logic gate operation results.

[0068] In one embodiment, the present application performs forward tracing analysis on a circuit under test, starting with an analog signal at the circuit's input and sequentially determining the level changes at each circuit node in the circuit under test. In this embodiment, starting with the circuit's input (e.g., power supply, control switch, sensor signal), the simulation is performed step by step, following the circuit's connections, to simulate how the signal propagates through each component to the output.

[0069] In another embodiment, the present application performs reverse tracing analysis on the circuit under test, starting from the target circuit node and determining the upstream signal sources that affect the target circuit node. Reverse tracing is to start from the target node and reversely trace all upstream signal sources that may affect its state. The target node to be analyzed is clearly defined, and the same directed acyclic graph as the forward tracing is used, but in the opposite direction. Starting from the target node, all upstream nodes are traversed in reverse until all possible signal sources are found, and the degree of influence of each upstream signal on the target node is determined.

[0070] This application uses an LED flashing circuit as an example, combining forward tracing and reverse tracing for signal analysis. The circuit components include: switch S, which controls the circuit on and off; resistor R1, a current-limiting resistor; transistor Q1, which acts as a switching element; and an LED. The circuit operates as follows: When switch S1 is closed, current flows through R1 into the base of Q1, triggering Q1 to turn on. Once Q1 turns on, current flows through the LED, causing it to illuminate.

[0071] Forward tracing analysis assumes that switch S1 is initially open (low level) and then closed (high level). Node 1 represents S1's output, initially low (switch open). When the switch closes, the output becomes high. Node 2 represents Q1's base voltage. Initially, the base is low because the switch is open. When the switch closes, current flows through R1, causing the base voltage to gradually rise. Verifying the logic model: Check whether the base voltage reaches the threshold. If so, Q1 turns on, current flows through the LED, and it illuminates. If not, the LED turns off.

[0072] For reverse source analysis, assume the target node is the LED state (on / off). Reversely trace all upstream signal sources that may affect its state: Node 1 represents the LED state, which is determined by the on / off state of Q1. Node 2 represents the base voltage of Q1, whose on state depends on whether the base voltage reaches the threshold. Node 3 represents the initial state of S1's output, whose base voltage is determined by its output state. If the LED is off, the base voltage has not reached the threshold, and the initial state of S1's output is low. If the LED is on, the base voltage has reached the threshold, and the initial state of S1's output is high.

[0073] S143, detecting design defects of the circuit under test through a rule engine and topology analysis, and generating a defect report.

[0074] In one embodiment, the rule engine uses predefined circuit detection rules to detect short circuits and overloads in the circuit under test. In this embodiment, the short circuit detection rule detects whether there is a direct connection between the power supply and the ground line (except for a clearly designed 0Ω resistor). For example, detecting the presence of an unlabeled wire between the power supply VCC and GND triggers a "potential short circuit risk" alarm. The overload detection rule calculates whether the actual power consumption of the component exceeds the rated value. For example, it is found that the power consumption of resistor R1 (10Ω) under 5V power supply is 2.5W, far exceeding its rated value of 0.25W.

[0075] In another embodiment, the present application determines the signal loop path of the circuit under test through topological analysis. In this embodiment, the topological analysis converts the topological diagram of the circuit under test into a directed graph, where nodes represent key points in the circuit (such as logic gates, amplifiers, capacitors, etc.), and edges represent signal transmission paths and their directions. Feedback loop detection is performed on the circuit under test, automatically identifying all existing feedback loops in the circuit. For each loop, the following checks are performed: whether an amplifier (gain unit) is present; whether an energy storage element (capacitor, inductor) is present; and whether the loop constitutes positive feedback. If these conditions are met, a determination is made as to whether the resonant frequency matches the load time constant. If there is a risk of parasitic oscillation, a visual annotation is generated.

[0076] The present application also determines the isolation nodes of the circuit to be tested through topological analysis and performs an isolation check on the circuit to be tested. Topological analysis converts the topological diagram of the circuit to be tested into an undirected graph, in which the nodes represent the key points in the circuit (such as digital ground, analog ground, magnetic beads, etc.) and the edges represent the physical connection relationship and its impedance characteristics. The present application performs isolation checks on multiple connection paths in the undirected graph, automatically identifies multi-point connections or non-isolated connections between digital ground and analog ground, and determines whether they meet the single-point connection specifications. For example, check that the digital ground and analog ground are only connected at a single point through a magnetic bead.

[0077] In one embodiment, the present application analyzes the circuit to be tested, generates a defect analysis report of the circuit to be tested based on the analysis results, and searches the defect modification solution database to obtain relevant modification solutions. The present application marks the defect area on the circuit diagram to be tested in an intuitive manner, for example: highlighting: using different colors to mark different types of problem areas. In this embodiment, the defect modification solution database is a structured storage system for storing information such as modification schematics and reference cases related to circuit design defects. For example, there are multiple connection paths between the analog ground and the digital ground, and the database responds: it is recommended to add magnetic beads for single-point isolation; it provides magnetic bead model recommendations, etc.

[0078] The present application also provides a terminal device. Exemplarily, the terminal device includes a processor and a memory, wherein the memory stores a computer program, and the processor runs the computer program, thereby enabling the terminal device to execute the above-mentioned circuit diagram-based fault diagnosis method.

[0079] The processor can be an integrated circuit chip with signal processing capabilities. The processor can be a general-purpose processor, including at least one of a central processing unit (CPU), a graphics processing unit (GPU), a network processor (NP), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The general-purpose processor can be a microprocessor or any conventional processor, etc., and can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of this application.

[0080] The memory may be, but is not limited to, random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), and electrically erasable programmable read-only memory (EEPROM). The memory is used to store computer programs, and the processor can execute the computer programs accordingly after receiving execution instructions.

[0081] This application also provides a computer-readable storage medium for storing a computer program used in the terminal device. For example, the computer-readable storage medium may include, but is not limited to, various media capable of storing program code, such as a USB flash drive, a mobile hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0082] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and structure diagrams in the accompanying drawings show the possible architectures, functions and operations of the devices, methods and computer program products according to the multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and the module, program segment or a part of the code contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in an alternative implementation, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the structure diagram and / or flowchart, and the combination of boxes in the structure diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or can be implemented using a combination of dedicated hardware and computer instructions.

[0083] In addition, the functional modules or units in the various embodiments of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0084] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a smart phone, personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application.

[0085] The above is only a specific implementation method of the present application, but the scope of protection of the present application is not limited thereto. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed in this application, which should be covered by the scope of protection of the present application.

Claims

1. A fault diagnosis method based on a circuit diagram, characterized in that: include: Obtaining component information and wire connection relationships in the circuit diagram to be tested after image preprocessing; Constructing a topology diagram based on the component information and the wire connection relationship of the circuit diagram to be tested, and generating a circuit digital model; Acquire fault information described by the user, and perform circuit logic analysis on the fault information based on the circuit digital model to generate a fault list; All fault types in the fault list are matched with the maintenance database to obtain maintenance recommendation information.

2. The circuit diagram-based fault diagnosis method according to claim 1, characterized in that: Also includes: Constructing a circuit logic model according to the component information of the circuit diagram to be tested; Analyzing the signal flow direction of the circuit to be tested and the functional relationship between various components based on the topological relationship diagram of the circuit to be tested and the circuit logic model; The design defects of the circuit to be tested are detected through a rule engine and topology analysis, and a defect report is generated.

3. The circuit diagram-based fault diagnosis method according to claim 1, characterized in that: The component information includes component type and component parameters, and the component information and wire connection relationship in the circuit diagram to be tested obtained after image preprocessing include: Inputting the circuit diagram to be tested into a pre-trained component recognition model to identify the component types in the circuit diagram to be tested; Performing text recognition on the text area of the circuit diagram to be tested to obtain the component parameters; The wires in the circuit diagram to be tested are used as detection targets to identify the connection relationship of the wires in the circuit diagram to be tested.

4. The circuit diagram-based fault diagnosis method according to claim 3, characterized in that: The constructing a topology diagram based on the component information and the wire connection relationship of the circuit diagram to be tested includes: Constructing a topology diagram based on the component types and the wire connection relationships, and marking the component parameters to the corresponding components in the topology diagram; The topological relationship diagram after parameter annotation is used as the circuit digital model.

5. The circuit diagram-based fault diagnosis method according to claim 1, characterized in that: The fault information includes a fault component and a fault phenomenon. The circuit logic analysis of the fault information based on the circuit digital model to generate a fault list includes: Taking the faulty component as a starting point, searching and identifying a portion of circuit elements related to the fault information in the topology diagram; Performing logical reasoning on the searched circuit elements to determine the fault point; Determine the fault type corresponding to the fault point according to the fault database; The fault types are sorted according to the fault probabilities to generate the fault list.

6. The circuit diagram-based fault diagnosis method according to claim 1, characterized in that: The maintenance recommendation information includes maintenance suggestions, maintenance procedures, and maintenance time. Acquiring the maintenance recommendation information includes: Obtaining the maintenance suggestion and the maintenance process corresponding to the fault type based on a maintenance database; The total operation time of the maintenance process is determined based on a time weight library, and the total operation time is adjusted based on preset constraints to determine the maintenance time.

7. The circuit diagram-based fault diagnosis method according to claim 2, characterized in that: The analyzing the signal flow direction of the circuit to be tested and the functional relationship between various components based on the topological relationship diagram of the circuit to be tested and the circuit logic model includes: Starting from the analog signal at the input end of the circuit to be tested, sequentially determining the level change of each circuit node in the circuit to be tested; Starting from a target circuit node, an upstream signal source affecting the target circuit node is determined.

8. The circuit diagram-based fault diagnosis method according to claim 2, characterized in that: The detecting design defects of the circuit to be tested by using a rule engine and topology analysis and generating a defect report includes: Performing short circuit and overload detection on the circuit to be tested using predefined circuit detection rules; Determine a signal loop path of the circuit to be tested by topological analysis, and perform loop detection on the circuit to be tested; The isolation node of the circuit to be tested is determined through topological analysis, and an isolation check is performed on the circuit to be tested.

9. A terminal device, characterized in that: The terminal device includes a processor and a memory, wherein the memory stores a computer program, and the processor is configured to execute the computer program to implement the circuit diagram-based fault diagnosis method according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that The computer program is stored therein, and when the computer program is executed on a processor, the circuit diagram-based fault diagnosis method according to any one of claims 1 to 8 is implemented.

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