Communication system signal receiving method, circuit, device and equipment based on memristor

Abstract

The invention discloses a communication system signal receiving method, circuit, device and equipment based on a memristor, and belongs to the field of integrated circuits and the field of communication signal processing. According to the communication system signal receiving method provided by the invention, element values of a real number field channel matrix and a variance value of a noise signal vector are mapped into a conductivity value of a memristor, a real number field receiving signal vector is mapped into a voltage signal vector, the voltage signal vector is input into an analog domain calculation circuit, the output of the circuit is measured, and detection of all emission signal components is realized. The communication system signal receiving circuit, device and equipment are realized based on the method. Compared with a traditional processor based on digital domain calculation, the analog domain calculation circuit based on the memristor, which is realized by aiming at a serial interference elimination detection algorithm, is shorter in calculation delay and higher in energy efficiency, and compared with an existing linear detection algorithm circuit based on the memristor, the analog domain calculation circuit based on the memristor has the advantages of better detection performance and lower bit error rate.

Description

Technical Field

[0001] The present invention relates to the fields of integrated circuits and communication signal processing, and in particular to a memristor-based communication system signal receiving method, circuit, device, and equipment. Background Art

[0002] In communication systems, signal reception detection technology is one of the key technologies that impacts system capacity and user access capabilities. The Successive Interference Cancellation (SIC) detection algorithm (also known as the Continuous Interference Cancellation (CIC) detection algorithm) is one of the most commonly used signal reception detection algorithms in communication systems. The core concept of this algorithm is to detect and judge each transmitted signal component in a certain order, and after each detection, eliminate the interference of the detected transmitted signal component on the remaining signal. Compared with traditional linear detection algorithms such as the Zero-Forcing (ZF) algorithm and the Minimum Mean Squared Error (MMSE) algorithm, the SIC detection algorithm has superior detection performance.

[0003] Memristors are nonvolatile devices with memory properties. Their conductance can be adjusted within a certain range and remains constant even after power is removed. Arrays of memristors can efficiently and quickly perform large-scale matrix operations using analog-domain computing. Analog-domain matrix computing technology based on memristor arrays boasts computational speeds and energy efficiency far exceeding those of traditional digital-domain computing methods, making it particularly well-suited for large-scale parallel matrix computing tasks.

[0004] In recent years, researchers have shown that analog-domain matrix computing technology based on memristor arrays can be used to accelerate baseband signal processing algorithms in large-scale multiple-input multiple-output (MIMO) systems. For example, reference 1 (P. Mannocci, E. Melacarne and D. Ielmini, "An Analogue In-Memory Ridge Regression Circuit With Application to Massive MIMO Acceleration," in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 12, no. 4, pp. 952-962, Dec. 2022.) designed a matrix computing circuit based on a memristor array and used it to perform matrix operations in the signal detection and precoding process of large-scale MIMO systems. The results show that the circuit is four orders of magnitude more energy efficient and three orders of magnitude more area efficient than commercial graphics processing units (GPUs).

[0005] Research on analog-domain matrix computing technology for signal reception and detection in communication systems currently focuses primarily on linear detection algorithms. Under high signal-to-noise ratio conditions, the bit error rate performance of linear detection algorithms often struggles to match that of nonlinear detection algorithms, such as serial interference cancellation algorithms. However, no memristor array-based computing circuits specifically designed for serial interference cancellation algorithms exist. Summary of the Invention

[0006] Based on the above problems, the present invention provides a communication system signal reception method, circuit, device and equipment based on a memristor, which realizes communication signal reception detection based on a serial interference cancellation algorithm in a high energy efficiency and low latency manner.

[0007] The present invention provides a communication system signal receiving method based on a memristor, comprising the following steps:

[0008] Step 1: Obtain the received signal vector and channel matrix of the communication system, and obtain the variance value of the noise signal vector of the communication system.

[0009] Step 2: Use the memristor-based analog domain computing circuit provided by the present invention to execute the serial interference cancellation algorithm. First, the element values of the real domain channel matrix and the variance value of the noise signal vector are mapped to the conductance value of the memristor in the serial interference cancellation algorithm computing circuit. Then, the real domain received signal vector is mapped to a voltage signal, and this voltage signal is input to the voltage input port of the serial interference cancellation algorithm computing circuit. Finally, the output voltage of the serial interference cancellation algorithm computing circuit is measured to obtain the calculation result.

[0010] Step 3: Output the calculation results.

[0011] In order to realize the above-mentioned communication system signal receiving method based on memristor provided by the present invention, the present invention provides a circuit for communication system signal reception, specifically an analog domain calculation circuit of a serial interference elimination algorithm based on memristor. The calculation circuit includes K analog domain matrix calculation modules, K real part decision modules and K imaginary part decision modules, where K is the dimension of the transmitted signal vector; the real domain received signal vector y is mapped into a voltage signal and input into the analog domain calculation circuit, specifically, the voltage input port of the K analog domain matrix calculation modules; the kth iteration in the serial interference elimination algorithm is used to detect the mth k The transmitted signal components, the detection result is e k .

[0012] The two outputs of analog-domain matrix calculation module k are connected to the inputs of real-part decision module k and imaginary-part decision module k, respectively, where k = 1, 2, …, K. The outputs of real-part decision module 1 through real-part decision module k-1 and the outputs of imaginary-part decision module 1 through imaginary-part decision module k-1 are all connected to the input of analog-domain matrix calculation module k.

[0013] The analog domain matrix calculation module is implemented based on a memristor crossbar array. k The equivalent real form of the matrix calculation required for the transmission signal component is used to map the element values of the real domain channel matrix and the variance of the noise signal vector to the conductance value of the memristor in the analog domain matrix calculation module k. The two output terminals of the analog domain matrix calculation module k output the mth k The detection result of the transmitted signal component e k The real part of and the imaginary part The real part decision module k and the imaginary part decision module k respectively make decisions on the output of the analog domain matrix calculation module k and output and The corresponding analog voltage value. Measure the output voltage of the real part decision module k and the imaginary part decision module k to obtain the mth k The detection result of the transmitted signal component e k .

[0014] In the analog domain calculation circuit of the serial interference cancellation algorithm of the present invention, an analog domain matrix calculation module 1 is provided, which includes a first memristor cross array, a second memristor cross array, a first group of operational amplifiers, a second group of operational amplifiers, a group of voltage input ports, and two voltage output ports. Each row of the first memristor cross array corresponds one-to-one to each operational amplifier in the first group of operational amplifiers, and is respectively connected to one of the non-inverting input or inverting input of the corresponding operational amplifier. The input of each operational amplifier in the first group of operational amplifiers that is not connected to the first memristor cross array is grounded, and at least one memristor or resistor is connected between the input of the operational amplifier connected to the first memristor cross array and the output of the operational amplifier. Each column of the second memristor cross array corresponds one-to-one to each operational amplifier in the second group of operational amplifiers, and is respectively connected to one of the non-inverting input or inverting input of the corresponding operational amplifier. The input of each operational amplifier in the second group of operational amplifiers that is not connected to the second memristor cross array is grounded, and an inverting amplifier and at least one memristor or resistor are connected between the input of the operational amplifier connected to the second memristor cross array and the output of the operational amplifier. Each column of the first memristor crossbar array can be connected to one end of an inverting amplifier, the other end of which is then connected to the output of an operational amplifier in the second group of operational amplifiers; alternatively, each column of the first memristor crossbar array can be directly connected to the output of an operational amplifier in the second group of operational amplifiers. Similarly, any row of the second memristor crossbar array can be connected to one end of an inverting amplifier, the other end of which is then connected to the output of an operational amplifier in the first group of operational amplifiers; alternatively, any row of the second memristor crossbar array can be directly connected to the output of an operational amplifier in the first group of operational amplifiers. Each row of the first memristor crossbar array corresponds one-to-one to each voltage input port in a group of voltage input ports, and at least one memristor or resistor is connected between each row of the first memristor crossbar array and the corresponding voltage input port. Two voltage output ports are respectively connected to any two columns of the first memristor crossbar array, and the two voltage output ports are respectively connected to the inputs of real part decision module 1 and imaginary part decision module 1.

[0015] In the analog domain calculation circuit of the serial interference elimination algorithm, the circuit structure of the analog domain matrix calculation module k (2≤k≤K) is set as follows: including a first memristor cross array, a second memristor cross array, a third memristor cross array, a first group of operational amplifiers, a second group of operational amplifiers, a first group of voltage input ports, a second group of voltage input ports, and two voltage output ports. Each row of the first memristor cross array corresponds one-to-one to each voltage input port in the first group of voltage input ports, and at least one memristor or resistor is connected between each row of the first memristor cross array and the corresponding voltage input port. Any column of the first memristor cross array can be connected to one end of an inverting amplifier, and then the other end of the inverting amplifier is connected to one of the voltage input ports in the second group; or any column of the first memristor cross array can also be directly connected to one of the voltage input ports in the second group. Each row of the first memristor cross array corresponds one-to-one to each row of the second memristor cross array and is connected respectively. Each row of the second memristor crossbar array corresponds one-to-one with each operational amplifier in the first group of operational amplifiers and is connected to either the non-inverting input or the inverting input of the corresponding operational amplifier. The input of each operational amplifier in the first group of operational amplifiers not connected to the second memristor crossbar array is grounded, and at least one memristor or resistor is connected between the input of the operational amplifier connected to the second memristor crossbar array and the output of the operational amplifier. Each column of the third memristor crossbar array corresponds one-to-one with each operational amplifier in the second group of operational amplifiers and is connected to either the non-inverting input or the inverting input of the corresponding operational amplifier. The input of each operational amplifier in the second group of operational amplifiers not connected to the third memristor crossbar array is grounded, and an inverting amplifier and at least one memristor or resistor are connected between the input of the operational amplifier connected to the third memristor crossbar array and the output of the operational amplifier. Any column of the second memristor crossbar array can be connected to one end of an inverting amplifier, the other end of which is then connected to the output of one of the operational amplifiers in the second group of operational amplifiers; alternatively, any column of the second memristor crossbar array can be directly connected to the output of one of the operational amplifiers in the second group of operational amplifiers. Any row of the third memristor crossbar array can be connected to one end of an inverting amplifier, the other end of which is then connected to the output of one of the operational amplifiers in the first group. Alternatively, any row of the third memristor crossbar array can be directly connected to the output of one of the operational amplifiers in the first group. Each voltage input port in the second group of voltage input ports is also connected to the output of the first k-1 real part decision modules and the first k-1 imaginary part decision modules, respectively. The two voltage output ports are respectively connected to any two columns of the second memristor crossbar array and are also connected to the inputs of real part decision module k and imaginary part decision module k, respectively.

[0016] In the analog domain calculation circuit of the serial interference cancellation algorithm, the circuit structure of the imaginary part decision module and the real part decision module is as follows: the circuit includes a voltage input port, a voltage output port, a first voltage supply module, a second voltage supply module, a multi-way switch, and at least one voltage comparator. One of the non-inverting input and inverting input of each voltage comparator is connected to the voltage input port, and the other input is connected to the second voltage supply module. The output of the voltage comparator is directly connected to the gate control signal input of the multi-way switch, or is connected to the gate control signal input of the multi-way switch through a combinational logic circuit. The output of the multi-way switch is connected to the voltage output port of the imaginary part decision module or the real part decision module. The first voltage supply module is connected to at least two of the input channels of the multi-way switch to provide the multi-way switch with voltages corresponding to all possible decision results. The second voltage supply module provides each voltage comparator with a voltage corresponding to a decision threshold.

[0017] Furthermore, the present invention also provides a device for receiving signals in a communication system, specifically a computing device for a memristor-based serial interference cancellation algorithm. The device includes a memristor programming module, an analog domain computing circuit for a memristor-based serial interference cancellation algorithm provided by the present invention, and a voltage measurement module. The memristor programming module programs and modifies the conductance value of the memristor in the serial interference cancellation algorithm computing circuit. Based on the equivalent real number form of the matrix calculation performed to detect the transmitted signal vector, the element values of the real domain channel matrix and the variance of the noise signal vector are mapped to the conductance value of the memristor in the analog domain matrix computing module. The analog domain computing circuit of the serial interference cancellation algorithm inputs the analog voltage corresponding to the real domain received signal vector as input voltage to a set of voltage input ports of the analog domain matrix computing module 1 and the first set of voltage input ports of the analog domain matrix computing module k (2≤k≤K), thereby implementing the computational process of the serial interference cancellation algorithm. The voltage measurement module is used to measure the output voltage vector of the analog domain computing circuit of the serial interference cancellation algorithm, which corresponds to the detection result of the transmitted signal vector calculated by the serial interference cancellation algorithm.

[0018] Furthermore, the present invention provides three implementations of a communication system signal receiving device based on a memristor.

[0019] A first implementation of the memristor-based communication system signal receiving device of the present invention is as follows: the device includes an antenna, a first radio frequency filter, a low-noise amplifier, a second radio frequency filter, a mixer, a local oscillator, an intermediate frequency filter, an intermediate frequency amplifier, a demodulator, an analog-to-digital converter, a voltage supply module, a channel estimation module, and a computing device for the memristor-based serial interference elimination algorithm implemented by the present invention. The output end of the local oscillator is connected to the input end of the mixer; the antenna, the first radio frequency filter, the low noise amplifier, the second radio frequency filter, the mixer, the intermediate frequency filter, and the intermediate frequency amplifier are connected in sequence to convert the radio frequency signal received by the antenna into an intermediate frequency signal; the output end of the intermediate frequency amplifier is connected to the input end of the demodulator, and the demodulator converts the intermediate frequency signal into a baseband reception signal in the form of an analog signal; the output end of the demodulator is connected to the input end of the analog-to-digital converter, and the analog-to-digital converter converts the baseband reception signal in the form of an analog signal into a baseband reception signal in the form of a digital signal; the output end of the analog-to-digital converter is connected to the input end of the voltage providing module and also to the input end of the channel estimation module; the channel estimation module estimates the channel based on the baseband reception signal and outputs the channel matrix to the serial interference cancellation algorithm calculation device; the voltage providing module converts the baseband reception signal in the form of a digital signal into a corresponding voltage vector and provides it to the serial interference cancellation algorithm calculation device; the serial interference cancellation algorithm calculation device outputs the detection result of the transmission signal vector.

[0020] A second implementation of the memristor-based communication system signal receiving device of the present invention is as follows: the device includes an antenna, a first radio frequency filter, a low-noise amplifier, a second radio frequency filter, a mixer, a local oscillator, an intermediate frequency filter, an intermediate frequency amplifier, a sampling and holding circuit, a channel estimation module, and a computing device for the memristor-based serial interference elimination algorithm implemented by the present invention. The output end of the local oscillator is connected to the input end of the mixer; the antenna, the first radio frequency filter, the low noise amplifier, the second radio frequency filter, the mixer, the intermediate frequency filter, and the intermediate frequency amplifier are connected in sequence to convert the radio frequency signal received by the antenna into an intermediate frequency signal; the output end of the intermediate frequency amplifier is connected to the input end of the sampling and holding circuit, and the sampling and holding circuit converts the intermediate frequency signal into a baseband received signal in the form of an analog signal; the output end of the sampling and holding circuit is connected to the input end of the channel estimation module, and the channel estimation module estimates the channel based on the baseband received signal and outputs the channel matrix to the serial interference cancellation algorithm calculation device; the output end of the sampling and holding circuit is also connected to the input end of the serial interference cancellation algorithm calculation device, and the baseband received signal in the form of an analog signal is provided to the serial interference cancellation algorithm calculation device as an input voltage vector; the serial interference cancellation algorithm calculation device outputs the detection result of the transmitted signal vector.

[0021] A third implementation of the memristor-based communication system signal receiving device of the present invention is as follows: the device includes an antenna, a first radio frequency filter, a low-noise amplifier, a second radio frequency filter, a mixer, a local oscillator, an intermediate frequency filter, an intermediate frequency amplifier, a demodulator, a channel estimation module, and a computing device for the memristor-based serial interference elimination algorithm implemented by the present invention. The output end of the local oscillator is connected to the input end of the mixer; the antenna, the first radio frequency filter, the low noise amplifier, the second radio frequency filter, the mixer, the intermediate frequency filter, and the intermediate frequency amplifier are connected in sequence to convert the radio frequency signal received by the antenna into an intermediate frequency signal; the output end of the intermediate frequency amplifier is connected to the input end of the demodulator, and the demodulator converts the intermediate frequency signal into a baseband received signal in the form of an analog signal; the output end of the demodulator is connected to the input end of the channel estimation module, and the channel estimation module estimates the channel based on the baseband received signal and outputs the channel matrix to the serial interference cancellation algorithm calculation device; the output end of the demodulator is also connected to the input end of the serial interference cancellation algorithm calculation device, and the baseband received signal in the form of an analog signal is provided to the serial interference cancellation algorithm calculation device as an input voltage vector; the serial interference cancellation algorithm calculation device outputs the detection result of the transmitted signal vector.

[0022] The advantages and positive effects of the present invention are as follows: the present invention's memristor-based communication system signal reception method, circuit, device, and apparatus utilize memristor-based analog-domain matrix computing technology to implement serial interference cancellation algorithm calculations and signal reception detection. Compared with traditional digital-domain computing processors, the present invention's memristor-based computing circuit offers shorter computational latency and higher energy efficiency. Compared with existing memristor-based linear detection algorithm circuits, the present invention offers improved detection performance and lower bit error rates. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 This is a flow chart of the implementation of the signal receiving method of the communication system based on the memristor provided by the present invention;

[0024] Figure 2 Schematic diagram of the structure of a calculation circuit for a serial interference elimination algorithm based on a memristor implemented in an embodiment of the present invention;

[0025] Figure 3 Schematic diagram of the circuit structure of the analog domain matrix calculation module 1 implemented in an embodiment of the present invention;

[0026] Figure 4 Schematic diagram of the circuit structure of the analog domain matrix calculation module k (2≤k≤K) implemented in an embodiment of the present invention;

[0027] Figure 5 This is a schematic diagram of a first circuit structure of a real part decision module and an imaginary part decision module according to an embodiment of the present invention;

[0028] Figure 6 2 is a schematic diagram of a second circuit structure of the real part decision module and the imaginary part decision module according to an embodiment of the present invention;

[0029] Figure 7 2 is a schematic structural diagram of a memristor-based serial interference cancellation algorithm calculation device according to an embodiment of the present invention;

[0030] Figure 8 This is a schematic diagram of a first structure of a memristor-based signal receiving device according to an embodiment of the present invention;

[0031] Figure 9 is a second structural diagram of a memristor-based signal receiving device according to an embodiment of the present invention;

[0032] Figure 10 This is a third structural diagram of a memristor-based signal receiving device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0033] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0034] Before describing the present invention, the serial interference cancellation signal detection algorithm is first introduced:

[0035] make Represents a received signal vector (complex vector) in the communication system, R is the received signal vector The dimension of make Indicates the transmitted signal vector corresponding to the received signal vector, K is the transmitted signal vector The dimension of Transmit signal vector After normalization, the average power constraint of each symbol is 1, that is, make represents the channel matrix, The relationship between the transmitted signal, received signal and channel matrix is generally expressed as in is a noise signal vector, the mean of each element of which is 0 and the variance is The successive interference cancellation algorithm requires a known and In the case of transmitting signal vector The serial interference cancellation algorithm detects the transmitted signals one by one in a certain order, using {m1,m2,…,m K} represents the detection order, and the kth iteration in the serial interference cancellation algorithm is used to detect the mth k The transmitted signal components, the detection result is e k .

[0036] The first detection of the serial interference cancellation algorithm calculates e1. The matrix calculation expression required for the first detection is:

[0037]

[0038] in is the calculation result vector of the first detection, (·) H represents the conjugate transpose of the matrix, (·) -1 represents the inverse of the matrix, I is the identity matrix, represents the variance of the noise signal vector.

[0039] Assumptions The n1th column is the channel coefficient corresponding to the m1th transmitted signal component. In general, n1=m1. The n1th element of is determined to be the symbol with the shortest Euclidean distance to the element among all the symbols of the modulation constellation, and the determination result is the detection result of the m1th transmitted signal component, that is, e1.

[0040] The kth detection pair e of the serial interference cancellation algorithm k Calculation is performed, and the matrix calculation expression required for the k-th detection is:

[0041]

[0042] in is the calculation result vector of the k-th detection, is the channel matrix composed of the channel coefficients corresponding to the K-k+1 transmitted signal components that were not detected during the k-th detection. is the channel matrix composed of the channel coefficients corresponding to the k-1 transmitted signal components that have been detected at the kth detection.

[0043] is a vector consisting of the detection results of the k-1 transmitted signal components that have been detected at the kth detection. Assume nth k Ranked as mth k The corresponding channel coefficients of the transmitted signal components are nth k The element is judged to be the symbol with the closest Euclidean distance to the element among all the symbols of the modulation constellation, and the judgment result is the mth k The detection result of the transmitted signal component, that is, e k .

[0044] The analog domain matrix calculation circuit based on memristors can only perform calculation operations on real matrices and real vectors. Therefore, the present invention first provides the equivalent real form expressions of formula (1) and formula (2), as well as the equivalent real form of the corresponding decision operation. The equivalent real form expression of formula (1) is:

[0045]

[0046] The field of real numbers (·) T represents transpose, represents the real part of a complex number, Represents the imaginary part of a complex number.

[0047] The n1th element of b1 is judged as the value with the smallest difference from the element among all possible values of the real part of the symbol of the modulation constellation. The judgment result is The n1+Kth element of b1 is determined to be the value with the smallest difference from the imaginary part of the symbol of the modulation constellation. The result of the determination is

[0048] The equivalent real number expression of formula (2) is:

[0049]

[0050] The field of real numbers

[0051] b k nth k The element is judged to be the value with the smallest difference from all possible values of the imaginary part of the symbol of the modulation constellation, and the judgment result is b k nth k The +K-k+1 elements are judged as the value with the smallest difference from the element among all possible values of the imaginary part of the symbol of the modulation constellation. The judgment result is

[0052] The present invention provides a communication system signal receiving method based on memristor, such as Figure 1 As shown, it includes the following steps 1 to 3:

[0053] Step 1: Obtain the received signal vector and channel matrix of the communication system, and obtain the variance value of the noise signal vector of the communication system.

[0054] Step 2: Using the memristor-based analog domain computing circuit provided by the present invention to execute the serial interference cancellation algorithm, specifically including the following steps 2.1 to 2.3:

[0055] Step 2.1: Map the element values of the real-domain channel matrix H and the variance value of the noise signal vector to the conductance value of the memristor in the serial interference cancellation algorithm calculation circuit;

[0056] Step 2.2: Map the real domain received signal vector y into a voltage signal, and input the voltage signal into the voltage input port of the serial interference cancellation algorithm calculation circuit;

[0057] Step 2.3: Measure the output voltage of the serial interference cancellation algorithm calculation circuit to obtain the calculation result.

[0058] Step 3: Output the calculation results.

[0059] Figure 2 This is a schematic diagram of the circuit structure of the memristor-based serial interference elimination algorithm calculation circuit provided by the present invention. The circuit structure of the serial interference elimination algorithm calculation circuit provided by the present invention includes K analog domain matrix calculation modules, K real part decision modules and K imaginary part decision modules, where K is the dimension of the transmitted signal vector. The two output ends of the analog domain matrix calculation module k are respectively connected to the input end of the real part decision module k and the input end of the imaginary part decision module k, k=1,2,...K. For the analog domain matrix calculation module k, the output ends of the real part decision module 1 to the real part decision module k-1 (a total of k-1 real part decision modules) are connected to the input end of the analog domain matrix calculation module k; the output ends of the imaginary part decision module 1 to the imaginary part decision module k-1 (a total of k-1 imaginary part decision modules) are connected to the input end of the analog domain matrix calculation module k. The two output ends of the analog domain matrix calculation module k respectively output the mth k The detection result of the transmitted signal component e k The real part of and the imaginary part The real part decision module k and the imaginary part decision module k respectively make decisions on the output of the analog domain matrix calculation module k and output and The corresponding analog voltage value. Measure the output voltage of the real part decision module k and the imaginary part decision module k to obtain the mth k The detection result of the transmitted signal component e k .

[0060] Figure 3 The circuit structure diagram of the analog domain matrix calculation module 1 of the serial interference elimination algorithm calculation circuit based on the memristor provided by the present invention. The analog domain matrix calculation module 1 is used to calculate b1 based on expression (3) in the analog domain matrix calculation method. Figure 3As shown, the analog domain matrix calculation module 1 includes a first memristor crossbar array, a second memristor crossbar array, a first group of operational amplifiers, a second group of operational amplifiers, a group of voltage input ports, and two voltage output ports. Each row of the first memristor crossbar array corresponds one-to-one to each operational amplifier in the first group of operational amplifiers and is respectively connected to one of the non-inverting inputs or inverting inputs of the corresponding operational amplifier. The input of each operational amplifier in the first group of operational amplifiers that is not connected to the first memristor crossbar array is grounded, and at least one memristor or resistor is connected between the input of the operational amplifier connected to the first memristor crossbar array and the output of the operational amplifier. Each column of the second memristor crossbar array corresponds one-to-one to each operational amplifier in the second group of operational amplifiers and is respectively connected to one of the non-inverting inputs or inverting inputs of the corresponding operational amplifier. The input of each operational amplifier in the second group of operational amplifiers that is not connected to the second memristor crossbar array is grounded, and an inverting amplifier and at least one memristor or resistor are connected between the input of the operational amplifier connected to the second memristor crossbar array and the output of the operational amplifier. Any column of the first memristor crossbar array can be connected to one end of an inverting amplifier, the other end of which is then connected to the output of one of the operational amplifiers in the second group. Any column of the first memristor crossbar array can also be directly connected to the output of one of the operational amplifiers in the second group. Similarly, any row of the second memristor crossbar array can be connected to one end of an inverting amplifier, the other end of which is then connected to the output of one of the operational amplifiers in the first group. Any row of the second memristor crossbar array can also be directly connected to the output of one of the operational amplifiers in the first group. Each row of the first memristor crossbar array corresponds one-to-one to each voltage input port in a group of voltage input ports, and at least one memristor or resistor is connected between each row of the first memristor crossbar array and the corresponding voltage input port. Two voltage output ports are respectively connected to any two columns of the first memristor crossbar array, and the two voltage output ports are respectively connected to the inputs of real part decision module 1 and imaginary part decision module 1.

[0061] Use v in Represents the input voltage vector of the circuit, with v out Represents the vector consisting of the voltage values of each column of the memristor crossbar array connected to the voltage output port, v in With v out satisfy:

[0062]

[0063] Where p1 and p2 are both constants, p1 is the conductance of the resistor or memristor connected to the voltage input port, and p2 is obtained by multiplying the conductance of the cross-resistor or cross-memristor of the operational amplifier in the first group of operational amplifiers and the conductance of the cross-resistor or cross-memristor of the operational amplifier in the second group of operational amplifiers. M1 and M2 are called the equivalent conductance matrices of the first memristor cross array and the second memristor cross array, respectively. The equivalent conductance matrices are obtained by linearly combining the sub-matrices of the conductance matrices of the corresponding memristor cross arrays. Map y to the input voltage vector v in , map H to M1, M2, and Mapped to p2, then v out is the analog voltage value corresponding to b1. Therefore, the analog domain matrix calculation module 1 can calculate the analog domain matrix in the form of and pre-judgment estimate of .

[0064] Figure 4 The schematic diagram of the circuit structure of the analog domain matrix calculation module 2 to the analog domain matrix calculation module K of the memristor-based serial interference elimination algorithm calculation circuit provided by the present invention. The analog domain matrix calculation module k (2≤k≤K) is used to calculate b based on expression (4) in the analog domain matrix calculation method. k .like Figure 5As shown, the analog domain matrix calculation module k includes a first memristor crossbar array, a second memristor crossbar array, a third memristor crossbar array, a first group of operational amplifiers, a second group of operational amplifiers, a first group of voltage input ports, a second group of voltage input ports, and two voltage output ports. Each row of the first memristor crossbar array corresponds one-to-one with each voltage input port in the first group, and at least one memristor or resistor is connected between each row of the first memristor crossbar array and the corresponding voltage input port. Any column of the first memristor crossbar array can be connected to one end of an inverting amplifier, and the other end of the inverting amplifier is then connected to one of the voltage input ports in the second group; any column of the first memristor crossbar array can also be directly connected to one of the voltage input ports in the second group. Each row of the first memristor crossbar array corresponds one-to-one with each row of the second memristor crossbar array and is respectively connected. Each row of the second memristor crossbar array corresponds one-to-one with each operational amplifier in the first group and is respectively connected to one of the non-inverting input or inverting input of the corresponding operational amplifier. The input terminal of each operational amplifier in the first group of operational amplifiers not connected to the second memristor cross array is grounded, and at least one memristor or resistor is connected between the input terminal of the operational amplifier connected to the second memristor cross array and the output terminal of the operational amplifier. Each column of the third memristor cross array corresponds one-to-one to each operational amplifier in the second group of operational amplifiers and is respectively connected to one of the non-inverting input terminal or the inverting input terminal of the corresponding operational amplifier. The input terminal of each operational amplifier in the second group of operational amplifiers not connected to the third memristor cross array is grounded, and an inverting amplifier and at least one memristor or resistor are connected between the input terminal of the operational amplifier connected to the third memristor cross array and the output terminal of the operational amplifier. Any column of the second memristor cross array can be connected to one end of an inverting amplifier, and the other end of the inverting amplifier is then connected to the output terminal of an operational amplifier in the second group of operational amplifiers; any column of the second memristor cross array can also be directly connected to the output terminal of an operational amplifier in the second group of operational amplifiers. Any row of the third memristor crossbar array can be connected to one end of an inverting amplifier, the other end of which is then connected to the output of one of the operational amplifiers in the first group. Any row of the third memristor crossbar array can also be directly connected to the output of one of the operational amplifiers in the first group. Each voltage input port in the second group of voltage input ports is also connected to the outputs of the first k-1 real part decision modules and the first k-1 imaginary part decision modules, respectively. The two voltage output ports are each connected to any two columns of the second memristor crossbar array and are also connected to the inputs of real part decision module k and imaginary part decision module k, respectively.

[0065] Use v in1 Represents the input voltage vector of the first group of voltage input ports, with vin2 Indicates the input voltage vector of the second set of voltage input ports, with v out The vectors representing the voltage values of each column of the memristor crossbar array connected to the voltage output port are:

[0066]

[0067] Where p1 and p2 are both constants, p1 is the conductance of the resistor or memristor connected to the voltage input port, and p2 is obtained by multiplying the conductance of the cross-resistor or cross-memristor of the operational amplifier in the first group of operational amplifiers and the conductance of the cross-resistor or cross-memristor of the operational amplifier in the second group of operational amplifiers. M1, M2, and M3 are respectively called the equivalent conductance matrices of the first memristor cross array, the second memristor cross array, and the third memristor cross array. The equivalent conductance matrices are obtained by linearly combining the sub-matrices of the conductance matrices of the corresponding memristor cross arrays. Since each voltage input port in the second group of voltage input ports is connected to the output of the first k-1 real part decision modules and the first k-1 imaginary part decision modules, e (k-1) has been mapped to v in2 , map y to p1v in1 , G (k) Map to M2, M3, Map to p2, H (k-1) Mapped to M1, then v out for b k The corresponding analog voltage value, so the analog domain matrix calculation module k can be calculated in the analog domain matrix calculation way and pre-judgment estimate of .

[0068] Figure 5 This is a schematic diagram of the first circuit structure of the real part decision module and the imaginary part decision module of the memristor-based serial interference elimination algorithm calculation circuit provided by the present invention. Figure 5 The illustrated real part decision module or imaginary part decision module includes: a voltage input port, a voltage output port, a first voltage supply module, a second voltage supply module, a multi-way switch, and at least one voltage comparator. One of the non-inverting input and inverting input of each voltage comparator is connected to the voltage input port, and the other input is connected to the second voltage supply module. The output of the voltage comparator is directly connected to the selection control signal input of the multi-way switch. The output of the multi-way switch is connected to the voltage output port of the imaginary part decision module or the real part decision module. The first voltage supply module is connected to at least two of the input channels of the multi-way switch to provide the multi-way switch with voltages corresponding to all possible decision results. The second voltage supply module provides each voltage comparator with a voltage corresponding to a decision threshold.

[0069] Let W be the number of voltage comparators. If the module is a real part determination module, W can be the number of possible values of the real part of the modulation constellation symbol minus one; if the module is an imaginary part determination module, W can be the number of possible values of the imaginary part of the modulation constellation symbol minus one. The function of the real (or imaginary) part determination module is to determine the module's input voltage as the value with the smallest difference from the input value among all possible values of the real (or imaginary) part of the modulation constellation symbol. The real (or imaginary) part has W+1 possible values, so it is necessary to determine the relative magnitude relationship between the module's input voltage and W different threshold voltages. Figure 5 In the circuit shown, the second voltage providing module provides W different threshold voltages for W voltage comparators. The outputs of the W voltage comparators form a W-dimensional Boolean control vector. When the module input voltage takes different values, the Boolean vector has a total of W+1 possible values, thereby controlling the multi-way switch to output one of the voltage values of the W+1 input channels. The first voltage providing module applies the voltage corresponding to the mapping decision result to these W+1 input channels. Figure 5 The real part (or imaginary part) decision module shown can realize the required decision function.

[0070] Figure 6 This is a second circuit structure diagram of the real part decision module and the imaginary part decision module of the memristor-based serial interference elimination algorithm calculation circuit provided by the present invention. Figure 6 The illustrated real part decision module or imaginary part decision module includes: a voltage input port, a voltage output port, a first voltage supply module, a second voltage supply module, a combinational logic circuit, a multi-way switch, and at least one voltage comparator. One of the non-inverting input and inverting input of each voltage comparator is connected to the voltage input port, and the other input is connected to the second voltage supply module. The output of the voltage comparator is connected to the selection control signal input of the multi-way switch after passing through the combinational logic circuit. The output of the multi-way switch is connected to the voltage output port of the imaginary part decision module or the real part decision module. The first voltage supply module is connected to at least two of the input channels of the multi-way switch to provide the multi-way switch with voltages corresponding to all possible decision results. The second voltage supply module provides each voltage comparator with a voltage corresponding to a decision threshold.

[0071] Figure 6In the circuit shown, the second voltage supply module applies W different threshold voltages to W voltage comparators. The outputs of the W voltage comparators then form a W-dimensional Boolean control vector with W+1 possible values. The combinational logic circuit can change the dimension of the control vector. Assuming the output of the combinational logic circuit is a W'-dimensional Boolean vector, this vector can also control the multiplexer to output one of the voltage values of its W+1 input channels. The first voltage supply module applies the voltage corresponding to the mapping decision result to these W+1 input channels. Figure 6 The real part (or imaginary part) decision module shown can realize the required decision function.

[0072] Figure 7 This is a schematic diagram of the structure of the serial interference elimination algorithm calculation device based on memristor provided by the present invention. Figure 7 As shown, the computing device includes: a memristor programming module, a memristor-based serial interference elimination algorithm computing circuit provided by the present invention, and a voltage measurement module.

[0073] The functions of each module are as follows: the memristor programming module programs and modifies the conductance value of the memristor in the memristor-based serial interference cancellation algorithm calculation circuit provided by the present invention according to the variance value of the channel matrix and the noise signal vector, and maps the element values of the real domain channel matrix and the variance of the noise signal vector to the conductance value of the memristor in the analog domain matrix calculation module according to the equivalent real number form of the matrix calculation performed by detecting the transmitted signal vector; the memristor-based serial interference cancellation algorithm calculation circuit is used to implement the calculation of the serial interference cancellation algorithm. To complete the calculation, the analog voltage corresponding to the real domain received signal vector needs to be input as the input voltage to a group of voltage input ports of the analog domain matrix calculation module 1 and the first group of voltage input ports of the analog domain matrix calculation module k (2≤k≤K); the voltage measurement module is used to measure the output voltage vector of the serial interference cancellation algorithm calculation circuit, which corresponds to the detection result of the transmitted signal vector calculated by the serial interference cancellation algorithm. The voltage measurement module can be an analog to digital converter (ADC) or a high-precision voltage measurement chip or other device.

[0074] Figure 8 This is a schematic diagram of the first structure of the signal receiving device based on memristor provided by the present invention. Figure 8As shown, the signal receiving device includes: an antenna, a first radio frequency filter, a low noise amplifier, a second radio frequency filter, a mixer, a local oscillator, an intermediate frequency filter, an intermediate frequency amplifier, a demodulator, an analog-to-digital converter, a voltage supply module, a channel estimation module, and a computing device for a serial interference cancellation algorithm based on a memristor implemented in the present invention. The output of the local oscillator is connected to the input of the mixer; the antenna, the first radio frequency filter, the low noise amplifier, the second radio frequency filter, the mixer, the intermediate frequency filter, the intermediate frequency amplifier, the demodulator, and the analog-to-digital converter are connected in sequence; the output of the analog-to-digital converter is connected to the input of the voltage supply module and the input of the channel estimation module; the output of the channel estimation module is connected to the input of the computing device for a serial interference cancellation algorithm based on a memristor; the output of the voltage supply module is connected to the input of the computing device for a serial interference cancellation algorithm based on a memristor; and the computing device for a serial interference cancellation algorithm based on a memristor outputs a detection result.

[0075] The functions of each module are as follows: the antenna, the first RF filter, the low-noise amplifier, the second RF filter, the mixer, the intermediate frequency filter, and the intermediate frequency amplifier convert the RF signal received by the antenna into an intermediate frequency signal; the demodulator converts the intermediate frequency signal into a baseband receiving signal in the form of an analog signal; the analog-to-digital converter converts the baseband receiving signal in the form of an analog signal into a baseband receiving signal in the form of a digital signal; the channel estimation module estimates the channel based on the baseband receiving signal, and provides the estimated channel matrix to the serial interference elimination algorithm calculation device based on the memristor; the voltage providing module converts the baseband receiving signal in the form of a digital signal into a corresponding voltage vector and provides it to the serial interference elimination algorithm calculation device based on the memristor. The voltage providing module can be a digital-to-analog converter (DAC) or an adjustable voltage source or other device; the serial interference elimination algorithm calculation device based on the memristor calculates and outputs the signal detection result.

[0076] Figure 9 This is a second structural diagram of the signal receiving device based on memristor provided by the present invention. Figure 9As shown, the signal receiving device includes: an antenna, a first radio frequency filter, a low noise amplifier, a second radio frequency filter, a mixer, a local oscillator, an intermediate frequency filter, an intermediate frequency amplifier, a sample-and-hold circuit, a channel estimation module, and the memristor-based serial interference cancellation algorithm calculation device provided by the present invention. The output of the local oscillator is connected to the input of the mixer; the antenna, the first radio frequency filter, the low noise amplifier, the second radio frequency filter, the mixer, the intermediate frequency filter, the intermediate frequency amplifier, and the sample-and-hold circuit are connected in sequence; the output of the sample-and-hold circuit is connected to the input of the channel estimation module and the input of the memristor-based serial interference cancellation algorithm calculation device; the output of the channel estimation module is connected to the input of the memristor-based serial interference cancellation algorithm calculation device; and the memristor-based serial interference cancellation algorithm calculation device outputs a detection result.

[0077] The functions of each module are as follows: the antenna, the first RF filter, the low-noise amplifier, the second RF filter, the mixer, the intermediate frequency filter, and the intermediate frequency amplifier convert the RF signal received by the antenna into an intermediate frequency signal; the sampling and holding circuit converts the intermediate frequency signal into a baseband reception signal in the form of an analog signal, and provides the baseband reception signal in the form of an analog signal as an input voltage vector to the serial interference cancellation algorithm calculation device based on the memristor; the channel estimation module estimates the channel based on the baseband reception signal, and provides the estimated channel matrix to the serial interference cancellation algorithm calculation device based on the memristor; the serial interference cancellation algorithm calculation device based on the memristor calculates and outputs the detection result.

[0078] Figure 10 This is a schematic diagram of the third structure of the signal receiving device based on memristor provided by the present invention. Figure 10 As shown, the signal receiving device includes: an antenna, a first radio frequency filter, a low noise amplifier, a second radio frequency filter, a mixer, a local oscillator, an intermediate frequency filter, an intermediate frequency amplifier, a demodulator, a channel estimation module, and the memristor-based serial interference cancellation algorithm calculation device provided by the present invention. The output end of the local oscillator is connected to the input end of the mixer; the antenna, the first radio frequency filter, the low noise amplifier, the second radio frequency filter, the mixer, the intermediate frequency filter, the intermediate frequency amplifier, and the demodulator are connected in sequence; the output end of the demodulator is connected to the input end of the channel estimation module and the input end of the memristor-based serial interference cancellation algorithm calculation device; the output end of the channel estimation module is connected to the input end of the memristor-based serial interference cancellation algorithm calculation device; and the memristor-based serial interference cancellation algorithm calculation device outputs a detection result.

[0079] The functions of each module are as follows: the antenna, the first RF filter, the low-noise amplifier, the second RF filter, the mixer, the intermediate frequency filter, and the intermediate frequency amplifier convert the RF signal received by the antenna into an intermediate frequency signal; the demodulator converts the intermediate frequency signal into a baseband reception signal in the form of an analog signal, and provides the baseband reception signal in the form of an analog signal as an input voltage vector to the serial interference cancellation algorithm calculation device based on the memristor; the channel estimation module estimates the channel based on the baseband reception signal, and provides the estimated channel matrix to the serial interference cancellation algorithm calculation device based on the memristor; the serial interference cancellation algorithm calculation device based on the memristor calculates and outputs the detection result.

[0080] In general, various example embodiments of the present disclosure may be implemented in hardware or dedicated circuitry, software, firmware, logic, or any combination thereof. Certain aspects may be implemented in hardware, while other aspects may be implemented in firmware or software executed by a controller, microprocessor, or other computing device. When various aspects of the embodiments of the present disclosure are illustrated or described as block diagrams, flow charts, or using some other graphical representation, it will be understood that the blocks, devices, systems, techniques, or methods described herein may be implemented, as non-limiting examples, in hardware, software, firmware, dedicated circuitry or logic, general-purpose hardware or a controller or other computing device, or some combination thereof.

[0081] Except for the technical features described in the specification, all other technical features are known to those skilled in the art. The present invention omits descriptions of well-known components and well-known technologies to avoid redundancy and unnecessary limitation of the present invention. The implementation methods described in the above embodiments do not represent all implementation methods consistent with the present application. Based on the technical solution of the present invention, various modifications or variations that can be made by those skilled in the art without creative effort are still within the scope of protection of the present invention.

Claims

1. A communication system signal receiving method based on memristor, characterized in that: The method includes: Step 1: Obtain the received signal vector and channel matrix of the communication system, and obtain the variance value of the noise signal vector of the communication system; Step 2: Using a memristor-based analog domain computing circuit to execute the serial interference cancellation algorithm, the method includes: first, mapping the element values of the real domain channel matrix and the variance value of the noise signal vector to the conductance value of the memristor in the serial interference cancellation algorithm computing circuit; then, mapping the real domain received signal vector to a voltage signal, and inputting the voltage signal to the voltage input port of the serial interference cancellation algorithm computing circuit; and finally, measuring the output voltage of the serial interference cancellation algorithm computing circuit to obtain a calculation result. Step 3: Output the calculation results.

2. An analog domain computing circuit based on a serial interference cancellation algorithm of a memristor, used in the signal receiving method according to claim 1, characterized in that: The invention comprises K analog domain matrix calculation modules, K real part decision modules and K imaginary part decision modules, where K is the dimension of the transmitted signal vector; wherein the two output ends of the analog domain matrix calculation module k are respectively connected to the input end of the real part decision module k and the input end of the imaginary part decision module k, k=1,2,...K; the output ends of the real part decision module 1 to the real part decision module k-1 and the output ends of the imaginary part decision module 1 to the imaginary part decision module k-1 are all connected to the input end of the analog domain matrix calculation module k; the real domain received signal vector y is mapped into a voltage signal and input to the voltage input ports of the K analog domain matrix calculation modules of the analog domain calculation circuit; it is assumed that the kth iteration in the serial interference elimination algorithm is used to detect the mth k The transmitted signal components, the detection result is e k ; The analog domain matrix calculation module is implemented based on a memristor cross array; according to the detection of the mth k The equivalent real form of the matrix calculation required for the transmitted signal component is used to map the element values of the real domain channel matrix and the variance of the noise signal vector to the conductance value of the memristor in the analog domain matrix calculation module k. The two output terminals of the analog domain matrix calculation module k respectively output the mth k The detection result of the transmitted signal component e k The real part of and the imaginary part pre-judgment estimate of The real part decision module k and the imaginary part decision module k respectively make decisions on the output of the analog domain matrix calculation module k, and output and The corresponding analog voltage value; measure the output voltage of the real part decision module k and the imaginary part decision module k, and obtain the mth k The detection result of the transmitted signal component e k .

3. The circuit according to claim 2, characterized in that In the analog domain calculation circuit of the serial interference elimination algorithm, the circuit structure of the analog domain matrix calculation module 1 is set as follows: the circuit includes a first memristor cross array, a second memristor cross array, a first group of operational amplifiers, a second group of operational amplifiers, a group of voltage input ports and two voltage output ports; each row of the first memristor cross array corresponds one-to-one to each operational amplifier in the first group of operational amplifiers, and is respectively connected to one of the non-inverting input terminals or the inverting input terminals of the corresponding operational amplifier; the input terminal of each operational amplifier in the first group of operational amplifiers that is not connected to the first memristor cross array is grounded, and at least one memristor or resistor is connected between the input terminal of the operational amplifier connected to the first memristor cross array and the output terminal of the operational amplifier; each column of the second memristor cross array corresponds one-to-one to each operational amplifier in the second group of operational amplifiers, and is respectively connected to one of the non-inverting input terminals or the inverting input terminals of the corresponding operational amplifier; each operational amplifier in the second group of operational amplifiers The input end of the operational amplifier that is not connected to the second memristor cross array is grounded, and an inverting amplifier and at least one memristor or resistor are connected between the input end of the operational amplifier connected to the second memristor cross array and the output end of the operational amplifier; any column of the first memristor cross array is connected to the output end of an operational amplifier in the second group of operational amplifiers through an inverting amplifier or directly; any row of the second memristor cross array is connected to the output end of an operational amplifier in the first group of operational amplifiers through an inverting amplifier or directly; each row of the first memristor cross array corresponds one-to-one to each voltage input port in a group of voltage input ports, and at least one memristor or resistor is connected between each row of the first memristor cross array and the corresponding voltage input port; the two voltage output ports are respectively connected to any two columns of the first memristor cross array, and the two voltage output ports are respectively connected to the input ends of the real part judgment module 1 and the imaginary part judgment module 1.

4. The circuit according to claim 3, characterized in that In the analog domain matrix calculation module 1, the equivalent conductance matrices of the first memristor cross array and the second memristor cross array are respectively M1 and M2, and v in Represents the input voltage vector of the circuit, with v out represents the vector of voltage values of each column of the memristor crossbar array connected to the voltage output port, then v in With v out satisfy: Among them, p1 and p2 are constants, p1 is the conductance of the resistor or memristor connected to the voltage input port, and the variance of the noise signal vector is Mapped to p2, where p2 is obtained by multiplying the cross-resistance of the operational amplifiers in the first group of operational amplifiers or the conductance of the cross-resistor and the cross-resistance of the operational amplifiers in the second group of operational amplifiers; (·) T represents transpose; I is the identity matrix; let the channel matrix be The real domain form is H, and H is mapped to M1 and M2; let the received signal vector in the real domain form be y, and map y to the input voltage vector v in ; At this time, the output voltage vector v out The analog voltage value vector corresponding to the calculation result of the matrix calculation performed for detecting the m1-th transmitted signal component.

5. The circuit according to claim 2, characterized in that In the analog domain calculation circuit of the serial interference elimination algorithm, the circuit structure of the analog domain matrix calculation module k (2≤k≤K) is set as follows: the circuit includes a first memristor cross array, a second memristor cross array, a third memristor cross array, a first group of operational amplifiers, a second group of operational amplifiers, a first group of voltage input ports, a second group of voltage input ports and two voltage output ports; each row of the first memristor cross array corresponds to each voltage input port in the first group of voltage input ports, and at least one memristor or resistor is connected between each row of the first memristor cross array and the corresponding voltage input port; any column of the first memristor cross array is connected to one end of an inverting amplifier, and then the other end of the inverting amplifier is connected to the inverting amplifier. One end is connected to one of the voltage input ports of the second group of voltage input ports; or any column of the first memristor cross array can also be directly connected to one of the voltage input ports of the second group; each row of the first memristor cross array corresponds to each row of the second memristor cross array and is respectively connected; each row of the second memristor cross array corresponds to each operational amplifier in the first group of operational amplifiers, and is respectively connected to one of the in-phase input terminal or the inverting input terminal of the corresponding operational amplifier; the input terminal of each operational amplifier in the first group of operational amplifiers that is not connected to the second memristor cross array is grounded, and at least one is connected between the input terminal of the operational amplifier connected to the second memristor cross array and the output terminal of the operational amplifier memristor or resistor; each column of the third memristor cross array corresponds to each operational amplifier in the second group of operational amplifiers, and is respectively connected to one of the non-inverting input terminal or the inverting input terminal of the corresponding operational amplifier; the input terminal of each operational amplifier in the second group of operational amplifiers that is not connected to the third memristor cross array is grounded, and an inverting amplifier and at least one memristor or resistor are connected between the input terminal of the operational amplifier connected to the third memristor cross array and the output terminal of the operational amplifier; any column of the second memristor cross array is connected to one end of an inverting amplifier, and then the other end of the inverting amplifier is connected to the output terminal of one of the operational amplifiers in the second group of operational amplifiers; or any column of the second memristor cross array is directly connected The output end of one of the operational amplifiers in the second group of operational amplifiers; any row of the third memristor cross array is connected to one end of an inverting amplifier, and then the other end of the inverting amplifier is connected to the output end of one of the operational amplifiers in the first group of operational amplifiers; or any row of the third memristor cross array is directly connected to the output end of one of the operational amplifiers in the first group of operational amplifiers; each voltage input port in the second group of voltage input ports is also respectively connected to the output ends of the first k-1 real part decision modules and the first k-1 imaginary part decision modules; the two voltage output ports are respectively connected to any two columns of the second memristor cross array, and at the same time, the two voltage output ports are respectively connected to the input ends of the real part decision module k and the imaginary part decision module k.

6. The circuit according to claim 5, characterized in that In the analog domain matrix calculation module k (2≤k≤K), the equivalent conductance matrices of the first memristor cross array, the second memristor cross array and the third memristor cross array are respectively M1, M2 and M3, and v in1 Represents the input voltage vector of the first group of voltage input ports, with v in2 Indicates the input voltage vector of the second set of voltage input ports, with v out represents the vector of voltage values of each column of the memristor crossbar array connected to the voltage output port, then Where p1 and p2 are constants, p1 is the conductance of the resistor or memristor connected to the voltage input port, and the variance of the noise signal vector is Map to p2, p2 is obtained by multiplying the cross-resistance of the operational amplifier in the first group of operational amplifiers or the conductance of the cross-resistance of the memristor and the cross-resistance of the operational amplifier in the second group of operational amplifiers or the conductance of the memristor; map y to p1v in1 ;set up is the channel matrix composed of the channel coefficients corresponding to the K-k+1 transmitted signal components that were not detected during the k-th detection. The real number field form is G (k) , G (k) Map to M2, M3; is the channel matrix composed of the channel coefficients corresponding to the k-1 transmitted signal components that have been detected at the kth detection. The real number field form is H (k-1) , H (k-1) Mapped to M1; at this time the output voltage vector v out To detect the mth k The analog voltage value vector corresponds to the calculation result of the matrix calculation performed on the transmitted signal components.

7. The circuit according to claim 2, characterized in that A circuit structure of the imaginary part judgment module and the real part judgment module is as follows: the circuit includes a voltage input port, a voltage output port, a first voltage supply module, a second voltage supply module, a multi-way switch and at least one voltage comparator; one of the non-inverting input terminal and the inverting input terminal of each voltage comparator is connected to the voltage input port, and the other input terminal is connected to the second voltage supply module; the output terminal of the voltage comparator is directly connected to the selection control signal input terminal of the multi-way switch, or is connected to the selection control signal input terminal of the multi-way switch through a combinational logic circuit; the output terminal of the multi-way switch is connected to the voltage output port of the imaginary part judgment module or the real part judgment module; the first voltage supply module is connected to at least two input channels of the input channels of the multi-way switch to provide the multi-way switch with voltages corresponding to all possible judgment results, and the second voltage supply module provides each voltage comparator with a voltage corresponding to a judgment threshold.

8. A memristor-based serial interference cancellation algorithm computing device, characterized in that: The device includes a memristor programming module, an analog domain computing circuit of a serial interference cancellation algorithm based on a memristor as described in any one of claims 2 to 7, and a voltage measurement module; the memristor programming module programs and modifies the conductance value of the memristor in the analog domain computing circuit of the serial interference cancellation algorithm, and maps the element values of the real domain channel matrix and the variance of the noise signal vector to the conductance value of the memristor in the analog domain matrix computing module according to the equivalent real number form of the matrix calculation performed for detecting the transmitted signal vector; the analog domain computing circuit of the serial interference cancellation algorithm inputs the analog voltage corresponding to the real domain received signal vector as the input voltage to a group of voltage input ports of the analog domain matrix computing module 1 and the first group of voltage input ports of the analog domain matrix computing module k (2≤k≤K), thereby implementing the calculation process of the serial interference cancellation algorithm; the voltage measurement module is used to measure the output voltage vector of the analog domain computing circuit of the serial interference cancellation algorithm, where the output voltage vector corresponds to the detection result of the transmitted signal vector calculated by the serial interference cancellation algorithm.

9. A communication system signal receiving device based on a memristor, characterized in that: The device includes an antenna, a first radio frequency filter, a low noise amplifier, a second radio frequency filter, a mixer, a local oscillator, an intermediate frequency filter, an intermediate frequency amplifier, a demodulator, an analog-to-digital converter, a voltage supply module, a channel estimation module, and a computing device for a serial interference cancellation algorithm based on a memristor as claimed in claim 8; an output end of the local oscillator is connected to an input end of the mixer; The antenna, the first radio frequency filter, the low noise amplifier, the second radio frequency filter, the mixer, the intermediate frequency filter, and the intermediate frequency amplifier are connected in sequence to convert the radio frequency signal received by the antenna into an intermediate frequency signal; the output end of the intermediate frequency amplifier is connected to the input end of the demodulator, and the demodulator converts the intermediate frequency signal into a baseband received signal in the form of an analog signal; the output end of the demodulator is connected to the input end of the analog-to-digital converter, and the analog-to-digital converter converts the baseband received signal in the form of an analog signal into a baseband received signal in the form of a digital signal; The output end of the analog-to-digital converter is connected to the input end of the voltage providing module and is also connected to the input end of the channel estimation module; The channel estimation module estimates the channel based on the baseband received signal and outputs the channel matrix to the serial interference cancellation algorithm calculation device; the voltage providing module converts the baseband received signal in the form of a digital signal into a corresponding voltage vector and provides it to the serial interference cancellation algorithm calculation device; the serial interference cancellation algorithm calculation device outputs the detection result of the transmitted signal vector.

10. A communication system signal receiving device based on a memristor, characterized in that: The device includes an antenna, a first radio frequency filter, a low-noise amplifier, a second radio frequency filter, a mixer, a local oscillator, an intermediate frequency filter, an intermediate frequency amplifier, a sampling and holding circuit, a channel estimation module, and a computing device for a serial interference cancellation algorithm based on a memristor as claimed in claim 8; the output end of the local oscillator is connected to the input end of the mixer; the antenna, the first radio frequency filter, the low-noise amplifier, the second radio frequency filter, the mixer, the intermediate frequency filter, and the intermediate frequency amplifier are connected in sequence to convert a radio frequency signal received by the antenna into an intermediate frequency signal; the output end of the intermediate frequency amplifier is connected to the input end of the sampling and holding circuit, which converts the intermediate frequency signal into a baseband received signal in the form of an analog signal; the output end of the sampling and holding circuit is connected to the input end of the channel estimation module, which estimates a channel based on the baseband received signal and outputs a channel matrix to the computing device for the serial interference cancellation algorithm; the output end of the sampling and holding circuit is also connected to the input end of the computing device for the serial interference cancellation algorithm, and provides the baseband received signal in the form of an analog signal as an input voltage vector to the computing device for the serial interference cancellation algorithm based on the memristor; the computing device for the serial interference cancellation algorithm based on the memristor outputs a detection result of a transmitted signal vector.

11. A communication system signal receiving device based on a memristor, characterized in that: The device includes an antenna, a first radio frequency filter, a low noise amplifier, a second radio frequency filter, a mixer, a local oscillator, an intermediate frequency filter, an intermediate frequency amplifier, a demodulator, a channel estimation module, and a computing device for a serial interference cancellation algorithm based on a memristor as claimed in claim 8; an output end of the local oscillator is connected to an input end of the mixer; The antenna, the first radio frequency filter, the low noise amplifier, the second radio frequency filter, the mixer, the intermediate frequency filter, and the intermediate frequency amplifier are connected in sequence to convert the radio frequency signal received by the antenna into an intermediate frequency signal; the output end of the intermediate frequency amplifier is connected to the input end of the demodulator, and the demodulator converts the intermediate frequency signal into a baseband received signal in the form of an analog signal; The output end of the demodulator is connected to the input end of the channel estimation module, which estimates the channel based on the baseband received signal and outputs the channel matrix to the serial interference cancellation algorithm calculation device; The output end of the demodulator is also connected to the input end of the serial interference cancellation algorithm calculation device, and the baseband received signal in the form of an analog signal is provided as an input voltage vector to the calculation device of the serial interference cancellation algorithm; The calculation device of the serial interference cancellation algorithm outputs the detection result of the transmission signal vector.

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