Phased-array antenna unit phase shifting method and system based on FPGA and electronic equipment

Abstract

A phased-array antenna unit phase shift method and system based on an FPGA, and an electronic device, the method comprising: receiving a protocol data packet issued by an upper computer, and performing escape processing on protocol data; decoding and analyzing the protocol data packet after escape, dividing the analyzed data into initial phase value data and configuration parameter data, and storing the initial phase value data and the configuration parameter data; calculating the phase shift value of each phased array unit by using the initial phase value data and the configuration parameter data, and outputting a phase calculation completion mark after the calculation is completed; mapping the matrix phase transplantation according to the phase calculation completion mark, and distributing and subpackaging the multi-channel FIFO data; receiving the mapped multi-channel phase shift value data packet, and then outputting data according to synchronous serial port sequential logic to complete external multifunctional chip phase shift configuration; and the external multifunctional chip completes the control of the antenna beam by receiving the phase shift values of different channels configured by the serial port. According to the invention, the problem that the real-time performance and the accuracy of phase shifting of the phased array unit are not enough is solved.

Description

Technical Field

[0001] The present invention relates to the field of wireless communication technology, and more particularly to a FPGA-based phase-shifting method, system, and electronic equipment for a phased array antenna unit. Background Art

[0002] In many fields such as wireless communications, satellite Internet, radar systems, and electronic warfare, the phase-shifting system of phased array antennas can quickly complete beamforming control and accurately shift the phase of the array units to the specified direction, playing a very important role in the search, tracking, and monitoring of targets.

[0003] Current phased array antenna phase-shifting systems face three core challenges: First, in dynamic multi-target scenarios, both beamforming accuracy and real-time response must be balanced, and traditional systems struggle to meet microsecond-level delay control requirements; second, the coordinated suppression of phase quantization error and multipath interference places higher demands on algorithm robustness; and third, the exponential growth in the complexity of multi-dimensional parameter optimization brought about by large-scale arrays, such as those with more than 1024 elements.

[0004] With the emergence and rapid development of FPGA, its parallel pipeline processing method gives it ultra-fast data processing speed and performance; its flexible reprogrammability greatly improves the feasibility of repeated algorithm verification; and its rich logic resources including LUT, RAM, DSP, etc. provide logical support for the implementation of complex algorithms.

[0005] To address the technical challenges of phased array antenna phase-shifting systems in terms of real-time beam steering, phase precision control, and multi-channel synchronization, FPGA-based digital phase-shifting system architectures have become the industry's mainstream solution. Leveraging the highly parallel processing capabilities and flexible digital signal processing characteristics of programmable logic devices (PLDs), this solution effectively enables rapid phase calculation, dynamic beamforming, and real-time system-level configuration for large-scale array antennas. However, addressing phase shifting in phased array elements still presents technical limitations in terms of real-time performance and accuracy. Summary of the Invention

[0006] The present invention aims to overcome at least one defect (shortcoming) of the above-mentioned prior art and provide a FPGA-based phased array antenna unit phase shifting method and system for solving the problem of insufficient real-time and precision technology of phase shifting of phased array units.

[0007] The technical solution adopted by the present invention is a phase shifting method of a phased array antenna unit based on FPGA, the method comprising the following steps:

[0008] S1: Receives the protocol data packet sent by the host computer and performs escape processing on the protocol data;

[0009] S2: Decode and parse the escaped protocol data packet, divide the parsed data into initial phase value data and configuration parameter data, and store them;

[0010] S3: Calculate the phase shift value of each phased array unit using the initial phase value data and configuration parameter data, and output a phase calculation completion flag after the calculation is completed;

[0011] S4: Mapping the matrix phase transplantation and allocating and packaging the multi-channel FIFO data according to the phase calculation completion flag;

[0012] S5: Receive the multi-channel phase shift value data packet after mapping, and then output the data according to the synchronous serial port timing logic to complete the phase shift configuration of the external multi-function chip;

[0013] S6: The external multi-function chip controls the antenna beam by receiving the phase shift values of different channels configured through the serial port.

[0014] In this application, by first receiving the protocol data packet sent by the host computer and performing escape processing, and then decoding and parsing the protocol data, the accurate transmission and timely processing of the data can be ensured. After the data is parsed, the initial phase value data and the configuration parameter data are effectively separated and stored in the FPGA, providing the necessary basis for the subsequent phase shift value calculation. In addition, the parallel processing capability of the FPGA is used to ensure that in a large-scale phased array system, the phase shift calculation of each antenna unit can be completed quickly, reducing the delay in the traditional method. At the same time, by parsing the initial phase value and configuration parameter data obtained, the phase shift value of each phased array unit can be accurately calculated. After the calculation is completed, the phase calculation completion flag is output to ensure that the system can accurately synchronize when performing subsequent operations, avoiding data errors or calculation delays. In addition, the present application also uses mapping processing and multi-channel FIFO data distribution and subpackaging to efficiently transfer the phase shift value data to the target antenna unit, ensuring that each antenna unit obtains the correct control data. By outputting data through the synchronous serial port timing logic, it is possible to achieve precise control and distribution of multi-channel phase shift value data, so that the phase shift configuration of each channel can be accurately completed. It also collaborates with external multi-function chips to ensure precise adjustment of the antenna beam, improving the system's adaptability and stability in dynamic environments. Therefore, the method described in this application leverages the high parallelism and flexibility of FPGAs to handle complex control tasks, offering high scalability and reliability. It can adapt to phased array antenna systems of varying sizes and is compatible and collaborative with a variety of external devices, meeting a wider range of application needs.

[0015] Preferably, the step S4 includes:

[0016] S41: Using the received phase calculation completion flag as a mapping process trigger start signal;

[0017] S42: Mapping the phase shift value to a true value using a phase shift value mapping table;

[0018] S43: reallocating the phase shift value matrix through the matrix physical position mapping table;

[0019] S44: Packetize the phase shift values for different channels.

[0020] In the present application, by using the received phase calculation completion flag as the trigger start signal for mapping processing, it is ensured that the mapping process starts immediately after the phase calculation is completed, effectively avoiding errors caused by data delay or synchronization problems, and improving the collaborative work efficiency between various links in the system during the processing process. The phase shift value mapping table is also used for true value mapping, so that the phase shift value data can be accurately mapped to the corresponding antenna unit. After the mapping is completed, the phase shift value matrix is reallocated through the matrix physical position mapping table, so that the phase shift value of each antenna unit can be optimized and allocated according to its actual physical position, ensuring that the phase shift operation of each antenna unit in the physical array matches its actual position, further improving the control accuracy of the antenna beam, and subpackaging the phase shift value for different channels, so that the phase shift configuration data of each channel can be independently processed and accurately transmitted to each channel, optimizing the transmission efficiency of multi-channel data, reducing data congestion and transmission delay, and improving the processing capability and stability of the system.

[0021] Preferably, in step S42, the phase shift value mapping relationship in the phase shift value mapping table is generated by generating a .vh file and then calling the .vh file using include, or by editing and assigning values using task or function.

[0022] In this step, by generating a phase-shift mapping table using a .vh file and calling it through include, or by editing and assigning values using a task or function, the system's flexibility and maintainability are significantly improved. This approach makes the phase-shift mapping table more efficient to manage and facilitates subsequent modification and expansion. It also simplifies the code structure, reduces redundancy, and improves code reusability. This approach allows the system to flexibly respond to changing requirements, improves development and debugging efficiency, and ensures the accuracy and consistency of the phase-shift mapping.

[0023] Preferably, in the matrix physical position mapping table in step S43, different SPI serial ports and multi-function chips are mapped and assigned to positions in the matrix, thereby allocating the values of the phase matrix to corresponding SPI channels.

[0024] By using the matrix physical location mapping table to map different SPI serial ports and multifunction chips to different positions on the matrix, the phase matrix values can be effectively and accurately assigned to the corresponding SPI channels, optimizing system resource allocation and management, and improving the efficiency and accuracy of data transmission. Furthermore, the matrix's physical location mapping enables the system to more flexibly respond to different hardware configurations and changing requirements, enhancing system scalability and compatibility, helping to reduce hardware resource conflicts and redundancy, and ensuring efficient and stable performance.

[0025] Preferably, in step S44, the data output form of the phase shift value packetization for different channels adopts a FIFO interface form, and the packetization includes: setting the channel switch package as the chip address + channel register address + channel switch form according to the SPI control timing and storing it in the FIFO, and then setting the phase shift value package as the chip address + configuration register address + phase shift value form and storing it in the FIFO; wherein, the FIFO storing the switch package and the FIFO storing the phase shift value package can be set to the same FIFO or separated into two FIFOs for storage according to needs.

[0026] By using a FIFO interface to package phase-shift values, data output from different channels can be efficiently managed. Packaging the channel switches into a format of chip address + channel register address + channel switch, and packaging the phase-shift values into a format of chip address + configuration register address + phase-shift value, and storing them in the FIFO ensures that data is transmitted in a precise order and format, avoiding data conflicts and errors. Furthermore, separate FIFOs for storing switch data packets and phase-shift value data packets as needed make data transmission more organized and efficient, improving the system's data processing capabilities and stability, and contributing to improved system response speed and processing accuracy.

[0027] Preferably, the step S3 includes:

[0028] S31: parse the configuration parameters from the FIFO data, and then judge the validity of the configuration parameters by monitoring the rising edge of the data valid flag, so as to determine the range of the input configuration parameters. Configuration parameters outside the range are not calculated, and wait for the next data valid signal;

[0029] S32: Phase shift rotation angle for input configuration parameters The phase shift pitch angle θ is pre-processed, and when the phase shift rotation angle No processing is done; , subtract 360°, thus Controlled within the range of [-180°, 180°); and the complementary angle of the phase shift pitch angle θ is obtained;

[0030] S33: Calculate the product of the array element unit spacing and the center frequency of the frequency band using multiplier 1 to obtain parameter value 1;

[0031] S34: using divider 1 and divider 2 to convert the pre-processed phase shift rotation angle into radian 1 and convert the pre-processed phase shift pitch angle into radian 2 respectively;

[0032] S35: using the CORDIC IP core to calculate the sine value and cosine value of the radian 1 and the radian 2 respectively, and then performing fixed-point processing on the obtained values;

[0033] S36: Calculate the product of the sine value of radian 2 and the cosine value of radian 1 by using multiplier 2 to obtain parameter value 2, and calculate the product of the sine value of radian 2 and the sine value of radian 1 by using multiplier 3 to obtain parameter value 3;

[0034] S37: Calculate the product of parameter 2 and parameter 1 using multiplier 4 to obtain a row coefficient value, and calculate the product of parameter 3 and parameter 1 using multiplier 5 to obtain a column coefficient value;

[0035] S38: Then, multiplier 6 is used to calculate the product of the row coordinate and the row coefficient value to obtain the row score, and multiplier 7 is used to calculate the product of the column coordinate and the column coefficient value to obtain the column score;

[0036] S39: The obtained row scores and column scores are stored in RAM1 and RAM2 respectively. Then, based on the size of the phased array matrix, the row and column scores of RAM1 and RAM2 are read out by coordinates and added together to obtain a phase shift value 1. Simultaneously, the initial phase is preprocessed using multiplier 8, and the preprocessed initial phase is then added to the phase shift value 1 to obtain a phase shift value 2.

[0037] S310: Use divider 3 to divide the phase shift value 2 by the quantized constant, and then take the decimal place to obtain the phase shift value 3; then quantize the phase shift value 3 to obtain the phase shift value 4, and truncate and round the phase shift value 4 to obtain the phase shift value 5, and finally positively number the phase shift value 5 to obtain the final phase shift value, thereby obtaining the phase shift value of the entire phased array by traversing all coordinates, and storing it in RAM, and generating a pulse phase calculation completion flag at the same time.

[0038] In this application, the parallel pipeline design of FPGA is utilized in combination with its own multiplier and divider cores to realize the rapid calculation of the phase shift value of each unit, meeting the high efficiency and real-time performance of phase shift calculation and control. RAM storage is also used instead of array storage of phase shift values, which effectively reduces the timing convergence difficulty of FPGA design and improves the operation speed of the system. In terms of data accuracy control, the floating-point fixed-point method is also used to strictly and accurately control the accuracy of the unit phase shift value, greatly improving the accuracy of phase shift calculation and control.

[0039] Preferably, in step S3, the calculation formula of the phase shift value is:

[0040]

[0041] Where d represents the unit spacing of the array elements; f represents the center frequency of the frequency band; sinθ′ represents the sine value of radian 2; m represents the row number; Indicates the cosine value of radian 1; n indicates the column number; represents the sine value of radian 1; p(m,n) represents the initial phase of the unit array element.

[0042] By using the above formula, a highly accurate phase shift value can be calculated, ensuring high accuracy and high reliability of the phased array antenna beam control.

[0043] Preferably, the method further comprises quantizing the input configuration parameter data in advance when the upper computer issues the data.

[0044] By incorporating a pre-quantization step into the method before sending configuration parameter data from the host computer, the system's processing efficiency and accuracy can be effectively improved. This pre-quantization ensures that the input configuration parameters are formatted appropriately for the system before data transmission, preventing data mismatches or errors during subsequent processing. This not only reduces data transmission latency but also improves the system's adaptability and stability to input data. This optimization enables the antenna system to respond and process configuration parameters more quickly, ensuring efficiency and accuracy in real-time operation.

[0045] On the other hand, the present application also provides a phase shift system for phased array antenna units based on FPGA, the system comprising: a serial port driver module, an escape module, a protocol decoding module, an initial phase storage module, a phase shift value calculation module, a matrix mapping module, a multi-channel serial port driver module, and an external multi-function chip; wherein,

[0046] The input of the serial port driver module is connected to the external host computer of FPGA, and the output is connected to the escape module, which is used to realize the communication between FPGA and the host computer;

[0047] The input of the escape module is connected to the serial port driver module, and the output is connected to the protocol decoding module, and is used to perform numerical escape on the received data;

[0048] The input of the protocol decoding module is connected to the transfer module, and the output is connected to the initial phase storage module and the phase shift value calculation module. It is used to decode the received data packet, including data verification and data packet correctness detection, and then selectively send the parsed data to the initial phase storage module and the phase shift value calculation module;

[0049] The input of the initial phase storage module is connected to the protocol decoding module, and the output is connected to the phase shift value calculation module, and is used to store the actual initial phase of the unit array element measured by the test;

[0050] The input of the phase shift value calculation module is connected to the initial phase storage module, and the output is connected to the matrix mapping module, and is used to calculate the required shift phase value according to the input initial phase value and configuration parameters, and output a phase calculation completion flag;

[0051] The input of the matrix mapping module is connected to the phase shift value calculation module, and the output is connected to the multi-channel serial port driver module, and is used to complete the multi-channel distribution and sub-packaging of the phase shift value according to the input matrix phase shift RAM interface, phase calculation completion flag, phase shift value mapping table, and matrix physical position mapping table;

[0052] The input of the multi-channel serial port driver module is connected to the matrix mapping module, and the output is physically connected to the external multi-function chip, so as to receive the multi-channel phase shift value data packet after mapping processing, and then output the data according to the synchronous serial port timing logic to complete the phase shift configuration of the external multi-function chip;

[0053] The external multifunctional chip module is used to control the antenna beam by receiving the phase shift values of different channels configured by the serial port.

[0054] In the system described in this application, the flexibility, stability and accuracy of the system are improved through the collaborative work of multiple modules. First, the serial port driver module and the escape module are used to realize efficient communication between the FPGA and the external host computer, and the received data is numerically escaped to ensure the accuracy of data transmission. The protocol decoding module is used to verify and parse the data to ensure the correctness of the data packet. At the same time, the data is selectively sent to the initial phase storage module and the phase shift value calculation module to provide an accurate basis for subsequent phase adjustment. The initial phase storage module is used to store the actual measured initial phase, and the phase shift value calculation module calculates the required phase shift value based on the initial phase and configuration parameters, and distributes and maps the calculation results through the matrix mapping module to ensure that the phase shift value of each array element can be correctly configured. Finally, the processed phase shift value data packet is transmitted to the external multi-function chip through the multi-channel serial port driver module to complete the precise control of the antenna beam. Through this efficient data processing and phase shift control method, the system can accurately adjust the beam of the array antenna in real time, improve the system's response speed and beam control accuracy, and meet the high performance requirements of the phased array antenna. In addition, the system is highly scalable and can flexibly adjust the configuration of each module as needed to adapt to different application scenarios.

[0055] On the other hand, the present application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and runnable on the processor. When the processor executes the program, it implements the FPGA-based phased array antenna unit phase shifting method as described above.

[0056] The present application also provides a non-transitory computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the FPGA-based phased array antenna unit phase shifting method as described above is implemented.

[0057] The present application also provides a computer program product, including a computer program, which, when executed by a processor, implements the above-mentioned FPGA-based phased array antenna unit phase shifting method.

[0058] Compared with the prior art, the present invention has the following beneficial effects:

[0059] The present invention provides a method and system for phase shifting of phased array antenna units based on FPGA. In terms of logic design, high-speed calculation of phase shift values of phased array units is achieved by calling FPGA internal logic resources including divider cores, DSP multiplier cores, CORDIC cores, RAM, LUT tables, etc., thereby ensuring the real-time performance of the system. In terms of matrix application, RAM storage is used instead of array storage for phase shift values, which effectively reduces the difficulty of timing convergence in FPGA design and improves the operating speed of the system. In terms of data accuracy control, strict control of the data bit width of floating-point fixed-point conversion and optional data truncation and rounding methods greatly improves the accuracy of phase shift value calculation of phased array units. At the system level, compared with traditional phased array phase shift systems, the complete data link of protocol data packets sent by the host computer improves the flexible configuration of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] Figure 1 The present invention provides a flow chart of the method.

[0061] Figure 2 This is a structural diagram of the communication protocol data packet between the host computer and FPGA provided by the present invention.

[0062] Figure 3 This is a flowchart of the matrix mapping process provided by the present invention.

[0063] Figure 4 This is a schematic diagram of the system structure provided by the present invention.

[0064] Figure 5 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0065] The accompanying drawings are for illustrative purposes only and are not to be construed as limiting the present invention. To better illustrate the following embodiments, some components in the accompanying drawings may be omitted, enlarged, or reduced in size, and do not represent actual product dimensions. Those skilled in the art will appreciate that some well-known structures and their descriptions may be omitted from the accompanying drawings.

[0066] Example 1

[0067] like Figure 1 As shown, this embodiment provides a phase shifting method for a phased array antenna unit based on FPGA, the method comprising the following steps:

[0068] Step S1: Receive the protocol data packet sent by the host computer and perform escape processing on the protocol data;

[0069] Specifically, this embodiment supports communication with a host computer and receives customized protocol data packets through a serial port, thereby achieving dynamic loading and real-time effectiveness of configuration parameters, improving the flexible configuration of the system. The order in which initial phase value data and configuration parameter data are issued is as follows: the initial phase value data is issued first, followed by the configuration parameter data. The configuration parameter data includes the initial phase value, array element spacing, target angle, center frequency of the beam band, etc. The received single-bit serial data is then converted into 8-bit parallel data. Numerical escape is performed to convert consecutive 0x7D and 0x5E in the received data into 7E, and vice versa. This completes the escape process.

[0070] Step S2: Decode and parse the escaped protocol data packet, divide the parsed data into initial phase value data and configuration parameter data and store them;

[0071] Specifically, decoding and parsing the escaped protocol data packet includes:

[0072] Decoding: The 8-bit parallel data converted in step S1 is decoded according to Figure 2 The protocol data packet structure shown is used for data comparison and identification and data accumulation verification. After verification, the rest of the data is removed and only the command code, data length, and data content are left.

[0073] Parsing: Determine the command code to identify the initial phase data packet and configuration parameter data packet, and store their respective command codes, data lengths, and data contents into their corresponding FIFOs.

[0074] Preferably, if Figure 2 As shown, the data structure of the protocol data packet to be parsed includes: 8-bit frame start 0x7E, 8-bit address code 0x00, 8-bit control code 0x00, 8-bit command code, 16-bit data length, data content, 16-bit check code, and 8-bit frame end 0x7E.

[0075] Among them, the data length describes the length of the data content in bytes. Specifically, for example, the data length is 0x0006, which means that the data content has 6 bytes; the 16-bit check code verification method is the cumulative sum, and the high bit is not carried. Specifically, the check code can be obtained by calculating the cumulative sum of the address code, control code, command code, data length, and data content; and different FIFOs are also used to store the initial phase data packet and configuration parameter data packet as well as their respective command codes and lengths.

[0076] Step S3: Calculate the phase shift value of each phased array unit using the initial phase value data and the configuration parameter data, and output a phase calculation completion flag after the calculation is completed;

[0077] Specifically, step S3 includes:

[0078] Step S31: parse the configuration parameters from the FIFO data. In this embodiment, the parsed configuration information includes data valid flag, phase shift angle, Phase shift pitch angle θ, center frequency f of the beam band, unit spacing d of phased array elements, initial phase p(m, n) of unit elements, number of row elements R, number of column elements C, etc.

[0079] Then, the validity of the configuration parameters is judged by monitoring the rising edge of the data valid flag, thereby determining the range of the input configuration parameters. Configuration parameters outside the range are not calculated, and the next data valid signal is waited for; the rising edge is in the form of a pulse, and this pulse is obtained by performing rising edge detection on the data valid flag generated in step S31.

[0080] In this embodiment, the validity of the parameters is mainly determined by determining two parameters: phase shift angle Is it between 0 and 360 degrees, and is the phase shift pitch angle θ between 0 and 90 degrees. Therefore, the phase shift rotation angle in the input configuration parameters The phase shift angle θ is limited to 0 to 360 degrees, and the phase shift angle θ is limited to 0 to 90 degrees.

[0081] Step S32: Phase shift rotation angle for input configuration parameters The phase shift pitch angle θ is pre-processed, and when the phase shift rotation angle No processing is done; , subtract 360°, thus Controlled within the range of [-180°, 180°); and the complementary angle of the phase shift pitch angle θ is obtained;

[0082] After completing the above data preprocessing, the phase shift value is formally calculated. The calculation formula is as follows:

[0083]

[0084] Where d represents the unit spacing of the array elements; f represents the center frequency of the frequency band; sinθ′ represents the sine value of radian 2; m represents the row number; Indicates the cosine value of radian 1; n indicates the column number; represents the sine value of radian 1; p(m,n) represents the initial phase of the unit array element, m = {1, 2, ..., R}; n = {1, 2, ..., C}.

[0085] Furthermore, in order to maintain the calculation accuracy of each coordinate component to the greatest extent possible, the above formula is expanded into the following form:

[0086]

[0087] Therefore, the above formula can be used to calculate the phase shift value with high precision, ensuring the high precision and high reliability of the phased array antenna beam control.

[0088] Furthermore, in the method, the input configuration parameter data is quantized in advance when the host computer sends it, including the phase shift angle In this embodiment, the quantization factor for the phase shift elevation angle θ, the center frequency f of the beam band, and the unit spacing d of the phased array elements can be set to 2m, effectively improving the accuracy of phase calculation and enhancing the processing efficiency and accuracy of the system. Pre-quantization ensures that the input configuration parameters are processed into a format suitable for the system before data transmission, avoiding data mismatches or errors in subsequent processing. This not only reduces data transmission latency but also improves the system's adaptability and stability to input data. Through this optimization, the antenna system can respond and process configuration parameters more quickly, ensuring efficiency and accuracy in real-time operation.

[0089] Preferably, step S33: using multiplier 1 to calculate the product of the array element unit spacing and the center frequency of the frequency band to obtain parameter value 1;

[0090] Preferably, step S34: using divider 1 and divider 2 to convert the pre-processed phase shift rotation angle into radian 1 and convert the pre-processed phase shift pitch angle into radian 2 respectively;

[0091] The radian conversion formula is: radian = angle·π / 180(3);

[0092] Preferably, step S35: using the CORDIC IP core to calculate the sine value and cosine value of the radian 1 and radian 2 respectively, wherein the sine value and cosine value of the radian 1 are respectively expressed as and The sine and cosine values of the radian 2 are expressed as sinθ′ and cosθ′ respectively; and then the obtained values are fixed-point processed;

[0093] In this embodiment, the fixed-point processing mainly includes three steps:

[0094] 1) Determine the number of integer digits n and decimal digits m required for fixed-point conversion;

[0095] 2) Amplify the data by 2m;

[0096] 3) truncate the data;

[0097] Specifically, we only need to adjust the factors sinθ′, as well as Quantization is performed. According to the 64-bit maximum input bit width limit of the FPGA divider, the quantization multiple selected in this embodiment is 2 to the power of 14. Quantization amplification can be completed by shifting, reducing the consumption of three multipliers.

[0098] Preferably, step S36: using multiplier 2 to calculate the product of the sine value of radian 2 and the cosine value of radian 1 to obtain parameter value 2, and using multiplier 3 to calculate the product of the sine value of radian 2 and the sine value of radian 1 to obtain parameter value 3;

[0099] Preferably, step S37: using multiplier 4 to calculate the product of parameter 2 and parameter 1 to obtain the row coefficient value d m , use multiplier 5 to calculate the product of parameter value 3 and parameter value 1 to obtain the column coefficient value d n ;

[0100] Preferably, step S38: then using multiplier 6 to calculate the product of the row coordinate and the row coefficient value to obtain the row score, and using multiplier 7 to calculate the product of the column coordinate and the column coefficient value to obtain the column score;

[0101] Preferably, step S39: storing the obtained row scores and column scores in RAM1 and RAM2 respectively, and then reading the row and column scores of RAM1 and RAM2 by coordinates according to the size of the phased array matrix and adding them together to obtain a phase shift value 1; at the same time, using the multiplier 8 to preprocess the initial phase p(m, n), and then adding the preprocessed initial phase to the phase shift value 1 to obtain a phase shift value 2;

[0102] S310: Use divider 3 to divide the phase shift value 2 by the quantized constant 299.79, and then take the decimal place to obtain the phase shift value 3; then quantize the phase shift value 3 to obtain the phase shift value 4, where the quantization multiple in this step is 2 to the power of 6, and the phase shift value is kept between negative 62 and positive 63.

[0103] The phase shift value 4 is further truncated and rounded to obtain a phase shift value 5. Optionally, in this embodiment, the truncation process can be rounded down or rounded up according to the accuracy requirement, and the phase shift value 5 is obtained by truncation.

[0104] Specifically, the design of truncation and rounding adopts two optional methods. Assuming the truncation width is x, the first method is to round down to the integer floor, which can also be called direct truncation. In the FPGA, the low x bits of the data can be directly discarded according to the selected truncation width x. The second method is to round up the truncation, which is implemented in the FPGA as follows:

[0105] When the truncated number is positive, first add 2 to the power of x minus 1 to the truncated number, and then discard the lower x bits of the data;

[0106] When the truncated number is negative, first add 2 to the power of x minus 1 to the truncated number, then subtract 1, and finally discard the lower x bits of the data;

[0107] Finally, the phase shift value 5 is positively converted to obtain the final phase shift value. Specifically, the positive conversion method is to keep the positive number unchanged and add 64 to the negative number. This processing can keep the phase shift value between 0 and 63, and keep the phase shift step at 5.625. 0 to 63 can traverse all directions representing 0 degrees to 360 degrees.

[0108] Finally, the phase shift value of the entire phased array is obtained by traversing all coordinates and stored in RAM, and a pulse phase calculation completion flag is generated at the same time.

[0109] Therefore, in this embodiment, by utilizing the parallel pipeline design of the FPGA in combination with its own multiplier and divider cores, the phase shift value of each unit is quickly calculated, meeting the high efficiency and real-time performance of phase shift calculation and control. In addition, RAM storage is used instead of array storage for phase shift values, which effectively reduces the timing convergence difficulty of FPGA design and improves the operating speed of the system. In terms of data precision control, the floating-point fixed-point method is also used to strictly and accurately control the precision of the unit phase shift value, greatly improving the accuracy of phase shift calculation and control.

[0110] Preferably, step S4: mapping the matrix phase transplantation and allocating and packaging the multi-channel FIFO data according to the phase calculation completion flag;

[0111] like Figure 3 As shown, step S4 further includes the following sub-steps:

[0112] Step S41: Using the received phase calculation completion flag as a trigger start signal for mapping processing; in this embodiment, by using the received phase calculation completion flag as a trigger start signal for mapping processing, it is ensured that the mapping process starts immediately after the phase calculation is completed, effectively avoiding errors caused by data delays or synchronization problems, and improving the collaborative work efficiency between various links in the system during the processing process.

[0113] Step S42: mapping the phase shift value to a true value using a phase shift value mapping table;

[0114] Specifically, the phase shift value mapping relationship can be obtained through actual measurement or from the multifunctional chip calibration manual. The phase shift value mapping relationship is used to calibrate the fixed deviation between the actual phase shift value and the theoretical phase shift of the multifunctional chip.

[0115] Specifically, the phase shift value mapping relationship can be implemented by generating a .vh file and then calling the .vh file using include, or by editing and assigning values one by one using a task or function.

[0116] By generating a phase-shift mapping table using a .vh file and calling it through include, or by editing and assigning values using tasks or functions, the system's flexibility and maintainability can be significantly improved. This approach makes phase-shift mapping table management more efficient and facilitates subsequent modification and expansion. It also simplifies the code structure, reduces redundancy, and improves code reusability. This approach allows the system to flexibly respond to changing requirements, improves development and debugging efficiency, and ensures the accuracy and consistency of phase-shift mapping.

[0117] Step S43: reallocating the phase shift value matrix through the matrix physical position mapping table;

[0118] Specifically, the matrix physical position mapping table is an actual physical position allocation table, which maps and allocates different SPI serial ports and multi-function chips in the matrix. The matrix physical position mapping is used to allocate the phase matrix value to the corresponding SPI channel;

[0119] Specifically, taking an actual phased array system as an example, if a phased array with 576 elements needs to be controlled, a 4-element multifunction chip requires 144 multifunction chips, which are driven and controlled by 32 SPI interfaces. Each SPI interface controls 4 or 5 multifunction chips according to the chip address, so one SPI interface needs to be configured with 16 or 20 elements. The phase values required for these 16 or 20 elements can be selected and allocated through matrix physical position mapping.

[0120] Therefore, flexible configuration of phased arrays of different sizes and multifunctional chips can be achieved through matrix physical position mapping.

[0121] Step S44: the phase shift values are divided into packets for different channels, and the data is output in the form of a FIFO interface.

[0122] Specifically, the packetized data in the FIFO can be configured with the channel switch, chip address, channel address, and phase shift value;

[0123] Taking an actual phased array system analysis as an example, after redistribution in step S43, 16 or 20 phase values that need to be driven and outputted by each SPI interface are obtained. Since the multi-function chip controls four array elements, each chip address can be configured with four phase shifts.

[0124] Preferably, the phase shift value control of each array element can correspond to a different channel register address according to the multi-function chip manual, and the switch of each channel also corresponds to a different configuration register address;

[0125] Preferably, the packetization method is to first store the channel switch packet in the form of chip address + channel register address + channel switch in the FIFO according to the SPI control timing, and then store the phase shift value packet in the form of chip address + configuration register address + phase shift value in the FIFO; then, according to the needs, set the FIFO for storing the switch data packet and the FIFO for storing the phase shift value data packet, which can be set to the same FIFO or separated into two FIFOs for storage;

[0126] Step S5: receiving the multi-channel phase shift value data packet after mapping processing, and then outputting the data according to the synchronous serial port timing logic to complete the phase shift configuration of the external multi-function chip;

[0127] Preferably, in this embodiment, the serial port driver used can be a 4-wire SPI serial port, the FPGA can be the host, and the multi-function chip can be the slave; wherein, the composition of the serial port includes a chip select signal CS, a clock signal SCLK, an output data signal MOSI, and an input data signal MISO; the sending and receiving timing of the serial port is that the host first sends the chip address, then sends the read / write flag, then sends the channel address, and finally sends the data; in this embodiment, for the data sent, the host sends write data in the case of writing, and the slave sends read data in the case of reading, thereby completing the phase shift configuration of the external multi-function chip

[0128] Step S6: The external multi-function chip controls the antenna beam by receiving the phase shift values of different channels configured via the serial port.

[0129] Preferably, in this embodiment, antenna beam control is accomplished using the XND1523MM multifunctional receiver chip. This chip contains 32 internal phase-shifting channels, each integrated with functional units such as a phase shifter, attenuator, and amplifier. Multiple external multifunctional chips can be combined to create phased array matrices of varying sizes, suitable for applications such as satellite communication transmission systems.

[0130] Further preferably, in this embodiment, the selected FPGA chip can be the Kinetex-7 series programmable chip XC7K160T manufactured by Xilinx. The chip is manufactured using a 28nm process, has 676 programmable interfaces, 325 BLOCKRAMs and 600 DSP48E1 cores, and can be widely used in high-performance computing, communications, industrial control and other fields.

[0131] The required number of phased array elements is 576, the number of rows is set to 24, and the number of columns is set to 24, forming a square matrix. The phased array antenna matrix can be composed of 144 XND1523MM chips;

[0132] Then, set the configurable parameters inside the FPGA according to the requirements to generate 32-channel SPI serial port drivers. Each SPI is configured to drive 4 or 5 XND1523MM by setting different chip select CS and chip address.

[0133] The FPGA system's main clock can be constrained to 125Mhz, the SPI clock can be set to 20Mhz, and the RS485 communication bit rate can be set to 921600bps, which can achieve timing convergence with sufficient margin.

[0134] In summary, in this embodiment, by first receiving the protocol data packet sent by the host computer and performing escape processing, and then decoding and parsing the protocol data, the accurate transmission and timely processing of the data can be ensured. After the data is parsed, the initial phase value data and the configuration parameter data are effectively separated and stored in the FPGA, providing the necessary foundation for the subsequent phase shift value calculation. In addition, the parallel processing capability of the FPGA is utilized to ensure that the phase shift calculation of each antenna unit in a large-scale phased array system can be completed quickly, reducing the delay in traditional methods. At the same time, by parsing the initial phase value and configuration parameter data, the phase shift value of each phased array unit can be accurately calculated. After the calculation is completed, the phase calculation completion flag is output to ensure that the system can accurately synchronize when performing subsequent operations, avoiding data errors or calculation delays. In addition, the present application also uses mapping processing and multi-channel FIFO data distribution and subpackaging to efficiently transmit the phase shift value data to the target antenna unit, ensuring that each antenna unit obtains the correct control data. By outputting data through the synchronous serial port timing logic, it is possible to achieve precise control and distribution of multi-channel phase shift value data, so that the phase shift configuration of each channel can be accurately completed. It also collaborates with external multi-function chips to ensure precise adjustment of the antenna beam, improving the system's adaptability and stability in dynamic environments. Therefore, the method described in this application leverages the high parallelism and flexibility of FPGAs to handle complex control tasks, offering high scalability and reliability. It can adapt to phased array antenna systems of varying sizes and is compatible and collaborative with a variety of external devices, meeting a wider range of application needs.

[0135] Example 2

[0136] like Figure 4 As shown, this embodiment provides a phase shift system for phased array antenna units based on FPGA, the system comprising: a serial port driver module, an escape module, a protocol decoding module, an initial phase storage module, a phase shift value calculation module, a matrix mapping module, a multi-channel serial port driver module, and an external multi-function chip; wherein,

[0137] The input of the serial port driver module is connected to the FPGA external host computer, and the output is connected to the escape module, which is used to realize the communication between the FPGA and the host computer; wherein the external host computer interface can be a USB interface, and the FPGA physical interface can be an RS485 serial port. The host computer and FPGA can be connected and communicated through a USB to RS485 converter;

[0138] Preferably, the serial port driver module can receive parameters configured in real time, and the configurable parameters include an initial phase value, array element spacing, a target angle, and a center frequency of a beam frequency band; and the serial port driver module converts the received single-bit serial data into 8-bit parallel data, and then outputs and sends the data to the escape decoding module; the serial port driver module receives data in the order of receiving the low byte first and then the high byte, and each byte receives the low bit first and then the high bit.

[0139] Preferably, the input of the escape module is connected to the serial port driver module, and the output is connected to the protocol decoding module, for performing numerical escape on the received data;

[0140] In the transfer module, the received data is numerically escaped by escaping the consecutive 0x7D and 0x5E to 7E and the consecutive 0x7D and 0x5D to 7D.

[0141] Preferably, the input of the protocol decoding module is connected to the transfer module, and the output is connected to the initial phase storage module and the phase shift value calculation module, so as to decode the received data packet, including data verification and data packet correctness detection, and then selectively send the parsed data to the initial phase storage module and the phase shift value calculation module;

[0142] The data structure of the protocol data packet that the protocol decoding module needs to parse includes: an 8-bit frame start 0x7E, an 8-bit address code 0x00, an 8-bit control code 0x00, an 8-bit command code, a 16-bit data length, data content, a 16-bit check code, and an 8-bit frame end 0x7E;

[0143] Further preferably, the data length describes the length of the data content in bytes. Specifically, for example, a data length of 0x0006 indicates that the data content has 6 bytes.

[0144] Furthermore, the 16-bit length check code is checked in a cumulative sum manner with no carry in the high bit. Specifically, the check code can be obtained by calculating the cumulative sum of the address code, control code, command code, data length, and data content.

[0145] Furthermore, the protocol decoding module outputs interfaces to the initial phase storage module and the phase shift calculation module as four FIFO interfaces corresponding to four FIFOs. The first and second FIFO interfaces are connected to the initial phase storage module, while the second and third FIFO interfaces are connected to the phase shift calculation module. Each FIFO interface group includes a single-bit null signal, a single-bit read signal, and an 8-bit data signal.

[0146] Furthermore, FIFO1 stores the command code and length of the initial phase data packet, FIFO2 stores the initial phase data packet, FIFO3 stores the command code and length of the configuration parameter data packet, and FIFO4 stores the configuration parameter data packet;

[0147] Preferably, the input of the initial phase storage module is connected to the protocol decoding module, and the output is connected to the phase shift value calculation module. It is used to store the actual initial phase of the unit array element measured in the test, and the output is in the form of a RAM interface with an address bit width of 16 bits and a data bit width of 8 bits. It is necessary to parse and read the command code and data length of FIFO1. When the command code is correct, the initial phase data packet of FIFO2 is read according to the data length, and then written into the RAM in sequence.

[0148] Preferably, the input of the phase shift value calculation module is connected to the initial phase storage module, and the output is connected to the matrix mapping module, and is used to calculate the required mobile phase value based on the input initial phase value and configuration parameters, and output a phase calculation completion flag. The output phase shift value is in the form of a RAM interface, the address bit width is 16 bits, and the output data bit width is 6 bits; it is necessary to parse and read the command code and data length of FIFO3. When the command code is correct, the configuration parameter data packet of FIFO4 is read according to the data length.

[0149] Preferably, the input of the matrix mapping module is connected to the phase shift value calculation module, and the output is connected to the multi-channel serial port driver module, and is used to complete the multi-channel distribution and sub-packaging of the phase shift value according to the input matrix phase shift RAM interface, phase calculation completion flag, phase shift value mapping table, and matrix physical position mapping table, and the output interface is a FIFO interface; wherein the phase shift value mapping table can be obtained through actual measurement to calibrate the fixed deviation between the actual phase shift value and the theoretical phase shift of different multi-function chips; the matrix physical position mapping table is an actual physical position allocation table, mapping and allocating different SPI serial ports and multi-function chips in the matrix position; and the sub-packetized data in the FIFO can be configured with channel switches, chip addresses, channel addresses, and phase shift values;

[0150] Preferably, the input of the multi-channel serial port driver module is connected to the matrix mapping module, and the output is physically connected to the external multi-function chip, so as to receive the multi-channel phase shift value data packet after mapping processing, and then output the data according to the synchronous serial port timing logic to complete the phase shift configuration of the external multi-function chip;

[0151] Preferably, the serial port driver used can be a 4-wire SPI serial port, the FPGA can be the host, and the multi-function chip can be the slave; the composition of the serial port includes a chip select signal CS, a clock signal SCLK, an output data signal MOSI, and an input data signal MISO; the sending and receiving timing of the serial port is that the host first sends the chip address, then sends the read / write flag, then sends the channel address, and finally sends the data; the data sent, in the case of writing, the host sends write data, and in the case of reading, the slave sends read data;

[0152] Preferably, the external multifunctional chip module is used to control the antenna beam by receiving phase shift values for different channels configured via the serial port, including functions such as RF phase shifting and amplitude attenuation. In this embodiment, the multifunctional chip can be an XND1523MM multifunctional receiver chip, which contains 32 phase-shift channels, each integrated with functional units such as a phase shifter, attenuator, and amplifier. Multiple external multifunctional chips can be combined to form phased array matrices of varying sizes for applications in satellite communication transmission systems.

[0153] The FPGA-based phased array antenna unit phase shifting system provided in the embodiment of this solution is used to execute the above-mentioned FPGA-based phased array antenna unit phase shifting method of this solution. Its implementation method is consistent with the implementation method of the FPGA-based phased array antenna unit phase shifting method provided in this solution, and can achieve the same beneficial effects, which will not be repeated here.

[0154] Thus, in the system described in this embodiment, the coordinated operation of multiple modules enhances the flexibility, stability, and accuracy of the system. First, a serial port driver module and an escape module are used to achieve efficient communication between the FPGA and an external host computer, and numerical escape is performed on the received data to ensure the accuracy of data transmission. A protocol decoding module is used to verify and parse the data to ensure the correctness of the data packet. The data is selectively sent to the initial phase storage module and the phase shift value calculation module, providing a precise basis for subsequent phase adjustment. The initial phase storage module is used to store the actual measured initial phase, while the phase shift value calculation module calculates the required phase shift value based on the initial phase and configuration parameters. The calculation results are distributed and mapped through the matrix mapping module to ensure that the phase shift value of each array element can be correctly configured. Finally, the processed phase shift value data packet is transmitted to the external multi-function chip through the multi-channel serial port driver module to achieve precise control of the antenna beam. Through this efficient data processing and phase shift control method, the system can accurately adjust the array antenna beam in real time, improving the system's response speed and beam control accuracy, and meeting the high-performance requirements of phased array antennas. In addition, the system is highly scalable and can flexibly adjust the configuration of each module as needed to adapt to different application scenarios.

[0155] Example 3

[0156] This embodiment provides an electronic device, such as Figure 5 As shown, the electronic device may include: a processor (processor) 510, a communication interface (Communications Interface) 520, a memory (memory) 530 and a communication bus 540, wherein the processor 810, the communication interface 520, and the memory 530 communicate with each other through the communication bus 540. The processor 510 can call the logic instructions in the memory 530 to execute the FPGA-based phase shifting method of the phased array antenna unit, which includes: S1: receiving the protocol data packet sent by the host computer and escaping the protocol data; S2: decoding and parsing the escaped protocol data packet, dividing the parsed data into initial phase value data and configuration parameter data and storing them; S3: using the initial phase value data and configuration parameter data to calculate the phase shift value of each phased array unit, and outputting the phase calculation completion flag after the calculation is completed; S4: mapping the matrix phase shift and allocating and subpackaging the multi-channel FIFO data according to the phase calculation completion flag; S5: receiving the multi-channel phase shift value data packet after mapping, and then outputting the data according to the synchronous serial port timing logic to complete the phase shift configuration of the external multi-function chip; S6: the external multi-function chip completes the control of the antenna beam by receiving the phase shift values of different channels configured by the serial port.

[0157] In addition, the logic instructions in the above-mentioned memory 530 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when sold or used as an independent product. Based on this understanding, the technical solution of this solution, or the part that contributes to the existing technology, or the part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of this solution. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0158] On the other hand, the present solution also provides a computer program product, which includes a computer program, which can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the FPGA-based phased array antenna unit phase shifting method provided by the above methods, the method including: S1: receiving a protocol data packet sent by a host computer and escaping the protocol data; S2: decoding and parsing the escaped protocol data packet, dividing the parsed data into initial phase value data and configuration parameter data and storing them; S3: using the initial phase value data and configuration parameter data to calculate the phase shift value of each phased array unit, and outputting a phase calculation completion flag after the calculation is completed; S4: mapping the matrix phase shift and allocating and subpackaging the multi-channel FIFO data according to the phase calculation completion flag; S5: receiving the multi-channel phase shift value data packet after mapping, and then outputting the data according to the synchronous serial port timing logic to complete the phase shift configuration of the external multi-function chip; S6: the external multi-function chip completes the control of the antenna beam by receiving the phase shift values of different channels configured by the serial port.

[0159] On the other hand, the present solution also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to execute the FPGA-based phased array antenna unit phase shifting method provided by the above methods, the method comprising: S1: receiving a protocol data packet sent by a host computer and performing escape processing on the protocol data; S2: decoding and parsing the escaped protocol data packet, dividing the parsed data into initial phase value data and configuration parameter data and storing them; S3: using the initial phase value data and configuration parameter data to calculate the phase shift value of each phased array unit, and outputting a phase calculation completion flag after the calculation is completed; S4: mapping the matrix phase shift and allocating and subpackaging the multi-channel FIFO data according to the phase calculation completion flag; S5: receiving the multi-channel phase shift value data packet after mapping, and then outputting the data according to the synchronous serial port timing logic to complete the phase shift configuration of the external multi-function chip; S6: the external multi-function chip completes the control of the antenna beam by receiving the phase shift values of different channels configured by the serial port.

[0160] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one location or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0161] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, or of course, by hardware. Based on this understanding, the essence of the above technical solution or the part that contributes to the existing technology can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or certain parts of the embodiments.

[0162] Obviously, the above embodiments of the present invention are merely examples for the purpose of clearly illustrating the technical solutions of the present invention, and are not intended to limit the specific implementation methods of the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the claims of the present invention shall be included within the scope of protection of the claims of the present invention.

Claims

1. A phase shifting method for phased array antenna units based on FPGA, characterized in that: The method comprises the following steps: S1: Receives the protocol data packet sent by the host computer and performs escape processing on the protocol data; S2: Decode and parse the escaped protocol data packet, divide the parsed data into initial phase value data and configuration parameter data, and store them; S3: Calculate the phase shift value of each phased array unit using the initial phase value data and configuration parameter data, and output a phase calculation completion flag after the calculation is completed; S4: Mapping the matrix phase transplantation and allocating and packaging the multi-channel FIFO data according to the phase calculation completion flag; S5: Receive the multi-channel phase shift value data packet after mapping, and then output the data according to the synchronous serial port timing logic to complete the phase shift configuration of the external multi-function chip; S6: The external multi-function chip controls the antenna beam by receiving the phase shift values of different channels configured through the serial port.

2. The FPGA-based phase-shifting method for phased array antenna units according to claim 1, characterized in that: In the step S4, it includes: S41: Using the received phase calculation completion flag as a mapping process trigger start signal; S42: Mapping the phase shift value to a true value using a phase shift value mapping table; S43: reallocating the phase shift value matrix through the matrix physical position mapping table; S44: Packetize the phase shift values for different channels.

3. The FPGA-based phased array antenna unit phase shifting method according to claim 2, characterized in that: In step S42, the phase shift value mapping relationship in the phase shift value mapping table is generated by generating a .vh file and then calling the .vh file using include, or by editing and assigning values using task or function.

4. The FPGA-based phased array antenna unit phase shifting method according to claim 3, characterized in that: In the matrix physical position mapping table in step S43, different SPI serial ports and multi-function chips are mapped and assigned to positions in the matrix, thereby allocating the values of the phase matrix to corresponding SPI channels.

5. The FPGA-based phased array antenna unit phase shifting method according to claim 4, characterized in that: In step S44, the data output form of the phase shift values for different channels is packaged in a FIFO interface form, and the package includes: setting the channel switch package as the chip address + channel register address + channel switch form according to the SPI control timing and storing it in the FIFO, and then setting the phase shift value package as the chip address + configuration register address + phase shift value form and storing it in the FIFO; wherein, the FIFO storing the switch package and the FIFO storing the phase shift value package can be set to the same FIFO or separated into two FIFOs for storage according to needs.

6. The FPGA-based phase-shifting method for phased array antenna units according to claim 1, characterized in that: The step S3 includes: S31: parse the configuration parameters from the FIFO data, and then judge the validity of the configuration parameters by monitoring the rising edge of the data valid flag, so as to determine the range of the input configuration parameters. Configuration parameters outside the range are not calculated, and wait for the next data valid signal; S32: Phase shift rotation angle for input configuration parameters The phase shift pitch angle θ is pre-processed, and when the phase shift rotation angle No processing is done; , subtract 360°, thus Controlled within the range of [-180°, 180°); and the complementary angle of the phase shift pitch angle θ is obtained; S33: Calculate the product of the array element unit spacing and the center frequency of the frequency band using multiplier 1 to obtain parameter value 1; S34: using divider 1 and divider 2 to convert the pre-processed phase shift rotation angle into radian 1 and convert the pre-processed phase shift pitch angle into radian 2 respectively; S35: Calculate the sine value and cosine value of the radian 1 and radian 2 respectively using the CORDIC IP core, and then perform fixed-point processing on the obtained values; S36: Calculate the product of the sine value of radian 2 and the cosine value of radian 1 by using multiplier 2 to obtain parameter value 2, and calculate the product of the sine value of radian 2 and the sine value of radian 1 by using multiplier 3 to obtain parameter value 3; S37: Calculate the product of parameter 2 and parameter 1 using multiplier 4 to obtain a row coefficient value, and calculate the product of parameter 3 and parameter 1 using multiplier 5 to obtain a column coefficient value; S38: Then, multiplier 6 is used to calculate the product of the row coordinate and the row coefficient value to obtain the row score, and multiplier 7 is used to calculate the product of the column coordinate and the column coefficient value to obtain the column score; S39: The obtained row scores and column scores are stored in RAM1 and RAM2 respectively. Then, based on the size of the phased array matrix, the row and column scores of RAM1 and RAM2 are read out by coordinates and added together to obtain a phase shift value 1. Simultaneously, the initial phase is preprocessed using multiplier 8, and the preprocessed initial phase is then added to the phase shift value 1 to obtain a phase shift value 2. S310: Use divider 3 to divide the phase shift value 2 by the quantized constant, and then take the decimal place to obtain the phase shift value 3; then quantize the phase shift value 3 to obtain the phase shift value 4, and truncate and round the phase shift value 4 to obtain the phase shift value 5, and finally positively number the phase shift value 5 to obtain the final phase shift value, thereby obtaining the phase shift value of the entire phased array by traversing all coordinates, and storing it in RAM, and generating a pulse phase calculation completion flag at the same time.

7. The FPGA-based phased array antenna unit phase shifting method according to claim 6, characterized in that: In step S3, the calculation formula of the phase shift value is: Where d represents the unit spacing of the array elements; f represents the center frequency of the frequency band; sinθ′ represents the sine value of radian 2; m represents the row number; Indicates the cosine value of radian 1; n indicates the column number; represents the sine value of radian 1; p(m,n) represents the initial phase of the unit array element.

8. The FPGA-based phased array antenna unit phase shifting method according to any one of claims 1 to 7, characterized in that: The method also includes pre-quantizing the input configuration parameter data when the upper computer sends it down.

9. A phase-shifting system for phased array antenna units based on FPGA, characterized in that: The system includes: a serial port driver module, an escape module, a protocol decoding module, an initial phase storage module, a phase shift value calculation module, a matrix mapping module, a multi-channel serial port driver module, and an external multi-function chip; wherein, The input of the serial port driver module is connected to the external host computer of FPGA, and the output is connected to the escape module, which is used to realize the communication between FPGA and the host computer; The input of the escape module is connected to the serial port driver module, and the output is connected to the protocol decoding module, and is used to perform numerical escape on the received data; The input of the protocol decoding module is connected to the transfer module, and the output is connected to the initial phase storage module and the phase shift value calculation module. It is used to decode the received data packet, including data verification and data packet correctness detection, and then selectively send the parsed data to the initial phase storage module and the phase shift value calculation module; The input of the initial phase storage module is connected to the protocol decoding module, and the output is connected to the phase shift value calculation module, and is used to store the actual initial phase of the unit array element measured by the test; The input of the phase shift value calculation module is connected to the initial phase storage module, and the output is connected to the matrix mapping module, and is used to calculate the required shift phase value according to the input initial phase value and configuration parameters, and output a phase calculation completion flag; The input of the matrix mapping module is connected to the phase shift value calculation module, and the output is connected to the multi-channel serial port driver module, and is used to complete the multi-channel distribution and sub-packaging of the phase shift value according to the input matrix phase shift RAM interface, phase calculation completion flag, phase shift value mapping table, and matrix physical position mapping table; The input of the multi-channel serial port driver module is connected to the matrix mapping module, and the output is physically connected to the external multi-function chip, so as to receive the multi-channel phase shift value data packet after mapping processing, and then output the data according to the synchronous serial port timing logic to complete the phase shift configuration of the external multi-function chip; The external multifunctional chip module is used to control the antenna beam by receiving the phase shift values of different channels configured by the serial port.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the program, the FPGA-based phased array antenna unit phase shifting method according to any one of claims 1 to 8 is implemented.

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