An efficient routing method and device for network-on-chip dual perception

Abstract

The application discloses a kind of high-efficiency routing method and device of network-on-chip dual perception, including according to the determination congestion information and area information of calculation tight centrality and intermediate centrality;Determine the legal candidate output port;Calculate the metric congestion value and obtain the node number connected;By comparing the size of metric congestion value, select the appropriate output port.The application provides better adaptability by using local network state information, and uses prospective area information to avoid congestion problems existing in the network in advance, to reduce message transmission delay, with good practical value.

Description

Technical Field

[0001] This invention pertains to network routing technology, and particularly relates to an efficient routing method and apparatus for dual-sensing on-chip networks. Background Technology

[0002] On-chip networks (ONCs) are the foundation of chip core interconnection in high-performance computer systems and are central to multi-core / many-core system architectures. The goal of ONCs is to enable fast and efficient message transmission between computing resources (computing cores and memory units), thereby improving system performance. ONC performance evaluation encompasses not only metrics such as network latency and throughput but also a broader range of performance indicators. For example, ONC design must consider factors such as area and power consumption to ensure its feasibility and effectiveness in practical applications. Achieving high-efficiency network performance in ONC design is a significant challenge.

[0003] In a given network topology, routing algorithm design plays a crucial role in on-chip networks. It determines the transmission path of packets from the source router to the destination router by selecting appropriate output ports, directly impacting network performance and packet transmission efficiency. Therefore, this invention primarily focuses on optimizing the shortest adaptive routing algorithm. The goal of adaptive routing algorithms is to select a transmission path with lower congestion levels based on current network state information. From the perspective of obtaining current network state information, current adaptive routing algorithms rely on increasingly rich network state information. Local adaptive routing algorithms only make routing decisions based on the network state information of the current node's connected nodes. Due to the short-sightedness of local adaptive routing algorithms, they only consider the network state of connected nodes and do not consider the network state information of the next-hop node. Specifically, assuming that the router only has one buffer queue with a buffer size of 4, and the rectangles in the router represent the buffers in the queue, such as... Figure 1 As shown, the currently waiting packet will select a candidate output port in dimension Y. However, from an overall perspective, the currently waiting packet should select a candidate output port in dimension X. To compensate for the shortsightedness of local adaptive routing algorithms, researchers have successively proposed various global adaptive routing algorithms. Although adaptive routing algorithms use increasingly rich network state information, problems such as information redundancy, insufficient information, and outdated information still exist, leading to inaccurate assessment of congestion status. Due to the inability to accurately assess network congestion, existing heuristic adaptive routing algorithms cannot effectively solve the load balancing problem. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide an efficient routing method and apparatus with dual-awareness on-chip network, which provides better adaptability by utilizing local network state information and uses forward-looking regional information to avoid congestion problems in the network in advance, thereby reducing message transmission delay and improving network performance.

[0005] The technical solution provided by this invention is as follows:

[0006] An efficient routing method for dual-aware on-chip networks includes the following steps:

[0007] Step 1: Pre-identify congested area nodes and boundary area nodes of the on-chip network;

[0008] Step 2: Receive the transmitted message and determine the candidate output port based on the minimum adaptive routing method;

[0009] Step 3: Calculate the buffer size and relative remaining jump value of the candidate output port;

[0010] Step 4: Compare the buffer size information of the candidate output ports to determine the output port direction; otherwise, determine whether the next-hop router corresponding to the candidate output port is located in the congested node area to determine the output port direction; otherwise, compare the candidate ports according to the relative remaining hop value and select the output port direction with the larger relative remaining hop value; otherwise, randomly select the output port direction to complete the packet transmission.

[0011] In step 1, the congested region nodes and the boundary region nodes are determined based on the tight centrality and betweenness centrality of the nodes.

[0012] The close centrality is calculated using the following formula:

[0013]

[0014] Where Cc(v) represents the compact centrality of node v, and d(v,u) represents the shortest path length from node v to node u;

[0015] The betweenness centrality is calculated using the following formula:

[0016]

[0017] Among them, C B (v) denotes the betweenness centrality of node v, σst(v) denotes the number of intermediate nodes of node v on the shortest path, and σ st This represents the number of shortest paths from node s to node t.

[0018] The on-chip network is a 2D Mesh network topology, with one candidate output port corresponding to each of the X and Y dimensions.

[0019] Step 4 is as follows: Specifically, compare the buffer sizes of candidate output ports in the X and Y dimensions, and select the candidate output port with the smaller value as the output port direction; otherwise, further determine whether the next-hop router node corresponding to the candidate output port is located in the congested node area. If the next-hop router node is in the congested node area, the packet continues to be transmitted according to the output port direction selected in the previous step; otherwise, compare the candidate ports based on the relative remaining hop count, and select the output port direction with the larger relative remaining hop count. If a decision cannot be made based on the relative remaining hop count, the output port is randomly selected.

[0020] The buffer size is calculated by the router node itself based on its credit value, specifically the total buffer size minus the free buffer size.

[0021] The relative remaining hop count is specifically the number of packets whose remaining hop count in the input port of the next-hop router is less than the remaining hop count of the current route packet, calculated using Euclidean distance based on the current router node number and the destination node number.

[0022] This invention also provides a high-efficiency routing device for dual-awareness on-chip networks, characterized in that it is applied to an on-chip network, the on-chip network including a plurality of router nodes, the router nodes including the device, to implement the above method, specifically including:

[0023] The data input port receives messages to be transmitted and obtains the size of the adjacent node buffer.

[0024] The shortest adaptive routing module compares the buffer sizes in the X and Y dimensions and determines the output port direction based on the network status information of the connected nodes.

[0025] The pre-selection congestion area module stores the coordinates of the congestion node area in a register. It receives the coordinates of the next-hop router from the shortest adaptive routing module and compares them with the coordinates in the register. If the next-hop router is located in the congestion node area, it returns "1"; otherwise, it returns "0". It uses an OR gate to obtain the final output port direction.

[0026] The module calculates the relative remaining jump steps, compares the candidate output ports based on the relative remaining jump step value, and selects the output port direction with the larger relative remaining jump step value; if a decision cannot be made based on the relative remaining jump step value, the output port is randomly selected.

[0027] The efficient routing method and apparatus for dual-aware on-chip networks provided by this invention provides better adaptability by utilizing local network state information and uses forward-looking regional information to avoid network congestion problems in advance, thereby reducing message transmission delay and having great practical value. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a schematic diagram illustrating the shortsightedness phenomenon in local adaptive routing algorithms.

[0030] Figure 2 This is a flowchart illustrating the efficient routing method for dual-sensing on-chip networks according to the present invention.

[0031] Figure 3 This diagram illustrates the area nodes and convenient area nodes of 4×4 and 8×8 2D Mesh networks.

[0032] Figure 4 The router shown is a schematic diagram of the architecture of the dual-aware high-efficiency routing method of the present invention.

[0033] Figure 5 This is a schematic diagram of the efficient routing method with dual sensing according to an embodiment of the present invention. Detailed Implementation

[0034] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0035] like Figure 2 The flowchart of the efficient routing method for dual-awareness on-chip networks of the present invention is as follows: The efficient routing method for dual-awareness provided by the present invention includes the following steps:

[0036] S1. Determine congestion and region information; pre-identify congested and boundary regions in the on-chip network based on two metrics: tight centrality and betweenness centrality. Tight centrality measures the proximity of a node to all other nodes, specifically calculated as the reciprocal of the average distance from a node to all other nodes. A higher tight centrality indicates that the node is closer to other nodes in the network and has better connectivity. Betweenness centrality measures the degree to which a node acts as a mediator in the shortest paths between other nodes in the network, i.e., the number of times the node appears in all shortest paths in the network. By using both tight centrality and betweenness centrality metrics to dual-identify congested regions in the network, congestion problems can be avoided in advance.

[0037] S2. Process the data packet, which carries information about the source node and the destination node; determine the legal candidate output port; under the 2DMesh network topology, the minimum adaptive route is used for route design, so there are at most two candidate output ports, one in the X dimension and one in the Y dimension.

[0038] S3. Calculate the congestion metric and obtain the connected node number; calculate the buffer size and relative remaining hop count RHC(Rport) of the candidate ports output in step 2. In addition, calculate the router number connected to the candidate port based on the pattern of router numbering in the 2D Mesh network topology.

[0039] The port buffer size is calculated by the router itself based on a credit value, which is a statistical measure of the free buffer size of neighboring nodes' ports. The buffer size of a port is the total buffer size minus the free buffer size.

[0040] The Relative Hop Count (RHC) value is calculated by taking the number of packets whose remaining hop count in the input port of the next-hop router is less than the remaining hop count of the current route packet. It is calculated using Euclidean distance based on the current node number and the destination node number.

[0041] S4. Select a suitable output port; compare the buffer size information of the candidate output ports calculated in step S3 to determine the output port direction. Specifically, compare the buffer sizes in the X and Y dimensions, and select the candidate output port with the smaller value as the output port direction. Otherwise, further determine whether the next-hop router corresponding to the candidate output port is located in a congested node area. If the next-hop router is in a congested node area, the packet continues to be transmitted according to the output port direction selected in the previous step; otherwise, compare the candidate ports based on the relative remaining hop count, and select the output port direction with the larger relative remaining hop count. If a decision cannot be made based on the relative remaining hop count, then a random output port is selected.

[0042] Step S1 details the design process. Tight centrality and betweenness centrality are two commonly used centrality parameters in network analysis, used to measure the importance of nodes in a network. These two parameters reveal the status and role of a node in the network from different perspectives. Tight centrality measures the proximity of a node to all other nodes; specifically, it is calculated as the reciprocal of the average distance from a node to all other nodes. The higher the tight centrality of a node, the closer it is to other nodes in the network, indicating better connectivity. The parameter Cc(v) calculates the tight centrality of node v using the following formula:

[0043]

[0044] Where d(v, u) represents the shortest path length from node v to node u. This invention designs an adaptive routing algorithm on a 2D Mesh network topology, thus calculating the Manhattan distance based on the node coordinates to obtain the shortest path length between two nodes. Betweenness centrality measures the degree to which a node acts as a mediator in the shortest paths between other nodes in a network, i.e., the number of times a node appears in all shortest paths in the network. The more shortest transmission paths a node appears on between other node pairs, the higher its betweenness centrality. Nodes with high betweenness centrality are often key bridges in the network, capable of propagating information between different nodes. This parameter index C... B (v) Calculate the betweenness centrality of node v, using the following formula:

[0045]

[0046] Where σst(v) represents the number of intermediate nodes of node v on the shortest path. st This represents the number of shortest paths from node s to node t.

[0047] Since the process of calculating tight centrality and betweenness centrality relies on data transmission between all nodes, but different synthetic traffic loads or applications have different traffic transmission characteristics, this scheme pre-divides the network area into congested area nodes and boundary area nodes, such as... Figure 3As shown, (a) represents a 4×4 2D Mesh network area node, and (b) represents an 8×8 2D Mesh network area node. The central red node is a congested area node, and the edge blue nodes are boundary area nodes. The dual-aware adaptive routing algorithm can pre-determine congested node areas to avoid network congestion. The dual-aware adaptive routing algorithm first uses the size of the local network state information buffer and the relative remaining hop count as the basis for routing decisions. Second, it pre-determines whether the next-hop router node corresponding to the output port is located in a congested node area. Finally, this adaptive routing algorithm improves routing adaptability through local network state information and avoids network congestion as early as possible by pre-determining congested areas. Therefore, the dual-aware adaptive routing algorithm is a low-overhead and efficient adaptive routing algorithm.

[0048] In a specific implementation, a high-efficiency routing device with on-chip network dual awareness is also provided, as shown in the schematic diagram below. Figure 4 As shown. This device is applied to a network-on-a-chip (NAT), which includes several router nodes. The classic virtual tunnel router microarchitecture of these router nodes mainly consists of: Input Units, Routing Computation Units, Virtual Channel Allocators (VC Allocators), Switch Allocators, Crossbars, and Output Units. Compared to the classic NAT microarchitecture, the dual-aware router microarchitecture adds a module for pre-determining congested areas and a module for calculating the relative remaining hops (RHC). To obtain buffer size information, the dual-aware router uses a credit link to obtain the congestion level. x and Congestion y Congestion value.

[0049] Specifically, the dual-aware routing device provided in this embodiment is designed based on the shortest adaptive routing algorithm, and all transmitted packets have at most two candidate output ports in two dimensions (X dimension and Y dimension). These include:

[0050] The data input port receives messages to be transmitted and uses a credit link to obtain the buffer size of adjacent nodes.

[0051] The shortest adaptive routing module compares the buffer sizes on the credit links in the X and Y dimensions and determines the output port based on the network status information of the connected nodes, thus making the routing algorithm highly adaptive.

[0052] The pre-selection congestion area determination module primarily determines whether the next-hop router is located within a congested node area. It stores the coordinates of the congested node area in a register and compares the coordinates of the next-hop router from the shortest adaptive route with the coordinates in the register. This module uses a comparator to perform the comparison; if the next-hop router is located within the congested node area, it returns "1"; otherwise, it returns "0". Finally, an OR gate is used to obtain the final output port direction.

[0053] The Relative Remaining Hop Count (RHC) module compares candidate output ports based on their relative remaining hop counts and selects the output port with the larger value. If a decision cannot be made based on the relative remaining hop count, an output port is randomly selected. This module utilizes RHC network state information to assess network congestion and improve the accuracy of network state information.

[0054] like Figure 5 This is a schematic diagram of the efficient routing method with dual-awareness according to an embodiment of the present invention. In this embodiment, the current packet is transmitted from the source router (0,0) to the destination router (3,3), as detailed below:

[0055] Step 1): Determine congestion and region information. In a 4×4 2D Mesh network topology, nodes in the middle 2×2 region have higher compact centrality than nodes in the boundary region. Similarly, in an 8×8 2D Mesh network topology, nodes in the middle 4×4 region also have higher compact centrality than nodes in the boundary region. Nodes in the middle region are closer to other nodes, indicating that nodes in the middle region are more prone to congestion. In a 4×4 2D Mesh network topology, nodes in the middle 2×2 region have higher betweenness centrality than nodes in the boundary region. In an 8×8 2D Mesh network topology, nodes in the middle 4×4 region also have higher betweenness centrality than nodes in the boundary region. Nodes in the middle region appear more frequently in the shortest paths of other nodes, indicating that nodes in the middle region are more prone to congestion. By calculating compact centrality and betweenness centrality, the network can be naturally divided into two parts: congested node region and boundary node region, as shown below. Figure 3 As shown.

[0056] Step 2): Determine the valid candidate output ports. In the 2D Mesh network topology, the minimum adaptive routing algorithm is used. The current packet is transmitted from the source router (0,0) to the destination router (3,3), and the candidate output ports are the east output port and the south output port.

[0057] Step 3): Calculate the congestion metric and obtain the connected node number. When measuring the network state of the east output port, the dual-sensor adaptive routing algorithm calculates the buffer size of router (0, 1). When measuring the network state of the south output port, the adaptive routing algorithm calculates the buffer size of router (1, 0).

[0058] Step 4): Select a suitable output port. The dual-aware adaptive routing algorithm also pre-determines whether the next-hop router corresponding to the candidate output port is located in a congested area. This adaptive routing algorithm will determine whether routers (0, 1) and (1, 0) are located in a congested node area. Figure 5 (The red node in the middle) is used to proactively avoid network congestion. If the next-hop router is located in a congested node area, the current packet continues to maintain the previous output port. Otherwise, the routing algorithm continues to evaluate the east and south output ports based on the relative remaining hop count information to better dynamically isolate congestion in the network.

[0059] It is understood that the present invention has been described through some embodiments, and those skilled in the art will recognize that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the invention. Furthermore, under the teachings of the present invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of the present invention.

Claims

1. A high-efficiency routing method for on-chip network dual-sensing, characterized in that, Includes the following steps: Step 1: Pre-identify congested region nodes and boundary region nodes in the on-chip network; congested region nodes and boundary region nodes are determined based on the tight centrality and betweenness centrality of the nodes. Step 2: Receive the transmitted message and determine the candidate output port based on the minimum adaptive routing method; Step 3: Calculate the buffer size and relative remaining jump value of the candidate output port; Step 4: Compare the buffer size information of the candidate output ports to determine the output port direction; Otherwise, determine whether the next-hop router corresponding to the candidate output port is located in a congested node area to determine the output port direction; Otherwise, the candidate ports are compared based on the relative remaining hop count, and the output port direction with the larger relative remaining hop count is selected; otherwise, the output port direction is randomly selected to complete the message transmission. The on-chip network is a 2D Mesh network topology, with one candidate output port corresponding to each of the X and Y dimensions; Step 4 is as follows: Specifically, compare the buffer sizes of candidate output ports in the X and Y dimensions, and select the candidate output port with the smaller value as the output port direction; otherwise, further determine whether the next-hop router node corresponding to the candidate output port is located in the congested node area. If the next-hop router node is in the congested node area, the packet continues to be transmitted according to the output port direction selected in the previous step; otherwise, compare the candidate ports based on the relative remaining hop count, and select the output port direction with the larger relative remaining hop count. If a decision cannot be made based on the relative remaining hop count, the output port is randomly selected.

2. The efficient routing method for on-chip network dual-awareness according to claim 1, characterized in that, The close centrality is calculated using the following formula: in, Cc(v) For nodes v tight centrality, d ( v,u ) represents a node v To the node u The shortest path length; The betweenness centrality is calculated using the following formula: in, C B (v) Represents a node v The centrality of the middle, σst(v) Represents a node v The number of intermediate nodes on the shortest path σ st Represents a node s To the node t The number of shortest paths.

3. The efficient routing method for on-chip network dual-awareness according to claim 2, characterized in that, The buffer size is calculated by the router node itself based on its credit value, specifically the total buffer size minus the free buffer size.

4. The efficient routing method for on-chip network dual-awareness according to claim 3, characterized in that, The relative remaining hop count is specifically the number of packets whose remaining hop count in the input port of the next-hop router is less than the remaining hop count of the current route packet, calculated using Euclidean distance based on the current router node number and the destination node number.

5. A high-efficiency routing device with on-chip network dual-sensing, characterized in that, Applied to a network-on-a-chip (NAT), the NAT includes a plurality of router nodes, each router node including the aforementioned device, the device implementing the method as described in any one of claims 1-4, specifically including: The data input port receives messages to be transmitted and obtains the size of the adjacent node buffer. The shortest adaptive routing module compares the buffer sizes in the X and Y dimensions and determines the output port direction based on the network status information of the connected nodes. The pre-selection congestion area module stores the coordinates of the congestion node area in a register. It receives the coordinates of the next-hop router from the shortest adaptive routing module and compares them with the coordinates in the register. If the next-hop router is located in the congestion node area, it returns "1"; otherwise, it returns "0". An OR gate is used to obtain the final output port direction. The module calculates the relative remaining jump steps, compares the candidate output ports based on the relative remaining jump step value, and selects the output port direction with the larger relative remaining jump step value; if a decision cannot be made based on the relative remaining jump step value, the output port is randomly selected.

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