DPDK multi-process-based message playback method, device, medium, and product

By using the DPDK multi-process message playback method, shared memory and load balancing algorithms, the resource waste problem caused by memory copying in traditional message playback tools is solved, achieving efficient message processing and throughput improvement.

CN120434209BActive Publication Date: 2025-09-12WUHAN BOYIXUN INFORMATION TECH CO LTD
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Patent Information

Application Number
CN202510935763.3
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2025-07-08
Publication Date
2025-09-12
Estimated Expiration
2045-07-08

AI Technical Summary

Technical Problem

Existing message playback tools frequently perform memory copy operations during data transmission, resulting in high CPU resource consumption and high latency, and are unable to meet the testing requirements of modern high-speed network environments.

Method used

A DPDK multi-process-based message playback method is adopted to achieve data interaction through shared memory. Combined with load balancing algorithms and multi-core parallel processing, memory copy operations are avoided and the computing power of multi-core CPUs is utilized.

Benefits of technology

Significantly reduce CPU and memory bandwidth consumption, improve message processing efficiency, increase system throughput, and meet network testing needs in high-concurrency and high-traffic scenarios.

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Abstract

The present application relates to the field of network message playback technology and discloses a DPDK multi-process-based message playback method, device, medium, and product. The method includes a message playback process and a packet processing process interacting with each other via shared memory. The message playback process reads messages from a PCAP file and loads them into the shared memory according to a preset sending mode. A load balancing algorithm is used to distribute messages in the shared memory to the packet processing process. The packet processing process reads messages from the shared memory, processes them in parallel using multi-core threads, and sends them to the target network. This method can at least address the technical issue of wasted message playback resources.
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Description

Technical Field

[0001] The present application relates to the technical field of network message playback, and in particular to a message playback method, device, medium, and product based on DPDK multi-process. Background Art

[0002] Most existing packet replay tools are based on virtual I / O technology. However, these tools have exposed numerous performance bottlenecks in practical applications. During data transmission, traditional tools require multiple memory copy operations, reading packet data from disk into kernel space, then copying it from kernel space to user space, and finally sending it to the network interface. This frequent memory copying not only consumes a large amount of CPU resources and reduces data processing efficiency, but also results in high latency, making the packet replay rate difficult to meet the testing requirements of modern high-speed network environments.

[0003] The continuous increase in network bandwidth and the explosive growth in data traffic have placed higher demands on the throughput and processing capabilities of packet playback tools. Traditional tools often suffer from insufficient processing power when faced with high-concurrency, high-traffic testing scenarios, failing to accurately simulate real network traffic, which in turn affects the performance evaluation and optimization of network devices and applications. Summary of the Invention

[0004] One purpose of the present application is to provide a DPDK multi-process-based message playback method, device, medium and product, at least to solve the technical problem of message playback resource waste.

[0005] To achieve the above objectives, some embodiments of the present application provide the following aspects:

[0006] In the first aspect, some embodiments of the present application also provide a message playback method based on DPDK multi-process, including a message playback process and a packet processing process interacting with data through shared memory; the message playback process is used to read messages from a PCAP file, and load the messages into the shared memory according to a preset sending mode, and at the same time use a load balancing algorithm to distribute the messages in the shared memory to the packet processing process; the packet processing process is used to read messages from the shared memory, use multi-core threads to process the messages in parallel and send them to the target network.

[0007] In a second aspect, some embodiments of the present application further provide an electronic device comprising: one or more processors; and a memory storing computer program instructions, wherein the computer program instructions, when executed, cause the processor to perform the steps of the method described above.

[0008] In a third aspect, some embodiments of the present application further provide a computer-readable medium having computer program instructions stored thereon, wherein the computer program instructions can be executed by a processor to implement the method described above.

[0009] In a fourth aspect, some embodiments of the present application further provide a computer program product, comprising a computer program / instruction, which implements the steps of the above-described method when executed by a processor.

[0010] Compared with related technologies, the solution provided in the embodiment of the present application uses DPDK shared memory to achieve zero-copy data interaction, eliminating the CPU and memory bandwidth overhead caused by frequent memory copies in traditional virtual I / O technology; based on a multi-core parallel processing framework and a dynamic load balancing algorithm, the system throughput increases approximately linearly with the number of CPU cores, breaking through the single-core performance bottleneck; it supports three sending modes: original speed, full speed, and fixed bps, and through time difference simulation, immediate sending, and token bucket precise speed limiting, it covers a variety of scenarios such as real traffic reproduction, extreme performance testing, and custom rate control. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0012] Figure 1 A flowchart of a message playback method based on DPDK multi-process provided according to an embodiment of the present application;

[0013] Figure 2 A flowchart of another method for replaying messages based on DPDK multi-process according to an embodiment of the present application is provided;

[0014] Figure 3 Schematic diagram of a flow chart of a method for original speed playback provided according to an embodiment of the present application;

[0015] Figure 4 A flowchart of a full-speed playback method provided according to an embodiment of the present application is shown;

[0016] Figure 5 A flowchart of a fixed-speed playback method provided according to an embodiment of the present application is shown;

[0017] Figure 6 This is a schematic diagram of an exemplary structure of an electronic device provided according to an embodiment of the present application. DETAILED DESCRIPTION

[0018] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0019] First embodiment

[0020] The first embodiment of the present application relates to a message playback method based on DPDK multi-process. Figure 1 As shown, the method may include the following steps:

[0021] S101: The message playback process and the packet processing process exchange data through shared memory:

[0022] The packet replay process creates a shared memory space to store pending packet data. The packet processing process registers and maps to this shared memory area using the memory access interface provided by DPDK, establishing a direct data channel between the two processes. This shared memory mechanism avoids the overhead of multiple memory copies in traditional virtual I / O technologies, allowing packet data to be directly read and manipulated by both processes, significantly reducing CPU and memory bandwidth consumption.

[0023] S102, the message playback process is used to read the message from the PCAP file and load the message into the shared memory according to a preset sending mode:

[0024] The message playback process reads raw messages stored on disk into user space in a single pass, using PCAP files as units, without passing through the kernel. During reading, the message data, along with metadata such as timestamp and length, is formatted and stored in shared memory based on the preset transmission mode (e.g., original rate, full rate, or fixed rate).

[0025] S103: Distribute the messages in the shared memory to the packet processing process using a load balancing algorithm.

[0026] The message replay process monitors the multi-core thread status of the packet processing process (e.g., thread idleness, current processing workload, etc.) and uses a load balancing algorithm (such as round-robin, hashing, or dynamic load distribution strategies, the specific algorithm is not limited) to dynamically distribute messages in shared memory to different processing threads. For example, the round-robin algorithm sequentially distributes messages to each thread, ensuring a balanced processing workload for each thread. The dynamic load distribution algorithm prioritizes messages to threads with lower current loads based on real-time CPU core load, preventing overloading of some cores while leaving others idle, thus achieving efficient utilization of multi-core resources.

[0027] S104: The packet processing process is used to read the message from the shared memory, process the message in parallel using multi-core threads, and send the message to the target network.

[0028] Each processing thread in the packet processing process is bound to a separate CPU core and directly reads assigned packet data through a shared memory interface, eliminating the need for additional data copying. Each thread executes packet processing logic (such as protocol parsing and traffic forwarding) in parallel. Once processed, the packet is sent to the target network via the high-speed network interface provided by DPDK. This multi-core parallel processing architecture fully unleashes the computing power of multi-core processors, increasing system throughput linearly with the number of CPU cores, meeting the packet playback requirements in high-concurrency, high-traffic scenarios.

[0029] It is not difficult to find that compared with the related technology, the solution provided in the embodiment of the present application utilizes the high-performance packet processing framework of DPDK, and the packet processing process and the packet playback process realize the transmission of packets through shared memory, avoiding the memory copy operation in the traditional virtual I / O technology, and significantly reducing the CPU overhead and memory bandwidth occupancy; the packet processing process directly accesses the packet data in the shared memory without the need for additional data copying, thereby greatly improving the efficiency of packet processing and being able to handle higher throughput network traffic; the DPDK framework naturally supports multi-core parallel processing, and the main packet playback process can make full use of the computing power of the multi-core processor to improve the overall throughput and response speed of the system.

[0030] Second embodiment

[0031] The second embodiment of the present application relates to a method for replaying packets based on DPDK multi-process. The second embodiment is an improvement on the first embodiment, and the specific improvements are:

[0032] like Figure 2 As shown in the figure, after the message playback tool is started, the messages in the PCAP file are batch read into the message buffer pool of the shared memory, and then the sending mode selection is entered: the original speed playback mode controls the queue entry rate according to the original speed time of the message; the full speed playback mode immediately adds the read message to the packet processing queue; the fixed bps playback mode uses the token bucket to control the overall queue entry rate.

[0033] Next, a packet processing queue is selected using a load balancing algorithm (such as round-robin), and packets cached in shared memory are added to the queue to ensure balanced task distribution. During playback, real-time playback statistics are output, including playback rate (pps or bps), packet loss rate, and shared memory usage, providing users with a basis for monitoring and adjustment.

[0034] After the packet processing process starts, it initializes shared resources (such as registering shared memory areas and communication interfaces). Each packet processing thread is initialized and a packet processing queue is assigned to each thread. Each thread is bound to an independent CPU core and executes different tasks in parallel, leveraging multi-core parallel processing to improve packet processing and delivery efficiency.

[0035] Third embodiment

[0036] The third embodiment of the present application relates to a method for replaying packets based on DPDK multi-process. The third embodiment is an improvement on the first embodiment, and the specific improvements are:

[0037] The sending modes include: original speed mode, full speed mode and fixed speed mode.

[0038] like Figure 3 As shown, the original speed mode includes: reading all messages in the file into shared memory in units of PCAP files, saving the time difference between the current message and the first message as the first time difference when reading the current message, and recording the first message reading time as the program reference time; when the program is running, subtracting the program current time from the program reference time to obtain a second time difference; when the second time difference exceeds the first time difference, adding the current message to the packet processing queue.

[0039] After starting playback at full speed, the system reads all packets in the PCAP file into shared memory at once. As each packet is read, the system obtains the time difference between the current packet and the first packet, saving it as the first time difference. The system also records the time the first packet was read as the program's reference time.

[0040] During the program running process, the system calculates the difference between the current time of the program and the reference time of the program in real time to obtain the second time difference. At this time, the system will compare the second time difference with the first time difference of each message. When the second time difference exceeds the first time difference of a certain message, it means that the time point when the message should be sent at the original speed has been reached. The system adds the current message to the packet processing queue to achieve the effect of playing back the message at the original rate. Subsequently, the system continues to determine whether all messages in the current file have been sent: if not, continue to process the next message and repeat the above comparison operation; if all messages in the current file have been sent, then determine whether all PCAP files have been sent. If all are completed, end the process, otherwise continue to process the next PCAP file. In this way, the time characteristics of the original network traffic are accurately simulated to meet the needs of time-sensitive network testing scenarios.

[0041] like Figure 4As shown, the full-speed mode includes: reading all packets in the file into the shared memory in units of PCAP files, processing each packet in turn, and adding each packet to the packet processing queue.

[0042] When full-speed playback is triggered, the system reads all packets within a PCAP file into shared memory at once, processing each packet in turn. Each packet is then processed sequentially and added to the packet processing queue upon completion. Upon addition, the system immediately determines whether all packets in the current file have been sent. If not, the system proceeds to the next packet, repeating the process of processing and adding it to the packet processing queue. If all packets in the current file have been sent, the system further determines whether all PCAP files have been sent. If all PCAP files have been sent, the process ends. If any unprocessed PCAP files exist, the system proceeds to the next PCAP file, extracting all packets from that file, processing them sequentially, and adding them to the packet processing queue, repeating this cycle until all PCAP files have been processed. In this way, full-speed mode ignores the original time interval between packets and sends packets to the packet processing queue as quickly as possible. This makes it ideal for quickly testing the processing limits of network equipment, applying high traffic pressure to network equipment in a short period of time to verify its performance under extreme loads.

[0043] like Figure 5 As shown in the figure, the fixed-rate mode includes: using the token bucket algorithm for flow rate control, reading all messages in the file into the shared memory in units of PCAP files, obtaining a pass token before each message is queued, and the number of pass tokens obtained is the time difference between the current time and the last time the token was obtained multiplied by the user-specified flow rate; the original traffic is deducted from the number of "pass tokens" and added to the packet processing queue.

[0044] First, a user-specified fixed flow rate (bps) is obtained to define the flow control target. All packets within the file are then read, in units of PCAP files, into shared memory for buffering. Before each packet is queued, the time difference between the program's execution time and the last token acquisition is calculated. This time difference is multiplied by the user-specified flow rate to calculate the number of currently available pass tokens. After deducting the corresponding number of "pass tokens" from the original traffic, the current packet is added to the packet processing queue. After processing the current packet, a check is performed to determine whether all packets in the current file have been sent. If not, the next packet is processed, repeating the token acquisition, token deduction, and enqueuing steps. If all packets in the current file have been sent, the check is further performed to determine whether all PCAP files have been sent. If all PCAP files have been sent, the process ends. If not, the next PCAP file is processed until all are processed. A token bucket algorithm precisely controls the packet enqueue rate, ensuring that playback traffic remains stable at the user-specified flow rate. This meets diverse network testing requirements and is particularly suitable for scenarios requiring simulation of specific bandwidth environments.

[0045] Using a load balancing algorithm to distribute the messages in the shared memory to the packet processing process includes: the message playback process dynamically distributes the messages to the corresponding packet processing threads according to the multi-core thread status of the packet processing process; calculating the load balance of the packet processing threads through a load balancing algorithm, and the load balancing algorithm includes a polling algorithm, a hash algorithm or dynamic distribution based on the CPU core load.

[0046] When dispatching packets, the message replay process continuously monitors the multi-core thread status of the packet processing process. This status information includes thread busyness, number of packets processed, CPU utilization, and more. Based on this real-time status, the message replay process dynamically assigns packets in shared memory to the appropriate packet processing thread, ensuring that the load on each thread is as balanced as possible, avoiding situations where some threads are overloaded while others are idle.

[0047] The packet processing process is used to read the message from the shared memory, including: the packet processing process reads the message captured by the message playback process through the shared memory; after obtaining the message, the corresponding message processing task is assigned to the corresponding packet processing thread; the packet processing thread is bound to an independent CPU core.

[0048] The packet processing process and the message playback process establish an efficient data exchange channel through shared memory. After the message playback process reads and processes the messages from the PCAP file according to the preset mode and loads them into the shared memory, the packet processing process reads these messages directly from the shared memory through the pre-configured shared memory access interface.

[0049] After successfully receiving a packet, the packet processing process assigns the corresponding packet processing tasks to the corresponding packet processing thread based on specific rules. This allocation process can be implemented in conjunction with the previously mentioned load balancing algorithm. For example, if a round-robin algorithm is used, the packet processing process will assign packet processing tasks sequentially according to the order of the threads. If a hash algorithm is used, a hash value is calculated based on the specific characteristics of the packet (such as the source IP address and destination IP address), and the task is assigned to the corresponding thread based on the hash value. If a dynamic allocation algorithm based on CPU core load is used, the packet processing process will monitor the load of the CPU core to which each packet processing thread is bound in real time and prioritize packet processing tasks to threads with lower loads to achieve balanced utilization of system resources.

[0050] To fully leverage the performance advantages of multi-core CPUs, each packet processing thread is bound to a separate CPU core. Thread binding is implemented through mechanisms provided by the operating system. By pinning a thread to a specific CPU core, it avoids the context switching overhead associated with frequent thread switching between cores and improves thread execution efficiency. When a packet processing thread receives a packet processing task, it processes the message in parallel on the bound CPU core, performing operations such as parsing, protocol analysis, modification, and forwarding. Once processing is complete, the message is sent to the target network.

[0051] Through the above approach, the packet processing process can efficiently read messages from the shared memory and quickly process messages using the parallel processing capabilities of the multi-core CPU, thereby improving the performance and processing efficiency of the entire message playback system.

[0052] When the packet processing process completes processing a batch of packets (e.g., sending them to the target network or completing a specified service), it sends a playback completion response to the packet replay process. Upon receiving this response, the packet replay process immediately initiates statistical operations: Statistical replay rate: This records the number of processed packets or bytes reported by the packet processing process during that time period, measured in units of time (e.g., per second). These statistical metrics (such as replay rate and shared memory usage) are recorded in real time by the packet replay process and provided to users through log output and visual interfaces. This allows users to monitor the replay status in real time, enabling them to adjust sending modes, optimize load balancing strategies, or expand resources, ensuring efficient and stable operation of the packet replay process.

[0053] The step division of the above various methods is only for the purpose of clear description. During implementation, they can be combined into one step or some steps can be split and decomposed into multiple steps. As long as they include the same logical relationship, they are all within the scope of protection of this application; adding insignificant modifications or introducing insignificant designs to the algorithm or process without changing the core design of the algorithm and process are all within the scope of protection of this application.

[0054] In addition, some embodiments of the present application further provide an electronic device. The electronic device may be various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, etc. The electronic device may also be various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices.

[0055] The electronic device includes: one or more processors; and a memory storing computer program instructions, wherein the computer program instructions, when executed, enable the processor to perform the steps of the method provided in any one or more of the above embodiments. Figure 6 An exemplary structural diagram of the electronic device is disclosed. Figure 6 As shown, the electronic device includes: one or more processors 1101, memory 1102, and interfaces for connecting various components, including high-speed and low-speed interfaces. The various components are interconnected using different buses and can be mounted on a common motherboard or in other ways as needed. The processor can process instructions executed within the electronic device, including instructions stored in or on the memory for displaying graphical information of a GUI on an external input / output device (such as a display device coupled to the interface). In some other embodiments, if desired, multiple processors and / or multiple buses can be used with multiple memories and multiple storage devices. Similarly, multiple electronic devices can be connected, with each device providing some of the necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present application described and / or claimed herein.

[0056] The electronic device may further include: an input device 1103 and an output device 1104. The processor 1101, the memory 1102, the input device 1103 and the output device 1104 may be connected via a bus or other means. Figure 6 The bus connection is taken as an example.

[0057] Input device 1103 can receive input digital or character information and generate key signal input related to user settings and function control of the electronic device. Examples include a touch screen, keypad, mouse, trackpad, touchpad, pointing stick, one or more mouse buttons, trackball, joystick, and other input devices. Output device 1104 may include a display device, auxiliary lighting devices (e.g., LEDs), and tactile feedback devices (e.g., vibration motors). The display device may include, but is not limited to, a liquid crystal display (LCD), a light-emitting diode (LED) display, and a plasma display. In some embodiments, the display device may be a touch screen.

[0058] To provide user interaction, the electronic device may be a computer. The computer includes a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user, as well as a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices may also be used to provide user interaction; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback), and input from the user may be received in any form, including acoustic input, voice input, or tactile input.

[0059] In the embodiments of the present application, a computer program / instruction is stored on a computer-readable medium. When executed by a processor, the computer program / instruction implements the steps of the method provided in any one or more of the above embodiments. The computer-readable medium may be included in the electronic device described in the above embodiments, or it may exist independently and not be incorporated into the device. The computer-readable medium carries one or more computer-readable instructions.

[0060] The memory 1102 can be used as a non-transitory computer-readable storage medium to store non-transitory software programs, non-transitory computer executable programs, and modules. The processor 1101 executes the non-transitory software programs, instructions, and modules stored in the memory 1102 to execute various functional applications and data processing of the server, thereby implementing the program instructions / modules corresponding to the method provided in any one or more of the above embodiments of the present application.

[0061] The memory 1102 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and applications required for at least one function; the data storage area may store data created based on the use of the electronic device, etc. In addition, the memory 1102 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory 1102 may optionally include a memory remotely located relative to the processor 1101, and these remote memories may be connected to the electronic device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0062] It should be noted that the computer-readable medium described in this application may be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. Computer-readable media may include, for example, but not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or components, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to, an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In this application, a computer-readable medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, device, or component.

[0063] Computer-readable media includes both permanent and non-permanent, removable and non-removable media, and can be implemented using any method or technology for information storage. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc-read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic tape, disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device.

[0064] Computer program code for performing the operations of the present application can be written in one or more programming languages, or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0065] In the above embodiments, all or part of the embodiments may be implemented using software, hardware, firmware, or any combination thereof. For example, implementation may be achieved using an application-specific integrated circuit (ASIC), a general-purpose computer, or any other similar hardware device. In some embodiments, the software program of the present application may be executed by a processor to implement the above steps or functions. Similarly, the software program of the present application (including related data structures) may be stored in a computer-readable recording medium, such as a RAM memory, a magnetic or optical drive, a floppy disk, or the like. In addition, some steps or functions of the present application may be implemented using hardware, for example, as a circuit that cooperates with a processor to perform the various steps or functions.

[0066] The computer program product provided in the embodiments of the present application includes one or more computer programs / instructions, which, when executed by a processor, generate, in whole or in part, the processes or functions described in the embodiments of the present application. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or data center that includes one or more available media. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state disk (SSD)).

[0067] The flowcharts or block diagrams in the accompanying drawings illustrate the possible architectures, functions and operations of the devices, methods and computer program products according to various embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, program segment or part of code, and the module, program segment or part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, as well as the combination of boxes in the block diagram and / or flowchart, can be implemented with a dedicated hardware-specific system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0068] The scope of this application is defined by the appended claims rather than the foregoing description and is therefore intended to encompass within this application all changes that come within the meaning and range of equivalents of the claims. Any reference signs in the claims should not be construed as limiting the claims to which they relate. In addition, it is clear that the word "comprising" does not exclude other units or steps, and the singular does not exclude the plural. Multiple units or devices stated in a device claim may also be implemented by one unit or device through software or hardware. Words such as "first" and "second" are only used to distinguish the description and do not indicate any particular order, nor should they be understood as indicating or implying relative importance.

[0069] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any person skilled in the art may easily propose variations or substitutions within the technical scope disclosed in the present application, and such variations or substitutions shall be encompassed within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be subject to the scope of protection of the claims, and the above embodiments shall be regarded as exemplary and non-limiting.

Claims

1. A message playback method based on DPDK multi-process, characterized in that: The method comprises: The message playback process and the packet processing process exchange data through shared memory; The message playback process is used to read messages from the PCAP file and load the messages into the shared memory according to a preset sending mode, and at the same time use a load balancing algorithm to distribute the messages in the shared memory to the packet processing process; The packet processing process is used to read the message from the shared memory, process the message in parallel using multi-core threads and send the message to the target network.

2. The method according to claim 1, characterized in that The sending modes include: original speed mode, full speed mode and fixed speed mode.

3. The method according to claim 2, characterized in that The original speed mode includes: Read all messages in the file into shared memory in units of PCAP files. When reading the current message, save the time difference between the current message and the first message as the first time difference, and record the time when the first message is read as the program reference time. When the program is running, the current time of the program is subtracted from the program reference time to obtain a second time difference; when the second time difference exceeds the first time difference, the current message is added to the packet processing queue.

4. The method according to claim 2, characterized in that The full speed mode includes: Read all packets in the PCAP file into shared memory, process each packet in turn, and add each packet to the packet processing queue.

5. The method according to claim 2, characterized in that The fixed speed mode includes: The token bucket algorithm is used for flow rate control. All messages in the file are read into shared memory in units of PCAP files. A pass token is obtained before each message is queued. The number of pass tokens obtained is the time difference between the current time and the last time the token was obtained multiplied by the user-specified flow rate; after deducting the number of pass tokens from the remaining number of tokens in the original token bucket, the current message is added to the packet processing queue.

6. The method according to any one of claims 1 to 5, characterized in that The adopting of a load balancing algorithm to distribute the messages in the shared memory to the packet processing process comprises: The message playback process dynamically allocates messages to corresponding packet processing threads according to the multi-core thread status of the packet processing process; The load balancing algorithm is used to calculate the load balance of the packet processing threads. The load balancing algorithm includes a round-robin algorithm, a hash algorithm, or a dynamic allocation based on the CPU core load.

7. The method according to claim 6, characterized in that The packet processing process is used to read the message from the shared memory, including: The packet processing process reads the message captured by the message playback process through the shared memory; After acquiring the message, the corresponding message processing task is assigned to the corresponding packet processing thread; the packet processing thread is bound to an independent CPU core.

8. An electronic device, characterized in that: The electronic device comprises: one or more processors; and A memory storing computer program instructions, which, when executed, cause the processor to perform the steps of the method according to any one of claims 1 to 7.

9. A computer-readable medium having a computer program / instruction stored thereon, characterized in that: When the computer program / instructions are executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instructions are executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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