Image sensor based on gain adjustment and control method

Abstract

The invention provides an image sensor based on gain adjustment and a control method. The image sensor comprises a plurality of pixel blocks arranged in an array and a node sharing structure. The pixel block comprises a light sensing unit, an overflow unit and a gain unit, the light sensing unit and the gain unit are coupled to the first floating diffusion node, the overflow unit is coupled to the light sensing unit or the gain unit, and the light sensing unit generates a first charge signal and a second charge signal based on photoelectric conversion and stores the first charge signal; the overflow unit is used for storing the second charge signal, and the gain unit is used for switching different gain modes; the node sharing structure is coupled between the gain units of the at least two pixel blocks and is used for increasing the storage capacity of the first floating diffusion node based on node sharing when the gain units are opened. According to the invention, the problem that the storage capacity of the image sensor in a low-gain mode cannot be suitable for highlight scene demands and gradually increases is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of image sensors, and particularly to an image sensor based on gain adjustment and a control method therefor. Background Art

[0002] Existing image sensors can achieve a large dynamic range by designing a low-gain mode and a high-gain mode. However, the storage capacity in the low-gain mode is fixed and cannot meet the increasing requirements of high-light scenarios. As a result, the fineness of the output image becomes insufficient when the requirements of high-light scenarios increase gradually. Therefore, how to improve the storage capacity of an image sensor in the low-gain mode is a technical problem that those skilled in the art urgently want to solve.

[0003] It should be noted that the above introduction of the technical background is only for the convenience of clearly and completely explaining the technical solution of the present invention and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art just because these solutions are described in the background art part of the present invention. Summary of the Invention

[0004] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide an image sensor based on gain adjustment and a control method therefor, which are used to solve the problem that the storage capacity of the existing image sensor in the low-gain mode cannot meet the increasing requirements of high-light scenarios.

[0005] To achieve the above object and other related objects, the present invention provides an image sensor based on gain adjustment, including a plurality of pixel blocks arranged in an array and a node sharing structure;

[0006] Each pixel block includes a photosensitive unit, an overflow unit, and a gain unit. The photosensitive unit and the gain unit are coupled to a first floating diffusion node. The overflow unit is coupled to the photosensitive unit or the gain unit. The photosensitive unit generates a first charge signal and a second charge signal based on photoelectric conversion and stores the first charge signal. The overflow unit is used to store the second charge signal. The gain unit is used to switch between different gain modes;

[0007] The node sharing structure is coupled between the gain units of at least two pixel blocks and is used to increase the storage capacity of the first floating diffusion node based on node sharing when the gain unit is turned on.

[0008] Optionally, when the overflow unit is coupled to the photosensitive unit, the overflow unit includes an overflow path and a quantization path, and the second charge signal is stored in the overflow unit through the overflow path and transferred to the second floating diffusion node through the quantization path, wherein the first charge signal is transferred to the first floating diffusion node.

[0009] Optionally, when the overflow unit is coupled to the photosensitive unit, the overflow unit includes an overflow path and a quantization path, and the second charge signal is stored in the overflow unit through the overflow path and transferred to the first floating diffusion node through the quantization path, wherein the first charge signal is transferred to the first floating diffusion node.

[0010] Optionally, the second charge signal is stored in the overflow unit through the overflow path and transferred to the second floating diffusion node through the quantization path, wherein:

[0011] The first floating diffusion node and the second floating diffusion node belong to the same pixel block, and the pixel block further includes a first reset unit, a second reset unit, a first readout unit, and a second readout unit; the first reset unit is coupled to the first floating diffusion node through the gain unit and is configured to reset the first floating diffusion node and the photosensitive unit; the second reset unit is coupled to the second floating diffusion node and is configured to reset the second floating diffusion node; the first readout unit is coupled to the first floating diffusion node and is configured to at least perform quantization readout on the first charge signal transferred to the first floating diffusion node; the second readout unit is coupled to the second floating diffusion node and is configured to at least perform quantization readout on the second charge signal transferred to the second floating diffusion node; the first reset unit and / or the second reset unit are further configured to reset the overflow unit;

[0012] Alternatively, the first floating diffusion node and the second floating diffusion node belong to pixel blocks in different rows in the same column, and the pixel block further includes a third reset unit and a third readout unit; the third reset unit is coupled to the corresponding floating diffusion node through the gain unit and is configured to reset the corresponding floating diffusion node, the photosensitive unit, and the overflow unit; the third readout unit is coupled to the corresponding floating diffusion node and is configured to at least perform quantization readout on the corresponding charge signal transferred to the corresponding floating diffusion node. [[ID=?]]

[0013] Optionally, when the pixel block includes a first readout unit and a second readout unit, the first readout unit and the second readout unit perform quantization readout through different column lines; when the pixel block includes a third readout unit, the third readout units of the pixel blocks in different rows in the same column perform quantization readout through different column lines.

[0014] Optionally, when the first floating diffusion node and the second floating diffusion node belong to pixel blocks in different rows of the same column, the pixel blocks in different rows of the same column include pixel blocks in adjacent two rows of the same column; wherein, among the pixel blocks in adjacent two rows of the same column, the pixel block in the upper row always uses the floating diffusion node corresponding to the pixel block in the lower row as its second floating diffusion node, or the pixel block in the lower row always uses the floating diffusion node corresponding to the pixel block in the upper row as its second floating diffusion node; or, the floating diffusion nodes corresponding to the two pixel blocks are each other's second floating diffusion nodes.

[0015] Optionally, the overflow unit includes a first overflow transistor, a first quantization transistor, and a first storage device; the control terminal of the first overflow transistor receives a first overflow control signal, the first terminal is coupled to the photosensitive unit, and the second terminal is coupled to the first terminal of the first storage device; the control terminal of the first quantization transistor receives a first quantization control signal, the first terminal is coupled to the second floating diffusion node or is coupled to the second floating diffusion node through the gain unit or is coupled to the first floating diffusion node through the corresponding gain unit, and the second terminal is coupled to the first terminal of the first storage device; the second terminal of the first storage device is coupled to a reference potential; wherein, the path where the first overflow transistor is located is the overflow path, and the path where the first quantization transistor is located is the quantization path;

[0016] Or, when the first floating diffusion node and the second floating diffusion node belong to the same pixel block, the overflow unit removes the first quantization transistor, and at this time, the first terminal of the first storage device is further coupled to the second floating diffusion node.

[0017] Optionally, when the first floating diffusion node and the second floating diffusion node belong to pixel blocks in different rows of the same column, the overflow unit includes a second overflow transistor, a second quantization transistor, and a second storage device; the control terminal of the second overflow transistor receives a second overflow control signal, the first terminal is coupled to the photosensitive unit, and the second terminal is coupled to the first terminal of the second storage device; the control terminal of the second quantization transistor receives a second quantization control signal, the first terminal is coupled to the second floating diffusion node through the gain unit corresponding to the second floating diffusion node by the node sharing structure, and the second terminal is coupled to the first terminal of the second storage device; the second terminal of the second storage device is coupled to a reference potential; wherein, the path where the second overflow transistor is located is the overflow path, and the path where the second quantization transistor is located is the quantization path.

[0018] Optionally, the node sharing structure includes a first connection line, which is coupled between the gain units of at least two pixel blocks.

[0019] Optionally, the node sharing structure further includes at least one first switching transistor, serially coupled to the first connection line, and its control terminal receives a first switching control signal.

[0020] Optionally, when the overflow unit is coupled to the gain unit, the overflow unit includes a common path, and the second charge signal is stored in the overflow unit through the common path and transferred to the first floating diffusion node through the common path, wherein the first charge signal is transferred to the first floating diffusion node;

[0021] The pixel block further includes a fourth reset unit and a fourth readout unit; the fourth reset unit is coupled to the first floating diffusion node through the gain unit, and is configured to reset the first floating diffusion node, the photosensitive unit, and the overflow unit; the fourth readout unit is coupled to the first floating diffusion node, and is configured to at least perform quantization readout on the first charge signal and the second charge signal transferred to the first floating diffusion node.

[0022] Optionally, the overflow unit includes an overflow quantization transistor and a third storage device; the control terminal of the overflow quantization transistor receives an overflow quantization control signal, the first end is coupled to the high-gain quantization node or the low-gain quantization node of the gain unit, and the second end is coupled to the first end of the third storage device; the second end of the third storage device is coupled to a reference potential; wherein, the path where the overflow quantization transistor is located is the common path;

[0023] When the first end of the overflow quantization transistor is coupled to the high-gain quantization node of the gain unit, the node sharing structure includes a second connection line, coupled between the gain units of at least two pixel blocks; when the first end of the overflow quantization transistor is coupled to the low-gain quantization node of the gain unit, the node sharing structure further includes a second switching transistor, serially coupled to the second connection line, and its control terminal receives a second switching control signal;

[0024] And / or, the fourth readout units of the pixel blocks in different rows in the same column perform quantization readout through different column lines.

[0025] The present invention further provides a control method for an image sensor based on gain adjustment as described above, including:

[0026] Quantization stage, performing quantization readout on the first charge signal in different gain modes, and performing quantization readout on the second charge signal; wherein, when the gain unit is turned on, node sharing is performed through the node sharing structure to increase the storage capacity of the first floating diffusion node.

[0027] Optionally, when the overflow unit is coupled to the photosensitive unit, the quantization stage includes:

[0028] Controlling the node sharing structure to open, controlling the gain unit to open and then close, so as to perform quantization readout of the first reset signal in the first gain mode and the second gain mode respectively based on the shared node and the first floating diffusion node, controlling the gain unit to close and then open, so as to perform quantization readout of the first charge signal in the second gain mode and the first gain mode respectively based on the first floating diffusion node and the shared node;

[0029] Controlling the quantization path in the overflow unit to close, so as to perform quantization readout of the second reset signal based on the second floating diffusion node or a new node including the second floating diffusion node or the first floating diffusion node, controlling the quantization path to open, so as to perform quantization readout of the second charge signal based on the second floating diffusion node or a new node including the second floating diffusion node or the first floating diffusion node; and / or, controlling the quantization path in the overflow unit to open, so as to perform quantization readout of the second charge signal based on the second floating diffusion node or a new node including the second floating diffusion node or the first floating diffusion node, performing a reset operation on the second floating diffusion node or the first floating diffusion node, so as to perform quantization readout of the second reset signal based on the second floating diffusion node or a new node including the second floating diffusion node or the first floating diffusion node.

[0030] Optionally, when performing quantization readout of the second reset signal and the second charge signal based on the second floating diffusion node or a new node including the second floating diffusion node, if the first floating diffusion node and the second floating diffusion node belong to the same pixel block, the second charge signal is quantized and read out simultaneously with the first charge signal in the first gain mode or the second gain mode, if the first floating diffusion node and the second floating diffusion node belong to pixel blocks in different rows in the same column, the second charge signal is quantized and read out simultaneously with the first charge signal in the second gain mode; and / or, for the case where the second reset signal is quantized and read out before the second charge signal: if the first floating diffusion node and the second floating diffusion node belong to the same pixel block, the second reset signal is quantized and read out simultaneously with the first reset signal in the first gain mode or the second gain mode, if the first floating diffusion node and the second floating diffusion node belong to pixel blocks in different rows in the same column, the second reset signal is quantized and read out simultaneously with the first reset signal in the second gain mode.

[0031] Optionally, when the overflow unit is coupled to the low-gain quantization node of the gain unit, the quantization stage includes:

[0032] Control the common path and the gain unit in the overflow unit of the read row to be turned on and control the node sharing structure to be turned off, so as to perform quantization readout of the second charge signal based on the first floating diffusion node, and perform a reset operation on the first floating diffusion node to perform quantization readout of the second reset signal based on the first floating diffusion node;

[0033] Control the common path in the overflow unit of the read row to be turned off and control the node sharing structure to be turned on, control the gain unit of the read row to be turned on and then turned off, so as to perform quantization readout of the first reset signal in the first gain mode and the second gain mode based on the shared node and the first floating diffusion node respectively, control the gain unit of the read row to be turned off and then turned on, so as to perform quantization readout of the first charge signal in the second gain mode and the first gain mode based on the first floating diffusion node and the shared node respectively.

[0034] Optionally, when the overflow unit is coupled to the high-gain quantization node of the gain unit, the quantization stage includes:

[0035] Control the common path in the overflow unit of the read row to be turned off and control the node sharing structure to be turned on, control the gain unit of the read row to be turned on and then turned off, so as to perform quantization readout of the first reset signal in the first gain mode and the second gain mode based on the shared node and the first floating diffusion node respectively, control the gain unit of the read row to be turned off and then turned on, so as to perform quantization readout of the first charge signal in the second gain mode and the first gain mode based on the first floating diffusion node and the shared node respectively;

[0036] Control the common path in the overflow unit of the read row to be turned on and the gain unit to be turned off, so as to perform quantization readout of the second charge signal based on the first floating diffusion node, perform a reset operation on the first floating diffusion node to perform quantization readout of the second reset signal based on the first floating diffusion node, and / or, control the gain unit to be turned off to perform quantization readout of the second reset signal based on the first floating diffusion node, then control the common path in the overflow unit of the read row to be turned on and then turned off, transfer the second charge signal to the first floating diffusion node through the common path, so as to perform quantization readout of the second charge signal based on the first floating diffusion node.

[0037] As described above, the gain-adjusted image sensor and control method of the present invention realize, through the design of pixel blocks and node sharing structures, that when the gain unit is turned on, node sharing is performed through the node sharing structure to increase the storage capacity of the floating diffusion node in the current pixel block, so as to be applicable to the situation where the requirements for high-light scenarios gradually increase. Brief Description of the Drawings

[0038] Figure 1 It shows a schematic structural diagram of an image sensor in Embodiment 1 of the present invention.

[0039] Figure 2 It shows another schematic structural diagram of an image sensor in Embodiment 1 of the present invention.

[0040] Figure 3 It shows yet another schematic structural diagram of an image sensor in Embodiment 1 of the present invention.

[0041] Figure 4 It shows a schematic structural diagram of an image sensor in Embodiment 2 of the present invention.

[0042] Figure 5 It shows another schematic structural diagram of an image sensor in Embodiment 2 of the present invention.

[0043] Figure 6 It shows a schematic structural diagram of an image sensor in Embodiment 3 of the present invention.

[0044] Figure 7 It shows a schematic structural diagram of an image sensor in Embodiment 4 of the present invention.

[0045] Figure 8 It shows Figure 7 The timing diagram corresponding to the pixel block in the shown image sensor.

[0046] Figure 9 It shows a schematic structural diagram of an image sensor in Embodiment 5 of the present invention.

[0047] Figure 10 It shows Figure 9 One timing diagram corresponding to the pixel block in the shown image sensor.

[0048] Figure 11 It shows Figure 9 Another timing diagram corresponding to the pixel block in the shown image sensor.

[0049] Description of Component Labels

[0050] 100 Image sensor

[0051] 110 Pixel block

[0052] 111 Photosensitive unit

[0053] 112 Overflow unit

[0054] 113 Gain unit

[0055] 114a First reset unit

[0056] 114b Second reset unit

[0057] 114c Third reset unit

[0058] 114d Fourth reset unit

[0059] 115a First readout unit

[0060] 115b Second readout unit

[0061] 115c Third readout unit

[0062] 115d Fourth readout unit

[0063] 120 Node sharing structure

[0064] 121a First connection line

[0065] 121b Second connection line

[0066] 122a First switching transistor

[0067] 122b Second switching transistor Detailed implementation manners

[0068] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0069] Please refer to Figures 1 to 11 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The form, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the layout form of its components may also be more complex.

[0070] Embodiment 1

[0071] As Figure 1 shown, this embodiment provides an image sensor 100 based on gain adjustment, including a plurality of pixel blocks 110 arranged in an array and a node sharing structure 120.

[0072] Pixel block 110 includes a photosensitive unit 111, an overflow unit 112, and a gain unit 113. Further, it also includes a first reset unit 114a, a second reset unit 114b, a first readout unit 115a, and a second readout unit 115b. Among them, pixel block 110 includes two floating diffusion nodes, namely, a first floating diffusion node FD1 and a second floating diffusion node FD2.

[0073] The photosensitive unit 111 is coupled to the first floating diffusion node FD1, generates a first charge signal and a second charge signal based on photoelectric conversion, stores the first charge signal, and transfers the first charge signal to the first floating diffusion node FD1.

[0074] As an example, the photosensitive unit 111 includes at least one photosensitive element PD and at least one transfer transistor M1. The control terminal of the transfer transistor M1 receives a transfer control signal TX. The first terminal is coupled to the first floating diffusion node FD1, the second terminal is coupled to the first terminal of the photosensitive element PD, and the second terminal of the photosensitive element PD is coupled to a ground potential or a negative potential.

[0075] Among them, the photosensitive element PD includes a photodiode, and the transfer transistor M1 includes an NMOS transistor. At this time, the gate of the transfer transistor M1 receives the transfer control signal TX, the drain is connected to the first floating diffusion node FD1, the source is connected to the first terminal of the photosensitive element PD (such as an N-type ion-doped region), and the second terminal of the photosensitive element PD (such as a P-type ion-doped region) is connected to a ground potential or a negative potential. Of course, in other examples, it is also feasible that the photosensitive element PD includes a grating or a photoconductor, and the transfer transistor M1 includes a PMOS transistor, which has no impact on this embodiment.

[0076] Generally, the photosensitive element PD and the transfer transistor M1 are designed in one-to-one correspondence, and the number of the photosensitive element PD and the transfer transistor M1 can be designed according to actual needs. For example, the photosensitive element PD can be one, or a shared structure formed by two, four, eight, etc. This embodiment does not limit this.

[0077] For the photosensitive unit 111, in combination with the actual application scenario, the first charge signal refers to the charge signal corresponding to the potential well part, and the second charge signal refers to the charge signal corresponding to the overflow part after the charge exceeds the potential well; when the amount of charge sensed by the photosensitive unit 111 does not reach the overflow state, the converted charge signal only includes the first charge signal and is stored in the photosensitive element PD. At this time, it can be considered that the second charge signal is zero; when the amount of charge sensed by the photosensitive unit 111 reaches the overflow state, the converted charge signal includes the first charge signal and the second charge signal. The first charge signal is stored in the photosensitive element PD, and the second charge signal overflows outside the photosensitive element PD and is stored in the overflow unit 112. In some applications, the first charge signal can also be defined as the potential well charge signal, and the second charge signal can be defined as the overflow charge signal.

[0078] The overflow unit 112 is coupled to the photosensitive unit 111 and is used to store the second charge signal; wherein, the overflow unit 112 includes an overflow path and a quantization path, and the second charge signal is stored in the overflow unit 112 through the overflow path and transferred to the second floating diffusion node FD2 through the quantization path.

[0079] As an example, in one implementation, the overflow unit 112 includes a first overflow transistor M21, a first quantization transistor M31, and a first storage device C11; the control terminal of the first overflow transistor M21 receives the first overflow control signal OFG1, the first terminal is coupled to the photosensitive unit 111, for example, coupled to the first terminal of the photosensitive element PD, and the second terminal is coupled to the first terminal of the first storage device C11; the control terminal of the first quantization transistor M31 receives the first quantization control signal OF_CTL1, the first terminal is coupled to the second floating diffusion node FD2, and the second terminal is coupled to the first terminal of the first storage device C11; the second terminal of the first storage device C11 is coupled to a reference potential, for example, coupled to the ground potential; wherein, the path where the first overflow transistor M21 is located is the overflow path, and the path where the first quantization transistor M31 is located is the quantization path.

[0080] Among them, the first storage device C11 includes a capacitor device, the first overflow transistor M21 includes an NMOS transistor, the first quantization transistor M31 includes an NMOS transistor, the gate of the first overflow transistor M21 receives the first overflow control signal OFG1, the drain is connected to one end of the photosensitive element PD, and the source is connected to the first terminal of the first storage device C11. The gate of the first quantization transistor M31 receives the first quantization control signal OF_CTL1, the drain is connected to the second floating diffusion node FD2, and the source is connected to the first terminal of the first storage device C11; of course, in other examples, it is also feasible that the first overflow transistor M21 includes a PMOS transistor and the first quantization transistor M31 includes a PMOS transistor, which has no impact on this embodiment.

[0081] In another implementation, such asFigure 2 As shown, the overflow unit 112 can also remove the first quantization transistor M31. At this time, the first end of the first storage device C11 is coupled to the second end of the first overflow transistor M21 and also coupled to the second floating diffusion node FD2. In this embodiment, the overflow unit 112 includes a first overflow transistor M21 and a first storage device C11. The control terminal of the first overflow transistor M21 receives a first overflow control signal OFG1. The first end is coupled to the photosensitive unit 111, for example, coupled to the first end of the photosensitive element PD. The second end is coupled to the first end of the first storage device C11. The first end of the first storage device C11 is coupled to the second floating diffusion node FD2, and the second end is coupled to a reference potential, for example, coupled to a ground potential. Among them, the path where the first overflow transistor M21 is located is the overflow path, and the path from the first end of the first storage device C11 to the second floating diffusion node FD2 is the quantization path.

[0082] As an example, the pixel block 110 further includes a fast reset unit (not shown in the figure), which is coupled to both ends of the first storage device C11 in the overflow unit 112 and is used to reset the overflow unit 112. In applications, the fast reset unit can cooperate with the corresponding reset unit to reset the first storage device C11.

[0083] In one implementation, the fast reset unit can include a fast reset transistor. The control terminal receives a fast reset control signal. The first end is coupled to one end of the first storage device C11, and the second end is coupled to the other end of the first storage device C11. Optionally, the fast reset transistor includes an NMOS transistor. At this time, the gate of the fast reset transistor receives the fast reset control signal, the drain is connected to the first end of the first storage device C11, and the source is connected to the second end of the first storage device C11.

[0084] As an optional solution, the other end of the first storage device C11 is coupled to a variable potential. At this time, the corresponding end of the fast reset transistor is also coupled to the variable potential, and the two can be regulated simultaneously based on the variable potential. In other embodiments, the other end of the first storage device C11 can also be coupled to a ground potential instead of a variable potential. In addition, according to the threshold value of the fast reset transistor, the control terminal of the fast reset transistor can be short-circuited with the end coupled to the variable potential while ensuring the normal switching of the transistor. Among them, the overflow unit 112 can be quickly reset during the global reset of the circuit or the reset reading of the signal in the first storage device C11, which is beneficial to the reset of the first storage device C11 and beneficial to improving the timing control of the device.

[0085] The gain unit 113 is coupled to the first floating diffusion node FD1 for switching between different gain modes, such as switching between a first gain mode and a second gain mode. In one embodiment, the first gain mode includes a low gain (LCG) mode and the second gain mode includes a high gain (HCG) mode.

[0086] As an example, the gain unit 113 includes a gain transistor M4, a control terminal receiving a gain control signal DCG, a first terminal coupled to a first reset unit 114a, and a second terminal coupled to a first floating diffusion node FD1. If the gain transistor M4 is turned on, the image sensor operates in a first gain mode. If the gain transistor M4 is turned off, the image sensor operates in a second gain mode. It should be noted that the gain unit 113 may also have more than two gain modes, for example, implemented by at least two gain transistors. In this case, gain nodes greater than the minimum gain can be considered high-gain nodes, and gain nodes less than the maximum gain can be considered low-gain nodes. For example, when there is one gain transistor, and the first gain mode is a low-gain (LCG) mode and the second gain mode is a high-gain (HCG) mode, the low-gain node corresponds to the drain of the gain transistor, and the high-gain node corresponds to the source of the gain transistor, that is, the first floating diffusion node FD1.

[0087] The gain transistor M4 includes an NMOS transistor, a gate of which receives the gain control signal DCG, a drain connected to the first reset unit 114a, and a source connected to the first floating diffusion node FD1; of course, in other examples, it is also feasible for the gain transistor M4 to include a PMOS transistor, which has no effect on this embodiment.

[0088] The first reset unit 114 a is coupled to the first floating diffusion node FD1 through the gain unit 113 , and is configured to reset the first floating diffusion node FD1 and the photosensitive unit 111 , and further, is configured to reset the overflow unit 112 .

[0089] As an example, the first reset unit 114a includes a first reset transistor M51, whose control terminal receives a first reset control signal RST1, a first terminal is coupled to a first power supply potential, and a second terminal is coupled to the gain unit 113, e.g., to the drain of the gain transistor M4. The first reset transistor M51 includes an NMOS transistor, whose gate receives the first reset control signal RST1, whose drain is connected to the first power supply potential, and whose source is connected to the drain of the gain transistor M4. The first power supply potential is typically the operating voltage and is always a high voltage. Of course, in other examples, it is also feasible for the first reset transistor M51 to include a PMOS transistor, which has no impact on this embodiment.

[0090] The second reset unit 114b is coupled to the second floating diffusion node FD2, and is used to reset the second floating diffusion node FD2. Further, it is also used to reset the overflow unit 112. In practical applications, the second reset unit 114b is usually used instead of the first reset unit 114a to reset the overflow unit 112.

[0091] As an example, the second reset unit 114b includes a second reset transistor M52. The control terminal receives the second reset control signal RST2. The first terminal is coupled to the second power supply potential, and the second terminal is coupled to the second floating diffusion node FD2. Among them, the second reset transistor M52 includes an NMOS transistor. The gate receives the second reset control signal RST2, the drain is connected to the second power supply potential, and the source is connected to the second floating diffusion node FD2. The second power supply potential is usually the potential of the working voltage and is always a high potential. Of course, in other examples, it is also feasible that the second reset transistor M52 includes a PMOS transistor, which has no impact on this embodiment.

[0092] The first readout unit 115a is coupled to the first floating diffusion node FD1, and is used to at least quantitatively read out the first charge signal transferred to the first floating diffusion node FD1.

[0093] As an example, the first readout unit 115a includes a first source follower transistor M61 and a first selection transistor M71. The control terminal of the first source follower transistor M61 is coupled to the first floating diffusion node FD1. The first terminal is coupled to the third power supply potential, and the second terminal is coupled to the first terminal of the first selection transistor M71. The control terminal of the first selection transistor M71 receives the first selection control signal SEL1, and the second terminal is coupled to the first column line BIT1.

[0094] Among them, the first source follower transistor M61 includes an NMOS transistor, the first selection transistor M71 includes an NMOS transistor. The gate of the first source follower transistor M61 is connected to the first floating diffusion node FD1, the drain is connected to the third power supply potential, and the source is connected to the drain of the first selection transistor M71. The gate of the first selection transistor M71 receives the first selection control signal SEL1, and the source is connected to the first column line BIT1. The third power supply potential is usually the potential of the working voltage and is always a high potential. Of course, in other examples, it is also feasible that the first source follower transistor M61 includes a PMOS transistor and the first selection transistor M71 includes a PMOS transistor, which has no impact on this embodiment.

[0095] The second readout unit 115b is coupled to the second floating diffusion node FD2, and is used to at least quantitatively read out the second charge signal transferred to the second floating diffusion node FD2.

[0096] As an example, the second readout unit 115b includes a second source-follower transistor M62 and a second selection transistor M72. The control terminal of the second source-follower transistor M62 is coupled to the second floating diffusion node FD2, the first terminal is coupled to the fourth power supply potential, the second terminal is coupled to the first terminal of the second selection transistor M72. The control terminal of the second selection transistor M72 receives the second selection control signal SEL2, and the second terminal is coupled to the second column line BIT2.

[0097] Among them, the second source-follower transistor M62 includes an NMOS transistor, and the second selection transistor M72 includes an NMOS transistor. The gate of the second source-follower transistor M62 is connected to the second floating diffusion node FD2, the drain is connected to the fourth power supply potential, and the source is connected to the drain of the second selection transistor M72. The gate of the second selection transistor M72 receives the second selection control signal SEL2, and the source is connected to the second column line BIT2. The fourth power supply potential is usually the potential of the working voltage and is always a high potential. Of course, in other examples, it is also feasible that the second source-follower transistor M62 includes a PMOS transistor and the second selection transistor M72 includes a PMOS transistor, which has no impact on this embodiment.

[0098] In the pixel block 110 of this embodiment, the first readout unit 115a and the second readout unit 115b perform quantization readout through different column lines. For example, the first readout unit 115a performs quantization readout through the first column line BIT1, and the second readout unit 115b performs quantization readout through the second column line BIT2. In this way, simultaneous quantization readout of the first charge signal and the second charge signal can be achieved, improving the quantization readout speed. Of course, it is also feasible for the first readout unit 115a and the second readout unit 115b to perform quantization readout through the same column line.

[0099] The node sharing structure 120 is coupled between the gain units 113 of at least two pixel blocks 110, and is used to increase the storage capacity of the first floating diffusion node FD1 based on node sharing when the gain unit 113 is turned on, so that the first gain mode has a lower conversion gain, thereby being applicable to the situation where the requirements for high-light scenarios gradually increase. Among them, the node sharing structure 120 can be coupled between the gain nodes of any requirements of different gain units 113, and can be coupled between high and low gain nodes according to actual requirements. In the embodiments of the present invention, it is preferably coupled between the lowest gain nodes of each gain unit 113 that needs to be coupled.

[0100] In an alternative solution, the node sharing structure 120 is coupled between the gain units 113 of different row pixel blocks 110 in the same column; further, the node sharing structure 120 is coupled between the gain units 113 of adjacent two rows of pixel blocks 110 in the same column. Of course, it can also be coupled between two or more required rows according to actual requirements. For example, it is coupled between the rows corresponding to the same-color pixels, which is beneficial to preventing the mutual influence of signals between pixels of different colors.

[0101] As an example, the node sharing structure 120 includes a first connection line 121a, which is coupled between the gain units 113 of at least two pixel blocks 110. For example, it is coupled between the first ends of the gain transistors M4 in the corresponding pixel blocks 110; when the gain unit 113 is turned on, the storage capacity of the first floating diffusion node FD1 is increased based on node sharing. At this time, the shared node storage capacity corresponds to at least 2*Cfd1, where Cfd1 is the storage capacity of the first floating diffusion node FD1.

[0102] Further, as Figure 3 shown, the node sharing structure 120 further includes at least one first switching transistor 122a, which is serially coupled to the first connection line 121a, and its control terminal receives a first switching control signal SW1; wherein, the first switching transistor 122a includes an NMOS transistor. Of course, it is also feasible that the first switching transistor 122a includes a PMOS transistor, which has no impact on this embodiment.

[0103] After adding the first switching transistor 122a to the node sharing structure 120 of this embodiment, if node sharing is desired, in addition to controlling the gain unit 113 to be turned on, the first switching transistor 122a should also be controlled to be turned on.

[0104] Correspondingly, this embodiment also provides a control method for an image sensor, including a quantization stage. Further, it also includes a reset stage and an exposure stage; wherein, the image sensor is implemented by using the circuit structure described above.

[0105] Reset stage:

[0106] Perform a reset operation on the first floating diffusion node FD1, the second floating diffusion node FD2, the photosensitive unit 111, and the overflow unit 112; further, perform a reset operation on the first floating diffusion node FD1 and the photosensitive unit 111 through the first reset unit 114a, and perform a reset operation on the second floating diffusion node FD2 and the overflow unit 112 through the second reset unit 114b.

[0107] For example, taking Figure 1For example, control the first reset transistor M51, gain transistor M4, and transfer transistor M1 to turn on, and clear the charges of the first floating diffusion node FD1 and photosensitive element PD to achieve signal reset; control the second reset transistor M52 and the first quantization transistor M31 to turn on, and clear the charges of the second floating diffusion node FD2 and the first storage device C11 to achieve signal reset; thus, the reset operation is completed. After that, control the first reset transistor M51, transfer transistor M1, second reset transistor M52, and first quantization transistor M31 to turn off.

[0108] Exposure stage:

[0109] Store the second charge signal in the overflow unit 112. Specifically, open the overflow path and close the quantization path, and store the second charge signal in the overflow unit 112 through the overflow path.

[0110] For example, Figure 1 For example, control the first overflow transistor M21 in the overflow unit 112 to turn on. At this time, the overflow path is opened, and the second charge signal overflowed from the photosensitive element PD in the photosensitive unit 111 is transferred to the first storage device C11 in the overflow unit 112 through this overflow path for storage. After that, control the first overflow transistor M21 to turn off.

[0111] When the amount of charge sensed by the photosensitive element PD does not reach the overflow state, the converted charge signal only includes the first charge signal and is stored on the photosensitive element PD. At this time, although the overflow path is opened, no second charge signal is transferred to the first storage device C11 through the overflow path, and it can be considered that the corresponding second charge signal is zero in this process. When the amount of charge sensed by the photosensitive element PD reaches the overflow state, the converted charge signal includes the first charge signal and the second charge signal. Among them, the first charge signal is stored on the photosensitive element PD, and the second charge signal is transferred to the first storage device C11 through the overflow path for storage.

[0112] Quantization stage:

[0113] Quantize and read out the first charge signal in different gain modes, and quantize and read out the second charge signal; among them, when the gain unit 113 is turned on, node sharing is performed through the node sharing structure 120 to increase the storage capacity of the first floating diffusion node FD1, and the first floating diffusion node with increased storage capacity is defined as the shared node.

[0114] In one implementation, the quantization stage includes: performing correlated double sampling on the first charge signal in different gain modes, and performing correlated double sampling on the second charge signal.

[0115] Specifically, it includes: controlling the node sharing structure 120 to be opened, and after the gain control unit 113 is opened and then closed, the first reset signal in the first gain mode and the second gain mode is quantized and read out respectively based on the shared node and the first floating diffusion node FD1. After the gain control unit 113 is closed and then opened, the first charge signal in the second gain mode and the first gain mode is quantized and read out respectively based on the first floating diffusion node FD1 and the shared node; controlling the quantization path in the overflow unit 112 to be closed, and the second reset signal is quantized and read out based on the second floating diffusion node FD2. Controlling the quantization path to be opened, and the second charge signal is quantized and read out based on the second floating diffusion node FD2.

[0116] In an optional solution, the first readout unit 115a and the second readout unit 115b perform quantization readout through different column lines. At this time, the second reset signal is quantized and read out simultaneously with the first reset signal in the first gain mode or the second gain mode, and the second charge signal is quantized and read out simultaneously with the first charge signal in the first gain mode or the second gain mode, thereby improving the quantization readout speed.

[0117] It should be noted that when the node sharing structure 120 only includes the first connection line 121a, there is no need to additionally control the node sharing structure 120 to be opened, and it is default that the node sharing structure 120 is in the open state; when the node sharing structure 120 further includes the first switching transistor 122a, the node sharing structure 120 is controlled to be opened by controlling the first switching transistor 122a to be opened.

[0118] Take Figure 1 as an example. The node sharing structure 120 only includes the first connection line 121a, and the second reset signal is quantized and read out simultaneously with the first reset signal in the first gain mode, and the second charge signal is quantized and read out simultaneously with the first charge signal in the first gain mode;

[0119] Since the gain transistor M4 in the gain unit 113 is opened and remains open during the reset stage, the image sensor operates in the first gain mode. Also, since the node sharing structure 120 only includes the first connection line 121a, when the gain transistor M4 is opened, the first floating diffusion nodes FD1 in the adjacent two rows of pixel blocks 110 are coupled together through the first connection line 121a to achieve node sharing;

[0120] Control the first selection transistor M71 in the first readout unit 115a and the second selection transistor M72 in the second readout unit 115b to be opened, so as to simultaneously quantize and read out the first reset signal and the second reset signal in the first gain mode respectively based on the shared node and the second floating diffusion node FD2;

[0121] The control gain transistor M4 is turned off to switch the image sensor to the second gain mode, and the first reset signal in the second gain mode is quantized and read out based on the first floating diffusion node FD1. Then, the transfer transistor M1 in the photosensitive unit 111 is turned on and then off to transfer the first charge signal stored in the photosensitive element PD to the first floating diffusion node FD1, and the first charge signal in the second gain mode is quantized and read out based on the first floating diffusion node FD1.

[0122] The control gain transistor M4 is turned on to switch the image sensor back to the first gain mode. The transfer transistor M1 is turned on and then off to transfer the first charge signal stored in the photosensitive element PD to the shared node. At the same time, the first quantization transistor M31 in the overflow unit 112 is turned on, and the second charge signal stored in the first storage device C11 in the overflow unit 112 is transferred to the second floating diffusion node FD2 through the quantization path, so as to simultaneously quantize and read out the first charge signal and the second charge signal in the first gain mode based on the shared node and the second floating diffusion node FD2 respectively.

[0123] In another embodiment, the quantization stage includes: performing correlated double sampling on the first charge signal in different gain modes, and performing non-genuine correlated double sampling on the second charge signal.

[0124] Specifically, it includes: controlling the node sharing structure 120 to be turned on, and controlling the gain unit 113 to be turned on and then off to respectively quantize and read out the first reset signal in the first gain mode and the second gain mode based on the shared node and the first floating diffusion node FD1. Then, the gain unit 113 is turned off and then on to respectively quantize and read out the first charge signal in the second gain mode and the first gain mode based on the first floating diffusion node FD1 and the shared node. Controlling the quantization path in the overflow unit 112 to be turned on to quantize and read out the second charge signal based on the second floating diffusion node FD2, and performing a reset operation on the second floating diffusion node FD2 to quantize and read out the second reset signal based on the second floating diffusion node FD2.

[0125] In an optional solution, the first readout unit 115a and the second readout unit 115b perform quantization readout through different column lines. At this time, the second charge signal is quantized and read out simultaneously with the first charge signal in the first gain mode or the second gain mode, thereby improving the quantization readout speed.

[0126] It should be noted that when the node sharing structure 120 only includes the first connection line 121a, there is no need to additionally control the node sharing structure 120 to be turned on, and the node sharing structure 120 is default to be in the on state. When the node sharing structure 120 further includes the first switching transistor 122a, the node sharing structure 120 is controlled to be turned on by controlling the first switching transistor 122a to be turned on.

[0127] Taking Figure 1 as an example, the node sharing structure 120 only includes the first connection line 121a, and the second charge signal and the first charge signal in the first gain mode are quantized and read out simultaneously;

[0128] Since the gain transistor M4 in the gain unit 113 is turned on and remains on during the reset phase, the image sensor operates in the first gain mode; and since the node sharing structure 120 includes the first connection line 121a, when the gain transistor M4 is turned on, the first floating diffusion nodes FD1 in adjacent two rows of pixel blocks 110 are coupled together through the first connection line 121a to achieve node sharing;

[0129] Control the first selection transistor M71 in the first readout unit 115a and the second selection transistor M72 in the second readout unit 115b to be turned on to quantize and read out the first reset signal in the first gain mode based on the shared node; and then control the gain transistor M4 to be turned off to switch the image sensor to the second gain mode to quantize and read out the first reset signal in the second gain mode based on the first floating diffusion node FD1; then control the transfer transistor M1 in the photosensitive unit 111 to be turned on and then off to transfer the first charge signal stored in the photosensitive element PD to the first floating diffusion node FD1 to quantize and read out the first charge signal in the second gain mode based on the first floating diffusion node FD1;

[0130] Control the gain transistor M4 to be turned on to switch the image sensor back to the first gain mode again, control the transfer transistor M1 to be turned on and then off to transfer the first charge signal stored in the photosensitive element PD to the shared node, and at the same time, control the first quantization transistor M31 in the overflow unit 112 to be turned on to transfer the second charge signal stored in the first storage device C11 in the overflow unit 112 to the second floating diffusion node FD2 through the quantization path to simultaneously quantize and read out the first charge signal and the second charge signal in the first gain mode based on the shared node and the second floating diffusion node FD2 respectively; and then control the second reset transistor M52 in the second reset unit 114b to be turned on and then off to perform a secondary reset operation on the second floating diffusion node FD2 to quantize and read out the second reset signal based on the second floating diffusion node FD2.

[0131] Of course, in other embodiments, it is also possible to perform correlated double sampling on the second charge signal and perform non-genuine correlated double sampling on the second charge signal; in this case, usually, the correlated double sampling on the second charge signal is performed first, and then the non-genuine correlated double sampling on the second charge signal is performed.

[0132] In addition, for Figure 2The image sensor 100 shown. Since the overflow unit 112 in the pixel block 110 removes the first quantization transistor M31, the second charge signal overflowing in the exposure stage will not only be stored in the first storage device C11, but also in the second floating diffusion node FD2. To ensure signal accuracy, usually a non-genuine correlated double sampling is performed on the second charge signal, and the related control is the same as above. Of course, if both a genuine correlated double sampling and a non-genuine correlated double sampling are to be performed on the second charge signal, then the non-genuine correlated double sampling is first performed on the second charge signal, and then the genuine correlated double sampling is performed on the second charge signal.

[0133] Embodiment 2

[0134] As Figure 4 and Figure 5 shown, this embodiment provides an image sensor 100 based on gain adjustment, including a plurality of pixel blocks 110 arranged in an array and a node sharing structure 120.

[0135] The pixel block 110 includes a photosensitive unit 111, an overflow unit 112, and a gain unit 113. Further, it also includes a third reset unit 114c and a third readout unit 115c. Among them, the pixel block 110 includes a floating diffusion node, that is, the first floating diffusion node FD1.

[0136] The photosensitive unit 111 and the gain unit 113 are the same as those in Embodiment 1, and the overflow unit 112 is the same as one implementation in Embodiment 1. For the relevant content, refer to Embodiment 1 for details and will not be elaborated here. It should be noted that in the overflow unit 112 of this embodiment, the first end of the first quantization transistor M31 is no longer directly coupled to the second floating diffusion node FD2, but is coupled to the second floating diffusion node FD2 through the gain unit 113 of the pixel block 110 corresponding to the second floating diffusion node FD2. In addition, the first end of the gain transistor M4 in the gain unit 113 is coupled to the third reset unit 114c instead of the first reset unit 114a.

[0137] In the pixel block 110 of this embodiment, when transferring the first charge signal and the second charge signal to the first floating diffusion node FD1 and the second floating diffusion node FD2 respectively for quantization readout, the first floating diffusion node FD1 and the second floating diffusion node FD2 belong to two different pixel blocks 110. In an optional solution, the first floating diffusion node FD1 and the second floating diffusion node FD2 belong to pixel blocks 110 in different rows in the same column. In an optional solution, the first floating diffusion node FD1 and the second floating diffusion node FD2 belong to pixel blocks 110 in adjacent rows in the same column.

[0138] For adjacent pixel blocks 110 in the same column: In one implementation, as Figure 4As shown, the floating diffusion node corresponding to the pixel block 110 in the previous row is always used as its second floating diffusion node FD2 for the pixel block 110 in the next row. Of course, in other examples, it can also be that the floating diffusion node corresponding to the pixel block 110 in the next row is always used as its second floating diffusion node FD2 for the pixel block 110 in the previous row; in another implementation, as Figure 5 shown, the floating diffusion nodes corresponding to the two rows of pixel blocks 110 are second floating diffusion nodes FD2 for each other.

[0139] The third reset unit 114c is coupled to the corresponding floating diffusion node through the gain unit 113 and is used to reset the corresponding floating diffusion node, the photosensitive unit 111, and the overflow unit 112.

[0140] As an example, the third reset unit 114c includes a third reset transistor M53. The control terminal receives a third reset control signal RST3. The first terminal is coupled to the fifth power supply potential, and the second terminal is coupled to the gain unit 113, for example, coupled to the drain of the gain transistor M4. Among them, the third reset transistor M53 includes an NMOS transistor. The gate receives the third reset control signal RST3, the drain is connected to the fifth power supply potential, and the source is connected to the drain of the gain transistor M4. The fifth power supply potential is usually the potential of the operating voltage and is always a high potential; of course, in other examples, it is also feasible that the third reset transistor M53 includes a PMOS transistor, which has no impact on this embodiment.

[0141] The third readout unit 115c is coupled to the corresponding floating diffusion node and is used to at least quantify and read out the corresponding charge signal transferred to the corresponding floating diffusion node.

[0142] As an example, the third readout unit 115c includes a third source-follower transistor M63 and a third selection transistor M73. The control terminal of the third source-follower transistor M63 is coupled to the corresponding floating diffusion node. The first terminal is coupled to the sixth power supply potential, and the second terminal is coupled to the first terminal of the third selection transistor M73. The control terminal of the third selection transistor M73 receives a third selection control signal SEL3, and the second terminal is coupled to the corresponding column line.

[0143] Among them, the third source-follower transistor M63 includes an NMOS transistor, and the third selection transistor M73 includes an NMOS transistor. The gate of the third source-follower transistor M63 is connected to the corresponding floating diffusion node, the drain is connected to the sixth power supply potential, and the source is connected to the drain of the third selection transistor M73. The gate of the third selection transistor M73 receives the third selection control signal SEL3, and the source is connected to the corresponding column line. The sixth power supply potential is usually the potential of the operating voltage and is always a high potential; of course, in other examples, it is also feasible that the third source-follower transistor M63 includes a PMOS transistor and the third selection transistor M73 includes a PMOS transistor, which has no impact on this embodiment.

[0144] In an alternative solution, the third readout units 115c of the pixel blocks 110 in two adjacent rows in the same column perform quantization readout through different column lines. In this way, simultaneous quantization readout of the first charge signal and the second charge signal can be achieved, improving the quantization readout speed. Of course, it is also feasible for the third readout units 115c of the pixel blocks 110 in two adjacent rows in the same column to perform quantization readout through the same column line.

[0145] The node sharing structure 120 is the same as that in the first embodiment, and the relevant content can be found in the first embodiment in detail, which will not be elaborated here. Among them, only the first connection line 121a is shown in the figure as a schematic diagram of the node sharing structure 120.

[0146] Correspondingly, this embodiment further provides a control method for an image sensor, including a quantization stage. Further, it also includes a reset stage and an exposure stage. Among them, the image sensor is implemented by using the circuit structure described above.

[0147] Reset stage:

[0148] Perform reset operations on the first floating diffusion node FD1, the second floating diffusion node FD2, the photosensitive unit 111, and the overflow unit 112. Taking the first floating diffusion node FD1 and the second floating diffusion node FD2 belonging to the pixel blocks 110 in two adjacent rows in the same column as an example, and performing quantization readout on the upper pixel block 110 among the two adjacent pixel blocks 110. At this time, the floating diffusion node corresponding to the lower pixel block 110 serves as the second floating diffusion node FD2 of the upper pixel block 110. Perform reset operations on the first floating diffusion node FD1 and the photosensitive unit 111 through the third reset unit 114c in the upper pixel block 110, and perform reset operations on the second floating diffusion node FD2 and the overflow unit 112 in the upper pixel block 110 through the third reset unit 114c in the lower pixel block 110.

[0149] For example, control the third reset transistor M53, the gain transistor M4, and the transfer transistor M1 in the upper pixel block 110 to be turned on, and perform charge clearing on the first floating diffusion node FD1 and the photosensitive element PD to achieve signal reset; control the first quantization transistor M31 in the upper pixel block 110 to be turned on, and control the third reset transistor M53 and the gain transistor M4 in the lower pixel block 110 to be turned on, and perform charge clearing on the second floating diffusion node FD2 and the first storage device C11 in the upper pixel block 110 to achieve signal reset. In this way, the reset operation is completed. After that, control the third reset transistor M53, the transfer transistor M1, and the first quantization transistor M31 in the upper pixel block 110 to be turned off, and control the third reset transistor M53 in the lower pixel block 110 to be turned off.

[0150] The exposure stage is the same as that in the first embodiment. For the relevant content, please refer to the first embodiment for details and will not be elaborated here.

[0151] Quantization stage:

[0152] Quantitatively read out the first charge signals in different gain modes and quantitatively read out the second charge signals; wherein, when the gain unit 113 is turned on, node sharing is performed through the node sharing structure 120 to increase the storage capacity of the first floating diffusion node FD1, and the first floating diffusion node with increased storage capacity is defined as the shared node.

[0153] In one implementation, the quantization stage includes: performing correlated double sampling on the first charge signals in different gain modes and performing correlated double sampling on the second charge signals.

[0154] Specifically, it includes: controlling the node sharing structure 120 to be turned on, controlling the gain unit 113 to be turned on and then off, so as to quantitatively read out the first reset signals in the first gain mode and the second gain mode based on the shared node and the first floating diffusion node FD1 respectively, controlling the gain unit 113 to be turned off and then on, so as to quantitatively read out the first charge signals in the second gain mode and the first gain mode based on the first floating diffusion node FD1 and the shared node respectively; controlling the quantization path in the overflow unit 112 to be turned off, so as to quantitatively read out the second reset signal based on the second floating diffusion node FD2, and controlling the quantization path to be turned on, so as to quantitatively read out the second charge signal based on the second floating diffusion node FD2.

[0155] In an optional solution, the third readout units 115c of the pixel blocks 110 in two adjacent rows in the same column perform quantization readout through different column lines. At this time, the second reset signal and the first reset signal in the second gain mode are quantitatively read out simultaneously, and the second charge signal and the first charge signal in the second gain mode are quantitatively read out simultaneously, thereby improving the quantization readout speed.

[0156] It should be noted that when the node sharing structure 120 only includes the first connection line 121a, there is no need to additionally control the node sharing structure 120 to be turned on, and it is default that the node sharing structure 120 is in the on state; when the node sharing structure 120 further includes the first switching transistor 122a, the node sharing structure 120 is controlled to be turned on by controlling the first switching transistor 122a to be turned on.

[0157] Taking the example where the node sharing structure 120 only includes the first connection line 121a; since the gain transistors M4 in two adjacent rows of pixel blocks 110 are turned on and remain on during the reset phase, the image sensor operates in the first gain mode; and since the node sharing structure 120 only includes the first connection line 121a, when the gain transistors M4 are turned on, the floating diffusion nodes in two adjacent rows of pixel blocks 110 are coupled together through the first connection line 121a to achieve node sharing;

[0158] Control the third selection transistor M73 in two adjacent rows of pixel blocks 110 to be turned on to quantize and read out the first reset signal in the first gain mode based on the shared node; and control the gain transistors M4 in two adjacent rows of pixel blocks 110 to be turned off, so that the image sensor switches to the second gain mode to simultaneously quantize and read out the first reset signal and the second reset signal in the second gain mode based on the first floating diffusion node FD1 and the second floating diffusion node FD2;

[0159] Control the transfer transistor M1 in the upper row of pixel blocks 110 to be turned on and then off to transfer the first charge signal stored in the photosensitive element PD to the first floating diffusion node FD1. At the same time, control the first quantization transistor M31 in the upper row of pixel blocks 110 to be turned on, and control the gain transistors M4 in the lower row of pixel blocks 110 to be turned on and then off, and transfer the second charge signal stored in the first storage device C11 in the upper row of pixel blocks 110 to the second floating diffusion node FD2 through the quantization path to simultaneously quantize and read out the first charge signal and the second charge signal in the second gain mode based on the first floating diffusion node FD1 and the second floating diffusion node FD2 respectively;

[0160] Control the gain transistors M4 in two adjacent rows of pixel blocks 110 to be turned on, so that the image sensor switches back to the first gain mode again. Control the transfer transistor M1 in the upper row of pixel blocks 110 to be turned on and then off to transfer the first charge signal stored in the photosensitive element PD to the shared node to quantize and read out the first charge signal in the first gain mode based on the shared node.

[0161] In another embodiment, the quantization phase includes: performing correlated double sampling on the first charge signal in different gain modes and performing non - true correlated double sampling on the second charge signal.

[0162] Specifically, it includes: controlling the node sharing structure 120 to be opened, and after the gain control unit 113 is opened and then closed, respectively quantifying and reading out the first reset signal in the first gain mode and the second gain mode based on the shared node and the first floating diffusion node FD1. After the gain control unit 113 is closed and then opened, respectively quantifying and reading out the first charge signal in the second gain mode and the first gain mode based on the first floating diffusion node FD1 and the shared node; controlling the quantization path in the overflow unit 112 to be opened, quantifying and reading out the second charge signal based on the second floating diffusion node FD2, and performing a reset operation on the second floating diffusion node FD2 to quantify and read out the second reset signal based on the second floating diffusion node FD2.

[0163] In an alternative solution, the third readout units 115c of the pixel blocks 110 in adjacent two rows in the same column perform quantization readout through different column lines. At this time, the second charge signal and the first charge signal in the second gain mode are simultaneously quantized and read out, thereby improving the quantization readout speed.

[0164] It should be noted that when the node sharing structure 120 only includes the first connection line 121a, there is no need to additionally control the node sharing structure 120 to be opened, and it is default that the node sharing structure 120 is in an open state; when the node sharing structure 120 further includes the first switching transistor 122a, controlling the first switching transistor 122a to be opened to control the node sharing structure 120 to be opened.

[0165] Taking the case where the node sharing structure 120 only includes the first connection line 121a as an example: Since the gain transistors M4 in the pixel blocks 110 in adjacent two rows are opened and kept open during the reset stage, the image sensor operates in the first gain mode; and since the node sharing structure 120 only includes the first connection line 121a, when the gain transistors M4 are opened, the floating diffusion nodes in the pixel blocks 110 in adjacent two rows are coupled together through the first connection line 121a to achieve node sharing;

[0166] Controlling the third selection transistors M73 in the pixel blocks 110 in adjacent two rows to be opened to quantify and read out the first reset signal in the first gain mode based on the shared node; and controlling the gain transistors M4 in the pixel blocks 110 in adjacent two rows to be closed to switch the image sensor to the second gain mode to quantify and read out the first reset signal in the second gain mode based on the first floating diffusion node FD1.

[0167] After controlling the transfer transistor M1 in the pixel block 110 of the previous row to turn on and then off, the first charge signal stored in the photosensitive element PD is transferred to the first floating diffusion node FD1. At the same time, control the first quantization transistor M31 in the pixel block 110 of the previous row to turn on, and control the gain transistor M4 in the pixel block 110 of the next row to turn on and then off. The second charge signal stored in the first storage device C11 in the pixel block 110 of the previous row is transferred to the second floating diffusion node FD2 through the quantization path, so as to simultaneously perform quantization readout of the first charge signal and the second charge signal in the second gain mode based on the first floating diffusion node FD1 and the second floating diffusion node FD2 respectively;

[0168] Control the gain transistor M4 in the pixel blocks 110 of two adjacent rows to turn on, so that the image sensor switches to the first gain mode again. Control the transfer transistor M1 in the pixel block 110 of the previous row to turn on and then off, and transfer the first charge signal stored in the photosensitive element PD to the shared node, so as to perform quantization readout of the first charge signal in the first gain mode based on the shared node; Also control the third reset transistor M53 of the third reset unit 114c in the pixel block 110 of the next row to turn on and then off, and perform a secondary reset operation on the second floating diffusion node FD2, so as to perform quantization readout of the second reset signal based on the second floating diffusion node FD2.

[0169] Of course, in other embodiments, it is also possible to perform correlated double sampling on the second charge signal and perform non-genuine correlated double sampling on the second charge signal; in this case, usually, the second charge signal is first subjected to correlated double sampling, and then non-genuine correlated double sampling is performed on the second charge signal.

[0170] Embodiment III

[0171] As Figure 6 shown, this embodiment provides an image sensor 100 based on gain adjustment, including a plurality of pixel blocks 110 arranged in an array and a node sharing structure 120.

[0172] For pixel block 110, the difference between this embodiment and the second embodiment lies in the different circuit structures of the overflow unit 112. In this embodiment, the overflow unit 112 includes a second overflow transistor M22, a second quantization transistor M32, and a second storage device C12. The control terminal of the second overflow transistor M22 receives a second overflow control signal OFG2, the first terminal is coupled to the photosensitive unit 111, e.g., coupled to the first terminal of the photosensitive element PD, and the second terminal is coupled to the first terminal of the second storage device C12. The control terminal of the second quantization transistor M32 receives a second quantization control signal OF_CTL2, the first terminal is coupled to the second floating diffusion node FD2 through a node sharing structure 120 and a gain unit 113 corresponding to the second floating diffusion node FD2, and the second terminal is coupled to the first terminal of the second storage device C12. The second terminal of the second storage device C12 is coupled to a reference potential, e.g., coupled to a ground potential. Among them, the path where the second overflow transistor M22 is located is the overflow path, the path where the second quantization transistor M32 is located is the quantization path, and the second charge signal is stored in the overflow unit 112 through the overflow path and transferred to the second floating diffusion node FD2 through the quantization path.

[0173] Among them, the second storage device C12 includes a capacitor device, the second overflow transistor M22 includes an NMOS transistor, the second quantization transistor M32 includes an NMOS transistor, the gate of the second overflow transistor M22 receives the second overflow control signal OFG2, the drain is connected to one end of the photosensitive element PD, and the source is connected to the first end of the second storage device C12. The gate of the second quantization transistor M32 receives the second quantization control signal OF_CTL2, the drain is connected to the second floating diffusion node FD2 through the node sharing structure 120 and the gain unit 113, and the source is connected to the first end of the second storage device C12. Of course, in other examples, it is also feasible that the second overflow transistor M22 includes a PMOS transistor and the second quantization transistor M32 includes a PMOS transistor, which has no impact on this embodiment.

[0174] In other embodiments, in the overflow unit 112 of the pixel block 110 of this embodiment, the first end of the second quantization transistor M32 can also be regarded as being coupled to the first floating diffusion node FD1 through the corresponding gain unit 113. When the second quantization transistor M32 includes an NMOS transistor, i.e., the drain of the second quantization transistor M32 is connected to the first floating diffusion node FD1 through the gain unit 113. At this time, the path where the second overflow transistor M22 is located is the overflow path, the path where the second quantization transistor M32 is located is the quantization path, and the second charge signal is stored in the overflow unit 112 through the overflow path and transferred to the first floating diffusion node FD1 through the quantization path.

[0175] Regarding the node sharing structure 120, this embodiment is the same as the second embodiment. For related content, refer to the first embodiment for details and will not be elaborated here. Among them, the figure shows a schematic diagram of the node sharing structure 120 including the first connection line 121a and the first switching transistor 122a.

[0176] Correspondingly, this embodiment further provides a control method for an image sensor, including a quantization stage. Further, it also includes a reset stage and an exposure stage; wherein, the image sensor is implemented by using the circuit structure described above.

[0177] The reset stage and the exposure stage are the same as those in the second embodiment. For related content, refer to the second embodiment for details and will not be elaborated here.

[0178] Regarding the quantization stage, in one implementation, the difference between this embodiment and the second embodiment is that this embodiment quantifies and reads out the second charge signal and the second reset signal based on a new node including the second floating diffusion node FD2. Among them, the storage capacity of the new node is the sum of the storage capacity of the second floating diffusion node FD2 itself, the storage capacity of the gain unit 113 itself, and the storage capacity of the node sharing structure 120 itself. In addition, the control of the corresponding transistors in this embodiment is slightly different from that in the second embodiment. For example, when quantifying and reading out the second charge signal or the second reset signal, at least the gain transistor M4 in the pixel block 110 corresponding to the second floating diffusion node FD2 needs to be controlled to be turned on. When the node sharing structure 120 further includes the first switching transistor 122a, the first switching transistor 122a also needs to be controlled to be turned on.

[0179] In another embodiment, for the quantization stage, another possible method is as follows: The second charge signal is stored in the overflow unit 112 through the overflow path and transferred to the first floating diffusion node FD1 through the quantization path. Among them, after the quantization readout of the first reset signal and the first charge signal at different gains is completed, the quantization readout of the second charge signal and the second reset signal can be performed. The second charge signal and the second reset signal can adopt the correlated double sampling method and / or a method that is not a true correlated double sampling method (for example, controlling the quantization path in the overflow unit 112 to be closed to perform the quantization readout of the second reset signal based on the first floating diffusion node FD1, and controlling the quantization path to be open to perform the quantization readout of the second charge signal based on the first floating diffusion node FD1 to achieve the correlated double sampling of the second charge signal; controlling the quantization path in the overflow unit 112 to be open to perform the quantization readout of the second charge signal based on the first floating diffusion node FD1, and performing a reset operation on the first floating diffusion node FD1 to perform the quantization read of the second reset signal based on the first floating diffusion node FD1 to achieve the non-true correlated double sampling of the second charge signal). In an optional example, after the quantization readout of the first charge signal at the first gain is completed, the quantization readout of the second charge signal is directly performed without performing a reset operation.

[0180] Embodiment 4

[0181] As Figure 7 shown, this embodiment provides an image sensor 100 based on gain adjustment, including a plurality of pixel blocks 110 arranged in an array and a node sharing structure 120.

[0182] The pixel block 110 includes a photosensitive unit 111, an overflow unit 112, and a gain unit 113. Further, it also includes a fourth reset unit 114d and a fourth readout unit 115d; among them, the pixel block 110 includes a floating diffusion node, that is, the first floating diffusion node FD1.

[0183] The photosensitive unit 111 and the gain unit 113 are the same as those in Embodiment 1. For the relevant description, please refer to Embodiment 1 and will not be repeated here. It should be noted that in the gain unit 113 of this embodiment, the first end of the gain transistor M4 is coupled to the fourth reset unit 114d instead of the first reset unit 114a.

[0184] The overflow unit 112 is coupled to the gain unit 113. For example, it is coupled to the low-gain quantization node of the gain unit 113 and is used to store the second charge signal; among them, the overflow unit 112 includes a common path, and the second charge signal is stored in the overflow unit 112 through the common path and transferred to the first floating diffusion node FD1 through the common path.

[0185] As an example, the overflow unit 112 includes an overflow quantization transistor M8 and a third storage device C13; the control terminal of the overflow quantization transistor M8 receives an overflow quantization control signal OF, the first terminal is coupled to the low-gain quantization node of the gain unit 113, for example, coupled to the first terminal of the gain transistor M4, and the second terminal is coupled to the first terminal of the third storage device C13; the second terminal of the third storage device C13 is coupled to a reference potential, for example, coupled to a ground potential; wherein, the path where the overflow quantization transistor M8 is located is a shared path.

[0186] Among them, the third storage device C13 includes a capacitor device, the overflow quantization transistor M8 includes an NMOS transistor, the gate of the overflow quantization transistor M8 receives the overflow quantization control signal OF, the drain is connected to the drain of the gain transistor M4, and the source is connected to the first terminal of the third storage device C13; of course, in other examples, it is also feasible that the overflow quantization transistor M8 includes a PMOS transistor, which has no impact on this embodiment.

[0187] The fourth reset unit 114d is coupled to the first floating diffusion node FD1 through the gain unit 113, and is used to reset the first floating diffusion node FD1, the photosensitive unit 111 and the overflow unit 112.

[0188] As an example, the fourth reset unit 114d includes a fourth reset transistor M54, the control terminal receives a fourth reset control signal RST4, the first terminal is coupled to a seventh power supply potential, and the second terminal is coupled to the gain unit 113, for example, coupled to the drain of the gain transistor M4. Among them, the fourth reset transistor M54 includes an NMOS transistor, the gate receives the fourth reset control signal RST4, the drain is connected to the seventh power supply potential, and the source is connected to the drain of the gain transistor M4. The seventh power supply potential is usually the potential of the working voltage and is always a high potential; of course, in other examples, it is also feasible that the fourth reset transistor M54 includes a PMOS transistor, which has no impact on this embodiment.

[0189] The fourth readout unit 115d is coupled to the first floating diffusion node FD1, and is used to at least quantize and read out the first charge signal and the second charge signal transferred to the first floating diffusion node FD1; in an optional solution, the fourth readout units 115d of different row pixel blocks 110 in the same column are quantized and read out through different column lines.

[0190] As an example, the fourth readout unit 115d includes a fourth source-follower transistor M64 and a fourth selection transistor M74. The control terminal of the fourth source-follower transistor M64 is coupled to the first floating diffusion node FD1, the first terminal is coupled to an eighth power supply potential, the second terminal is coupled to the first terminal of the fourth selection transistor M74, and the control terminal of the fourth selection transistor M74 receives a fourth selection control signal SEL4, and the second terminal is coupled to the corresponding column line.

[0191] Among them, the fourth source follower transistor M64 includes an NMOS transistor, the fourth selection transistor M74 includes an NMOS transistor. The gate of the fourth source follower transistor M64 is connected to the first floating diffusion node FD1, the drain is connected to the eighth power supply potential, and the source is connected to the first end of the fourth selection transistor M74. The gate of the fourth selection transistor M74 receives the fourth selection control signal SEL4, and the source is connected to the corresponding column line. The eighth power supply potential is usually the potential of the working voltage and is always at a high potential. Of course, in other examples, it is also feasible that the fourth source follower transistor M64 includes a PMOS transistor and the fourth selection transistor M74 includes a PMOS transistor, which has no impact on this embodiment.

[0192] The node sharing structure 120 is coupled between the gain units 113 of at least two pixel blocks 110, and is used to increase the storage capacity of the first floating diffusion node FD1 based on node sharing when the gain unit 113 is turned on, so that the first gain mode has a lower conversion gain, thereby being applicable to the situation where the demand for high-light scenarios gradually increases.

[0193] In an alternative solution, the node sharing structure 120 is coupled between the gain units 113 of pixel blocks 110 in different rows in the same column; further, the node sharing structure 120 is coupled between the gain units 113 of adjacent pixel blocks 110 in the same column.

[0194] As an example, the node sharing structure 120 includes a second connection line 121b and a second switching transistor 122b. The second connection line 121b is coupled between the gain units 113 of at least two pixel blocks 110, for example, coupled between the first ends of the gain transistors M4 of adjacent pixel blocks 110 in the same column. The second switching transistor 122b is serially coupled to the second connection line 121b, and its control terminal receives the second switching control signal SW2. Among them, the second switching transistor 122b includes an NMOS transistor. Of course, it is also feasible that the second switching transistor 122b includes a PMOS transistor, which has no impact on this embodiment.

[0195] Correspondingly, as Figure 8 shown, this embodiment also provides a control method for an image sensor, including a quantization stage. Further, it also includes a reset stage and an exposure stage; among them, the image sensor is implemented by using the circuit structure described above.

[0196] Reset stage:

[0197] Perform a reset operation on the first floating diffusion node FD1, the photosensitive unit 111, and the overflow unit 112.

[0198] For example, control the fourth reset transistor M54, gain transistor M4, transfer transistor M1, and overflow quantization transistor M8 to turn on, and clear the charges of the first floating diffusion node FD1, photosensitive element PD, and third storage device C13 to achieve signal reset and complete the reset operation. After that, control the fourth reset transistor M54 and transfer transistor M1 to turn off.

[0199] Exposure stage:

[0200] Store the second charge signal in the overflow unit 112. Specifically, open the common path and store the second charge signal in the overflow unit 112 through the common path.

[0201] For example, since the overflow quantization transistor M8 is turned on and remains on during the reset stage, the common path is opened. At this time, the second charge signal overflowing from the photosensitive element PD in the photosensitive unit 111 is transferred through this common path and stored in the third storage device C13 of the overflow unit 112.

[0202] When the amount of charge sensed by the photosensitive element PD does not reach the overflow state, the converted charge signal only includes the first charge signal and is stored on the photosensitive element PD. At this time, although the common path is opened, no second charge signal is transferred through the common path to the third storage device C13, and it can be considered that the corresponding second charge signal is zero during this process. When the amount of charge sensed by the photosensitive element PD reaches the overflow state, the converted charge signal includes the first charge signal and the second charge signal. Among them, the first charge signal is stored on the photosensitive element PD, and the second charge signal is transferred through the common path and stored in the third storage device C13.

[0203] Quantization stage:

[0204] Quantize and read out the first charge signal under different gain modes, and quantize and read out the second charge signal. Among them, when the gain unit 113 is turned on, node sharing is performed through the node sharing structure 120 to increase the storage capacity of the first floating diffusion node FD1, and the first floating diffusion node with increased storage capacity is defined as the shared node.

[0205] In one embodiment, the quantization stage includes: first performing non-genuine correlated double sampling on the second charge signal, and then performing correlated double sampling on the first charge signal under different gain modes to avoid the second charge signal remaining on the first floating diffusion node FD1 from affecting the quantization and readout of other signals.

[0206] Specifically, it includes: controlling the common path and the gain unit 113 in the overflow unit 112 of the read row to be opened and controlling the node sharing structure 120 to be closed, so as to perform quantization readout of the second charge signal based on the first floating diffusion node FD1, and performing a reset operation on the first floating diffusion node FD1 to perform quantization readout of the second reset signal based on the first floating diffusion node FD1;

[0207] Controlling the common path in the overflow unit 112 of the read row to be closed and controlling the node sharing structure 120 to be opened, controlling the gain unit 113 of the read row to be opened and then closed, so as to perform quantization readout of the first reset signal in the first gain mode and the second gain mode based on the shared node and the first floating diffusion node FD1 respectively, controlling the gain unit 113 of the read row to be closed and then opened, so as to perform quantization readout of the first charge signal in the second gain mode and the first gain mode based on the first floating diffusion node FD1 and the shared node respectively.

[0208] For example, controlling the node sharing structure 120 to be closed by controlling the second switch transistor 122b to be closed. At the same time, since the gain transistor M4 and the overflow quantization transistor M8 are opened and kept open during the reset stage, the image sensor operates in the first gain mode and the common path is opened;

[0209] Controlling the fourth selection transistor M74 in the fourth read unit 115d to be opened to perform quantization readout of the second charge signal based on the first floating diffusion node FD1; then controlling the fourth reset transistor M54 to be opened and then closed to perform a secondary reset operation on the first floating diffusion node FD1 to perform quantization readout of the second reset signal based on the first floating diffusion node FD1, and then controlling the overflow quantization transistor M8 to be closed;

[0210] Controlling the second switch transistor 122b to be opened and then closed to perform quantization readout of the first reset signal in the first gain mode based on the shared node; and controlling the gain transistor M4 to be closed to switch the image sensor to the second gain mode to perform quantization readout of the first reset signal in the second gain mode based on the first floating diffusion node FD1;

[0211] Controlling the transfer transistor M1 to be opened and then closed to perform quantization readout of the first charge signal in the second gain mode based on the first floating diffusion node FD1; and controlling the gain transistor M4 to be opened to switch the image sensor back to the first gain mode again, controlling the transfer transistor M1 to be opened and then closed, and controlling the second switch transistor 122b to be opened and then closed to perform quantization readout of the first charge signal in the first gain mode based on the shared node.

[0212] Embodiment Five

[0213] Such as Figure 9As shown, this embodiment provides an image sensor 100 based on gain adjustment, including a plurality of pixel blocks 110 arranged in an array and a node sharing structure 120.

[0214] For the pixel block 110, the difference between this embodiment and the fourth embodiment is that the overflow unit 112 of this embodiment is coupled to the high-gain quantization node of the gain unit 113; specifically: the control end of the overflow quantization transistor M8 receives the overflow quantization control signal OF, the first end is coupled to the high-gain quantization node of the gain unit 113, for example, coupled to the second end of the gain transistor M4, the second end is coupled to the first end of the third storage device C13, and the second end of the third storage device C13 is coupled to the reference potential, for example, coupled to the variable potential; wherein, the path where the overflow quantization transistor M8 is located is a common path.

[0215] For the node sharing structure 120, the difference between this embodiment and the fourth embodiment is that the node sharing structure 120 of this embodiment may only include the second connection line 121b. Of course, it is also feasible to include the second switching transistor 122b at the same time.

[0216] Correspondingly, as Figure 10 and Figure 11 shown, this embodiment also provides a control method for an image sensor, including a quantization stage. Further, it also includes a reset stage and an exposure stage; wherein, the image sensor is implemented by using the circuit structure described above.

[0217] Reset stage:

[0218] Perform a reset operation on the first floating diffusion node FD1, the photosensitive unit 111 and the overflow unit 112.

[0219] For example, control the fourth reset transistor M54, the gain transistor M4, the transfer transistor M1 and the overflow quantization transistor M8 to be turned on, clear the charges of the first floating diffusion node FD1, the photosensitive element PD and the third storage device C13 to achieve signal reset, and complete the reset operation. After that, control the fourth reset transistor M54, the gain transistor M4 and the transfer transistor M1 to be turned off.

[0220] Of course, the fourth reset transistor M54 may not be turned off at the end of the reset stage. For example, it is turned off in the quantization stage. Further, the fourth reset transistor M54 is turned off when the fourth selection transistor M74 in the fourth readout unit 115d is first turned on, so as to avoid crosstalk of other pixel blocks to the corresponding floating diffusion node of the current pixel block in the exposure stage.

[0221] Exposure stage:

[0222] Store the second charge signal into the overflow unit 112. Specifically: open the common path, and store the second charge signal into the overflow unit 112 through the common path.

[0223] For example, since the overflow quantization transistor M8 is turned on and remains on during the reset phase, the common path is turned on. At this time, the second charge signal overflowing from the photosensitive element PD in the photosensitive unit 111 is transferred through the common path and stored in the third storage device C13 of the overflow unit 112. Then, the overflow quantization transistor M8 is controlled to turn off.

[0224] When the amount of charge sensed by the photosensitive element PD does not reach the overflow state, the converted charge signal only includes the first charge signal and is stored on the photosensitive element PD. At this time, although the common path is turned on, no second charge signal is transferred through the common path to the third storage device C13, and it can be considered that the corresponding second charge signal is zero during this process. When the amount of charge sensed by the photosensitive element PD reaches the overflow state, the converted charge signal includes the first charge signal and the second charge signal. Among them, the first charge signal is stored on the photosensitive element PD, and the second charge signal is transferred through the common path and stored in the third storage device C13.

[0225] Quantization phase:

[0226] In one embodiment, the quantization phase includes: performing correlated double sampling on the first charge signal in different gain modes and performing non-genuine correlated double sampling on the second charge signal.

[0227] Specifically, it includes: controlling the common path in the overflow unit 112 of the read row to close and controlling the node sharing structure 120 to open, controlling the gain unit 113 of the read row to open and then close, so as to perform quantization readout of the first reset signal in the first gain mode and the second gain mode respectively based on the shared node and the first floating diffusion node FD1, controlling the gain unit 113 of the read row to close and then open, so as to perform quantization read of the first charge signal in the second gain mode and the first gain mode respectively based on the first floating diffusion node and the shared node;

[0228] Controlling the common path in the overflow unit 112 of the read row to open and the gain unit 113 to close, so as to perform quantization readout of the second charge signal based on the first floating diffusion node FD1, performing a reset operation on the first floating diffusion node FD1, so as to perform quantization readout of the second reset signal based on the first floating diffusion node FD1.

[0229] It should be noted that when the node sharing structure 120 only includes the second connection line 121b, there is no need to additionally control the node sharing structure 120 to open, and the node sharing structure 120 is default to be in the open state; when the node sharing structure 120 further includes the second switching transistor 122b, the node sharing structure 120 is controlled to open by controlling the second switching transistor 122b to open.

[0230] Taking the example that the node sharing structure 120 only includes the second connection line 121b; the gain transistor M4 in the control gain unit 113 is turned on. Since the node sharing structure 120 only includes the second connection line 121b, node sharing is achieved when the gain transistor M4 is turned on, and the image sensor operates in the first gain mode;

[0231] Control the fourth selection transistor M74 in the fourth readout unit 115d to be turned on to perform quantization readout of the first reset signal in the first gain mode based on the shared node; then control the gain transistor M4 to be turned off to switch the image sensor to the second gain mode to perform quantization readout of the first reset signal in the second gain mode based on the first floating diffusion node FD1; then control the transfer transistor M1 in the photosensitive unit 111 to be turned on and then off to transfer the first charge signal stored in the photosensitive element PD to the first floating diffusion node FD1 to perform quantization readout of the first charge signal in the second gain mode based on the first floating diffusion node FD1; control the gain transistor M4 to be turned on to switch the image sensor back to the first gain mode, control the transfer transistor M1 to be turned on and then off to transfer the first charge signal stored in the photosensitive element PD to the shared node to perform quantization readout of the first charge signal in the first gain mode based on the shared node;

[0232] Control the gain transistor M4 to be turned off, control the overflow quantization transistor M8 to be turned on, and transfer the second charge signal stored in the third storage device C13 in the overflow unit 112 to the first floating diffusion node FD1 through the common path to perform quantization readout of the second charge signal based on the first floating diffusion node FD1; then control the fourth reset transistor M54 in the fourth reset unit 114d to be turned on and then off, and at the same time control the gain transistor M4 to be turned on and then off to perform a secondary reset operation on the first floating diffusion node FD1 to perform quantization readout of the second reset signal based on the first floating diffusion node FD1.

[0233] In another embodiment, the quantization stage includes: performing correlated double sampling on the first charge signal in different gain modes and performing correlated double sampling on the second charge signal.

[0234] Specifically, it includes: controlling the common path in the overflow unit 112 of the readout row to be closed and controlling the node sharing structure 120 to be opened, controlling the gain unit 113 of the readout row to be turned on and then off to perform quantization readout of the first reset signal in the first gain mode and the second gain mode based on the shared node and the first floating diffusion node FD1 respectively, and controlling the gain unit 113 of the readout row to be turned off and then on to perform quantization readout of the first charge signal in the second gain mode and the first gain mode based on the first floating diffusion node and the shared node respectively;

[0235] The control gain unit 113 is turned off to perform quantization readout of the second reset signal based on the first floating diffusion node FD1. Then, after the common path in the overflow unit 112 of the read row is turned on and then off, the second charge signal is transferred to the first floating diffusion node FD1 through the common path to perform quantization readout of the second charge signal based on the first floating diffusion node FD1.

[0236] It should be noted that when the node sharing structure 120 only includes the second connection line 121b, there is no need to additionally control the node sharing structure 120 to be turned on, and the node sharing structure 120 is default in the on state; when the node sharing structure 120 further includes the second switching transistor 122b, the node sharing structure 120 is controlled to be turned on by controlling the second switching transistor 122b to be turned on.

[0237] Taking the case where the node sharing structure 120 only includes the second connection line 121b as an example; the gain transistor M4 in the control gain unit 113 is turned on. Since the node sharing structure 120 only includes the second connection line 121b, node sharing is achieved when the gain transistor M4 is turned on, and the image sensor operates in the first gain mode;

[0238] The fourth selection transistor M74 in the fourth readout unit 115d is controlled to be turned on to perform quantization readout of the first reset signal in the first gain mode based on the shared node; then the gain transistor M4 is controlled to be turned off to switch the image sensor to the second gain mode to perform quantization readout of the first reset signal in the second gain mode based on the first floating diffusion node FD1; then the transfer transistor M1 in the photosensitive unit 111 is controlled to be turned on and then off to transfer the first charge signal stored in the photosensitive element PD to the first floating diffusion node FD1 to perform quantization readout of the first charge signal in the second gain mode based on the first floating diffusion node FD1; the gain transistor M4 is controlled to be turned on to switch the image sensor back to the first gain mode, the transfer transistor M1 is controlled to be turned on and then off to transfer the first charge signal stored in the photosensitive element PD to the shared node to perform quantization readout of the first charge signal in the first gain mode based on the shared node;

[0239] Control the fourth reset transistor M54 to turn on and then off, and then control the gain transistor M4 to turn off, perform a secondary reset operation on the first floating diffusion node FD1, and perform quantization readout of the second reset signal based on the first floating diffusion node FD1; control the overflow quantization transistor M8 to turn on, and transfer the second charge signal stored in the third storage device C13 in the overflow unit 112 to the first floating diffusion node FD1 through the common path, and perform quantization readout of the second charge signal based on the first floating diffusion node FD1. Of course, in other embodiments, it is also possible to perform both correlated double sampling and non-genuine correlated double sampling on the second charge signal; in this case, usually, the second charge signal is first subjected to correlated double sampling, and then non-genuine correlated double sampling is performed on the second charge signal.

[0240] In summary, an image sensor and control method based on gain adjustment according to the present invention, through the design of the pixel block and node sharing structure, realizes that when the gain unit is turned on, node sharing is performed through the node sharing structure to increase the storage capacity of the floating diffusion node in the current pixel block, so as to be applicable to the situation where the requirements for high-light scenes gradually increase. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0241] The above embodiments are only illustrative of the principles and effects of the present invention and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. An image sensor based on gain adjustment, characterized in that: It includes a plurality of pixel blocks and a node sharing structure arranged in an array; The pixel block includes a photosensitive unit, an overflow unit, and a gain unit, wherein the photosensitive unit and the gain unit are coupled to a first floating diffusion node, the overflow unit is coupled to the photosensitive unit or the gain unit, the photosensitive unit generates a first charge signal and a second charge signal based on photoelectric conversion and stores the first charge signal, the overflow unit is used to store the second charge signal, and the gain unit is used to switch between different gain modes; The node sharing structure is coupled between the gain units of at least two of the pixel blocks, and is configured to increase the storage capacity of the first floating diffusion node based on node sharing when the gain units are turned on.

2. The image sensor based on gain adjustment according to claim 1, characterized in that: When the overflow unit is coupled to the photosensitive unit, the overflow unit includes an overflow path and a quantization path, the second charge signal is stored in the overflow unit through the overflow path and transferred to the second floating diffusion node or the first floating diffusion node through the quantization path, wherein the first charge signal is transferred to the first floating diffusion node.

3. The image sensor based on gain adjustment according to claim 2, characterized in that: The second charge signal is stored in the overflow unit through the overflow path and transferred to the second floating diffusion node through the quantization path, wherein: The first floating diffusion node and the second floating diffusion node belong to the same pixel block, and the pixel block further includes a first reset unit, a second reset unit, a first readout unit, and a second readout unit; the first reset unit is coupled to the first floating diffusion node through the gain unit, and is used to reset the first floating diffusion node and the photosensitive unit; the second reset unit is coupled to the second floating diffusion node, and is used to reset the second floating diffusion node; the first readout unit is coupled to the first floating diffusion node, and is used to at least quantize and read out the first charge signal transferred to the first floating diffusion node; the second readout unit is coupled to the second floating diffusion node, and is used to at least quantize and read out the second charge signal transferred to the second floating diffusion node; the first reset unit and / or the second reset unit are further used to reset the overflow unit; Alternatively, the first floating diffusion node and the second floating diffusion node belong to the pixel blocks in different rows in the same column, and the pixel blocks also include a third reset unit and a third readout unit; the third reset unit is coupled to the corresponding floating diffusion node through the gain unit, and is used to reset the corresponding floating diffusion node, the photosensitive unit and the overflow unit; the third readout unit is coupled to the corresponding floating diffusion node, and is used to at least quantize and read out the corresponding charge signal transferred to the corresponding floating diffusion node.

4. The image sensor based on gain adjustment according to claim 3, characterized in that: When the pixel block includes a first readout unit and a second readout unit, the first readout unit and the second readout unit are quantized and read out through different column lines; when the pixel block includes a third readout unit, the third readout units of the pixel blocks in different rows in the same column are quantized and read out through different column lines.

5. The image sensor based on gain adjustment according to claim 3, characterized in that: When the first floating diffusion node and the second floating diffusion node belong to pixel blocks in different rows in the same column, the pixel blocks in different rows in the same column include pixel blocks in two adjacent rows in the same column; wherein, in the pixel blocks in two adjacent rows in the same column, the pixel blocks in the upper row always use the floating diffusion node corresponding to the pixel blocks in the lower row as its second floating diffusion node, or the pixel blocks in the lower row always use the floating diffusion node corresponding to the pixel blocks in the upper row as its second floating diffusion node, or, the floating diffusion nodes corresponding to the pixel blocks in the two rows are each other's second floating diffusion nodes.

6. The image sensor based on gain adjustment according to any one of claims 2 to 5, characterized in that: The overflow unit includes a first overflow transistor, a first quantization transistor and a first storage device; the control terminal of the first overflow transistor receives a first overflow control signal, the first terminal is coupled to the photosensitive unit, and the second terminal is coupled to the first terminal of the first storage device; the control terminal of the first quantization transistor receives a first quantization control signal, the first terminal is coupled to the second floating diffusion node or to the second floating diffusion node through the gain unit or to the first floating diffusion node through the corresponding gain unit, and the second terminal is coupled to the first terminal of the first storage device; the second terminal of the first storage device is coupled to a reference potential; wherein the path where the first overflow transistor is located is the overflow path, and the path where the first quantization transistor is located is the quantization path; Alternatively, when the first floating diffusion node and the second floating diffusion node belong to the same pixel block, the overflow unit removes the first quantization transistor. In this case, the first terminal of the first storage device is also coupled to the second floating diffusion node.

7. The image sensor based on gain adjustment according to claim 3, characterized in that: When the first floating diffusion node and the second floating diffusion node belong to the pixel blocks in different rows in the same column, the overflow unit includes a second overflow transistor, a second quantization transistor and a second storage device; the control end of the second overflow transistor receives a second overflow control signal, the first end is coupled to the photosensitive unit, and the second end is coupled to the first end of the second storage device; the control end of the second quantization transistor receives a second quantization control signal, the first end is coupled to the second floating diffusion node through the node sharing structure and the gain unit corresponding to the second floating diffusion node, and the second end is coupled to the first end of the second storage device; the second end of the second storage device is coupled to the reference potential; wherein, the path where the second overflow transistor is located is the overflow path, and the path where the second quantization transistor is located is the quantization path.

8. The image sensor based on gain adjustment according to claim 1, characterized in that: The node sharing structure includes a first connection line coupled between the gain units of at least two of the pixel blocks.

9. The image sensor based on gain adjustment according to claim 8, characterized in that: The node sharing structure further includes at least one first switch tube, which is coupled in series to the first connection line and has a control terminal receiving a first switch control signal.

10. The image sensor based on gain adjustment according to claim 1, characterized in that: When the overflow unit is coupled to the gain unit, the overflow unit includes a common path, the second charge signal is stored in the overflow unit through the common path and is transferred to the first floating diffusion node through the common path, wherein the first charge signal is transferred to the first floating diffusion node; The pixel block also includes a fourth reset unit and a fourth readout unit; the fourth reset unit is coupled to the first floating diffusion node through the gain unit, and is used to reset the first floating diffusion node, the photosensitive unit and the overflow unit; the fourth readout unit is coupled to the first floating diffusion node, and is used to quantize and read out at least the first charge signal and the second charge signal transferred to the first floating diffusion node.

11. The image sensor based on gain adjustment according to claim 10, characterized in that: The overflow unit includes an overflow quantization transistor and a third storage device; the overflow quantization transistor has a control terminal receiving an overflow quantization control signal, a first terminal coupled to a high gain quantization node or a low gain quantization node of the gain unit, and a second terminal coupled to a first terminal of the third storage device; The second terminal of the third storage device is coupled to a reference potential; wherein the path where the overflow quantization transistor is located is the common path; When the first terminal of the overflow quantization transistor is coupled to the high-gain quantization node of the gain unit, the node sharing structure includes a second connection line coupled between the gain units of at least two of the pixel blocks; when the first terminal of the overflow quantization transistor is coupled to the low-gain quantization node of the gain unit, the node sharing structure further includes a second switch transistor coupled in series to the second connection line, a control terminal of which receives a second switch control signal; And / or, the fourth readout units of the pixel blocks in different rows in the same column perform quantized readout through different column lines.

12. A control method for an image sensor based on gain adjustment according to any one of claims 1 to 11, characterized in that: include: In the quantization stage, the first charge signal in different gain modes is quantized and read out, and the second charge signal is quantized and read out; wherein, when the gain unit is turned on, the storage capacity of the first floating diffusion node is increased by node sharing through the node sharing structure.

13. The control method of the image sensor based on gain adjustment according to claim 12, characterized in that: When the overflow unit is coupled to the photosensitive unit, the quantization stage includes: Controlling the node sharing structure to be turned on, controlling the gain unit to be turned on and then turned off, so as to quantize and read out the first reset signal in the first gain mode and the second gain mode based on the shared node and the first floating diffusion node respectively, and controlling the gain unit to be turned off and then turned on, so as to quantize and read out the first charge signal in the second gain mode and the first gain mode respectively based on the first floating diffusion node and the shared node; Control the quantization path in the overflow unit to be closed so as to perform quantization reading of the second reset signal based on the second floating diffusion node or a new node including the second floating diffusion node or the first floating diffusion node, and control the quantization path to be opened so as to perform quantization reading of the second charge signal based on the second floating diffusion node or a new node including the second floating diffusion node or the first floating diffusion node; and / or control the quantization path in the overflow unit to be opened so as to perform quantization reading of the second charge signal based on the second floating diffusion node or a new node including the second floating diffusion node or the first floating diffusion node, and perform a reset operation on the second floating diffusion node or the first floating diffusion node so as to perform quantization reading of the second reset signal based on the second floating diffusion node or a new node including the second floating diffusion node or the first floating diffusion node.

14. The control method of the image sensor based on gain adjustment according to claim 13, characterized in that: When the second reset signal and the second charge signal are quantized and read out based on the second floating diffusion node or a new node including the second floating diffusion node, if the first floating diffusion node and the second floating diffusion node belong to the same pixel block, the second charge signal is quantized and read out simultaneously with the first charge signal in the first gain mode or the second gain mode; if the first floating diffusion node and the second floating diffusion node belong to the pixel blocks in different rows in the same column, the second charge signal is quantized and read out simultaneously with the first charge signal in the second gain mode; and / or, for the case where the second reset signal is quantized and read out before the second charge signal: if the first floating diffusion node and the second floating diffusion node belong to the same pixel block, the second reset signal is quantized and read out simultaneously with the first reset signal in the first gain mode or the second gain mode; if the first floating diffusion node and the second floating diffusion node belong to the pixel blocks in different rows in the same column, the second reset signal is quantized and read out simultaneously with the first reset signal in the second gain mode.

15. The control method of the image sensor based on gain adjustment according to claim 12, characterized in that: When the overflow unit is coupled to the low-gain quantization node of the gain unit, the quantization stage includes: Controlling the common path and the gain unit in the overflow unit of the readout row to be opened and controlling the node sharing structure to be closed, so as to perform quantized reading of the second charge signal based on the first floating diffusion node, and performing a reset operation on the first floating diffusion node, so as to perform quantized reading of the second reset signal based on the first floating diffusion node; Controlling the common path in the overflow unit of the readout line to close and controlling the node sharing structure to open, controlling the gain unit of the readout line to open and then close, so as to quantize and read out the first reset signal in the first gain mode and the second gain mode based on the shared node and the first floating diffusion node respectively, controlling the gain unit of the readout line to close and then open, so as to quantize and read out the first charge signal in the second gain mode and the first gain mode respectively based on the first floating diffusion node and the shared node.

16. The control method of the image sensor based on gain adjustment according to claim 12, characterized in that: When the overflow unit is coupled to the high-gain quantization node of the gain unit, the quantization stage includes: Controlling the common path in the overflow unit of the readout row to be closed and controlling the node sharing structure to be opened, controlling the gain unit of the readout row to be opened and then closed, so as to perform quantized reading of the first reset signal in the first gain mode and the second gain mode based on the shared node and the first floating diffusion node respectively, and controlling the gain unit of the readout row to be closed and then opened, so as to perform quantized reading of the first charge signal in the second gain mode and the first gain mode respectively based on the first floating diffusion node and the shared node; Control the common path in the overflow unit of the readout line to open and the gain unit to close, so as to perform quantized reading of the second charge signal based on the first floating diffusion node, perform a reset operation on the first floating diffusion node, so as to perform quantized reading of the second reset signal based on the first floating diffusion node, and / or control the gain unit to close, so as to perform quantized reading of the second reset signal based on the first floating diffusion node, and then control the common path in the overflow unit of the readout line to open and then close, and transfer the second charge signal to the first floating diffusion node through the common path, so as to perform quantized reading of the second charge signal based on the first floating diffusion node.

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