Operation panel alarm processing system supporting independent dimming

Abstract

The invention relates to an operation panel alarm processing system supporting independent dimming, and the system obtains a dimming instruction level, corresponding indicator light on-off and brightness information through the analysis of a CAN field bus network message, and adjusts the duty ratio of PWM1 and PWM2 signals through a PWM controller according to the dimming instruction level and a configurable alarm highlight level. According to the invention, the SCLK signal is shared, the CS1 and the CS2 are utilized to respectively control the output levels of the QnA pin and the Qn pin, grouping control is realized by sharing the SCLK signal and utilizing the CS1 and the CS2, and the cascade design of the SPI controller and the shift register chip set is utilized, so that the state and the brightness of each indicating lamp can be independently and accurately controlled, the state display of the other indicating lamps is not influenced, the occupation of the MCU pin is obviously reduced, and the cost is reduced. According to the invention, sailors can find alarm information in an early stage and leave sufficient time to deal with and process the alarm information, so that loss caused by untimely processing of the alarm information is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of ship electronic circuit design and control, and in particular to an operation panel alarm processing system supporting independent dimming. Background Art

[0002] An alarm operation panel is a device used to monitor and manage alarm status, commonly used in industrial control, security systems, fire protection systems, and other scenarios. It integrates alarm displays, operation buttons, and status indicators. Different colored lights indicate the operating status of the device or system. Flashing or steady alarm indicators indicate system anomalies. Some alarm operation panels have built-in buzzers or can be linked to external alarms, providing both visual and audible warnings to help operators quickly identify and address alarm events.

[0003] The navigation alarm panel, as a specific application of the navigation control system, receives navigation system data via the CAN fieldbus and performs monitoring and alarm processing for navigation system-related equipment and parameters. To adapt to the needs of the corresponding operating environment, the navigation alarm panel should have network or local dimming capabilities. The dimming command is ultimately output through a modulated PWM signal to control the brightness of the panel's indicators. A PWM signal duty cycle of 0% represents maximum brightness; a PWM signal duty cycle of 100% represents off.

[0004] When a vessel is sailing at night or in certain specific modes, if an abnormal data alarm occurs while the alarm panel is dimmed, the corresponding indicator light will be illuminated or flashing. However, due to the dimming, the alarm event may not be discovered by the crew in a timely manner, thus missing the optimal time to handle it, which may ultimately endanger navigation safety. In other words, if the navigation alarm panel dimming level is at a lower brightness level rather than the highest level when the abnormal data triggers the alarm, then even if the corresponding indicator light is illuminated or flashing due to the alarm, the dimming will make it difficult to detect the alarm information in a timely manner, delaying the optimal time to handle the alarm, and causing serious losses and impacts.

[0005] In view of this, there is an urgent need for an operation panel alarm processing system that supports independent dimming, which is used to monitor navigation data in real time, highlight alarm information, and provide sound and light alarm status. Summary of the Invention

[0006] In order to solve the problem that the current navigation alarm operation panel does not have the independent dimming function of the indicator light, which makes it difficult to discover the alarm information in time, etc., the present invention provides an operation panel alarm processing system that supports independent dimming, which can independently control the flat brightness, high brightness and off state of each indicator light. Each indicator light can be independently adjusted in brightness or turned off according to actual needs without affecting the state of other indicator lights, greatly improving the flexibility and response speed of the system.

[0007] The technical solutions of the present invention are as follows:

[0008] An operation panel alarm processing system supporting independent dimming includes a circuit board disposed on an alarm operation panel, the circuit board including an embedded MCU and a CAN communication circuit. The circuit board also includes a first group of chips consisting of multiple shift register chips, a second group of chips, and multiple indicator light control circuits; the embedded MCU includes a CAN controller, an SPI controller, and a PWM controller; the indicator light control circuit includes an indicator light and two Darlington transistors;

[0009] The CAN communication circuit is connected to the CAN controller in the embedded MCU, and the CAN communication circuit obtains the CAN field bus message and sends it to the CAN controller; the CAN controller receives the CAN field bus message and parses it according to the communication protocol to obtain the dimming instruction level, the alarm highlight level, and the indicator light on and off information and brightness information;

[0010] The NOE input pin of each shift register chip in the first group of chips is connected to the PWM1 pin of the PWM controller, and the multiple parallel output pins of each shift register chip in the first group of chips are marked as QnA pins, which are used to control the flat light display of the indicator light; the NOE input pin of each shift register chip in the second group of chips is connected to the PWM2 pin of the PWM controller, and the multiple parallel output pins of each shift register chip in the second group of chips are marked as Qn pins, which are used to control the bright light display of the indicator light;

[0011] The MOSI pin of the SPI controller is respectively connected to the serial data input pin of the first shift register chip in the first group of chips and the second group of chips, and starting from the first shift register chip in each group of chips, the serial data input pin of each subsequent shift register chip is cascaded to the serial data output pin of the previous adjacent shift register chip; the SCLK pin of the SPI controller is respectively connected to the shift register clock input pin of each shift register chip in the first group of chips and the second group of chips, the CS1 pin of the SPI controller is connected to the storage register input pin of each shift register chip in the first group of chips; the CS2 pin of the SPI controller is connected to the storage register input pin of each shift register chip in the second group of chips;

[0012] The embedded MCU pre-generates a composite dimming data frame according to the indicator light on / off information and brightness information and writes it into the SPI controller. The SPI controller sends the flat light data stream in the composite dimming data frame to each shift register chip in the first group of chips through the MOSI pin and the SCLK pin, and synchronously latches the flat light data of each shift register chip in the first group of chips into their respective internal storage registers through the CS1 pin; at the same time, the highlight data stream in the composite dimming data frame is sent to each shift register chip in the second group of chips through the MOSI pin and the SCLK pin, and synchronously latches the highlight data of each shift register chip in the second group of chips into their respective internal storage registers through the CS2 pin; the PWM controller adjusts the duty cycle of the PWM1 signal output by the PWM1 pin according to the dimming instruction level and controls the output level of the QnA pin in combination with the storage register to control the flat light display of the indicator light, and adjusts the duty cycle of the PWM2 signal output by the PWM2 pin according to the alarm highlight level and controls the output level of the Qn pin in combination with the storage register to control the highlight display of the indicator light;

[0013] The cathode of an indicator light in the indicator light control circuit is connected to the collectors of two Darlington transistors. The base of one Darlington transistor in the indicator light control circuit is connected to any QnA pin of a shift register chip in the first group of chips, and the base of the other Darlington transistor is connected to any Qn pin of a shift register chip in the second group of chips. The emitters of the two Darlington transistors are both grounded. The output levels of the QnA pin and the Qn pin control the on and off states of the corresponding Darlington transistors, thereby realizing independent regulation of the normal brightness, high brightness, and off state of the indicator light.

[0014] Preferably, when the output level of the QnA pin of the first group of chips is low or high resistance, the Darlington transistor connected thereto is turned off. At this time, the indicator light is controlled solely by the Qn pin of the second group of chips. The PWM controller adjusts the duty cycle of the PWM2 signal output by the PWM2 pin according to the alarm highlight level to control the output level of the Qn pin, so that the indicator light is highlighted when an alarm occurs.

[0015] When the output level of the Qn pin of the second group of chips is low or high resistance, the Darlington transistor connected to it is turned off. At this time, the indicator light is controlled solely by the QnA pin of the first group of chips. The PWM controller adjusts the duty cycle of the PWM1 signal output by the PWM1 pin according to the dimming instruction level to control the output level of the QnA pin, thereby achieving a flat brightness display of the indicator light.

[0016] When the output levels of the QnA pin of the first group of chips and the Qn pin of the second group of chips are both low or high resistance, the two Darlington transistors are turned off and the indicator light is off.

[0017] Preferably, it also includes a buzzer, a relay and a power supply. The buzzer is respectively connected to the GPIO pin of the embedded MCU and the power supply, and the relay is respectively connected to the GPIO pin of the embedded MCU and the external alarm device. When the embedded MCU receives the alarm signal, the buzzer is synchronously triggered to sound and the relay is closed to start the external alarm device.

[0018] Preferably, the buzzer and relay are connected to the GPIO pin of the embedded MCU through a transistor, the positive poles of the buzzer and relay are connected to the power supply, the negative poles of the buzzer and relay are connected to the collector of the transistor, the base of the transistor is connected to the GPIO pin of the embedded MCU, and the emitter of the transistor is grounded.

[0019] Preferably, the indicator light control circuit also includes a button, which is connected to the GPIO pin of the embedded MCU, and the indicator light is set on the button and connected to the button; the embedded MCU simultaneously controls the working status of the indicator light and the buzzer according to the signal generated by the button action.

[0020] Preferably, the buttons include a confirmation button, a mute button and a test button. When the system detects an alarm signal, the indicator light enters a high-brightness flashing state and the buzzer starts to sound; when the mute button is pressed, the indicator light maintains a high-brightness flashing state and the buzzer stops sounding; when the confirmation button or the test button is pressed, the indicator light returns to a flat light display and the buzzer stops sounding; when the alarm information disappears, the indicator light goes out.

[0021] Preferably, the number of shift register chips in the first group of chips is equal to the number of shift register chips in the second group of chips.

[0022] Preferably, the transistor is an NPN bipolar transistor, and the base of the transistor is connected to the GPIO pin of the embedded MCU through a current-limiting resistor.

[0023] Preferably, the frequencies of the PWM1 signal and the PWM2 signal are both within an interval consisting of a preset first frequency threshold and a second frequency threshold, and the duty cycle resolutions of the PWM1 signal and the PWM2 signal are greater than or equal to the preset resolution threshold.

[0024] Preferably, the shift register chip is a 74HC595 chip.

[0025] The technical effects of the present invention are as follows:

[0026] The present invention provides an operation panel alarm processing system supporting independent dimming, comprising a circuit board arranged on the alarm operation panel, the circuit board comprising an embedded MCU, a CAN communication circuit, a first group of chips consisting of multiple shift register chips, a second group of chips, and multiple indicator light control circuits; the embedded MCU comprises a CAN controller, an SPI controller, and a PWM controller; the indicator light control circuit comprises an indicator light and two Darlington tubes; the CAN communication circuit is connected to the CAN controller in the embedded MCU, and is used to obtain CAN field bus messages and send them to the CAN controller; the CAN controller receives the CAN field bus messages and parses them according to the communication protocol to obtain the dimming instruction level and the alarm highlight level; the NOE input pin of each shift register chip in the first group of chips is connected to the PWM1 pin of the PWM controller, and the multiple parallel output pins of each shift register chip in the first group of chips are marked as QnA pins, which are used to control the flat light of the indicator light. Display, can make all flat light control channels respond synchronously to PWM1 dimming signal, realize uniform brightness change of the whole group of indicator lights, eliminate brightness difference caused by traditional discrete control, and by establishing a unified flat light control network identification, clearly distinguish the highlight control line during PCB layout, reducing wiring error rate; the NOE input pin of each shift register chip in the second group of chips is connected to the PWM2 pin of the PWM controller, and the multiple parallel output pins of each shift register chip in the second group of chips are marked as Qn pins, which are used to control the highlight display of the indicator light, so that the alarm highlight signal can operate independently of the flat light system and can be forced to be fully illuminated in an emergency, forming an independent highlight control physical channel, which is completely isolated from the flat light line, avoiding false triggering caused by signal coupling; by adjusting the duty cycle of PWM1 and PWM2 signals through the PWM controller, the output levels of QnA and Qn pins can be controlled respectively, thereby realizing fine control of the flat light brightness and highlight brightness of the indicator light.

[0027] The MOSI pin of the SPI controller is connected to the serial data input pin (DS input pin) of the first shift register chip in the first group of chips and the second group of chips respectively, realizing dual data stream transmission and synchronous update of flat light and highlighted light data; starting from the first shift register chip in each group of chips, the DS input pin of each subsequent shift register chip is cascaded to the serial data output pin (QP output pin) of the previous adjacent shift register chip. By adopting the cascade method, the number of I / Os directly connected to the MCU is effectively reduced, thereby simplifying the circuit design and wiring complexity, and greatly improving the flexibility and scalability of the hardware design. The SCLK pin of the SPI controller is connected to the shift register clock input pin (SH_CP pin) of each shift register chip in the first group of chips and the second group of chips respectively, the CS1 pin is connected to the storage register input pin (ST_CP pin) of each shift register chip in the first group of chips, and the CS2 pin is connected to the ST_CP pin of each shift register chip in the second group of chips. The first and second groups of chips are controlled respectively by the CS1 and CS2 signals, thereby realizing independent control of flat display and high-brightness display, enabling the system to simultaneously handle two different display requirements (such as flat brightness adjustment and alarm high-brightness flashing), and using a shared SCLK signal to ensure the consistency of data transmission. At the same time, independent control of the two groups of chips is realized through independent CS1 and CS2 signals, thereby improving the flexibility and scalability of the system. By multiplexing the SCLK signal and using CS1 and CS2 to realize group control, the number of MCU pins used is reduced, and the utilization rate of hardware resources is optimized. Moreover, since the latch operation of each chip is controlled by an independent CS signal, data conflict or inconsistent status update problems are avoided, thereby further enhancing the stability and reliability of the system.

[0028] The cathode of an indicator light in the indicator light control circuit is connected to the collectors of two Darlington tubes. The base of one Darlington tube in the indicator light control circuit is connected to any QnA pin of a shift register chip in the first group of chips, and the base of the other Darlington tube is connected to any Qn pin of a shift register chip in the second group of chips. The emitters of the two Darlington tubes are grounded. The output levels of the QnA pin and the Qn pin control the on and off states of the corresponding Darlington tubes, thereby realizing independent regulation of the flat brightness, high brightness and off of the indicator light. By controlling the level states of the QnA and Qn pins respectively, the flat brightness and high brightness of the indicator light can be independently controlled, so that each indicator light can be independently adjusted in brightness or turned off according to actual needs, which greatly improves the flexibility and response speed of the system. At the same time, The use of Darlington transistors enhances the driving capability and reliability of the circuit, ensuring stable operation even under high load conditions. Through this design, the alarm system can not only provide eye-catching visual warnings (high-brightness flashing) in emergency situations, but also provide soft but clear indications (plain light display) under normal operating conditions. This helps to improve the overall user experience and ensure that important information is conveyed in a timely and effective manner. Since all shift register chips (such as the 74HC595 chip) share the same clock signal (SCLK) and latch signal (CS), it can ensure that the data input and latch actions of all chips are synchronized. Therefore, when sending a series of data frames, it can ensure that the data is correctly distributed to each target register and the output status is updated at the same time, avoiding display confusion or errors caused by asynchrony.

[0029] The present invention can independently control the flat brightness, high brightness and off state of each indicator light, and supports any brightness level adjustment from completely off to maximum brightness. Through PWM signals (PWM1 and PWM2) combined with a shift register chip, fine control of the indicator light brightness is achieved to meet the visual needs in different scenarios; each indicator light can independently realize functions such as high-brightness flashing, flat light display or off alarm according to the alarm information, without affecting the status of other indicator lights, supporting configurable alarm highlight levels, and can dynamically adjust the alarm brightness according to actual needs to ensure that a striking visual warning is provided in an emergency; receiving external instructions and parsing dimming levels and alarm information through the CAN communication circuit to ensure that the system can respond to external environmental changes or user needs in real time; by sharing the SCLK signal and utilizing CS1 and CS2 implement group control, and the cascade design of the SPI controller and shift register chipset only requires three MCU pins (MOSI, SCLK, CS) to control multiple groups of 74HC595 chips, significantly reducing MCU pin usage, achieving efficient data transmission and synchronous updates, and optimizing hardware resource utilization. By organically combining CAN communication, PWM control, SPI data transmission, shift register cascade, and Darlington transistor drive technologies, the state and brightness of each indicator light can be independently and precisely controlled. At the same time, it has strong compatibility and scalability, making it suitable for a variety of complex application scenarios.

[0030] The present invention supports an independently dimming operating panel alarm processing system. When a data anomaly alarm occurs, multiple indicator lights within the alarm operating panel can simultaneously exist in high-brightness, flashing, flat, and off states, and can be controlled independently without affecting each other. Simultaneously, an internal buzzer sounds, triggering a relay to output a closure signal for linkage to an external alarm, enabling crew members to detect alarm information early and respond to it promptly. Configurable alarm highlight levels can be gently adjusted to maximum brightness within a specified time. The preferred 74HC595 chipset allows for cascaded connections for IO expansion solutions. Theoretically, there is no upper limit on the number of button indicators within the alarm operating panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 This is a schematic diagram of the preferred structure of the alarm processing system for the operation panel supporting independent dimming of the present invention.

[0032] Figure 2 Schematic diagram of the indicator light dimming control of the present invention. DETAILED DESCRIPTION

[0033] In order to more clearly understand the content of the present invention, it will be described in detail with reference to the accompanying drawings and embodiments.

[0034] The present invention relates to an operation panel alarm processing system supporting independent dimming. The alarm operation panel is deployed in the ship's wheelhouse area and has a dimming function. The system comprises a circuit board arranged on the alarm operation panel. The circuit board includes an embedded MCU, a CAN communication circuit, a first group of chips and a second group of chips consisting of multiple shift register chips (preferably 74HC595 shift register output latch chips, referred to as 74HC595 chips), multiple indicator light control circuits, relays, and buzzers. The embedded MCU includes built-in functions such as a CAN controller, an SPI controller, and a PWM controller. The indicator light control circuit includes an indicator light and two Darlington tubes (preferably a ULN2803 Darlington tube chip), and supports both network and local dimming modes. When a data abnormality alarm occurs, the corresponding indicator light in the alarm operation panel flashes brightly, the buzzer sounds at the same time, and triggers a relay to output a closed signal for linkage with an external alarm; after the alarm, the corresponding indicator light should remain in the alarm state regardless of whether the data returns to normal before the personnel confirms it, until the "Confirm" or "Silence" button is pressed; when the "Silence" button on the alarm operation panel is pressed or the external silence signal is input, the corresponding indicator light continues to flash brightly, the buzzer goes off, and the relay outputs an open signal; when the "Confirm / Test" button on the alarm operation panel is pressed or the external confirmation signal is input After that, the corresponding indicator light is displayed flat, the brightness during dimming is restored, the buzzer goes out, and the relay outputs an open-circuit signal; when the alarm information disappears, the corresponding indicator light goes out. When an alarm occurs, all the indicator lights on the operation panel can independently realize the alarm functions of high brightness flashing, flat light and off, without affecting the status of other indicator lights. At the same time, it has configurable alarm highlight levels. Each indicator light is jointly controlled by two Darlington tubes. By controlling the Darlington tube base level signals QnA and Qn, the high brightness, flat light and off alarm functions are realized, which can enable the crew to discover the alarm information at an early stage and deal with the alarm information in time.

[0035] Specifically, if Figure 1 As shown, the system includes a circuit board arranged on the alarm operation panel, the circuit board includes an embedded MCU, a CAN communication circuit, a first group of chips (composed of multiple shift register chips U1), a second group of chips (composed of multiple shift register chips U2) and multiple indicator light control circuits; the embedded MCU includes a CAN controller, an SPI controller and a PWM controller; the indicator light control circuit includes an indicator light (K1, K2... or KN) and two Darlington transistors.

[0036] Among them, the CAN communication circuit is connected to the CAN controller in the embedded MCU, and the CAN communication circuit obtains CAN field bus messages (such as data abnormality alarm information) in real time and sends them to the CAN controller; the CAN controller in the embedded MCU realizes CAN field bus communication through peripheral devices such as isolation circuits and transceiver chips, and will receive CAN field bus messages in real time and parse them according to the communication protocol to obtain the dimming command level, alarm highlight level, and indicator light on and off information and brightness information, and combined with the user's key operation status, determine the position and number of the corresponding flat indicator lights and corresponding highlight indicator lights on the alarm operation panel.

[0037] Each shift register chip in the first group of chips (preferably a 74HC595 chip, a 74HC595 chip in the first group of chips such as Figure 1 The NOE input pins (also called output enable pins NOE) of the first group of chips are connected to the PWM1 pin of the PWM controller, and the multiple parallel output pins of each shift register chip in the first group of chips are marked as QnA pins (that is, the multiple parallel output pins of each shift register chip are marked as Q1A, Q2A...QnA in sequence), and its SPI data stream is a flat light data stream, which is used to control the flat light display of the indicator light; that is, the PWM1 pin of the PWM controller is connected to the output enable pin NOE of each 74HC595 chip in the first group of chips, and through the output enable pin NOE of the first group of chips combined with the internal storage register of the 74HC595 chip, the parallel output pin network of the first group of chips is marked as QnA PWM signal, and its SPI data stream is a flat light data stream, which is used for the flat light display of the indicator light. Preferably, when the output level signal of the QnA pin of the first chip group is low or high resistance, that is, when QnA = 0, the Darlington transistor connected thereto is turned off. At this time, the indicator light is controlled solely by the Qn pin of the second chip group. The PWM controller adjusts the duty cycle of the PWM2 signal output by the PWM2 pin according to the alarm highlight level to control the output level of the Qn pin, thereby achieving a highlighted display of the indicator light during an alarm. When the output level signal of the Qn pin of the second chip group is low or high resistance, that is, when Qn = 0, the Darlington transistor connected thereto is turned off. At this time, the indicator light is controlled solely by the QnA pin of the first chip group. The PWM controller adjusts the duty cycle of the PWM1 signal output by the PWM1 pin according to the dimming command level to control the output level of the QnA pin. Its SPI data stream is a flat light data stream, used to display the flat light brightness of the indicator light.

[0038] Each shift register chip in the second group of chips (preferably a 74HC595 chip, a 74HC595 chip in the second group of chips such as Figure 1The NOE input pins (represented by U2 in the figure) are all connected to the PWM controller's PWM2 pin, and the multiple parallel output pins of each shift register chip in the second group of chips are labeled Qn pins (that is, the multiple parallel output pins of each shift register chip are labeled Q1, Q2, ..., Qn in sequence) to control the highlight display of the indicator light. Specifically, the PWM controller's PWM2 pin is connected to the output enable pin (NOE) of each 74HC595 chip in the second group of chips. Through the output enable pins (NOE) of the second group of chips, combined with the internal storage registers of the 74HC595 chips, the parallel output pin network of the second group of chips is connected to the PWM signal labeled Qn. This SPI data stream is the highlight data stream used to highlight the indicator light alarm. If the PWM2 signal duty cycle is 0% or connected to signal ground, the indicator light alarm highlight level is the highest. The number of shift register chips in the first group of chips is equal to the number of shift register chips in the second group of chips, and the QP pin of the final shift register chip (the last shift register chip) in both groups of chips is connected to a 10kΩ pull-up resistor to the power supply voltage VCC to ensure that the QP pin remains in a high-level state when no valid signal is transmitted, thereby avoiding a possible floating state (i.e., an uncertain level), which helps to improve signal stability and reliability. In addition, the frequencies of the PWM1 signal and the PWM2 signal are both within the range formed by the preset first frequency threshold and the second frequency threshold, and the duty cycle resolution of the PWM1 signal and the PWM2 signal is greater than or equal to the preset resolution threshold, that is, the frequency is 1kHz±10%, and the duty cycle resolution is ≥8bit.

[0039] It's important to note that the 74HC595 chip is a combination 8-bit shift register and storage register. Signal changes on its output enable pin (NOE) only affect the link between the chip's storage register and the output pins; they don't affect the shift register's internal data storage. The 74HC595 chip latches serial input data into the storage register and controls the link between the chip's internal storage register and the chip's output pins through changes in the output enable pin (NOE). The link between the chip's internal storage register and output pins is linked via a signal from the output enable pin (NOE). The present invention preferably uses the 74HC595 shift register output latch chip, but this is not the only option. Since the 74HC595 chip has two functions: latching and output enable, other independent chips can also be used. Specifically, chips can be searched for according to each of these two functions. Similarly, the D-type flip-flop within the 74HC273 latch chip latches parallel bus data input, and then connects the PWM signal via the output enable pin (NOE) of the 74HC244 output enable chip, achieving the same high-brightness flashing, flat light, and extinguishing alarm functions. Furthermore, the 74HC273 and 74HC244 chips are also preferred, but not the only options.

[0040] The MOSI pin of the SPI controller is connected to the serial data input pin (i.e., DS input pin) of the first 74HC595 shift register chip in the first group of chips and the second group of chips respectively. Starting from the first 74HC595 shift register chip in each group of chips, the DS input pin of each subsequent 74HC595 shift register chip is cascaded to the serial data output pin (i.e., QP output pin) of the previous adjacent 74HC595 shift register chip, which can realize the cascading of multiple 74HC595 chips. The SCLK pin of the controller is connected to the shift register clock input pin (i.e., SH_CP pin) of each shift register chip in the first group of chips and the second group of chips respectively. The CS1 pin of the SPI controller is connected to the ST_CP pin (storage register input signal) of each shift register chip in the first group of chips for dimming control logic; the CS2 pin of the SPI controller is connected to the storage register input pin (i.e., ST_CP pin) of each 74HC595 shift register chip in the second group of chips for alarm highlight control logic. The embedded MCU pre-generates a composite dimming data frame based on the indicator light on / off information and brightness information and writes it into the SPI controller. The SPI controller sends two sets of data streams: the flat light data stream in the composite dimming data frame is sent to each shift register chip in the first group of chips via the MOSI pin and the SCLK pin, and the flat light data of each shift register chip in the first group of chips is synchronously latched into their respective internal storage registers via the CS1 pin. At the same time, the highlight light data stream in the composite dimming data frame is sent to each shift register chip in the second group of chips via the MOSI pin and the SCLK pin, and the highlight light data of each shift register chip in the second group of chips is synchronously latched into their respective internal storage registers via the CS2 pin. The PWM controller adjusts the duty cycle of the PWM1 signal output by the PWM1 pin according to the dimming command level and controls the output level of the QnA pin in combination with the storage register to control the flat light display of the indicator light. It also adjusts the duty cycle of the PWM2 signal output by the PWM2 pin according to the alarm highlight level and controls the output level of the Qn pin in combination with the storage register to control the highlight display of the indicator light.

[0041] When the corresponding bits of the normal light and highlight data streams latched into the chip's memory register are both 0, the chip's parallel output pins QnA and Qn remain low or in a high-resistance state, regardless of the changes in the PWM1 and PWM2 signals. This shuts down the subsequent Darlington transistors and turns off the corresponding indicators. When the corresponding bits of the normal light and highlight data streams latched into the chip's memory register are "0" and "1," respectively, the chip's output pin QnA remains low or in a high-resistance state, shutting down the subsequent Darlington transistors. In this case, the indicators are independently controlled by another set of chip output pins, Qn. The PWM2 signal can toggle the chip's output pins Qn between high and high resistance, turning the subsequent Darlington transistors on and off, thereby enabling the indicators to highlight the alarm. In this case, the on / off of the indicators is determined by the SPI data stream, while the alarm highlight level is controlled by the PWM2 signal.

[0042] Similarly, when the corresponding bits of the flat and bright data streams latched into the chip's memory register are "1" and "0," respectively, the chip's output pin Qn will remain low or high-resistance, regardless of the PWM2 signal's behavior, shutting down the subsequent Darlington transistor. At this point, the indicator lights are independently controlled by another set of chip output pins, QnA. By varying the PWM1 signal, the chip's output pin QnA can be toggled between high and high-resistance, turning the subsequent Darlington transistor on or off, thereby achieving a flat light display for the indicator lights. The on / off of the indicator lights is also determined by the SPI data stream, while the dimming level is controlled by the PWM1 signal.

[0043] Each indicator light is controlled by two NPN Darlington diodes. By controlling the base-level signals QnA and Qn of the Darlington diodes, the system can achieve high brightness, flat brightness, and off alarm functions. During an alarm, all indicators on the alarm panel can independently achieve high brightness flashing, flat brightness, and off alarm functions without affecting the status of other indicators. Configurable alarm brightness levels are also available. The cathode of each indicator light in the indicator control circuit is connected to the collectors of both Darlington diodes. The base of one Darlington diode in the indicator control circuit is connected to the QnA pin, and the base of the other Darlington diode is connected to the Qn pin. The emitters of both Darlington diodes are grounded. The output levels of the QnA and Qn pins control the on and off states of the corresponding Darlington diodes. All indicators on the alarm panel can be independently controlled to achieve flat brightness, high brightness, and off alarm functions. Preferably, the indicator light control circuit also includes a button, which is connected to the GPIO pin of the embedded MCU to realize button functions such as "confirm", "mute" and "test". The indicator light is set on the button and connected to the button to form a whole, forming a lighted button; the embedded MCU controls the working status of the indicator light and the buzzer at the same time according to the signal generated by the button action. Further preferably, the button includes function keys such as the confirmation key, the mute key and the test key. When the system detects an alarm signal, the indicator light enters a high-brightness flashing state and the buzzer starts to sound; when the mute key is pressed, the indicator light maintains a high-brightness flashing state and the buzzer stops sounding; when the confirmation key or the test key is pressed, the indicator light returns to a flat light display and the buzzer stops sounding; when the alarm information disappears, the indicator light goes out; in addition, the button also includes a dimming + button and a dimming - button. When the dimming control mode is switched to local, the brightness is adjusted by the dimming + button and the dimming - button.

[0044] Among them, such as Figure 1As shown, U1 is a 74HC595 chip in the first group of chips, and U2 is a 74HC595 chip in the second group of chips; U3 and U4 are Darlington array chips (that is, many Darlington tubes in multiple indicator light control circuits are integrated in the form of a tube array, preferably using ULN2803 Darlington array chip, each ULN2803 Darlington array chip contains 8 NPN Darlington tubes; of course, other types of Darlington array chips containing other numbers of NPN Darlington tubes can also be used, such as ULN2803 Darlington array chip). The 74HC595 chips in the first and second chip groups (i.e., U1 and U2) each have eight parallel output pins, designated QA, QB, QC, QD, QE, QF, QG, and QH, respectively. U1's eight parallel output pins are labeled QnA pins, namely, Q1A, Q2A, Q3A, Q4A, Q5A, Q6A, Q7A, and Q8A, respectively. U2's eight parallel output pins are labeled Qn pins, namely, Q1, Q2, Q3, Q4, Q5, Q6, Q7, and Q8, respectively. Taking the ULN2803 Darlington array chip as an example, an indicator light K1 can be controlled jointly by the two NPN Darlington transistors in U3, the two NPN Darlington transistors in U4, or one NPN Darlington transistor in U3 and one NPN Darlington transistor in U4. When the indicator light K1 is jointly controlled by the two NPN Darlington tubes in U3, the negative electrode of the indicator light K1 is connected to the load connection points (L1 and L2) corresponding to the collector output ends (such as 1C and 2C) of the two Darlington tubes in U3; the base input end (1B) of one of the two Darlington tubes is connected to the Q1A pin of U1 in the first group of chips, and the base input end (2B) of the other Darlington tube is connected to the Q1 pin of U2 in the second group of chips; the same applies when the indicator light K1 is jointly controlled by the two NPN Darlington tubes in U4, which will not be repeated here.

[0045] When the indicator light K1 is controlled by an NPN Darlington tube in U3 and an NPN Darlington tube in U4, as shown in the following example: Figure 1 As shown, the cathode of the indicator light K1 is connected to the load connection point (L1) corresponding to the collector output end (such as 1C) of a Darlington tube in U3; and is also connected to the load connection point (L1) corresponding to the collector output end (such as 1C) of a Darlington tube in U4; the base input end (1B) of a Darlington tube in U3 is connected to the Q1A pin of U1 in the first group of chips, and the base input end (1B) of a Darlington tube in U4 is connected to the Q1 pin of U2 in the second group of chips.

[0046] Preferably, it also includes a buzzer, a relay and a power supply, the buzzer is respectively connected to the GPIO pin of the embedded MCU and the power supply, and the relay is respectively connected to the GPIO pin of the embedded MCU and the external alarm device. When the embedded MCU receives the alarm signal, the buzzer is synchronously triggered to sound and the relay is closed (i.e., the relay is triggered to output a closed signal) to start the external alarm device, which enables the crew to discover the alarm information at an early stage, leaving sufficient time to respond and process the alarm information, and reduce the losses caused by the untimely processing of the alarm information. Further preferably, the buzzer and the relay are connected to the GPIO pin of the embedded MCU through a transistor, the positive poles of the buzzer and the relay are both connected to the power supply, the negative poles of the buzzer and the relay are both connected to the collector of the transistor (the transistor is preferably an NPN bipolar transistor), the base of the transistor is connected to the GPIO pin of the embedded MCU through a current limiting resistor (10kΩ), and the emitter of the transistor is grounded.

[0047] like Figure 2 As shown, when the output level signal of the QnA pin of the first group of chips is low or high resistance, that is, when QnA = 0, the Darlington transistor connected to it is turned off. At this time, the indicator light is controlled solely by the Qn pin of the second group of chips. The PWM controller adjusts the duty cycle of the PWM2 signal output by the PWM2 pin according to the alarm highlight level to control the output level of the Qn pin, achieving a high-brightness display of the indicator light during an alarm. When the output level signal of the Qn pin of the second group of chips is low or high resistance, that is, when Qn = 0, the Darlington transistor connected to it is turned off. At this time, the indicator light is controlled solely by the QnA pin of the first group of chips. The PWM controller adjusts the duty cycle of the PWM1 signal output by the PWM1 pin according to the dimming command level to control the output level of the QnA pin, achieving a flat brightness display of the indicator light.

[0048] Each indicator light is controlled by a combination of signals identified by the network as QnA and Qn. The QnA signal is controlled by a combination of the 74HC595 chip's internal memory register and the NOE's PWM1 signal, which is transmitted to the chip pin. The Qn signal is controlled by a combination of the 74HC595 chip's internal memory register and the NOE's PWM2 signal, which is transmitted to the chip pin. By cleverly utilizing the 74HC595 chip's output enable pin (NOE) to connect to the PWM signal, two PWM signals (PWM1 and PWM2) are used to individually control the brightness of all indicators on the alarm operation panel, from high to low, and from off. Alarm brightness levels are configurable.

[0049] The present invention provides an operation panel alarm processing system supporting independent dimming. By parsing CAN field bus network messages, the dimming command level, the corresponding indicator light on and off and brightness information are obtained. The dimming command level and the configurable alarm highlight level are used to set the PWM1 and PWM2 duty cycles. Two groups of data streams are sent through the SPI controller to realize functions such as highlight flashing, flat light and off of the corresponding indicator lights, without affecting the status display of other indicator lights. At the same time, when an alarm is triggered, a buzzer in the board sounds and a relay is triggered to output a closing signal for linkage with an external alarm. This enables the crew to discover the alarm information at an early stage, leaving sufficient time to respond to and process the alarm information, thereby reducing the loss caused by untimely processing of the alarm information.

[0050] It should be noted that the specific embodiments described above can enable those skilled in the art to more fully understand the present invention, but do not limit the present invention in any way. Therefore, although this specification has described the present invention in detail with reference to the drawings and embodiments, those skilled in the art should understand that the present invention can still be modified or replaced with equivalents. In short, all technical solutions and improvements that do not depart from the spirit and scope of the present invention should be included in the scope of protection of the patent for the present invention.

Claims

1. An alarm processing system for an operation panel supporting independent dimming, comprising a circuit board provided on an alarm operation panel, wherein the circuit board comprises an embedded MCU and a CAN communication circuit, and is characterized in that: The circuit board also includes a first group of chips consisting of multiple shift register chips, a second group of chips, and multiple indicator light control circuits; the embedded MCU includes a CAN controller, an SPI controller, and a PWM controller; the indicator light control circuit includes an indicator light and two Darlington transistors; The CAN communication circuit is connected to the CAN controller in the embedded MCU, and the CAN communication circuit obtains the CAN field bus message and sends it to the CAN controller; the CAN controller receives the CAN field bus message and parses it according to the communication protocol to obtain the dimming instruction level, the alarm highlight level, and the indicator light on and off information and brightness information; The NOE input pin of each shift register chip in the first group of chips is connected to the PWM1 pin of the PWM controller, and the multiple parallel output pins of each shift register chip in the first group of chips are marked as QnA pins, which are used to control the flat light display of the indicator light; the NOE input pin of each shift register chip in the second group of chips is connected to the PWM2 pin of the PWM controller, and the multiple parallel output pins of each shift register chip in the second group of chips are marked as Qn pins, which are used to control the bright light display of the indicator light; The MOSI pin of the SPI controller is connected to the serial data input pin of the first shift register chip in the first group of chips and the second group of chips respectively, and starting from the first shift register chip in each group of chips, the serial data input pin of each subsequent shift register chip is cascaded to the serial data output pin of the previous adjacent shift register chip; The SCLK pin of the SPI controller is connected to the shift register clock input pin of each shift register chip in the first group of chips and the second group of chips, respectively; the CS1 pin of the SPI controller is connected to the storage register input pin of each shift register chip in the first group of chips; the CS2 pin of the SPI controller is connected to the storage register input pin of each shift register chip in the second group of chips; The embedded MCU pre-generates a composite dimming data frame based on the indicator light on / off information and brightness information and writes it into the SPI controller. The SPI controller sends the flat light data stream in the composite dimming data frame to each shift register chip in the first group of chips through the MOSI pin and the SCLK pin, and synchronously latches the flat light data of each shift register chip in the first group of chips into their respective internal storage registers through the CS1 pin; at the same time, the highlight data stream in the composite dimming data frame is sent to each shift register chip in the second group of chips through the MOSI pin and the SCLK pin, and synchronously latches the highlight data of each shift register chip in the second group of chips into their respective internal storage registers through the CS2 pin; The PWM controller adjusts the duty cycle of the PWM1 signal output by the PWM1 pin according to the dimming instruction level and combines with the storage register to control the output level of the QnA pin to control the flat light display of the indicator light, and adjusts the duty cycle of the PWM2 signal output by the PWM2 pin according to the alarm highlight level and combines with the storage register to control the output level of the Qn pin to control the highlight display of the indicator light; The cathode of an indicator light in the indicator light control circuit is connected to the collectors of two Darlington transistors. The base of one Darlington transistor in the indicator light control circuit is connected to any QnA pin of a shift register chip in the first group of chips, and the base of the other Darlington transistor is connected to any Qn pin of a shift register chip in the second group of chips. The emitters of the two Darlington transistors are both grounded. The output levels of the QnA pin and the Qn pin control the on and off states of the corresponding Darlington transistors, thereby realizing independent regulation of the normal brightness, high brightness, and off state of the indicator light.

2. The operating panel alarm processing system supporting independent dimming according to claim 1 is characterized in that: When the output level of the QnA pin of the first group of chips is low or high resistance, the Darlington transistor connected to it is turned off. At this time, the indicator light is controlled solely by the Qn pin of the second group of chips. The PWM controller adjusts the duty cycle of the PWM2 signal output by the PWM2 pin according to the alarm highlight level to control the output level of the Qn pin, so that the indicator light is highlighted when an alarm occurs. When the output level of the Qn pin of the second group of chips is low or high resistance, the Darlington transistor connected to it is turned off. At this time, the indicator light is controlled solely by the QnA pin of the first group of chips. The PWM controller adjusts the duty cycle of the PWM1 signal output by the PWM1 pin according to the dimming instruction level to control the output level of the QnA pin, thereby achieving a flat brightness display of the indicator light. When the output levels of the QnA pin of the first group of chips and the Qn pin of the second group of chips are both low or high resistance, the two Darlington transistors are turned off and the indicator light is off.

3. The operating panel alarm processing system supporting independent dimming according to claim 1, characterized in that: It also includes a buzzer, a relay and a power supply. The buzzer is respectively connected to the GPIO pin of the embedded MCU and the power supply, and the relay is respectively connected to the GPIO pin of the embedded MCU and the external alarm device. When the embedded MCU receives an alarm signal, the buzzer is synchronously triggered to sound and the relay is closed to start the external alarm device.

4. The operating panel alarm processing system supporting independent dimming according to claim 3 is characterized in that: The buzzer and relay are connected to the GPIO pin of the embedded MCU through a transistor, the positive poles of the buzzer and the relay are connected to the power supply, the negative poles of the buzzer and the relay are connected to the collector of the transistor, the base of the transistor is connected to the GPIO pin of the embedded MCU, and the emitter of the transistor is grounded.

5. The operating panel alarm processing system supporting independent dimming according to claim 3 is characterized in that: The indicator light control circuit also includes a button, which is connected to the GPIO pin of the embedded MCU. The indicator light is set on the button and connected to the button; the embedded MCU controls the working status of the indicator light and the buzzer at the same time according to the signal generated by the button action.

6. The operating panel alarm processing system supporting independent dimming according to claim 5, characterized in that: The buttons include a confirmation button, a mute button and a test button. When the system detects an alarm signal, the indicator light enters a high-brightness flashing state and the buzzer starts to sound; when the mute button is pressed, the indicator light maintains a high-brightness flashing state and the buzzer stops sounding; when the confirmation button or the test button is pressed, the indicator light returns to a flat light display and the buzzer stops sounding; when the alarm information disappears, the indicator light goes out.

7. The operation panel alarm processing system supporting independent dimming according to claim 1, characterized in that: The number of shift register chips in the first group of chips is equal to the number of shift register chips in the second group of chips.

8. The operation panel alarm processing system supporting independent dimming according to claim 4, characterized in that: The transistor is an NPN bipolar transistor, and the base of the transistor is connected to the GPIO pin of the embedded MCU through a current limiting resistor.

9. The operation panel alarm processing system supporting independent dimming according to claim 1, characterized in that: The frequencies of the PWM1 signal and the PWM2 signal are both within an interval consisting of a preset first frequency threshold and a second frequency threshold, and the duty cycle resolutions of the PWM1 signal and the PWM2 signal are greater than or equal to the preset resolution threshold.

10. The operation panel alarm processing system supporting independent dimming according to claim 1, characterized in that: The shift register chip is a 74HC595 chip.

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