Chip and preparation method thereof, memory and electronic equipment

Abstract

The invention provides a chip and a preparation method thereof, a memory and electronic equipment, relates to the field of semiconductors, and can avoid the problem that the size of a vertical transistor cannot be miniaturized due to process limitation. The chip comprises a vertical transistor, the vertical transistor comprises a first pole, a channel and a second pole which are sequentially stacked on a substrate, and the channel comprises a groove. A first gate dielectric layer and a second gate dielectric layer, wherein the first gate dielectric layer and the second gate dielectric layer are in contact with the side wall of the groove; the first gate dielectric layer and the second gate dielectric layer are both located in the groove, or the first gate dielectric layer and the second gate dielectric layer are both located outside the groove. The first gate and the second gate are arranged at an interval, the first gate is arranged on one side, deviating from the channel, of the first gate dielectric layer, and the second gate is arranged on one side, deviating from the channel, of the second gate dielectric layer.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and particularly to a chip, a method for manufacturing the same, a memory, and an electronic device. Background Art

[0002] Memories are widely used in electronic devices. With the development of chip technology, the size of memories, like that of processors, has been continuously miniaturized to improve density and storage performance. A memory includes a plurality of memory cells, and each memory cell includes a transistor and a capacitor.

[0003] In the prior art, by using vertical transistors and integrating the vertical transistors and capacitor structures in the vertical direction, high-density memory cells can be achieved, and further miniaturization of the memory is expected.

[0004] However, the current mainstream vertical transistor structure is a gate-all-around structure, which requires opening a first through-hole in the gate, first depositing a gate dielectric layer in the first through-hole, then opening a second through-hole at the bottom of the gate dielectric layer, and forming a channel in the second through-hole to make the channel contact the bottom electrode. That is, in the plane perpendicular to the vertical direction, the size of the vertical transistor is affected by the sizes of the gate, the gate dielectric layer, and the channel, resulting in a relatively large area occupied by one transistor, which is not conducive to the miniaturization of the vertical transistor. Summary of the Invention

[0005] To solve the above technical problems, this application provides a chip, a method for manufacturing the same, a memory, and an electronic device, which can avoid the situation where the size of the vertical transistor cannot be miniaturized due to process limitations.

[0006] In a first aspect, this application provides a chip, which includes a vertical transistor. The vertical transistor includes: a first pole, a channel, and a second pole that are sequentially stacked on a substrate. The channel includes a trench. A first gate dielectric layer and a second gate dielectric layer, both the first gate dielectric layer and the second gate dielectric layer are in contact with the sidewalls of the trench; the first gate dielectric layer and the second gate dielectric layer are both located in the trench, or both the first gate dielectric layer and the second gate dielectric layer are located outside the trench. A first gate and a second gate that are spaced apart, the first gate is disposed on a side of the first gate dielectric layer away from the channel, and the second gate is disposed on a side of the second gate dielectric layer away from the channel.

[0007] In this application, by disposing the first gate and the second gate to be spaced apart, the first gate and the second gate can be located in different orientations of the channel. Therefore, compared with the solution where the vertical transistor only includes a non-ring gate first gate or only includes a non-ring gate second gate, the first gate and the second gate can perform gate control on the channel at different positions, thereby reducing the leakage current of the channel.

[0008] Moreover, on the one hand, since the first gate and the second gate of the present application are no longer in a surrounding shape, and the first gate dielectric layer and the second gate dielectric layer are no longer in a surrounding shape, the present application no longer adopts the process of the related art to first form a first through hole in the surrounding gate and then form a second through hole in the gate dielectric layer. Instead, a sacrificial structure (such as a sacrificial layer, a dummy channel, etc.) is first formed in the area where the channel to be formed is located, a groove is opened between adjacent sacrificial structures, and then the first gate dielectric layer and the second gate dielectric layer, as well as the first gate and the second gate, are formed on the side walls of the sacrificial structure. After that, by removing the sacrificial structure and forming a channel at the position where the sacrificial structure is located, the channel can be made to contact the first pole. That is, the present application does not need to form a second through hole between the first gate dielectric layer and the second gate dielectric layer, thereby avoiding the process limitation caused by forming the second through hole, resulting in the inability to miniaturize the size of the vertical transistor.

[0009] On the other hand, since the first gate and the second gate are arranged at intervals instead of surrounding the channel for one week, the total area of the first gate and the second gate is smaller than the total area of the gate in the gate-all-around scheme, thereby reducing the size of the vertical transistor in the X direction and / or the Y direction, enabling the vertical transistor to be miniaturized; at the same time, the first gate dielectric layer and the second gate dielectric layer used to isolate the channel from the first gate and the second gate can also be arranged at intervals instead of surrounding the channel for one week. Therefore, the total area of the first gate dielectric layer and the second gate dielectric layer of the present application is smaller than the total area of the gate dielectric layer in the gate-all-around scheme, thereby reducing the size of the vertical transistor in the X direction and / or the Y direction, enabling the vertical transistor to be miniaturized. The Y direction can be the direction from the first gate to the second gate, and the Z direction can be the direction from the first pole to the second pole.

[0010] On this basis, due to process limitations, the process of opening holes at the bottom of the gate dielectric layer usually requires reserving a certain etching area (such as reserving a space of about 20 nm in the X direction and the Y direction). When the size of the second through hole is fixed, the embodiments of the present application can reduce the thickness of the channel in the X direction and the Y direction by opening a groove in the channel, thereby improving the gate control ability of the vertical transistor.

[0011] In some possible implementation manners, both the first gate dielectric layer and the second gate dielectric layer are located outside the groove, the first gate is disposed on the side of the first gate dielectric layer away from the channel, and the second gate is disposed on the side of the second gate dielectric layer away from the channel.

[0012] In some possible implementation manners, the chip further includes a first insulating layer, and the first insulating layer is filled in the groove to use the first insulating layer to separate the first pole and the second pole. Alternatively, the groove further includes a bottom adjacent to the side walls, the bottom contacts the first pole, and the second pole is filled in the groove.

[0013] Those skilled in the art should know that the region in the channel that coincides with the first gate and the second gate and is located between the first pole and the second pole is called the channel region. When the second pole is filled in the trench, the size of the channel region in the Z direction will be smaller than the size of the channel region in the Z direction when the first insulating layer is filled in the trench. Therefore, in order to ensure the gate control ability and avoid the size of the channel region in the Z direction from being too small, the overlapping size of the second pole with the first gate and the second gate in the Z direction cannot be too large. For example, in this application, the overlapping size of the second pole with the first gate and the second gate in the Z direction does not exceed 30 nm.

[0014] In some possible implementation manners, both the first gate dielectric layer and the second gate dielectric layer are located in the trench, and the chip further includes a first insulating layer, and the first insulating layer is filled in the trench. The first gate is disposed between the first gate dielectric layer and the first insulating layer, and the second gate is disposed between the second gate dielectric layer and the first insulating layer.

[0015] In some possible implementation manners, the number of vertical transistors is multiple. Multiple vertical transistors arranged along the column direction share the same first pole; multiple vertical transistors arranged along the row direction share the same first gate and the same second gate.

[0016] In some possible implementation manners, when both the first gate dielectric layer and the second gate dielectric layer are located in the trench, the channels of adjacent vertical transistors arranged along the column direction are connected.

[0017] In some possible implementation manners, the first gate and the second gate are disposed opposite to each other.

[0018] In some possible implementation manners, when both the first gate dielectric layer and the second gate dielectric layer are located outside the trench, the longitudinal section of the trench is U-shaped, or the cross-section of the trench is a closed circle. The longitudinal section of the trench is the interface of the trench along the plane where the first direction and the second direction are located. The first direction is the direction from the first pole to the second pole, and the second direction is the direction from the first gate to the second gate; the cross-section of the trench is the section of the trench along the second direction.

[0019] In a second aspect, this application provides a chip, and the chip includes a vertical transistor. The vertical transistor includes: a first pole, a channel, and a second pole that are sequentially stacked on a substrate; the second pole includes a first sub-electrode and a second sub-electrode that are disposed opposite to each other, and the channel includes a first channel located between the first pole and the first sub-electrode and a second channel located between the first pole and the second sub-electrode. A first gate dielectric layer and a second gate dielectric layer, the first gate dielectric layer is in contact with the sidewall of the first channel, and the second gate dielectric layer is in contact with the sidewall of the second channel. A first gate and a second gate that are disposed opposite to each other, the first gate is disposed on the side of the first gate dielectric layer away from the first channel, and the second gate is disposed on the side of the second gate dielectric layer away from the second channel.

[0020] Compared with the related art, in the present application, a vertical transistor can be split into a first vertical transistor and a second vertical transistor, which can improve the integration density. Compared with the double-gate vertical transistor provided in the previous embodiment, in the direction from the first vertical transistor to the second vertical transistor, the distance between the center of the first vertical transistor and the center of the second vertical transistor can be less than 30 nm. That is to say, the pitch between the first vertical transistor and the second vertical transistor can be less than 30 nm. When applied to DRAM, a cell area smaller than that of the advanced processes 1 beta and 1 gamma can be achieved.

[0021] Moreover, on the one hand, since the first gate and the second gate in the present application are no longer in a surrounding shape, and the first gate dielectric layer and the second gate dielectric layer are no longer in a surrounding shape either. Therefore, in the present application, the process of the related art is not adopted to first form a first through hole in the surrounding gate and then form a second through hole in the gate dielectric layer. Instead, a sacrificial structure (such as a sacrificial layer, a dummy channel, etc.) is first formed in the region where the channel to be formed is located, a groove is opened between adjacent sacrificial structures, and then the first gate dielectric layer and the second gate dielectric layer, as well as the first gate and the second gate, are formed on the side walls of the sacrificial structure. After that, by removing the sacrificial structure and forming a channel at the position where the sacrificial structure is located, the channel can be made to contact the first pole. That is, in the present application, there is no need to form a second through hole between the first gate dielectric layer and the second gate dielectric layer, thereby avoiding the process limitation of forming the second through hole, which may cause the size of the vertical transistor not to be miniaturized.

[0022] On the other hand, the first gate and the second gate are arranged oppositely, rather than surrounding the channel in a circle as in the related art. Therefore, the sizes of the first vertical transistor and the second vertical transistor in the X direction and the Y direction can be reduced, enabling the first vertical transistor and the second vertical transistor to be miniaturized. At the same time, the first gate dielectric layer and the second gate dielectric layer can also be arranged oppositely, rather than surrounding the channel in a circle. Therefore, the total area of the first gate dielectric layer and the second gate dielectric layer in the present application is smaller than the total area of the gate dielectric layer in the gate-all-around scheme, thereby reducing the size of the vertical transistor in the X direction and / or the Y direction, enabling the vertical transistor to be miniaturized.

[0023] In some possible implementation manners, the first channel and the second channel enclose a groove, and the chip further includes a first insulating layer, and the first insulating layer is filled in the groove.

[0024] In some possible implementation manners, both the first gate dielectric layer and the second gate dielectric layer are located outside the groove, the first gate is disposed on a side of the first gate dielectric layer away from the first channel, and the second gate is disposed on a side of the second gate dielectric layer away from the second channel; or, both the first gate dielectric layer and the second gate dielectric layer are located inside the groove, the first gate is disposed between the first gate dielectric layer and the first insulating layer, and the second gate is disposed between the second gate dielectric layer and the second insulating layer.

[0025] In some possible implementations, the first channel is disconnected from the second channel.

[0026] In a third aspect, the present application provides a memory, which includes a memory array. The memory array includes the chip described in the first aspect or the second aspect. The memory array further includes a capacitor, and the capacitor is electrically connected to the vertical transistor in the chip.

[0027] In some possible implementations, the memory array includes the chip described in the first aspect. The memory array further includes word lines and bit lines; the gate of the vertical transistor is electrically connected to the word line, the first pole is electrically connected to the bit line, and the second pole is electrically connected to the capacitor; or, the memory array includes the chip described in the second aspect. The memory array further includes write word lines, read word lines, and bit lines; the second gate is electrically connected to the write word line, the second sub-electrode is electrically connected to the first gate, the first sub-electrode is electrically connected to the read word line, and the first pole is electrically connected to the bit line.

[0028] The third aspect and any implementation manner of the third aspect respectively correspond to the first aspect, the second aspect, and any implementation manner of the first aspect and the second aspect. For the technical effects corresponding to the third aspect and any implementation manner of the third aspect, reference can be made to the technical effects corresponding to the first aspect, the second aspect, and any implementation manner of the first aspect and the second aspect described above, and details are not elaborated herein.

[0029] In a fourth aspect, the present application provides an electronic device, which includes a circuit board and the chip described in the first aspect or the chip described in the second aspect or the memory described in the third aspect. The chip or the memory is disposed on the circuit board.

[0030] The fourth aspect and any implementation manner of the fourth aspect respectively correspond to the first aspect, the second aspect, and any implementation manner of the first aspect and the second aspect. For the technical effects corresponding to the fourth aspect and any implementation manner of the fourth aspect, reference can be made to the technical effects corresponding to the first aspect, the second aspect, and any implementation manner of the first aspect and the second aspect described above, and details are not elaborated herein.

[0031] In a fifth aspect, the present application provides a chip fabrication method, comprising: forming a first electrode, a first sacrificial layer, a second insulating layer, and a third insulating layer on a substrate; the first sacrificial layer covering the surface of the first electrode facing away from the substrate; the second insulating layer being located between adjacent first electrodes and between adjacent first sacrificial layers in a third direction; and the third insulating layer being located between adjacent first electrodes and covering the sidewalls of the first electrode in a second direction. A first gate dielectric layer, a second gate dielectric layer, a first gate, and a second gate are formed on the side of the third insulating layer facing away from the substrate; the first gate dielectric layer being located between the first gate and the second insulating layer, the second gate dielectric layer being located between the second gate and the second insulating layer, and the first gate and the second gate being spaced apart. The first sacrificial layer is removed to form a recess to expose the surface of the first electrode facing away from the substrate, and a channel and the first insulating layer are sequentially filled in the recess. A second electrode is formed on the side of the channel and the first insulating layer facing away from the substrate; wherein the second direction is perpendicular to the third direction, and both the second and third directions are perpendicular to the first direction from the first electrode to the second electrode.

[0032] In this application, a first sacrificial layer and a second insulating layer are first formed. Etchback is then used to create grooves between adjacent first sacrificial layers and adjacent second insulating layers. Then, first and second gate dielectric layers, as well as first and second gate electrodes, are formed on the sidewalls of the first and second sacrificial layers. Subsequently, the first sacrificial layer is removed and a channel is formed in the location of the first sacrificial layer, thereby enabling contact between the channel and the first electrode. This eliminates the need for forming a second via between the first and second gate dielectric layers, thereby avoiding the limitations of the process for forming the second via that prevents the vertical transistor from being miniaturized.

[0033] In some possible implementations, the second electrode includes a first sub-electrode and a second sub-electrode disposed opposite each other, and the channel includes a first channel and a second channel. The first channel is located between the first electrode and the first sub-electrode, and the second channel is located between the first electrode and the second sub-electrode.

[0034] The fifth aspect and any implementation of the fifth aspect correspond to the first aspect, the second aspect, and any implementation of the first and second aspects, respectively. The technical effects corresponding to the fifth aspect and any implementation of the fifth aspect can be found in the technical effects corresponding to the first aspect, the second aspect, and any implementation of the first and second aspects, and are not further described here.

[0035] In a sixth aspect, the present application provides a method for fabricating a chip, including: forming a third sacrificial layer, a fifth insulating layer, and a first electrode on a substrate; the third sacrificial layer has a hollowed-out portion that penetrates through the third sacrificial layer; the first electrode and the fifth insulating layer are filled in the hollowed-out portion, and the vertical distance from the surface of the fifth insulating layer facing away from the substrate to the substrate is greater than the vertical distance from the surface of the third sacrificial layer facing away from the substrate to the substrate. Forming a first gate dielectric layer, a second gate dielectric layer, a first gate electrode, and a second gate electrode; the first gate dielectric layer is located between the first gate electrode and the fifth insulating layer, the second gate dielectric layer is located between the second gate electrode and the fifth insulating layer, and the first gate electrode and the second gate electrode are arranged at intervals. Removing the fifth insulating layer and forming a channel in the hollowed-out portion, the channel including a first channel and a second channel. Forming a second electrode on the side of the channel facing away from the substrate, the second electrode including a first sub-electrode and a second sub-electrode arranged opposite to each other; the first channel is located between the first electrode and the first sub-electrode, and the second channel is located between the first electrode and the second sub-electrode.

[0036] In the present application, by forming a fifth insulating layer in the region where the channel is to be formed, then forming a first gate dielectric layer and a second gate dielectric layer, as well as a first gate electrode and a second gate electrode on the sidewalls of the fifth insulating layer, and then removing the fifth insulating layer and forming a channel at the position where the fifth insulating layer is located, the channel can be made to contact the first electrode. That is, the present application does not need to form a second through hole between the first gate dielectric layer and the second gate dielectric layer, thereby avoiding the process limitations caused by forming the second through hole, resulting in the inability to miniaturize the size of the vertical transistor.

[0037] In some possible implementation manners, the first channel and the second channel enclose a groove. Before forming the second electrode on the side of the channel facing away from the substrate, the fabrication method further includes: filling a first insulating layer in the groove.

[0038] In some possible implementation manners, forming a third sacrificial layer, a fifth insulating layer, and a first electrode on a substrate includes: forming a third sacrificial layer and a fourth insulating layer on the substrate, and the hollowed-out portion penetrates through the third sacrificial layer and the fourth insulating layer. Filling the first electrode and the fifth insulating layer in the hollowed-out portion in sequence. Removing the fourth insulating layer.

[0039] The sixth aspect and any implementation manner of the sixth aspect respectively correspond to the first aspect, the second aspect, and any implementation manner of the first aspect and the second aspect. For the technical effects corresponding to the sixth aspect and any implementation manner of the sixth aspect, reference can be made to the technical effects corresponding to the first aspect, the second aspect, and any implementation manner of the first aspect and the second aspect above, which will not be elaborated here.

[0040] In a seventh aspect, the present application provides a chip fabrication method, comprising: forming a first electrode and a fourth sacrificial layer on a substrate; the fourth sacrificial layer being located on a side of the first electrode facing away from the substrate; forming a first gate and a second gate on either side of the adjacent fourth sacrificial layer; forming a first gate dielectric layer, a second gate dielectric layer, a channel, and a second electrode; the channel being located on a side of the first gate dielectric layer facing away from the first gate and a side of the second gate dielectric layer facing away from the second gate; and the second electrode being located on a side of the channel facing away from the substrate.

[0041] In this application, the channel is brought into contact with the first electrode by forming a fourth sacrificial layer in the region where the channel is to be formed, then forming a first gate dielectric layer and a second gate dielectric layer, as well as a first gate and a second gate electrode, on the sidewalls of the fourth sacrificial layer. The fourth sacrificial layer is then removed, and a channel is formed in the location of the fourth sacrificial layer. In other words, this application eliminates the need to form a second via between the first and second gate dielectric layers, thereby avoiding the limitations of the process for forming the second via that would prevent the vertical transistor from being miniaturized.

[0042] In some possible implementations, forming the first gate dielectric layer, the second gate dielectric layer, and the channel includes: sequentially forming a gate dielectric layer and a dummy channel on the first gate and the second gate. Etching back the dummy channel, leaving the dummy channel covering the sidewalls of the gate dielectric layer. Under the protection of the dummy channel, removing the portion of the gate dielectric layer not covered by the dummy channel to obtain the first gate dielectric layer and the second gate dielectric layer. Removing the dummy channel, and forming a channel on the side of the first gate dielectric layer facing away from the first gate and on the side of the second gate dielectric layer and the second gate.

[0043] The seventh aspect and any implementation of the seventh aspect correspond to the first aspect, the second aspect, and any implementation of the first and second aspects, respectively. The technical effects corresponding to the seventh aspect and any implementation of the seventh aspect can be found in the technical effects corresponding to the first aspect, the second aspect, and any implementation of the first and second aspects, and are not further described here. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 A top view of a storage array provided for reference;

[0045] Figures 2a - 2d A structural diagram of a vertical transistor provided in an embodiment of the present application;

[0046] Figure 2e A top view of a vertical transistor provided in an embodiment of the present application;

[0047] Figure 2f A schematic diagram of the structure of the channel provided in an embodiment of the present application;

[0048] Figures 3a - 3bStructural diagram of the vertical transistor provided by the embodiment of the present application;

[0049] Figure 4a Structural diagram of the vertical transistor provided by the embodiment of the present application;

[0050] Figure 4b Schematic structural diagram of the channel provided by the embodiment of the present application;

[0051] Figure 5a Schematic structural diagram of the channel provided by the embodiment of the present application;

[0052] Figures 5b - 5c Structural diagram of the vertical transistor provided by the embodiment of the present application;

[0053] Figure 6 Structural diagram of the vertical transistor provided by the embodiment of the present application;

[0054] Figures 7a - 7e Structural diagram of the vertical transistor provided by the embodiment of the present application;

[0055] Figures 8a - 8c Structural diagram of the vertical transistor provided by the embodiment of the present application;

[0056] Figures 8d - 8e Top view of the vertical transistor provided by the embodiment of the present application;

[0057] Figures 9a - 9b Structural diagram of the vertical transistor provided by the embodiment of the present application;

[0058] Figures 10a - 10d Structural diagram of the storage unit provided by the embodiment of the present application;

[0059] Figure 10e For Figure 10d Circuit diagram of the storage unit shown in;

[0060] Figure 11a Top view of the storage unit provided by the embodiment of the present application;

[0061] Figure 11b For Figure 11a Circuit diagram of the storage unit shown in;

[0062] Figure 12 Preparation flow chart of the chip provided by the embodiment of the present application;

[0063] Figures 13a - 13f Three-view drawings during the preparation process of the chip provided by the embodiment of the present application;

[0064] Figures 14a - 14f Three-view drawings during the preparation process of the chip provided by the embodiment of the present application;

[0065] Figures 15a - 15g These are the three views in the preparation process of the chip provided by the embodiments of the present application;

[0066] Figure 16 This is the preparation flow chart of the chip provided by the embodiments of the present application;

[0067] Figures 17a - 17k These are the three views in the preparation process of the chip provided by the embodiments of the present application;

[0068] Figure 18 This is the preparation flow chart of the chip provided by the embodiments of the present application;

[0069] Figures 19a - 19j These are the three views in the preparation process of the chip provided by the embodiments of the present application. Detailed implementation manners

[0070] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0071] The term "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone.

[0072] The terms "first" and "second" in the description and claims of the embodiments of the present application are used to distinguish different objects, rather than to describe the specific order of the objects. For example, the first target object and the second target object are used to distinguish different target objects, rather than to describe the specific order of the target objects.

[0073] In the embodiments of the present application, words such as "exemplary" or "for example" are used to represent examples, illustrations or explanations. Any embodiment or design solution described as "exemplary" or "for example" in the embodiments of the present application should not be construed as being more preferred or more advantageous than other embodiments or design solutions. Exactly, using words such as "exemplary" or "for example" aims to present related concepts in a specific manner.

[0074] In the description of the embodiments of the present application, unless otherwise specified, the meaning of "multiple" refers to two or more. For example, multiple processing units refer to two or more processing units; multiple systems refer to two or more systems.

[0075] An embodiment of the present application provides an electronic device, which can be a device containing a memory such as a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, a communication electronic product, etc.

[0076] Consumer electronic products such as mobile phones, tablet computers, laptop computers, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smart watches, smart bracelets, etc.), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronic products such as smart door locks, TVs, smart speakers, refrigerators, floor cleaning robots, etc. Vehicle-mounted electronic products such as vehicle navigation devices, vehicle-mounted displays, etc. Financial terminal products such as automated teller machines (ATMs), terminals for self-service business handling, etc. Communication electronic products such as communication devices containing chips such as servers, memories, radars, base stations, etc.

[0077] For the convenience of description, a mobile phone is taken as an example for illustration below. A mobile phone may include a processor, which includes a logic circuit and a memory. The memory includes a storage array, a storage controller, a decoder, etc. The logic circuit can read and write data to the storage array through the storage controller and the decoder.

[0078] Taking the memory as a dynamic random access memory (DRAM) as an example, DRAM is widely used in electronic devices. Due to the capacitor structure used in traditional DRAM, the miniaturization of DRAM is slower than the processor process, and there is a performance gap with the processor, which also makes it gradually difficult to improve the overall memory and computing performance of electronic devices.

[0079] The prior art can achieve high-density storage cells by using vertical transistors and integrating the vertical transistors and the capacitor structure in the vertical direction, and it is expected to achieve further miniaturization of the memory. In addition, vertical transistors can also be applied to other devices besides the memory, and the embodiments of the present application do not limit this.

[0080] However, as Figure 1As shown in the figure, the current mainstream vertical transistor structure is a gate-all-around structure, which requires opening a first through-hole in the gate, first depositing a gate dielectric layer in the first through-hole, then opening a second through-hole at the bottom of the gate dielectric layer, forming a channel in the second through-hole and reserving an etching area. On the one hand, in the plane perpendicular to the vertical direction (Z direction) (the plane where the XY direction is located), the size of the vertical transistor is affected by the sizes of the gate, the gate dielectric layer, the channel, and the reserved etching area, making the area occupied by one transistor relatively large, which is not conducive to the miniaturization of the vertical transistor. On the other hand, after the gate dielectric layer is dug to obtain the second through-hole, the channel filled in the second through-hole can contact the bottom electrode. However, due to process limitations, the size of the second through-hole is relatively large, thus restricting the miniaturization of the vertical transistor.

[0081] For example, the total thickness of the gate in the X direction is about 10 nm, the total thickness of the gate dielectric layer in the X direction is about 10 nm, the diameter of the channel and the reserved etching area in the second through-hole is 30 nm, and the pitch between adjacent transistors in the X direction is about 15 nm. In this way, the size occupied by one transistor in the X direction is about 65 nm. Based on this, an embodiment of the present application provides a chip, which includes a vertical transistor. The gate of the transistor includes a first gate and a second gate arranged oppositely, and the miniaturization of the vertical transistor is achieved by reducing the area occupied by the gate.

[0082] Specifically, as Figures 2a - 2d shown, the vertical transistor includes a first electrode 11, a channel 12, and a second electrode 13 stacked in sequence on a substrate (substrate) 10. The channel 12 includes grooves. Among them, the first electrode 11 is a source electrode, and the second electrode 13 is a drain electrode; alternatively, the first electrode 11 is a drain electrode, and the second electrode 13 is a source electrode. In the present application, the direction from the first electrode 11 to the second electrode 13 can be the Z direction. The Z direction in this article is the first direction, the Y direction is the second direction, and the X direction is the third direction. The following descriptions will be made in terms of the Z direction, the Y direction, and the X direction.

[0083] The vertical transistor further includes a first gate dielectric layer 14, a second gate dielectric layer 15, a first gate 16, and a second gate 17. Both the first gate dielectric layer 14 and the second gate dielectric layer 15 are in contact with the sidewalls of the grooves. The first gate 16 is disposed on the side of the first gate dielectric layer 14 away from the channel 12, and the second gate 17 is disposed on the side of the second gate dielectric layer 15 away from the channel 12. Moreover, the first gate 16 and the second gate 17 are arranged at intervals. In this way, the first gate dielectric layer 14 for isolating the first gate 16 from the channel 12 and the second gate dielectric layer 15 for isolating the second gate 17 from the channel 12 can also be arranged at intervals.

[0084] Figure 2aThere are shown 2×2 vertical transistors. The first pole 11 can extend along the Y direction, and the 2 vertical transistors arranged along the Y direction can share the first pole 11. The first gate dielectric layer 14, the first gate 16, the second gate dielectric layer 15, and the second gate 17 can extend along the X direction, and the 2 vertical transistors arranged along the X direction can share the first gate dielectric layer 14, the first gate 16, the second gate dielectric layer 15, and the second gate 17.

[0085] Of course, as Figure 2d shown, the vertical transistors may also include independent first pole 11, first gate dielectric layer 14, first gate 16, second gate dielectric layer 15, second gate 17, and second pole 13. That is, for multiple transistors arranged either along the X direction or along the Y direction, they do not share the first pole 11, first gate dielectric layer 14, first gate 16, second gate dielectric layer 15, second gate 17, and second pole 13.

[0086] In some possible implementation manners, the embodiments of the present application do not limit the relative positions of the first gate 16 and the second gate 17, as long as the first gate 16 and the second gate 17 are arranged at intervals. Optionally, the first gate 16 and the second gate 17 may be arranged opposite to each other. For the convenience of description, unless otherwise stated hereinafter, the description will be made by taking the case where the first gate 16 and the second gate 17 are arranged opposite to each other as an example. In addition, those skilled in the art should know that in a vertical transistor, the first gate 16 and the second gate 17 can be electrically connected to jointly control the on or off of the vertical transistor. That is, the vertical transistor in the embodiments of the present application is a double-gate vertical transistor.

[0087] In the present application, by arranging the first gate 16 and the second gate 17 at intervals, the first gate 16 and the second gate 17 can be located at different orientations of the channel 12. Therefore, compared with the solution where the vertical transistor only includes the non-ring gate first gate 16 or only includes the non-ring gate second gate 17, the first gate 16 and the second gate 17 can perform gate control on the channel 12 at different positions, thereby reducing the leakage of the channel 12.

[0088] Moreover, on the one hand, since the first gate 16 and the second gate 17 of the present application are no longer in a surrounding shape, and the first gate dielectric layer 14 and the second gate dielectric layer 15 are no longer in a surrounding shape either. Therefore, the present application no longer adopts the process of the related art to first form a first through hole in the surrounding gate and then form a second through hole in the gate dielectric layer. Instead, a sacrificial structure (such as a sacrificial layer, a dummy channel, etc.) is first formed in the region where the channel 12 to be formed is located, a groove is opened between adjacent sacrificial structures, and then the first gate dielectric layer 14 and the second gate dielectric layer 15, as well as the first gate 16 and the second gate 17, are formed on the sidewalls of the sacrificial structure. After that, by removing the sacrificial structure and forming a channel 12 at the position where the sacrificial structure is located, the channel 12 can be made to contact the first pole 11. That is, the present application does not need to form a second through hole between the first gate dielectric layer 14 and the second gate dielectric layer 15, thereby avoiding the process limitation caused by forming the second through hole, resulting in the inability to miniaturize the size of the vertical transistor.

[0089] On the other hand, since the first gate 16 and the second gate 17 are arranged at intervals rather than surrounding the channel 12 in a circle, the total area of the first gate 16 and the second gate 17 is smaller than the total area of the gate in the gate-all-around scheme, thereby reducing the size of the vertical transistor in the X direction and / or the Y direction, enabling the vertical transistor to be miniaturized; at the same time, the first gate dielectric layer 14 and the second gate dielectric layer 15 used to isolate the channel 12 from the first gate 16 and the second gate 17 can also be arranged at intervals rather than surrounding the channel 12 in a circle. Therefore, the total area of the first gate dielectric layer 14 and the second gate dielectric layer 15 of the present application is smaller than the total area of the gate dielectric layer in the gate-all-around scheme, thereby reducing the size of the vertical transistor in the X direction and / or the direction, enabling the vertical transistor to be miniaturized.

[0090] On this basis, due to process limitations, the process of opening holes at the bottom of the gate dielectric layer usually requires reserving a certain etching area (such as reserving about 20 nm of space in the X direction and the Y direction). When the size of the second through hole is fixed, the embodiment of the present application can reduce the thickness of the channel 12 in the X direction and the Y direction by opening a groove in the channel, thereby improving the gate control ability of the vertical transistor.

[0091] In some possible implementation manners, the groove may include sidewalls but not the bottom; or, in addition to including sidewalls, the groove may also include the bottom adjacent to the sidewalls. Of course, in some other possible implementation manners, the channel 12 may not include a groove and is instead a solid integral structure, or the channel 12 is a hollow structure.

[0092] On this basis, the longitudinal cross-section of the groove is U-shaped ( Figure 4a and Figure 4b ), or, the cross-section of the groove is a closed circle ( Figure 2a and Figure 2f)。When the cross-section of the trench is closed in a full circle, the cross-section of the trench can be, for example, a "square" shape ( Figure 2f ), a circular shape, an elliptical shape or other shapes that are closed in a full circle. Among them, the longitudinal section of the trench is the section of the trench along the Z direction, and the cross-section of the trench is the section of the trench along the direction from the first gate 16 to the second gate 17.

[0093] As Figure 2c shown, when the trench includes a bottom adjacent to the side walls, the second pole 13 can be filled in the trench. Since the trench of the channel 12 includes a bottom, the second pole 13 will not directly contact the first pole 11. Or, as Figure 2b shown, regardless of whether the trench includes a bottom, the chip can also include a first insulating layer 21. The first insulating layer 21 can be filled in the trench to separate the first pole 11 and the second pole 13 by using the first insulating layer 21.

[0094] Those skilled in the art should know that the region in the channel 12 that coincides with the first gate 16 and the second gate 17 and is located between the first pole 11 and the second pole 13 is called the channel region. When the second pole 13 is filled in the trench, the size of the channel region in the Z direction will be smaller than the size of the channel region in the Z direction when the first insulating layer 21 is filled in the trench. Therefore, in order to ensure the gate control ability and avoid the size of the channel region in the Z direction from being too small, the overlapping size of the second pole 13 with the first gate 16 and the second gate 17 in the Z direction cannot be too large. For example, in this application, the overlapping size of the second pole 13 with the first gate 16 and the second gate 17 in the Z direction does not exceed 30 nm.

[0095] In some possible implementation manners, assume that the surface of the trench side wall facing the first pole 11 is the first surface, and the surface of the trench side wall facing the second pole 13 is the second surface. Outside the trench, the surface adjacent to the first surface and the second surface in the trench is the outer side wall of the trench; inside the trench, the surface adjacent to the first surface and the second surface in the trench is the inner side wall of the trench.

[0096] As Figures 2a - 2e shown, the first gate dielectric layer 14 and the second gate dielectric layer 15 can both be located outside the trench. The first gate dielectric layer 14 and the second gate dielectric layer 15 both contact the outer side wall of the trench, and the first gate 16 and the second gate 17 are also arranged outside the trench.

[0097] Or, as Figure 3a and Figure 3bAs shown, when the first insulating layer 21 is filled in the trench, the first gate dielectric layer 14 and the second gate dielectric layer 15 may also be located in the trench. The first gate dielectric layer 14 and the second gate dielectric layer 15 are both in contact with the inner sidewall of the trench. The first gate 16 and the second gate 17 are also disposed in the trench, and the first insulating layer 21 is disposed between the first gate 16 and the second gate 17. In this case, in order to prevent the trench from contacting the first gate 16 and the second gate 17, the trench of the channel 12 may not include a bottom.

[0098] As Figure 3a and Figure 3b shown, when both the first gate 16 and the second gate 17 are located in the trench, along the direction from the first gate 16 to the second gate 17, the channels 12 of adjacent vertical transistors are connected above the first pole 11. Compared with the case where the channels 12 of adjacent vertical transistors are disconnected, connecting the channels 12 of adjacent vertical transistors above the first pole 11 can increase the contact area between the channel 12 and the first pole 11. In this case, the longitudinal cross-section of the part of the channel 12 located between the first gate dielectric layer 14 and the second gate dielectric layer 15 of adjacent vertical transistors can be U-shaped.

[0099] In some possible implementation manners, as Figures 5a - 5c shown, the channel 12 further includes an extension part in addition to the trench, and the extension part is in contact with the second pole 13. The extension part is connected to the sidewall of the trench and extends outward to increase the contact area between the channel 12 and the second pole 13.

[0100] In addition to this, in some possible implementation manners, as Figure 5b and Figure 5c shown, the longitudinal cross-section of the first gate dielectric layer 14 and the second gate dielectric layer 15 can be L-shaped. The first gate dielectric layer 14 is located both between the first gate 16 and the channel 12 and between the first gate 16 and the first pole 11; the second gate dielectric layer 15 is located both between the second gate 17 and the channel 12 and between the second gate 17 and the first pole 11.

[0101] Based on this structure, the embodiments of the present application do not limit the sizes of each structure in the vertical transistor.

[0102] Optionally, in the Z direction, the gate length range of the first gate 16 and the second gate 17 can be 10 nm to 150 nm; the vertical distance range from the first gate 16 and the second gate 17 to the first pole 11 can be 5 nm to 50 nm; the vertical distance range from the first gate 16 and the second gate 17 to the second pole 13 can be 5 nm to 50 nm.

[0103] Taking the case where the first gate 16 and the second gate 17 are outside the trench as an example, in the X direction or the Y direction, the total diameter range of the channel 12 can be 10 nm to 150 nm, the sidewall thickness range of the channel 12 can be 1 nm to 15 nm, and the diameter of the trench does not exceed 148 nm; the thickness range of the first gate 16 and the second gate 17 can be 3 nm to 50 nm; the width range of the second pole 13 can be 10 nm to 150 nm; the spacing range between the centers of adjacent vertical transistors can be 15 nm to 200 nm; the spacing range between the centers of the channels 12 of adjacent vertical transistors can be 15 nm to 200 nm.

[0104] In some possible implementation manners, the vertical transistor of the present application can be an independent isolated device, that is, the first gate 16 of any vertical transistor is not shared with the first gate 16 of other vertical transistors on the chip, the second gate 17 of any vertical transistor is not shared with the second gate 17 of other vertical transistors on the chip, the first pole 11 of any vertical transistor is not shared with the first pole 11 of other vertical transistors on the chip, and the second pole 13 of any vertical transistor is not shared with the second pole 13 of other vertical transistors on the chip.

[0105] Multiple vertical transistors of the present application can also form a connected array structure. For example, as Figure 3a shown, along the Y direction, multiple vertical transistors in the same column share the same first pole 11; and / or, along the X direction, multiple vertical transistors in the same row share the same first gate 16 and the same second gate 17.

[0106] In some possible implementation manners, as Figure 2a and Figure 3a shown, multiple vertical transistors on the chip are not stacked in the Z direction; or, as Figure 6 shown, the vertical transistors can be stacked in multiple layers in the Z direction.

[0107] Please continue to refer to Figure 6 . In the case where the vertical transistors are stacked in multiple layers in the Z direction, the second pole 13 of the lower-layer vertical transistor can be reused as the first pole 11 of the upper-layer vertical transistor. Of course, there can also be other connection manners between the transistors stacked in the Z direction, and the embodiments of the present application do not limit this.

[0108] In addition, in addition to the L shape, the longitudinal cross-sections of the first gate dielectric layer 14 and the second gate dielectric layer 15 can also be other shapes. As Figure 7a shown, the longitudinal cross-sections of the first gate dielectric layer 14 and the second gate dielectric layer 15 can also be rectangular. The first gate dielectric layer 14 is only required to be located between the first gate 16 and the channel 12, and the second gate dielectric layer 15 is only required to be located between the second gate 17 and the channel 12. As Figure 7bAs shown, when both the first gate 16 and the second gate 17 are located on the side of the channel 12 away from the first insulating layer 21, the first gate dielectric layer 14 surrounds the first gate 16 and exposes the surface of the first gate 16 on the side away from the channel 12. On this basis, the first gate dielectric layer 14 can further extend in the Z direction towards the first stage 11 and / or the second stage 13; the second gate dielectric layer 15 surrounds the second gate 17 and exposes the surface of the second gate 17 on the side away from the channel 12. On this basis, the second gate dielectric layer 15 can further extend in the Z direction towards the first stage 11 and / or the second stage 13.

[0109] The process implementation method of this structure can be to first dig a groove on the side of the above-mentioned sacrificial structure, and then, form the first gate dielectric layer 14 and the second gate dielectric layer 15 laterally into the groove. Then, form the first gate 16 on the first gate dielectric layer 14 and form the second gate 17 on the second gate dielectric layer 15. Since the process of digging the groove is more controllable and the process accuracy is higher, the gate lengths of the first gate 16 and the second gate 17 filled in the groove are more controllable.

[0110] In some possible implementation ways, a buffer layer may further be included between the first stage 11 and / or the second stage 13 and the channel 12. As Figure 7c shown, the buffer layer 30 is disposed between the first stage 11 and the channel 12; as Figure 7d shown, the buffer layer 30 is disposed between the second stage 13 and the channel 12; as Figure 7e shown, the buffer layer 30 is disposed between the first stage 11 and the channel 12 and between the second stage 13 and the channel 12.

[0111] In some possible implementation ways, the embodiments of the present application do not limit the materials of each structure in the vertical transistor.

[0112] Optionally, the channel 12 can be an oxide semiconductor material deposited by a deposition process such as atomic layer deposition (ALD). Its materials can include elements such as indium (In), gallium (Ga), zinc (Zn), tin (Sn), tungsten (W), magnesium (Mg), aluminum (Al), silicon (Si), etc. For example, indium gallium zinc oxide (InGaZnO), indium tin oxide (InSnO), indium gallium oxide (InGaO), indium magnesium oxide (InMgO), etc. By using an oxide semiconductor material as the material of the channel 12, the leakage current of the vertical transistor can be reduced. In the scenario where the vertical transistor is applied to a memory, the retention time of the memory can also be improved, the power consumption of the memory can be reduced, and the area of the capacitor in the memory can be reduced, thereby improving the integration density.

[0113] Of course, the material of the channel 12 in this application can also be an amorphous structure, a partially crystallized structure, including other semiconductor materials, etc., such as polycrystalline silicon (poly-Si), amorphous silicon (a-Si), two-dimensional materials, etc.

[0114] The materials of the first gate dielectric layer 14 and the second gate dielectric layer 15 can include oxide dielectric materials, for example, hafnium oxide (HfO2), aluminum oxide (Al2O3), silicon dioxide (SiO2), hafnium silicon oxide (HfSiO), etc., or can be nitrides such as silicon nitride (SiN), or the materials of the first gate dielectric layer 14 and the second gate dielectric layer 15 can include HfO2 and Al2O3.

[0115] The first gate 16 and the second gate 17 can both be single-layer, or, the first gate 16 and the second gate 17 can also both be stacked layers. Taking the first gate 16 and the second gate 17 both being single-layer as an example, the materials of the first gate 16 and the second gate 17 can include metals such as tungsten (W), ruthenium (Ru), nickel (Ni), molybdenum (Mo), etc., or alloy materials such as nickel platinum (NiPt); or, the materials of the first gate 16 and the second gate 17 can also be conductive oxides / nitrides, such as InSnO, titanium nitride (TiN), tantalum nitride (TaN), etc. Taking the first gate 16 and the second gate 17 both being stacked layers as an example, the first gate 16 and the second gate 17 can both be stacked layers of TaN and W. Among them, the layer where TaN is located is between the layer where W is located and the first gate dielectric layer 14 / second gate dielectric layer 15.

[0116] The materials of the first pole 11 and the second pole 13 can include metals or nitrides or alloy electrodes, for example, W, Ni, Mo, Ru, NiPt, TiN, and the materials of the first pole 11 and the second pole 13 can also be conductive oxides, such as InSnO.

[0117] The material of the first insulating layer 21 can be oxides, nitrides, carbon oxides, etc., for example, silicon oxide (SiO), SiN, silicon carbon oxide (SiOC), aluminum oxide (AlO), etc.

[0118] In another embodiment, as Figures 8a - 9b shown, the embodiment of this application also provides a chip, which includes a vertical transistor. The vertical transistor includes a first pole 11, a channel 12, and a second pole 13 that are sequentially stacked. Among them, the second pole 13 includes a first sub-electrode 131 and a second sub-electrode 132 that are oppositely arranged. For example, the first pole 11 is a source electrode, the second pole 13 is a drain electrode, the first sub-electrode 131 is a first drain electrode, and the second sub-electrode 132 is a second drain electrode. Or, the first pole 11 is a drain electrode, the second pole 13 is a source electrode, the first sub-electrode 131 is a first source electrode, and the second sub-electrode 132 is a second source electrode. In this application, the direction from the first pole 11 to the second pole 13 can be the Z direction.

[0119] The chip further includes a first gate dielectric layer 14 and a second gate dielectric layer 15, and both the first gate dielectric layer 14 and the second gate dielectric layer are in contact with the sidewalls of the channel. The part of the channel 12 in contact with the first gate dielectric layer 14 is called the first channel 121, and the first channel 121 is located between the first pole 11 and the first sub-electrode 131; the part of the channel 12 in contact with the second gate dielectric layer 15 is called the second channel 122, and the second channel 122 is located between the first pole 11 and the second sub-electrode 132.

[0120] The chip further includes a first gate 16 and a second gate 17 which are oppositely arranged. The first gate 16 is disposed on a side of the first gate dielectric layer 14 away from the channel 12, and the second gate 17 is disposed on a side of the second gate dielectric layer 15 away from the channel 12. Moreover, since the first gate 16 and the second gate 17 are oppositely arranged, in this way, the first gate dielectric layer 14 for isolating the first gate 16 from the channel 12 and the second gate dielectric layer 15 for isolating the second gate 17 from the channel 12 can also be oppositely arranged.

[0121] The vertical transistors obtained from the above structure are respectively a first vertical transistor and a second vertical transistor. The first vertical transistor includes a first pole 11, a first channel 121, a first sub-electrode 131, a first gate dielectric layer 14, and a first gate 16. The second vertical transistor includes a first pole 11, a second channel 122, a second sub-electrode 132, a second gate dielectric layer 15, and a second gate 17. Among them, as in the previous embodiment, the first pole 11 of the first vertical transistor and the first pole 11 of the second vertical transistor can be shared, or the first pole 11 of the first vertical transistor and the first pole 11 of the second vertical transistor can also not be shared; the first gate 16 is used to control the conduction or cutoff of the first vertical transistor, and the second gate 17 is used to control the conduction or cutoff of the second vertical transistor. That is, both the first vertical transistor and the second vertical transistor in the embodiment of the present application are single-gate vertical transistors.

[0122] Compared with the related art, the present application can split a vertical transistor into a first vertical transistor and a second vertical transistor, which can improve the integration density. Compared with the double-gate vertical transistor provided in the previous embodiment, in the direction from the first vertical transistor to the second vertical transistor, the distance between the center of the first vertical transistor and the center of the second vertical transistor can be less than 30 nm. It can also be said that the pitch between the first vertical transistor and the second vertical transistor can be less than 30 nm, and when applied to DRAM, it can achieve a smaller cell area than the advanced processes 1beta and 1gamma.

[0123] Moreover, on the one hand, since the first gate 16 and the second gate 17 of the present application are no longer in a surrounding shape, and the first gate dielectric layer 14 and the second gate dielectric layer 15 are no longer in a surrounding shape either, the present application does not adopt the process of the related art to first form a first through hole in the surrounding gate and then form a second through hole in the gate dielectric layer. Instead, a sacrificial structure (such as a sacrificial layer, a dummy channel, etc.) is first formed in the region where the channel 12 to be formed is located, a groove is formed between adjacent sacrificial structures, and then the first gate dielectric layer 14 and the second gate dielectric layer 15, as well as the first gate 16 and the second gate 17, are formed on the side walls of the sacrificial structures. After that, by removing the sacrificial structures and forming a channel 12 at the position where the sacrificial structures are located, the channel 12 can be made to contact the first electrode 11. That is, the present application does not need to form a second through hole between the first gate dielectric layer 14 and the second gate dielectric layer 14, thereby avoiding the process limitation of forming the second through hole, which may cause the size of the vertical transistor not to be miniaturized.

[0124] On the other hand, the first gate 16 and the second gate 17 are disposed opposite to each other, rather than surrounding the channel 12 in a circle as in the related art. Therefore, the sizes of the first vertical transistor and the second vertical transistor in the X direction and the Y direction can be reduced, enabling the first vertical transistor and the second vertical transistor to be miniaturized. At the same time, the first gate dielectric layer 14 and the second gate dielectric layer 15 can also be disposed opposite to each other, rather than surrounding the channel 12 in a circle. Therefore, the total area of the first gate dielectric layer 14 and the second gate dielectric layer 15 of the present application is smaller than the total area of the gate dielectric layer in the gate-all-around scheme, thereby reducing the size of the vertical transistor in the X direction and / or the Y direction, enabling the vertical transistor to be miniaturized.

[0125] In some possible implementation manners, the present application embodiment does not limit the relative positions of the first sub-electrode 131 and the second sub-electrode 132, as long as the first sub-electrode 131 and the second sub-electrode 132 are disposed opposite to each other. Optionally, as Figure 8d shown, the first sub-electrode 131 and the second sub-electrode 132 are disposed directly opposite to each other in the X direction or the Y direction; or, as Figure 8e shown, the first sub-electrode 131 and the second sub-electrode 132 may also not be completely disposed directly opposite to each other in the X direction or the Y direction on the basis of being disposed opposite to each other.

[0126] Similarly, the present application embodiment does not limit the relative positions of the first gate 16 and the second gate 17, as long as the first gate 16 and the second gate 17 are disposed opposite to each other. Optionally, the first sub-electrode 131 and the second sub-electrode 132 are disposed directly opposite to each other in the X direction or the Y direction; or, the first gate 16 and the second gate 17 may also not be completely disposed directly opposite to each other in the X direction or the Y direction on the basis of being disposed opposite to each other.

[0127] For ease of description, unless otherwise specified hereinafter, the description will be given by taking the example that the first sub - electrode 131 and the second sub - electrode 132 are directly opposite in the Y direction, and the first gate 16 and the second gate 17 are arranged directly opposite in the Y direction.

[0128] In some possible implementation manners, such as Figure 8b shown, since the first pole 11 of the first vertical transistor and the first pole 11 of the second vertical transistor are shared, therefore, the first channel 121 and the second channel 122 can be connected and there will be no short - circuit problem; or, as Figure 8c shown, the first channel 121 and the second channel 122 can also be disconnected. Compared with the scheme where the first channel 121 and the second channel 122 are disconnected, the scheme where the first channel 121 and the second channel 122 can be connected does not require etching to disconnect the first channel 121 and the second channel 122, and the process is simple. Compared with the scheme where the first channel 121 and the second channel 122 can be connected, the scheme where the first channel 121 and the second channel 122 are disconnected can not only improve the crosstalk between the first vertical transistor and the second vertical transistor caused by the connection of the first channel 121 and the second channel 122, but also facilitate the preparation of the non - connected first vertical transistor and the second vertical transistor.

[0129] In the case where the first channel 121 and the second channel 122 are connected, such as Figure 8a shown, the first channel 121 and the second channel 122 form a solid integral structure or a hollow structure; or, referring to Figure 2f , the first channel 121 and the second channel 122 form a groove with a bottom, that is to say, a groove including a bottom is formed in the channel 12, and the cross - section of the groove is a closed loop. For example, the cross - section of the groove can be a closed - loop figure such as a "square" shape, a circular shape, an oval shape, etc.; or, as Figures 4a - 4b shown, the longitudinal cross - section of the groove is U - shaped.

[0130] Such as Figure 8c shown, in the case where the first channel 121 and the second channel 122 are disconnected, the first channel 121 and the second channel 122 can both be independent columns, and the column - shaped first channel 121 and the second channel 122 form a groove without a bottom, that is to say, a groove not including a bottom is formed in the channel 12.

[0131] In the case where the first channel 121 and the second channel 122 form a groove and the groove has a bottom, the second pole 13 can be filled in the groove. Because the groove of the channel 12 includes a bottom, the second pole 13 will not directly contact the first pole 11. Or, as Figure 8b and Figure 8cAs shown, whether the trench includes a bottom or not, the chip may further include a first insulating layer 21, and the first insulating layer 21 may be filled in the trench to separate the first pole 11 and the second pole 13 by using the first insulating layer 21.

[0132] In some possible implementation manners, assume that the surface of the trench facing the first pole 11 is the first surface, and the surface of the trench facing the second pole 13 is the second surface. Outside the trench, the surface adjacent to the first surface and the second surface in the trench is the outer sidewall of the trench; inside the trench, the surface adjacent to the second surface and the bottom surface of the trench is the inner sidewall of the trench.

[0133] As Figures 8a - 8c shown, the first gate dielectric layer 14 and the second gate dielectric layer 15 may both be located outside the trench, the first gate dielectric layer 14 and the second gate dielectric layer 15 both contact the outer sidewall of the trench, and the first gate 16 and the second gate 17 are also disposed outside the trench.

[0134] Or, as Figure 9a and Figure 9b shown, when the first insulating layer 21 is filled in the trench, the first gate dielectric layer 14 and the second gate dielectric layer 15 may also both be located inside the trench, the first gate dielectric layer 14 and the second gate dielectric layer 15 both contact the inner sidewall of the trench, the first gate 16 and the second gate 17 are also disposed inside the trench, and the first insulating layer 21 is disposed between the first gate 16 and the second gate 17. In this case, in order to avoid the trench contacting the first gate 16 and the second gate 17, the trench of the channel 12 may not include a bottom.

[0135] As Figure 9a and Figure 9b shown, when both the first gate 16 and the second gate 17 are located inside the trench, along the direction from the first gate 16 to the second gate 17, the channels 12 of adjacent vertical transistors are connected above the first pole 11. Compared with the case where the channels 12 of adjacent vertical transistors are disconnected, connecting the channels 12 of adjacent vertical transistors above the first pole 11 can increase the contact area between the channel 12 and the first pole 11. In this case, the partial longitudinal section of the channel 12 located between the first gate dielectric layer 14 and the second gate dielectric layer 15 of adjacent vertical transistors may be U-shaped.

[0136] As Figure 8c shown, the channel 12 further includes an extension portion other than the trench, and the extension portion contacts the second pole 13. The extension portion is connected to the sidewall of the trench and extends outward to increase the contact area between the channel 12 and the second pole 13. For example, taking the longitudinal section of the channel 12 being U-shaped as an example, the extension portion of the first channel 121 extends away from the second channel 122, and the extension portion of the second channel 122 extends away from the first channel 121.

[0137] On this basis, as Figure 8b and Figure 8c shown, the longitudinal cross-section of the first gate dielectric layer 14 and the second gate dielectric layer 15 can be L-shaped. The first gate dielectric layer 14 is located between the first gate 16 and the channel 12, and also between the first gate 16 and the first pole 11; the second gate dielectric layer 15 is located between the second gate 17 and the channel 12, and also between the second gate 17 and the first pole 11.

[0138] In addition, for the dimensions, materials, etc. of each structure in the chip of the embodiment of the present application, reference can be made to the dimensions and materials of each structure in the chip of the previous embodiment, and the embodiments of the present application will not elaborate on this.

[0139] The vertical transistors provided in the above two embodiments can be applied to a memory. The memory includes a storage array, the storage array includes storage cells, and the storage cells include at least one vertical transistor and at least one capacitor. Among them, the capacitor includes a first electrode 41, a second electrode 42, and a dielectric layer located between the first electrode 41 and the second electrode 42.

[0140] As Figure 10a shown, the capacitor is disposed above the vertical transistor, and the first electrode 41 of the capacitor is electrically connected to the second pole 13 of the vertical transistor.

[0141] As Figure 10b shown, the capacitor is disposed below the vertical transistor, and the first electrode 41 of the capacitor is electrically connected to the first pole 11 of the vertical transistor.

[0142] As Figure 10c shown, the capacitor is disposed above the vertical transistor, and the first electrode 41 of the capacitor is reused as the second pole 13 of the vertical transistor, forming a structure in which the capacitor wraps the vertical transistor.

[0143] As Figure 10d shown, single-gate vertical transistors are stacked in multiple layers in the Z direction, and a capacitor is also disposed above or below each vertical transistor. The second electrode 42 of the capacitor is electrically connected to the second pole 13 of the vertical transistor. As Figure 10d shown, taking two vertical transistors stacked in the Z direction as an example, the capacitor, the vertical transistor, the vertical transistor, and the capacitor are stacked in the Z direction in sequence. Among them, the second pole 13 of the lower vertical transistor is shared with the first pole 11 of the upper vertical transistor.

[0144] Figure 10d The vertical transistors and capacitors shown can be applied to Figure 10e the circuit diagram shown, Figure 10e which shows the circuit diagram of the memory. Any storage cell in the memory is 1T1C, that is, one vertical transistor and one capacitor. Figure 10eA common bit line BL is located between two rows of memory cells, corresponding to Figure 10d As shown in the structural diagram, the memory includes n columns of bit lines BL and m rows of word lines WL. The memory cells on both sides of the bit line BL are controlled by different word lines WL.

[0145] In the figure, 4 rows of memory cells corresponding to the same column are drawn, corresponding to word lines WL0 to word line WL3 respectively. On the one hand, this structure doubles the density of the memory. On the other hand, since two rows of memory cells share the same bit line BL, only one layer of bit line BL needs to be fabricated between two rows of memory cells, saving the number of masks and improving the capacity / cost ratio.

[0146] In some possible implementation manners, the embodiments of the present application are applicable not only to 1T1C memory cells but also to 2T0C memory cells. Figure 11a and Figure 11b shows a top view of a 2T0C memory cell. The memory cell includes a first vertical transistor and a second vertical transistor with a single gate. In addition to sharing the first pole 11 and being electrically connected to the bit line BL, the second sub - electrode 132 of the second vertical transistor is also electrically connected to the first gate 16 of the first vertical transistor to a pre - node SN (such as ​ SN00 in). In addition, the second gate is electrically connected to the write word line WWL in the memory array, and the first sub - electrode 131 is electrically connected to the read word line RWL.

[0147] It should be understood that in order to show that the second sub - electrode 132 of the second vertical transistor is also electrically connected to the first gate 16 of the first vertical transistor to the pre - node SN, ​ the first gate 16 and the second gate 17 can be seen in the shown top view. However, in the actual structure, the first gate 16 and the second gate 17 should be blocked by an insulating material. The first gate is electrically connected to the second sub - electrode 132 through a through - hole in the insulating material, and the second gate is electrically isolated from the second sub - electrode 132 by the insulating material.

[0148] Compared with memory cells that require RBL (read BL) and WBL (write BL), this circuit structure reduces one bit line, is simpler in the wiring structure, occupies less area, and can achieve a higher array density.

[0149] This structure features a second vertical transistor serving as a write transistor (Wtr) in the 2T0C memory cell, and a first vertical transistor serving as a read transistor (Rtr) in the 2T0C memory cell. Because the first gate SN of the ReadFET is an independent electrode, the interconnected first gates 16 of multiple first vertical transistors in the same row on the Rtr side are now separate, independent gates in the 2T0C, while the second gates 17 of multiple second vertical transistors in the same row on the Wtr side remain connected.

[0150] Of course, the vertical transistors and capacitors in the memory cell may also be arranged and electrically connected in other ways, which is not limited in the embodiments of the present application.

[0151] In another embodiment, the embodiment of the present application also provides a method for preparing a chip. As described in the above embodiment, the vertical transistors on the chip can be divided into dual-gate vertical transistors and single-gate vertical transistors. The preparation process of chips provided with dual-gate vertical transistors and single-gate vertical transistors will be described below in conjunction with the accompanying drawings.

[0152] In the first case, both the first gate 16 and the second gate 17 are in contact with the outer sidewalls of the channel 12, and the vertical transistor on the chip is a dual-gate vertical transistor. ​ As shown, this structure can be implemented through the following steps:

[0153] S110, such as ​ As shown, a first conductive layer 111 and a first sacrificial layer 51 are sequentially deposited on the substrate 10; ​ As shown, the first conductive layer 111 and the first sacrificial layer 51 are patterned. The patterned first conductive layer 111 is the first electrode 11. The patterned first sacrificial layer covers the surface of the first electrode 11 facing away from the substrate 10. ​ As shown, a second insulating layer 22 is formed on the first sacrificial layer 51 and the first electrode 11, and the second insulating layer 22 completely covers the first sacrificial layer 51 and the first electrode 11, and then polishing is performed, for example, chemical mechanical polishing (CMP); ​ As shown, the second insulating layer 22 is patterned. Along the X direction, the patterned second insulating layer 22 is located between adjacent first electrodes 11 and between adjacent first sacrificial layers 51 .

[0154] S120, such as ​As shown, a third insulating layer 23 is formed on the first sacrificial layer 51, the first electrode 11, and the second insulating layer 22. The third insulating layer 23 completely covers the first electrode 11, the sidewalls of the first sacrificial layer 51, and the sidewalls of the second insulating layer 22, exposing the surfaces of the second insulating layer 22 and the first sacrificial layer 51 facing away from the substrate 10. ​ As shown, the third insulating layer 23 is etched back. In the Y direction, the etched-back third insulating layer 23 is located between adjacent first electrodes 11 and covers the sidewalls of the first electrodes 11, exposing the second insulating layer 22 and part of the sidewalls of the first sacrificial layer 51 and the surface facing away from the substrate 10. The etching depth of the third insulating layer 23 determines the vertical distance between the subsequent first gate 16 and the second gate 17 and the first electrode 11. ​ As shown, a gate dielectric layer 141 and a second conductive layer 161 are sequentially formed on the third insulating layer 23 and the second insulating layer 22. The gate dielectric layer 141 completely covers the sidewalls and the surface of the second insulating layer 22 facing away from the substrate 10, as well as the surface of the third insulating layer 23 facing away from the substrate 10. ​ As shown, the second conductive layer 161 is etched back to etch the second conductive layer 161 to a certain depth and expose a portion of the surface of the gate dielectric layer 141 .

[0155] S130, such as ​ As shown, a second sacrificial layer 52 is formed on the gate dielectric layer 141. The second sacrificial layer 52 completely covers the sidewalls and the surface of the gate dielectric layer 141 facing away from the substrate 10, as well as the surface of the second conductive layer 161 facing away from the substrate 10. ​ As shown, the second sacrificial layer 52 is etched back, and the sidewalls of the second sacrificial layer 52 are retained and in contact with the outer sidewalls of the gate dielectric layer 141. ​ As shown, under the protection of the second sacrificial layer 52, the second conductive layer 161 and the gate dielectric layer 141 are etched back, and the portions of the second conductive layer 161 and the gate dielectric layer 141 covering the side walls of the second insulating layer 22 are retained. The retained portions of the gate dielectric layer 141 are the first gate dielectric layer 14 and the second gate dielectric layer 15, and the retained portions of the second conductive layer 161 are the first gate dielectric layer 16 and the second gate dielectric layer 17. Both the first gate dielectric layer 14 and the second gate dielectric layer 15 are in contact with the outer side walls of the second insulating layer 22. The first gate 16 is located on the side of the first gate dielectric layer 14 away from the second insulating layer 22, and the second gate is located on the side of the second gate dielectric layer 15 away from the second insulating layer 22.

[0156] S140, such as ​As shown, an insulating material is further formed on the first gate dielectric layer 14, the second gate dielectric layer 15, the first gate 16, the second gate 17, and the second sacrificial layer 52. The insulating material can be the same as the material of the third insulating layer 23, and is collectively referred to as the third insulating layer 23. The third insulating layer 23 covers the sidewalls of the first gate dielectric layer 14, the second gate dielectric layer 15, the first gate 16, the second gate 17, and the second sacrificial layer 52.

[0157] S150, such as ​ As shown, the first sacrificial layer 51 is removed and a groove is formed in the area where the channel 12 to be formed is located to expose the first electrode 11. The figure shows that in the above process, the second insulating layer 22 and the third insulating layer 23 around the first gate dielectric layer 14 and the second gate dielectric layer 15 may be partially etched, so that the first gate dielectric layer 14 and the second gate dielectric layer 15 may protrude. ​ As shown, a semiconductor layer 121 and a first insulating layer 21 are formed in sequence. The semiconductor layer 121 and the first insulating layer 21 cover the second insulating layer 22, the third insulating layer 23, the first gate dielectric layer 14, and the second gate dielectric layer 15. Since the first gate dielectric layer 14 and the second gate dielectric layer 15 are protruding, the portion of the semiconductor layer 121 that overlaps with the first gate dielectric layer 14 and the second gate dielectric layer 15 is also protruding. The portion of the semiconductor layer 121 that overlaps with the region between the first gate dielectric layer 14 and the second gate dielectric layer 15 is a trench. Then, as shown in FIG. ​ As shown, the first insulating layer 21 is etched back. After etching, the first insulating layer 21 is located in the trench of the semiconductor layer 121 .

[0158] ​ The YZ and XZ directions are side views, which do not reflect the area where the channel 12 to be formed is located. ​ The top view taken along the XY axis shows that after removing the first sacrificial layer 51, the surface of the first electrode 11 facing away from the substrate 10 is exposed, and a recess is formed in the region where the channel 12 is to be formed. The recess is surrounded by the first electrode 11, the second insulating layer 22, the first gate dielectric layer 14, and the second gate dielectric layer 15. Furthermore, the subsequently formed semiconductor layer 121 can be filled in the recess, and after subsequent step S160, the portion of the semiconductor layer 121 located in the recess becomes the channel 12.

[0159] S160, such as ​ and ​ As shown, a third conductive layer 1311 and a hard mask 60 are sequentially formed on the semiconductor layer 121 and the first insulating layer 21, as shown in FIG. ​ and ​As shown, under the protection of the hard mask 60, the third conductive layer 1311 and the semiconductor layer 121 are sequentially partially removed to obtain the second pole 13 and the channel 12. Among them, the second pole 13 contacts the surface of the channel 12 facing away from the substrate 10. Then, by removing the hard mask 60, a double-gate vertical transistor can be obtained, in which the first gate 16 and the second gate 17 both contact the outer sidewall of the channel 12 in the first embodiment described above.

[0160] Of course, if the second pole 13 formed in S160 includes a first sub-electrode 131 and a second sub-electrode 132 arranged opposite to each other, a single-gate first vertical transistor and a single-gate second vertical transistor can also be formed by using this process step (for example ​ ).

[0161] In this application, the first sacrificial layer 51 and the second insulating layer 22 are first formed, trenches are opened between adjacent first sacrificial layers 51 and between adjacent second insulating layers 22 by etch back, and then the first gate dielectric layer 14 and the second gate dielectric layer 15, as well as the first gate 16 and the second gate 17, are formed on the sidewalls of the first sacrificial layer 51 and the second insulating layer 22. After that, by removing the first sacrificial layer 51 and forming the channel 12 at the position where the first sacrificial layer 51 is located, the channel 12 can be made to contact the first pole 11. That is, in this application, there is no need to form a second through hole between the first gate dielectric layer 14 and the second gate dielectric layer 14, thus avoiding the process limitation caused by forming the second through hole, which leads to the inability to miniaturize the size of the vertical transistor.

[0162] In the second case, the first gate 16 and the second gate 17 both contact the outer sidewall of the channel 12, and the vertical transistors on the chip include a single-gate first vertical transistor and a single-gate second vertical transistor. As ​ shown, this structure can be realized through the following steps:

[0163] S210, as ​ shown, a third sacrificial layer 53 and a fourth insulating layer 24 are sequentially formed on the substrate 10. The third sacrificial layer 53 and the fourth insulating layer 24 have a hollow portion, and the hollow portion penetrates the third sacrificial layer 53 and the fourth insulating layer 24 in the Z direction, and the first pole 11 is filled in the hollow portion. In the Z direction, the thickness of the first pole 11 is less than the depth of the hollow portion. As ​ shown, a fifth insulating layer 25 is formed in the hollow portion, and the fourth insulating layer 24 is removed.

[0164] S220, as ​As shown, a first gate dielectric layer 14 and a second gate dielectric layer 15 are formed on the outer sidewall of the fifth insulating layer 25, and under the protection of the first protective layer 61, a first gate 16 and a second gate 17 are formed. Among them, the first gate dielectric layer 14 is located between the first gate 16 and the fifth insulating layer 24, the second gate dielectric layer 15 is located between the second gate 17 and the fifth insulating layer 25, and the first gate 16 and the second gate 17 are arranged at intervals.

[0165] S230, as ​ shown, a sixth insulating layer 26 is formed on the sidewalls of the first gate 16 and the second gate 17 to cover the sidewalls of the first gate 16 and the second gate 16 by using the sixth insulating layer 26. Then, the fifth insulating layer 25 is removed to expose the first electrode 11.

[0166] S240, a semiconductor layer 121 is formed, and the semiconductor layer 121 extends from the hollow part to outside the hollow part.

[0167] In some possible implementation manners, as ​ shown, if the channel 12 to be formed is a solid integral structure or a hollow structure, the semiconductor layer 121 can fill the part of the hollow part except the first electrode 11. Then, part of the semiconductor layer 121 is removed to obtain a semiconductor layer intermediate pattern 1211, and the semiconductor layer intermediate pattern 1211 extends in the Y direction.

[0168] Or, as ​ shown, if the channel 12 to be formed further has a groove and the groove is filled with a first insulating layer 21, the semiconductor layer 121 partially fills the first electrode 11 contacting the bottom in the hollow part. After forming the semiconductor layer 121, the first insulating layer 21 is also filled into the hollow part, and the first insulating layer 21 completely covers the semiconductor layer 121. Then, as ​ shown, the part of the first insulating layer 21 except the hollow part is removed; as ​ shown, part of the semiconductor layer 121 is removed to obtain a semiconductor layer intermediate pattern 1211, and the semiconductor layer intermediate pattern 1211 extends in the Y direction.

[0169] S250, as ​ shown, a third conductive layer 1311 and a hard mask 60 are formed. As ​ shown, under the protection of the hard mask 60, the third conductive layer 1311 is removed to obtain a second electrode 13, and the second electrode 13 includes a first sub - electrode 131 and a second sub - electrode 132 which are oppositely arranged. After that, the mask plate 60 can also be removed.

[0170] S260, as ​As shown, the semiconductor layer middle pattern 1211 is partially removed to obtain the channel 12, which includes a first channel 121 and a second channel 122. The first channel 121 is located between the first electrode 11 and the first sub-electrode 131, and the second channel 122 is located between the first electrode 11 and the second sub-electrode 132. Thus, the single-gate vertical transistor in the second embodiment described above is obtained, in which both the first gate 16 and the second gate 17 are in contact with the outer sidewalls of the channel 12.

[0171] Of course, if the second electrode 13 in a vertical transistor formed in S250 is an integral structure rather than including the first sub-electrode 131 and the second sub-electrode 132 arranged opposite to each other, and the first channel 121 and the second channel 122 formed in S260 form a trench, the first insulating layer 21 can also be filled in the trench to form a dual-gate vertical transistor (for example, ​ and ​ ).

[0172] In the present application, the fifth insulating layer 25 is formed in the region where the channel 12 is to be formed, and then the first gate dielectric layer 14 and the second gate dielectric layer 15, as well as the first gate electrode 16 and the second gate electrode 17, are formed on the sidewalls of the fifth insulating layer 25. Thereafter, the fifth insulating layer 25 is removed, and the channel 12 is formed at the location of the fifth insulating layer 25, so that the channel 12 can be brought into contact with the first electrode 11. That is, the present application does not require the formation of a second through hole between the first gate dielectric layer 14 and the second gate dielectric layer 14, thereby avoiding the limitation of the process for forming the second through hole that prevents the size of the vertical transistor from being reduced.

[0173] In the third case, the first gate 16 and the second gate 17 are both in contact with the inner sidewall of the channel 12, and the vertical transistor on the chip can be a dual-gate vertical transistor or a single-gate vertical transistor. ​ As shown, this structure can be implemented through the following steps:

[0174] S310, such as ​ As shown, a first electrode 11, an etch stop layer 70, and a fourth sacrificial layer 54 are sequentially formed on a substrate 10. In some possible implementations, the fourth sacrificial layer 54 may be directly formed on the first electrode 11 without forming the etch stop layer 70.

[0175] S320, such as ​ As shown, the fourth sacrificial layer 54 is partially removed, and the remaining fourth sacrificial layer 54 can be used as the first insulating layer 21 between the first gate 16 and the second gate 17 to be formed. ​ and ​As shown, the second conductive layer 161 is first filled in the area around the fourth sacrificial layer 54 , and then the second protection layer 71 is formed in the area where the first gate 16 and the second gate 17 to be formed are located.

[0176] S330, such as ​ As shown, under the protection of the second protective layer 71, the second conductive layer 161 and the etch stop layer 70 are partially removed in sequence to obtain the first gate 16 and the second gate 17, and the retained etch stop layer 70 overlaps with the first gate 16, the second gate 17, and the fourth sacrificial layer 54.

[0177] S340, such as ​ As shown, a gate dielectric layer 141 and a dummy channel 72 are formed in sequence. The gate dielectric layer 14 completely covers the first gate 16, the second gate 17, and the surface of the fourth sacrificial layer 54 facing away from the substrate 10, as well as the surface of the substrate 10. The dummy channel 72 is etched back to remove the portion of the dummy channel 72 except for the sidewalls. The remaining dummy channel 72 covers the sidewalls of the gate dielectric layer 141. ​ As shown, under the protection of the dummy channel 72 , the portion of the gate dielectric layer 141 not covered by the dummy channel 72 is removed to obtain the first gate dielectric layer 14 and the second gate dielectric layer 15 .

[0178] S350, such as ​ As shown in FIG. 1 , the dummy channel 72 is removed and the semiconductor layer 121 is formed. ​ As shown, a seventh insulating layer 27 is formed, and the seventh insulating layer 27 is used to isolate adjacent vertical transistors in the Y direction.

[0179] Afterwards, referring to the first and second cases mentioned above, the semiconductor layer 121 may be partially removed to obtain the channel 12 according to the dual-gate vertical transistor or the single-gate vertical transistor; and the second electrode 13 may be formed above the channel 12, which will not be described in detail here. ​ As shown, after the channel 12 is obtained by this process step, along the Y direction, ​ The first channel 121, the second channel 122, the first channel 121, and the second channel 122 are shown in sequence. The present application can also form the second electrode 13 on the middle second channel 122 and the first channel 121. In this way, the double-gate vertical transistor proposed in the first embodiment with the first gate 16 and the second gate 17 outside the trench can also be prepared through this process step.

[0180] In this application, a fourth sacrificial layer 54 is formed in the region where the channel 12 is to be formed. Then, a first gate dielectric layer 14, a second gate dielectric layer 15, a first gate 16, and a second gate 17 are formed on the sidewalls of the fourth sacrificial layer 54. After that, the fourth sacrificial layer 54 is removed, and a channel 12 is formed at the position where the fourth sacrificial layer 54 is located, so that the channel 12 can be in contact with the first pole 11. That is, in this application, there is no need to form a second through hole between the first gate dielectric layer 14 and the second gate dielectric layer 14, thereby avoiding the process limitations caused by the formation of the second through hole, which may prevent the miniaturization of the size of the vertical transistor.

[0181] In addition, the other explanations and beneficial effects of the embodiments of this application are the same as those of the previous two embodiments, and will not be elaborated here.

[0182] The embodiments of the present application have been described above in conjunction with the accompanying drawings. However, the present application is not limited to the above specific embodiments. The above specific embodiments are merely illustrative and not restrictive. Under the inspiration of the present application, those of ordinary skill in the art can also make many forms without departing from the purpose of the present application and the scope protected by the claims, and all of them belong to the protection scope of the present application.

Claims

1. A chip, characterized in that: A vertical transistor is included, the vertical transistor comprising: A first electrode, a channel, and a second electrode are sequentially stacked on a substrate, wherein the channel includes a groove; a first gate dielectric layer and a second gate dielectric layer, wherein the first gate dielectric layer and the second gate dielectric layer are both in contact with sidewalls of the trench; the first gate dielectric layer and the second gate dielectric layer are both located in the trench, or the first gate dielectric layer and the second gate dielectric layer are both located outside the trench; A first gate and a second gate are spaced apart, wherein the first gate is disposed on a side of the first gate dielectric layer away from the channel, and the second gate is disposed on a side of the second gate dielectric layer away from the channel.

2. The chip according to claim 1, characterized in that The first gate dielectric layer and the second gate dielectric layer are both located outside the trench. The first gate is located on a side of the first gate dielectric layer away from the trench, and the second gate is located on a side of the second gate dielectric layer away from the trench.

3. The chip according to claim 2, characterized in that The chip further includes a first insulating layer, and the first insulating layer is filled in the groove; or, The trench further includes a bottom adjacent to the sidewalls, wherein the bottom is in contact with the first pole; the second pole is filled in the trench.

4. The chip according to claim 1, characterized in that The first gate dielectric layer and the second gate dielectric layer are both located in the trench, and the chip further includes a first insulating layer, which is filled in the trench; The first gate is disposed between the first gate dielectric layer and the first insulating layer, and the second gate is disposed between the second gate dielectric layer and the first insulating layer.

5. The chip according to any one of claims 1 to 4, characterized in that: There are multiple vertical transistors; The plurality of vertical transistors arranged along the column direction share the same first electrode; The plurality of vertical transistors arranged along a row direction share the same first gate and the same second gate.

6. The chip according to claim 5, characterized in that When both the first gate dielectric layer and the second gate dielectric layer are located in the trench, channels of adjacent vertical transistors arranged along the column direction are connected.

7. The chip according to any one of claims 1 to 6, characterized in that: The first gate and the second gate are arranged opposite to each other.

8. The chip according to any one of claims 2-3, 5-7, characterized in that: In the case where both the first gate dielectric layer and the second gate dielectric layer are located outside the trench, the longitudinal section of the trench is U-shaped, or the cross section of the trench is a closed circle; The longitudinal section of the groove is the interface of the groove along the plane where the first direction and the second direction are located, the first direction is the direction from the first pole to the second pole, and the second direction is the direction from the first gate to the second gate; the cross-section of the groove is the cross-section of the groove along the second direction.

9. A chip, characterized in that: A vertical transistor is included, the vertical transistor comprising: A first electrode, a channel, and a second electrode are sequentially stacked on a substrate; the second electrode includes a first sub-electrode and a second sub-electrode opposite to each other, and the channel includes a first channel located between the first electrode and the first sub-electrode and a second channel located between the first electrode and the second sub-electrode; a first gate dielectric layer and a second gate dielectric layer, wherein the first gate dielectric layer contacts the sidewall of the first channel, and the second gate dielectric layer contacts the sidewall of the second channel; A first gate and a second gate are arranged opposite to each other, wherein the first gate is arranged on a side of the first gate dielectric layer away from the first channel, and the second gate is arranged on a side of the second gate dielectric layer away from the second channel.

10. The chip according to claim 9, characterized in that The first channel and the second channel form a trench, and the chip further includes a first insulating layer filled in the trench.

11. The chip according to claim 10, characterized in that The first gate dielectric layer and the second gate dielectric layer are both located outside the trench, the first gate is located on a side of the first gate dielectric layer away from the first channel, and the second gate is located on a side of the second gate dielectric layer away from the second channel; or The first gate dielectric layer and the second gate dielectric layer are both located in the trench, the first gate is disposed between the first gate dielectric layer and the first insulating layer, and the second gate is disposed between the second gate dielectric layer and the second insulating layer.

12. The chip according to claim 10, characterized in that The first channel is disconnected from the second channel.

13. A memory, characterized in that: Comprising a storage array, the storage array comprising the chip according to any one of claims 1 to 8 or any one of claims 9 to 12; The memory array further includes a capacitor electrically connected to the vertical transistor in the chip.

14. The memory according to claim 13, wherein: The memory array comprises the chip according to any one of claims 1 to 8, and the memory array further comprises a word line and a bit line; the gate of the vertical transistor is electrically connected to the word line, the first electrode is electrically connected to the bit line, and the second electrode is electrically connected to the capacitor; or, The memory array includes the chip described in any one of claims 9 to 12, and the memory array also includes a write word line, a read word line, and a bit line; the second gate is electrically connected to the write word line, the second sub-electrode is electrically connected to the first gate, the first sub-electrode is electrically connected to the read word line, and the first electrode is electrically connected to the bit line.

15. An electronic device, characterized in that: It comprises a circuit board and the chip according to any one of claims 1 to 8 or the chip according to any one of claims 8 to 12 or the memory according to any one of claims 13 to 14, wherein the chip or the memory is arranged on the circuit board.

16. A method for preparing a chip, characterized in that: include: forming a first electrode, a first sacrificial layer, a second insulating layer, and a third insulating layer on the substrate; The first sacrificial layer covers a surface of the first electrode facing away from the substrate; In the third direction, the second insulating layer is located between adjacent first electrodes and between adjacent first sacrificial layers; In the second direction, the third insulating layer is located between adjacent first electrodes and covers the sidewalls of the first electrodes; A first gate dielectric layer, a second gate dielectric layer, a first gate, and a second gate are formed on a side of the third insulating layer facing away from the substrate; the first gate dielectric layer is located between the first gate and the second insulating layer, the second gate dielectric layer is located between the second gate and the second insulating layer, and the first gate and the second gate are spaced apart; removing the first sacrificial layer to form a groove to expose the surface of the first electrode facing away from the substrate, and sequentially filling the groove with a channel and a first insulating layer; A second pole is formed on the side of the channel and the first insulating layer facing away from the substrate; wherein the second direction is perpendicular to the third direction, and both the second direction and the third direction are perpendicular to the first direction from the first pole to the second pole.

17. The preparation method according to claim 16, characterized in that The second electrode includes a first sub-electrode and a second sub-electrode arranged opposite to each other, and the channel includes a first channel and a second channel; The first channel is located between the first electrode and the first sub-electrode, and the second channel is located between the first electrode and the second sub-electrode.

18. A method for preparing a chip, characterized in that: include: forming a third sacrificial layer, a fifth insulating layer, and a first electrode on the substrate; wherein the third sacrificial layer has a hollow portion, and the hollow portion penetrates the third sacrificial layer; The first electrode and the fifth insulating layer are filled in the hollow portion, and a vertical distance from a surface of the fifth insulating layer facing away from the substrate to the substrate is greater than a vertical distance from a surface of the three sacrificial layers facing away from the substrate to the substrate; forming a first gate dielectric layer, a second gate dielectric layer, a first gate, and a second gate; wherein the first gate dielectric layer is located between the first gate and the fifth insulating layer, the second gate dielectric layer is located between the second gate and the fifth insulating layer, and the first gate and the second gate are spaced apart; removing the fifth insulating layer and forming a channel in the hollow portion, wherein the channel includes a first channel and a second channel; A second electrode is formed on the side of the channel away from the substrate, and the second electrode includes a first sub-electrode and a second sub-electrode arranged opposite to each other; the first channel is located between the first electrode and the first sub-electrode, and the second channel is located between the first electrode and the second sub-electrode.

19. The preparation method according to claim 18, characterized in that The first channel and the second channel form a groove; Before forming the second electrode on the side of the channel facing away from the substrate, the preparation method further includes: A first insulating layer is filled in the trench.

20. The preparation method according to claim 18 or 19, characterized in that: The step of forming a third sacrificial layer, a fifth insulating layer, and a first electrode on the substrate includes: forming the third sacrificial layer and the fourth insulating layer on the substrate, wherein the hollow portion penetrates the third sacrificial layer and the fourth insulating layer; sequentially filling the first electrode and the fifth insulating layer in the hollow portion; The fourth insulating layer is removed.

21. A method for preparing a chip, characterized in that: include: forming a first electrode and a fourth sacrificial layer on a substrate; wherein the fourth sacrificial layer is located on a side of the first electrode away from the substrate; forming a first gate and a second gate on both sides of the fourth sacrificial layer respectively; A first gate dielectric layer, a second gate dielectric layer, a channel, and a second electrode are formed; the channel is arranged on a side of the first gate dielectric layer away from the first gate and a side of the second gate dielectric layer away from the second gate; the second electrode is located on a side of the channel away from the substrate.

22. The preparation method according to claim 21, characterized in that Forming a first gate dielectric layer, a second gate dielectric layer, and a channel, including: forming a gate dielectric layer and a dummy channel on the first gate and the second gate in sequence; etching back the dummy channel, so that the remaining dummy channel covers the sidewall of the gate dielectric layer; Under the protection of the dummy channel, removing a portion of the gate dielectric layer not covered by the dummy channel to obtain the first gate dielectric layer and the second gate dielectric layer; The dummy channel is removed, and channels are formed on the side of the first gate dielectric layer away from the first gate electrode and on the side of the second gate dielectric layer and the second gate electrode.

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