Memory device and method of forming the same

Abstract

A memory device and a method of forming the same, the memory device comprising: a semiconductor substrate, a plurality of active regions formed in the semiconductor substrate, the plurality of active regions separated by a plurality of first trenches extending in a first direction, a plurality of second trenches, and a plurality of third trenches extending in a second direction; a bit line doping region in the semiconductor substrate at a bottom of the second trenches and at a bottom of the second trenches communicating with the third trenches; a first isolation layer in the first trenches and the third trenches, a surface of the first isolation layer being lower than a surface of the active regions; a gate dielectric layer surrounding the active regions at the surface of the active regions; a metal gate surrounding the active regions at a surface of the gate dielectric layer on a sidewall of the active regions, a top surface of the metal gate being lower than a top surface of the active regions; and a source region at the top surface of the active regions. The memory device of the present application has improved storage density.

Description

Technical Field

[0001] The present application relates to the field of memory, and in particular to a memory device and a method for forming the same. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory device commonly used in computers. It consists of many repeated memory cells. Each memory cell typically includes a capacitor and a transistor. The transistor's gate is connected to a word line, its drain is connected to a bit line, and its source is connected to a capacitor. A voltage signal on the word line controls the transistor's on and off state, allowing it to read data stored in the capacitor through the bit line or write data to the capacitor for storage.

[0003] To increase the integration density of memory structures, transistors in existing dynamic random access memories (DRAMs) typically use a trench-type transistor structure. However, the line width of existing trench-type transistor structures has already reached its limit, preventing further increases in DRAM storage capacity. Therefore, how to further increase DRAM storage capacity and storage density is an urgent problem for those skilled in the art. Summary of the Invention

[0004] In view of this, some embodiments of the present application provide a method for forming a memory device, including:

[0005] A semiconductor substrate is provided, wherein a plurality of active areas are formed in the semiconductor substrate, wherein the plurality of active areas are separated by a plurality of first trenches and second trenches extending along a first direction, and a plurality of third trenches extending along a second direction, wherein the first trenches and the second trenches are connected to the third trenches, the first trenches and the second trenches are spaced apart from each other in the first direction, the depth of the second trenches is less than the depth of the first trenches, and the depth of the third trenches outside the connection with the second trenches is greater than the depth of the second trenches;

[0006] forming a bit line doping region in the semiconductor substrate at the bottom of the second trench and at the bottom of the connection between the second trench and the third trench;

[0007] forming a first isolation layer in the first trench and the third trench, wherein a surface of the first isolation layer is lower than a surface of the active region;

[0008] forming a gate dielectric layer surrounding the active area on a surface of the active area;

[0009] forming a metal gate surrounding the active area on a surface of the gate dielectric layer on a sidewall of the active area, wherein a top surface of the metal gate is lower than a top surface of the active area;

[0010] A source region is formed on a top surface of the active region.

[0011] In some embodiments, the width of the bit line doping region is greater than or equal to the width of the bottom of the second trench.

[0012] In some embodiments, the bit line doping region is formed by a first ion implantation process, and the impurity ions implanted by the first ion implantation process are N-type impurity ions or P-type impurity ions.

[0013] In some embodiments, before performing the first ion implantation process, a protective layer is formed on the sidewalls and bottom surfaces of the first trench, the third trench, and the second trench; after forming the protective layer, a mask layer is formed on the surface of the semiconductor substrate, the mask layer having an opening exposing the bottom of the second trench and the bottom of the semiconductor substrate at the connection point between the second trench and the third trench; using the mask layer as a mask, the first ion implantation process is performed along the opening on the bottom of the second trench and the bottom of the semiconductor substrate at the connection point between the second trench and the third trench, forming a bit line doping region in the bottom of the second trench and the bottom of the semiconductor substrate at the connection point between the second trench and the third trench.

[0014] In some embodiments, the source region is formed by a second ion implantation process.

[0015] In some embodiments, the type of impurity ions doped into the source region is the same as the type of impurity ions doped into the bit line doping region.

[0016] In some embodiments, the metal gate formation process includes: forming a metal layer on the surface of the gate dielectric layer and the surface of the first isolation layer; removing the excess metal layer by maskless etching, and forming a metal gate surrounding the active area on the surface of the gate dielectric layer on the side wall of the active area.

[0017] In some embodiments, after forming the metal gate, a second isolation layer is formed covering the metal gate and filling the first trench, the third trench, and the second trench; and a conductive connection structure extending along the second direction and connecting several metal gates is formed in the second isolation layer in the third trench.

[0018] In some embodiments, the process of forming the metal gate includes: forming a metal layer filling the first trench, the third trench and the second trench on the surface of the gate dielectric layer and the surface of the first isolation layer; etching back the metal layer so that the top surface of the metal layer is lower than the top surface of the active area; after etching back the metal layer, cutting off the metal layer filled in the third trench along the second direction, and forming a metal gate surrounding the active area on the surface of the gate dielectric layer on the side wall of the active area.

[0019] In some embodiments, the further step further includes: forming a capacitor connected to the source region on the surface of the semiconductor substrate.

[0020] In some embodiments, the process of forming a capacitor connected to the source region on the surface of the semiconductor substrate includes: forming a first dielectric layer on the semiconductor substrate; forming a through hole in the first dielectric layer to expose the surface of the source region; forming a contact plug in the through hole; forming a second dielectric layer on the first dielectric layer; forming a capacitor hole in the second dielectric layer to expose the contact plug; and forming a capacitor in the capacitor hole.

[0021] In some embodiments, the plurality of active regions are arranged in rows and columns.

[0022] In some embodiments, the process of forming the plurality of active areas includes: forming a plurality of parallel first mask patterns extending along a first direction on the semiconductor substrate, with first openings and second openings alternately distributed between adjacent first mask patterns, and the width of the first openings being greater than the width of the second openings; forming a plurality of parallel second mask patterns extending along a second direction on the first mask pattern, with sixth openings between adjacent second mask patterns; etching the first mask pattern along the sixth openings using the second mask pattern as a mask, forming a plurality of third openings extending along the second direction in the first mask pattern, and the remaining first mask patterns forming a plurality of separate etching masks; etching the semiconductor substrate using the etching masks as a mask, forming a first trench corresponding to the first opening, a second trench corresponding to the second opening, and a third trench corresponding to the third opening in the semiconductor substrate, wherein an active area is formed between the first trench, the second opening, and the third trench, the first trench and the second trench are connected to the third trench, the depth of the second trench is less than the depth of the first trench, and the depth of the third trench outside the connection with the second trench is greater than the depth of the second trench.

[0023] In some embodiments, the first mask pattern and the second mask pattern are formed by a self-aligned double patterning process.

[0024] In some embodiments, the process of forming the first mask pattern includes: forming a first hard mask layer on the semiconductor substrate; forming a plurality of first strip structures extending along a first direction and arranged in parallel on the first hard mask layer; forming a first sacrificial spacer layer on the sidewalls and top surfaces of the first strip structures and on the surface of the first hard mask layer between the first strip structures; filling the first filling layer between the first strip structures; removing the first sacrificial spacer layer on the sidewall surfaces of the first strip structures to form a fourth opening between the first strip structures and the first filling layer; etching the first hard mask layer along the fourth opening to form a first opening in the first hard mask layer; forming a second filling layer that fills the first opening; forming a plurality of second strip structures extending along the first direction and arranged in parallel on the second filling layer, each of which The second strip structure covers the second filling layer in a first opening and part of the first hard mask layer on both sides of the first opening; a second sacrificial sidewall layer is formed on the sidewall and top surface of the second strip structure and the surface of the first hard mask layer and the first filling layer between the second strip structures; a third filling layer is filled between the second strip structures; the second sacrificial sidewall layer on the sidewall surface of the second strip structure is removed to form a fifth opening between the second strip structure and the second filling layer, and the width of the fifth opening is smaller than the width of the fourth opening; the first hard mask layer between the first openings is etched along the fifth opening to form a second opening in the first hard mask layer, and the width of the second opening is smaller than the width of the first opening. The remaining first hard mask layer between the second opening and the first opening is the first mask pattern.

[0025] Other embodiments of the present invention further provide a storage device, including:

[0026] A semiconductor substrate having a plurality of active areas formed therein, the plurality of active areas being separated by a plurality of first trenches and second trenches extending along a first direction, and a plurality of third trenches extending along a second direction, the first trenches and the second trenches being connected to the third trenches, the first trenches and the second trenches being spaced apart in the first direction, the depth of the second trenches being less than the depth of the first trenches, and the depth of the third trenches outside the connection with the second trenches being greater than the depth of the second trenches;

[0027] a bit line doping region in the semiconductor substrate located at the bottom of the second trench and at the bottom of the connection between the second trench and the third trench;

[0028] a first isolation layer located in the first trench and the third trench, wherein a surface of the first isolation layer is lower than a surface of the active area;

[0029] a gate dielectric layer surrounding the active area and located on a surface of the active area;

[0030] a metal gate surrounding the active area and located on the surface of the gate dielectric layer on the sidewall of the active area, wherein the top surface of the metal gate is lower than the top surface of the active area;

[0031] A source region is located on a top surface of the active region.

[0032] In some embodiments, the width of the bit line doping region is greater than or equal to the width of the bottom of the second trench.

[0033] In some embodiments, the impurity ions doped in the bit line doping region are N-type impurity ions or P-type impurity ions.

[0034] In some embodiments, the type of impurity ions doped into the source region is the same as the type of impurity ions doped into the bit line doping region.

[0035] In some embodiments, the metal gate is located on a surface of the gate dielectric layer on a sidewall of the active region and surrounds the active region, and the metal gate does not completely fill the first trench, the third trench, and the second trench.

[0036] In some embodiments, it also includes a second isolation layer covering the metal gate and filling the first trench, the third trench and the second trench; and a conductive connection structure located in the second isolation layer in the third trench, extending along the second direction and connecting the plurality of metal gates.

[0037] In some embodiments, the metal gate fills the first trench, the third trench, and the second trench, the metal gate is lower than a top surface of the active region, and a portion of the metal gate in the third trench is cut off along the second direction.

[0038] In some embodiments, the invention further includes a capacitor located on the semiconductor substrate and connected to the source region.

[0039] Some of the aforementioned embodiments of the present application provide methods for forming a memory device, providing a semiconductor substrate, forming a plurality of active areas in the semiconductor substrate, wherein the plurality of active areas are separated by a plurality of first trenches and a second trench extending along a first direction, and a plurality of third trenches extending along a second direction, wherein the first trenches and the second trenches are connected to the third trenches, the first trenches and the second trenches are spaced apart in the first direction, the depth of the second trenches is less than the depth of the first trenches, and the depth of the third trenches outside the connection with the second trenches is greater than the depth of the second trenches; forming a bit line doping region in the semiconductor substrate at the bottom of the second trenches and at the bottom of the connection between the second trenches and the third trenches; forming a first isolation layer in the first trenches and the third trenches, wherein the surface of the first isolation layer is lower than the surface of the active area; forming a gate dielectric layer surrounding the active area on the surface of the active area; forming a metal gate surrounding the active area on the surface of the gate dielectric layer on the sidewalls of the active area, wherein the top surface of the metal gate is lower than the top surface of the active area; and forming a source region on the top surface of the active area. Several vertical transistors are formed by the aforementioned method, each of which includes a corresponding active area, a gate dielectric layer located on the sidewall surface of the active area, a bit line doped region in the semiconductor substrate located at the bottom of the second trench, a source region located on the top surface of the active area, and a metal gate surrounding the active area on the surface of the gate dielectric layer located on the sidewalls of the first trench, the second trench, and the third trench. In the aforementioned vertical transistor with a specific structure, since the source and drain regions are located on the upper and lower sides of the active area, the formed channel region is located on the sidewall of the active area, so that the area of ​​the semiconductor substrate occupied by the vertical transistor is smaller, so that the number of vertical transistors formed per unit area can be increased, and accordingly, the number of capacitors connected to the source region of each transistor formed per unit area can also be increased, thereby improving the storage capacity and storage density of the memory. In addition, the vertical transistor with this specific structure can reduce the body effect, reduce the leakage current generated by the subsequently formed capacitor into the substrate, and improve the electrical performance of the memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1-Figure 43 This is a structural diagram of the memory device formation process according to some embodiments of the present application. DETAILED DESCRIPTION

[0041] As mentioned in the background art, how to further improve the storage capacity and storage density of DRAM is an urgent problem to be solved by those skilled in the art.

[0042] Research has found that trench transistors typically include at least one buried wordline in a semiconductor substrate, with a drain region and at least one source region located in the semiconductor substrate on either side of the buried wordline. Such trench transistors occupy a large area of ​​the semiconductor substrate, hindering the integration of DRAMs and limiting their storage capacity and density.

[0043] To this end, the present application provides a novel memory device and a method for forming the same, which can further improve the storage capacity and storage density of the memory device.

[0044] To make the above-mentioned purposes, features, and advantages of this application more clearly understood, the following detailed description of the specific embodiments of this application is provided in conjunction with the accompanying drawings. When describing the embodiments of this application, for ease of explanation, the schematic diagrams may be partially enlarged to a different scale. Furthermore, the schematic diagrams are merely illustrative and should not limit the scope of protection of this application. Furthermore, in actual production, the three-dimensional dimensions of length, width, and depth should be included.

[0045] refer to Figures 19-21 ,in Figure 19 for Figure 21 Schematic diagram of the cross-sectional structure along the cutting line AB, Figure 20 for Figure 21 A schematic diagram of the cross-sectional structure along the cutting line CD direction provides a semiconductor substrate 201, and a plurality of active areas 220 are formed in the semiconductor substrate 201. The plurality of active areas 220 are separated by a plurality of first trenches 217 and second trenches 218 extending along the first direction and a plurality of third trenches 219 extending along the second direction. The first trenches 217 and the second trenches 218 are connected to the third trenches 219. The first trenches 217 and the second trenches 218 are arranged at intervals in the first direction. The depth of the second trench 218 is less than the depth of the first trench 217, and the depth of the area outside the connection between the third trench 219 and the second trench 218 is greater than the depth of the second trench 218.

[0046] The material of the semiconductor substrate 201 can be silicon (Si), germanium (Ge), silicon-germanium (GeSi), or silicon carbide (SiC); it can also be silicon-on-insulator (SOI) or germanium-on-insulator (GOI); or it can be other materials, such as III-V compounds such as gallium arsenide. In this embodiment, the material of the semiconductor substrate 201 is silicon. The semiconductor substrate 201 needs to be doped with certain impurity ions depending on the type of vertical transistor to be formed subsequently. For example, the semiconductor substrate can be doped with a well region. The impurity ions can be N-type impurity ions or P-type impurity ions. The P-type impurity ions can be one or more of boron ions, gallium ions, or indium ions, and the N-type impurity ions can be one or more of phosphorus ions, arsenic ions, or antimony ions.

[0047] The active region 220 is subsequently used to form a channel region, a source region, and a drain region of a vertical transistor. Several active regions 220 are separate.

[0048] In some embodiments, the active regions 220 are arranged in rows and columns (see Figure 21 In other embodiments, the active areas may also be arranged in other ways.

[0049] In some embodiments, the first direction and the second direction are perpendicular to each other, and the angle between them is 90 degrees. In other embodiments, the first direction and the second direction may not be perpendicular, for example, the angle between the first direction and the second direction may be an acute angle.

[0050] In some embodiments, several of the second trenches 218 and the first trenches 217 extend along the first direction and are alternately distributed in the semiconductor substrate 201, and several of the third trenches 219 extend along the second direction. The third trenches 219 are connected with the first trench 217 and the second trench 218 at the intersection. The depth of the second trench 218 is less than the depth of the first trench 217. The depths of the third trenches 219 and the second trenches 218 at the connection point are the same or have a small difference, and the depth of the area outside the connection point of the third trench 219 with the second trench 218 is greater than the depth of the second trench 218.

[0051] In some embodiments, the width of the first trench 217 may be greater than the width of the second trench 218 .

[0052] In some embodiments, the semiconductor substrate 201 can be first etched to form a plurality of first trenches 217 and second trenches 218 extending along a first direction and spaced apart, the depth of the formed first trenches 217 being greater than the depth of the second trenches, and then the semiconductor substrate 201 can be etched to form a plurality of third trenches 219 extending along a second direction, thereby forming a plurality of discrete active areas 220, the depth of the third trenches 219 and the second trenches 218 at the connection point being the same or having a small difference therebetween, and the depth of the third trenches 219 outside the connection point with the second trenches 218 is greater than the depth of the second trenches 218 (when forming the third trenches 219, a mask layer is first formed on the semiconductor substrate 201, and the positions where the second trenches 218 and the first trenches 217 have been formed can be covered by the mask layer and will not be etched, and the mask layer will only expose the surface of the semiconductor substrate that needs to be etched between the first trench and the second trench). In some embodiments, the semiconductor substrate 201 may be etched first to form a plurality of first trenches 217, and then the semiconductor substrate may be etched to form a plurality of second trenches 218, wherein the depth of the second trenches 218 is less than that of the first trenches 217. Finally, the semiconductor substrate 201 may be etched to form a plurality of third trenches 219, thereby forming a plurality of discrete active areas 220. The depths of the third trenches 219 and the second trenches 218 at the connection point are the same or have a small difference therebetween, and the depth of the third trenches 219 outside the connection point with the second trenches 218 is greater than the depth of the second trenches 218. In other embodiments, the first trenches 217, the second trenches 218, and the third trenches 219 may be formed simultaneously by etching the semiconductor substrate 201.

[0053] In this embodiment, the plurality of active regions 220 are formed by a self-aligned double pattern mask process. Figures 1-21 The formation process of the active region 220 is described in detail.

[0054] refer to Figure 1 , forming a first hard mask layer 202 on the semiconductor substrate 201 ; and forming a first material layer 203 on the first hard mask layer 202 .

[0055] The first hard mask layer 202 is subsequently used to form a first mask pattern. In some embodiments, the first hard mask layer 202 can be a single layer or a multi-layer stacked structure, and the material of the first hard mask layer 202 can be one or more of polysilicon, amorphous silicon, amorphous carbon, silicon nitride, silicon oxynitride, silicon oxide, silicon carbonitride, silicon oxycarbide, silicon carbide, and silicon germanium. The first hard mask layer 202 can be formed by atmospheric pressure or low pressure chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), thermal chemical vapor deposition (Thermal CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, sputtering, electroplating, spin coating, other suitable methods and / or combinations thereof. In this embodiment, the material of the first hard mask layer 202 is polysilicon.

[0056] In some embodiments, a first etch stop layer (not shown) may be formed between the first hard mask layer 202 and the semiconductor substrate 201. The first etch stop layer is used to protect the underlying material layer from over-etching when patterning the first hard mask layer. The material of the first etch stop layer is different from that of the first hard mask layer. The material of the first etch stop layer is one or more of silicon nitride, silicon oxynitride, silicon oxide, silicon carbide nitride, and silicon oxycarbide. In this embodiment, the material of the first etch stop layer is silicon oxide.

[0057] The first material layer 203 is subsequently used to form a first strip-shaped structure. In some embodiments, the first material layer 203 may be a single layer or a multi-layer stacked structure. The material of the first material layer 203 may be one or more of polycrystalline silicon, amorphous silicon, amorphous carbon, silicon nitride, silicon oxynitride, silicon oxide, silicon carbonitride, silicon oxycarbide, silicon carbide, and silicon germanium. In this embodiment, the material of the first material layer 203 is amorphous carbon.

[0058] In some embodiments, a second etch-stop layer (not shown) may be formed between the first material layer 203 and the first hard mask layer 202. The second etch-stop layer is used to protect the underlying material layer from over-etching when patterning the first material layer 203. The material of the second etch-stop layer is different from that of the first material layer 203. The material of the second etch-stop layer is one or more of silicon nitride, silicon oxynitride, silicon oxide, silicon carbide, and silicon oxycarbide. In this embodiment, the material of the second etch-stop layer is silicon oxynitride.

[0059] refer to Figure 2 and Figure 3 , Figure 2 for Figure 3 Schematic diagram of the cross-sectional structure along the cutting line AB, the first material layer 203 is patterned (refer to Figure 1), a plurality of first strip structures 204 extending along a first direction and arranged in parallel are formed on the first hard mask layer 202.

[0060] The first strip-shaped structures 204 are in the shape of long strips. The plurality of first strip-shaped structures 204 are separate and parallel to each other, and there is an opening 205 between adjacent first strip-shaped structures 204 .

[0061] In some embodiments, the first material layer 203 is patterned using an anisotropic dry etching process, specifically an anisotropic plasma etching process.

[0062] In some embodiments, before patterning the first material layer 203, a patterned photoresist layer (not shown in the figure) can also be formed on the first material layer 203, and the patterned photoresist layer is used as a mask to etch the first material layer 203 to form a first strip structure 204; and the patterned photoresist layer is removed.

[0063] refer to Figure 4 A first sacrificial spacer layer 206 is formed on the sidewalls and top surfaces of the first strip structures 204 and on the surface of the first hard mask layer 202 between the first strip structures 204 .

[0064] The material of the first sacrificial spacer 206 is different from that of the first strip structures 204. The material of the first sacrificial spacer 206 can be one or more of polysilicon, amorphous silicon, amorphous carbon, silicon nitride, silicon oxynitride, silicon oxide, silicon carbide nitride, silicon oxycarbide, silicon carbide, and silicon germanium. The first sacrificial spacer 206 is formed using a deposition process, including an atomic layer deposition process.

[0065] refer to Figure 5 , a first filling layer 207 is filled between the first strip structures 204 .

[0066] The first filling layer 207 is located on the surface of the first sacrificial spacer layer 206 between the first strip structures 204 , and completely fills the openings between the first strip structures 204 .

[0067] Subsequently, the first sacrificial spacer layer 206 on the sidewall surface of the first strip structure 204 is removed to form a fourth opening between the first strip structure 204 and the first filling layer 207 .

[0068] The material of the first filling layer 207 is different from the material of the first sacrificial spacer 206. In some embodiments, the material of the first filling layer 207 can be one or more of polysilicon, amorphous silicon, amorphous carbon, silicon nitride, silicon oxynitride, silicon oxide, silicon carbonitride, silicon oxycarbide, silicon carbide, silicon germanium, and organic materials. The first filling layer 207 can be formed by atmospheric pressure or low pressure chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), thermal chemical vapor deposition (Thermal CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, sputtering, electroplating, spin coating, other suitable methods and / or combinations thereof.

[0069] In some embodiments, the surface of the formed first filling layer 207 may be flush with the first sacrificial spacer layer 206 on the top surface of the first strip structures 204. Specifically, after forming the first filling material layer covering the first sacrificial spacer layer 206 and filling the remaining openings between the first strip structures 204, the first filling layer above the surface of the first sacrificial spacer layer 206 on the top surface of the first strip structures 204 is removed using a chemical mechanical mask process, leaving the first filling material layer remaining in the openings as the first filling layer 207.

[0070] In some embodiments, a surface of the formed first filling layer may be flush with a top surface of the first strip-shaped structure 204 . Specifically, after forming the first sacrificial spacer layer 206 and the first filling material layer that fills the remaining openings between the first strip structures 204, the first sacrificial spacer layer 206 and the first filling material layer that are higher than the top surface of the first strip structure 204 are removed by a chemical mechanical mask process to expose the top surface of the first strip structure 204, and the remaining first filling material layer in the opening is used as the first filling layer, so that the top surface of the first filling layer formed is flush with the top surface of the first strip structure. Subsequently, after forming the third opening, when etching the first hard mask layer, the etching load effect caused by the different heights of the filling layer and the first strip structure can be reduced, the accuracy of the position and size of the formed first mask pattern is improved, and a good sidewall morphology is maintained, thereby making the position and size of the block mask pattern formed after disconnecting the first mask pattern more accurate and the sidewall morphology is maintained, and finally making the position and size of the active area formed by etching the semiconductor substrate using the block mask pattern as a mask more accurate and the sidewall morphology is maintained.

[0071] refer to Figure 6 The first sacrificial spacer layer on the sidewall surface of the first strip structure 204 is removed to form a fourth opening 208 between the first strip structure 204 and the first filling layer 207 .

[0072] In some embodiments, the first sacrificial spacer layer is removed from the sidewall surface of the first strip structure 204 by an anisotropic dry etching process, including an anisotropic plasma etching process.

[0073] It should be noted that, in some embodiments, when the first sacrificial spacer layer on the sidewall surface of the first strip structure 204 is removed, the first sacrificial spacer layer on the top surface of the first strip structure 204 is also removed.

[0074] refer to Figure 7-Figure 9 , Figure 7 for Figure 9 Schematic diagram of the cross-sectional structure along the cutting line AB, Figure 8 for Figure 9 In the cross-sectional structural diagram along the cutting line CD, the first hard mask layer 202 is etched along the fourth opening to form a plurality of first openings 210 extending along the first direction in the first hard mask layer 202 .

[0075] In some embodiments, etching the first hard mask layer 202 adopts an anisotropic dry etching process, including an anisotropic plasma etching process.

[0076] In the present application, the first opening 210 is formed by the aforementioned self-aligned double patterning process. When the active area is subsequently formed, the width of the first trench corresponding to the first opening between the active areas can be smaller, thereby making the area of ​​the active area larger.

[0077] refer to Figure 10 , Figure 10 exist Figure 7 On the basis of this, a second filling layer filling the first opening is formed; a plurality of second strip structures 211 extending along the first direction and arranged in parallel are formed on the second filling layer, each of the second strip structures 211 covers the second filling layer in a first opening and part of the first hard mask layer 202 on both sides of the first opening, and the second filling layer filled in one opening is exposed between two adjacent second strip structures 211.

[0078] In some embodiments, the second filling layer and the second strip structure 211 are formed in the same process step, and the specific process includes: forming a second material layer on the surface of the first hard mask layer 202, and the second material layer fills the first opening; etching and removing part of the second material layer to form a plurality of second strip structures 211 and a second filling layer that fills the first opening.

[0079] The material of the second filling layer and the second strip structures 211 is different from the material of the first hard mask layer 202. In some embodiments, the material of the second filling layer and the second strip structures 211 can be one or more of polysilicon, amorphous silicon, amorphous carbon, silicon nitride, silicon oxynitride, silicon oxide, silicon carbonitride, silicon oxycarbide, silicon carbide, silicon germanium, and organic materials.

[0080] refer to Figure 11 A second sacrificial spacer layer 212 is formed on the sidewalls and top surfaces of the second strip structures 211 and on the surfaces of the first hard mask layer 202 and the first filling layer between the second strip structures 211 .

[0081] The material of the second sacrificial spacer 212 is different from that of the second strip structures 211. In some embodiments, the material of the second sacrificial spacer 212 can be one or more of polysilicon, amorphous silicon, amorphous carbon, silicon nitride, silicon oxynitride, silicon oxide, silicon carbide nitride, silicon oxycarbide, silicon carbide, and silicon germanium. The second sacrificial spacer 212 is formed using a deposition process, including an atomic layer deposition process.

[0082] refer to Figure 12 , a third filling layer 213 is filled between the second strip structures 211 .

[0083] The third filling layer 213 is located on the second sacrificial spacer layer 212 between the second strip structures 211 and completely fills the space between the second strip structures 211 .

[0084] Subsequently, the second sacrificial spacer layer on the sidewall surface of the second strip structure 204 is removed to form a fifth opening between the second strip structure 211 and the third filling layer 213 .

[0085] The material of the third filling layer 213 is different from the material of the second sacrificial spacer 212. In some embodiments, the material of the third filling layer 213 can be one or more of polysilicon, amorphous silicon, amorphous carbon, silicon nitride, silicon oxynitride, silicon oxide, silicon carbonitride, silicon oxycarbide, silicon carbide, silicon germanium, and organic materials. The third filling layer 213 can be formed by atmospheric pressure or low pressure chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), thermal chemical vapor deposition (Thermal CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, sputtering, electroplating, spin coating, other suitable methods and / or combinations thereof.

[0086] refer to Figure 13-15 , Figure 13 for Figure 15 Schematic diagram of the cross-sectional structure along the cutting line AB, Figure 14 for Figure 15 The cross-sectional structure diagram along the cutting line CD direction is as follows: the second sacrificial sidewall layer 212 on the sidewall surface of the second strip structure 211 is removed (refer to Figure 12 ), a fifth opening is formed between the second strip structure 211 and the second filling layer 213, and the width of the fifth opening is smaller than the width of the fourth opening described above; the first hard mask layer between the first openings 210 is etched along the fifth opening to form a second opening 214 in the first hard mask layer, and the width of the second opening 214 is smaller than the width of the first opening 210. Several second openings 214 and first openings 210 are alternately distributed, and the remaining first hard mask layer between the second opening 214 and the first opening 210 is the first mask pattern 209.

[0087] In some embodiments, etching the first hard mask layer 202 adopts an anisotropic dry etching process, including an anisotropic plasma etching process.

[0088] The formed plurality of first mask patterns 209 are discrete. Specifically, the formed first mask patterns 209 extend along a first direction and are parallel to each other. Adjacent first mask patterns 209 have first openings 210 and second openings 214 that are alternately distributed.

[0089] The width of the formed second opening 214 is smaller than the width of the first opening 210. When the semiconductor substrate 201 is subsequently etched using the same etching process, the etching rate of the semiconductor substrate at the bottom of the second opening 214 is greater than the etching rate of the semiconductor substrate at the bottom of the first opening, thereby making the depth of the corresponding second trench formed in the semiconductor substrate 201 smaller than the depth of the first trench. While making the sizes of the first trench and the second trench smaller, the formation process of the first trench and the second trench can be simplified.

[0090] In the present application, the first mask pattern 209 is formed by the aforementioned self-aligned double patterning process. When the active area is subsequently formed, the widths of the first trench and the second trench between the active areas can be smaller, thereby making the area of ​​the active area larger.

[0091] After forming a plurality of parallel first mask patterns 209 extending along a first direction on the semiconductor substrate 201, with first openings 210 and second openings 214 alternately distributed between adjacent first mask patterns 209, and the width of the first openings 210 being greater than the width of the second openings 214, the method further includes: forming a plurality of parallel second mask patterns extending along a second direction on the first mask pattern 209, with a sixth opening between adjacent second mask patterns, and the second mask patterns also being formed using a self-aligned double patterning process; using the second mask pattern as a mask, etching the first mask pattern along the sixth opening to form a plurality of third openings 215 extending along the second direction in the first mask pattern, and the remaining first mask patterns forming a plurality of discrete etching masks 216 (refer to FIG. 2 ). Figure 16-Figure 18 , Figure 16 for Figure 18 Schematic diagram of the cross-sectional structure along the cutting line AB, Figure 17 for Figure 18 Schematic diagram of the cross-sectional structure along the cutting line CD).

[0092] refer to Figure 19-21 , using the etching mask as a mask, etching the semiconductor substrate 201, forming a first trench 217 corresponding to the first opening, a second trench 218 corresponding to the second opening, and a third trench 219 corresponding to the third opening in the semiconductor substrate 201, an active area 220 is formed between the first trench 217, the second opening 218 and the third trench 219, the first trench 217 and the second trench 218 are connected to the third trench 219, the depth of the second trench 218 is less than the depth of the first trench 217, and the depth of the area outside the connection between the third trench 219 and the second trench 218 is greater than the depth of the second trench 218.

[0093] The semiconductor substrate 201 is etched using an anisotropic dry etching process, including an anisotropic plasma etching process.

[0094] The etching mask can be removed simultaneously during the process of etching the semiconductor substrate, or can be removed by using an additional etching process after the active region is formed.

[0095] refer to Figure 22 and Figure 23 , Figure 22 exist Figure 19 On the basis of Figure 23 exist Figure 20 On the basis of the above, a protection layer 221 is formed on the sidewalls and bottom surfaces of the first trench 217 , the third trench 219 and the second trench 218 .

[0096] The protection layer 221 protects the sidewall surface of the active region 220 during subsequent ion implantation.

[0097] In some embodiments, the material of the protective layer 221 can be silicon oxide. The protective layer 221 is formed by an oxidation process, specifically, furnace tube oxidation.

[0098] refer to Figure 24 and Figure 25 After forming the protection layer 221, a mask layer 222 is formed on the surface of the semiconductor substrate 201, and the mask layer 222 has an opening of the semiconductor substrate 201 that exposes the bottom of the second trench 218 and the bottom of the connection between the second trench 218 and the third trench 219.

[0099] The mask layer 222 may be a single layer or a multi-layer stacked structure (e.g., a double-layer stacked structure). In some embodiments, the mask layer 222 may include a hard mask material layer and a photoresist layer located on a surface of the hard mask material layer. The hard mask material layer may be made of one or more of silicon nitride, silicon oxynitride, silicon oxide, silicon carbide nitride, and silicon oxycarbide.

[0100] refer to Figure 26 and Figure 27 Using the mask layer 222 as a mask, a first ion implantation process is performed along the opening on the bottom of the second trench 218 and the bottom of the semiconductor substrate 201 at the connection point between the second trench 218 and the third trench 219, thereby forming a bit line doping region 223 in the semiconductor substrate 201 at the bottom of the second trench 218 and the bottom of the connection point between the second trench 218 and the third trench 219.

[0101] The bit line doping region 223 is formed by first ion implantation. The type of impurity ions implanted in the bit line doping region 223 is different from the type of impurity ions implanted in the well region of the active region 220. For example, when P-type impurity ions are implanted in the well region of the active region 220, N-type impurity ions are implanted in the bit line doping region 217. When N-type impurity ions are implanted in the well region of the active region 220, P-type impurity ions are implanted in the bit line doping region 217. The impurity ions implanted in the bit line doping region 217 are either N-type impurity ions or P-type impurity ions. The P-type impurity ions are one or more of boron ions, gallium ions, or indium ions. The N-type impurity ions are one or more of phosphorus ions, arsenic ions, or antimony ions.

[0102] In some embodiments, after the first ion implantation, an annealing process is required to activate the doped ions.

[0103] In some embodiments, the width of the formed bit line doping region 223 is greater than or equal to the width of the bottom of the second trench 218, and the bottom of the bit line doping region 223 is flush with or higher than the bottom of the first trench 217 (the bottom of the bit line doping region 223 is closer to the surface of the active area 220 relative to the bottom of the first trench 217).

[0104] The portion of the bit line doping region 223 that contacts the active region 220 serves as the drain region of the vertical transistor. There are two active regions 220 between adjacent first openings 218. The vertical transistors formed in these two active regions 220 share a drain region to improve the integration of the device. Each bit line doping region 223 electrically connects the drain regions of each two adjacent rows of vertical transistors along the first direction to improve the controllability of the vertical transistors, thereby improving the operating capability (reading, writing and deleting) of the subsequently formed memory.

[0105] In some embodiments, reference Figure 28 and 29 After forming the bit line doping region 223 , the protection layer 221 and the mask layer 222 are removed.

[0106] The protection layer 221 and the mask layer 222 are removed by a wet etching process.

[0107] refer to Figure 30 and Figure 31 A first isolation layer 224 is formed in the first trench 217 and the third trench 219 , and a surface of the first isolation layer 224 is lower than a surface of the active region 220 .

[0108] The first isolation layer 224 is used to electrically isolate adjacent active regions and adjacent bit line doped regions 223. In some embodiments, the first isolation layer 224 is made of silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric (K less than 2.8) material, other suitable materials, and / or combinations thereof.

[0109] In some embodiments, the formation process of the first isolation layer 224 includes: forming a first isolation material layer on the surface of the active area 220 and in the first trench 217, the second trench 218 and the third trench 219 through a deposition process; etching back to remove part of the first isolation material layer, and forming a first isolation layer 224 in the first trench 217 and the third trench 219.

[0110] refer to Figure 32 and Figure 33, a gate dielectric layer 225 surrounding the active area 220 is formed on the surface of the active area 220 ; a metal gate 226 surrounding the active area 220 is formed on the surface of the gate dielectric layer 225 on the sidewall of the active area 220 , and the top surface of the metal gate 226 is lower than the top surface of the active area 220 .

[0111] The material of the gate dielectric layer 225 can be silicon oxide or a high-K (dielectric constant) dielectric material, and the high-K dielectric material is one or more of HfO2, TiO2, HfZrO, HfSiNO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3 or BaSrTiO.

[0112] The gate dielectric layer 225 can be formed by oxidation or deposition process.

[0113] In some embodiments, the gate dielectric layer 225 may be formed after removing the protective layer 236. In another embodiment, the protective layer 236 may not be removed, and a gate dielectric layer may be formed directly on the protective layer 236.

[0114] In some embodiments, when forming the gate dielectric layer 225 , the gate dielectric layer 225 may also be formed on the bottom surfaces of the first trench, the second trench, and the third trench and the top surface of the active region.

[0115] The formed metal gate 226 surrounds the sidewalls of each active area, and the top surface of the metal gate 226 is lower than the top surface of the active area 220, which can improve the control ability of the metal gate 220 on the formation of channels in the sidewalls of the active area and improve the performance of forming vertical transistors.

[0116] In some embodiments, the material of the metal gate 226 may be one or more of W, Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, WN, and WSi.

[0117] In some embodiments, the formation process of the metal gate 226 includes: forming a metal layer on the surface of the gate dielectric layer and the surface of the first isolation layer; removing the excess metal layer by maskless etching, and forming a metal gate 226 surrounding the active area on the surface of the gate dielectric layer on the sidewall of the active area. In this process, there is no electrical connection between the metal gates 226 on the sidewalls of adjacent active areas 220, and the metal gates 226 are discrete. Subsequently, a conductive connection structure can be formed to electrically connect the multiple metal gates in each row in the second direction, while the metal gates in adjacent rows remain disconnected, to improve the controllability of the vertical transistor, thereby improving the operational capabilities (read, write, and delete) of the subsequently formed memory.

[0118] In other embodiments, the metal gate formation process includes: forming a metal layer on the surface of the gate dielectric layer and the surface of the first isolation layer to fill the first trench, the third trench, and the second trench; etching back the metal layer so that the top surface of the metal layer is lower than the top surface of the active area; after etching back the metal layer, cutting off the metal layer filling the third trench along the second direction, and forming a metal gate surrounding the active area on the surface of the gate dielectric layer on the sidewall of the active area. In this manner, the metal gates in each row in the second direction are connected together, and the metal gates in adjacent rows in the second direction are disconnected.

[0119] refer to Figure 34 and Figure 35 , a source region 227 is formed on the top surface of the active region 220 .

[0120] The type of impurity ions doped into the source region 227 is the same as the type of impurity ions doped into the bit line doping region 223, and is different from the type of impurity ions doped into the well region of the active region. The source region 227 is formed by a second ion implantation process. The impurity ions implanted (doped) into the source region 227 are N-type impurity ions or P-type impurity ions. The P-type impurity ions are one or more of boron ions, gallium ions, or indium ions. The N-type impurity ions are one or more of phosphorus ions, arsenic ions, or antimony ions.

[0121] In some embodiments, reference Figure 36 and Figure 37 After forming several discrete metal gates 226, a second isolation layer 228 is formed to cover the metal gates 226 and fill the first trench, the third trench and the second trench; a conductive connection structure extending along the second direction and connecting the several metal gates 226 is formed in the second isolation layer 228 in the third trench.

[0122] In some embodiments, when multiple metal gates in each row formed in the second direction are connected together and the metal gates in adjacent rows in the second direction are disconnected, a second isolation layer is directly formed to fill the first trench, the third trench and the second trench without the need to form an additional conductive connection structure.

[0123] In the present application, a number of vertical transistors are formed through the aforementioned process. Each vertical transistor includes a corresponding active area 220, a gate dielectric layer 225 located on the sidewall surface of the active area 220, a bit line doped region 223 located in the semiconductor substrate at the bottom of the second trench, a source region 227 located on the top surface of the active area 220, and a metal gate 226 surrounding the active area 220 on the surface of the gate dielectric layer located on the sidewalls of the first trench, the second trench, and the third trench. In the aforementioned vertical transistor with a specific structure, since the source and drain regions are located on the upper and lower sides of the active area and the channel region is formed on the sidewall of the active area, the area of ​​the semiconductor substrate occupied by the vertical transistor is reduced, thereby increasing the number of vertical transistors formed per unit area. Correspondingly, the number of capacitors connected to the source region of each transistor formed per unit area can also be increased, thereby improving the storage capacity and storage density of the memory. In addition, the vertical transistor with this specific structure can reduce the body effect, reduce the leakage current generated by the subsequently formed capacitor into the substrate, and improve the electrical performance of the memory device.

[0124] In some embodiments, after forming the source region 227 , the method further includes forming a capacitor connected to the source region 227 on the surface of the semiconductor substrate 201 .

[0125] In some embodiments, the process of forming a capacitor connected to the source region on the surface of the semiconductor substrate includes: forming a first dielectric layer on the semiconductor substrate; forming a through hole in the first dielectric layer to expose the surface of the source region; forming a contact plug in the through hole; forming a second dielectric layer on the first dielectric layer; forming a capacitor hole in the second dielectric layer to expose the contact plug; and forming a capacitor in the capacitor hole.

[0126] In some embodiments, the process of forming a capacitor connected to the source region 223 on the surface of the semiconductor substrate 201 includes: referring to Figure 38 and Figure 39 , forming a first dielectric layer 230 on the second isolation layer 228; forming a through hole 231 in the first dielectric layer 230 and the second isolation layer 228 to expose the surface of the source region 227. In some embodiments, the opening of the formed through hole 231 can be widened to both sides to facilitate the subsequent formation of a contact plug and increase the contact area between the top surface of the formed contact plug and the subsequently formed capacitor. Figure 40 and Figure 41 , forming a contact plug 232 in the through hole, wherein the material of the contact plug 232 is metal. Figure 42 and Figure 43, forming a third dielectric layer 233 on the second dielectric layer 230 ; forming a capacitor hole exposing the contact plug 232 in the third dielectric layer 233 ; and forming a capacitor 234 in the capacitor hole.

[0127] In some embodiments, the capacitor 234 includes a lower electrode layer, a dielectric layer on the lower electrode layer, and an upper electrode layer on the dielectric layer.

[0128] In some embodiments, the material of the dielectric layer can be a high-K dielectric material to increase the capacitance value of the capacitor per unit area. The high-K dielectric material includes one of HfO2, TiO2, HfZrO, HfSiNO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3 or BaSrTiO, or a stack formed by two or more of the group consisting of the above materials.

[0129] In some embodiments, the material of the upper electrode layer and the lower electrode layer can be one of tungsten, titanium, nickel, aluminum, platinum, titanium nitride, N-type polysilicon, P-type polysilicon, or a stack formed by two or more of the group consisting of the above materials. It can also include a compound formed by one or two of metal nitrides and metal silicides, such as titanium nitride (Titanium Nitride), titanium silicide (Titanium Silicide), nickel silicide (TiSixNy), etc.

[0130] In some other embodiments, the capacitor may also be formed using an existing double-sided capacitor forming process.

[0131] Some embodiments of the present invention further provide a memory device, referring to Figure 42 and Figure 43 Combined with reference Figures 19-21 ,include:

[0132] A semiconductor substrate 201 having a plurality of active areas 220 formed therein. The plurality of active areas 220 are separated by a plurality of first trenches 217 and second trenches 218 extending along a first direction, and a plurality of third trenches 219 extending along a second direction. The first trenches 217 and the second trenches 218 are connected to the third trenches 219. The first trenches 217 and the second trenches 218 are spaced apart from each other in the first direction. The depth of the second trenches 218 is less than that of the first trenches 217. The depth of the third trenches 219 outside the connection with the second trenches 218 is greater than that of the second trenches 218.

[0133] a bit line doping region 223 in the semiconductor substrate 201 located at the bottom of the second trench 218 and at the bottom of the connection between the second trench 218 and the third trench 219;

[0134] a first isolation layer 224 located in the first trench 217 and the third trench 219 , wherein a surface of the first isolation layer 224 is lower than a surface of the active area 220 ;

[0135] a gate dielectric layer 225 located on a surface of the active area 220 and surrounding the active area 220 ;

[0136] A metal gate 226 surrounding the active area 220 and located on the surface of the gate dielectric layer 225 on the sidewall of the active area 220 , wherein the top surface of the metal gate 226 is lower than the top surface of the active area 220 ;

[0137] A source region 227 is located on the top surface of the active region 220 .

[0138] In some embodiments, the width of the bit line doping region 223 is greater than or equal to the width of the bottom of the second trench 218 .

[0139] In some embodiments, the impurity ions doped into the bit line doping region 223 are N-type impurity ions or P-type impurity ions.

[0140] In some embodiments, the type of impurity ions doped into the source region 227 is the same as the type of impurity ions doped into the bit line doping region 223 .

[0141] In some embodiments, the metal gate 226 is located on a surface of the gate dielectric layer on the sidewall of the active region and surrounds the active region, and the metal gate 226 does not completely fill the first trench, the third trench, and the second trench.

[0142] In some embodiments, the present invention further includes a second isolation layer 228 covering the metal gate 226 and filling the first trench, the third trench, and the second trench; a conductive connection structure 229 (see FIG. 2 ) extending in the second direction and connecting the plurality of metal gates in the second isolation layer 228 in the third trench. Figure 43 ).

[0143] In other embodiments, the metal gate fills the first trench, the third trench, and the second trench, and the metal gate is lower than the top surface of the active area, and the portion of the metal gate located in the third trench is cut off along the second direction.

[0144] In some embodiments, a capacitor 234 is further included and is located on the semiconductor substrate 201 and connected to the source region 227 .

[0145] It should be noted that the limitations or descriptions of the same or similar structures in this embodiment (storage device) and the aforementioned embodiment (storage device formation process) are not repeated in this embodiment. Please refer to the limitations or descriptions of the corresponding parts in the aforementioned embodiment for details.

[0146] Although the present application has been disclosed as above with preferred embodiments, it is not intended to limit the present application. Any person skilled in the art may make possible changes and modifications to the technical solution of the present application by using the methods and technical contents disclosed above without departing from the spirit and scope of the present application. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application shall fall within the scope of protection of the technical solution of the present application.

Claims

1. A method for forming a memory device, characterized in that: include: A semiconductor substrate is provided, wherein a plurality of active areas are formed in the semiconductor substrate, wherein the plurality of active areas are separated by a plurality of first trenches and second trenches extending along a first direction, and a plurality of third trenches extending along a second direction, wherein the first trenches and the second trenches are connected to the third trenches, the first trenches and the second trenches are spaced apart from each other in the first direction, the depth of the second trenches is less than the depth of the first trenches, and the depth of the third trenches outside the connection with the second trenches is greater than the depth of the second trenches; forming a bit line doping region in the semiconductor substrate at the bottom of the second trench and at the bottom of the connection between the second trench and the third trench; forming a first isolation layer in the first trench and the third trench, wherein a surface of the first isolation layer is lower than a surface of the active region; forming a gate dielectric layer surrounding the active area on a surface of the active area; forming a metal gate surrounding the active area on a surface of the gate dielectric layer on a sidewall of the active area, wherein a top surface of the metal gate is lower than a top surface of the active area; forming a source region on a top surface of the active region; The metal gate formation process includes: forming a metal layer on the surface of the gate dielectric layer and the surface of the first isolation layer; removing the excess metal layer by maskless etching, and forming a metal gate surrounding the active area on the surface of the gate dielectric layer on the side wall of the active area.

2. The method for forming a memory device according to claim 1, wherein: The width of the bit line doping region is greater than or equal to the width of the bottom of the second trench.

3. The method for forming a memory device according to claim 2, wherein: The bit line doping region is formed by a first ion implantation process, and the impurity ions implanted by the first ion implantation process are N-type impurity ions or P-type impurity ions.

4. The method for forming a memory device according to claim 3, wherein: Before performing the first ion implantation process, forming a protective layer on the sidewalls and bottom surfaces of the first trench, the third trench, and the second trench; After forming the protection layer, forming a mask layer on the surface of the semiconductor substrate, wherein the mask layer has an opening that exposes the bottom of the second trench and the bottom of the semiconductor substrate at the connection between the second trench and the third trench; Using the mask layer as a mask, a first ion implantation process is performed along the opening on the bottom of the second trench and the bottom of the semiconductor substrate at the connection point between the second trench and the third trench, thereby forming a bit line doping region in the semiconductor substrate at the bottom of the second trench and the bottom of the semiconductor substrate at the connection point between the second trench and the third trench.

5. The method for forming a memory device according to claim 1, wherein: The source region is formed by a second ion implantation process.

6. The method for forming a memory device according to claim 2, wherein: The type of impurity ions doped into the source region is the same as the type of impurity ions doped into the bit line doping region.

7. The method for forming a memory device according to claim 3, wherein: After forming the metal gate, a second isolation layer is formed to cover the metal gate and fill the first trench, the third trench and the second trench; and a conductive connection structure extending along the second direction and connecting the plurality of metal gates is formed in the second isolation layer in the third trench.

8. The method for forming a memory device according to claim 1, wherein: The process of forming the metal gate includes: forming a metal layer filling the first trench, the third trench and the second trench on the surface of the gate dielectric layer and the surface of the first isolation layer; etching back the metal layer so that the top surface of the metal layer is lower than the top surface of the active area; after etching back the metal layer, cutting off the metal layer filled in the third trench along the second direction, and forming a metal gate surrounding the active area on the surface of the gate dielectric layer on the side wall of the active area.

9. The method for forming a memory device according to claim 1, wherein: Also includes: A capacitor connected to the source region is formed on the surface of the semiconductor substrate.

10. The method for forming a memory device according to claim 9, wherein: The process of forming a capacitor connected to the source region on the surface of the semiconductor substrate includes: forming a first dielectric layer on the semiconductor substrate; forming a through hole in the first dielectric layer to expose the surface of the source region; forming a contact plug in the through hole; forming a second dielectric layer on the first dielectric layer; forming a capacitor hole in the second dielectric layer to expose the contact plug; and forming a capacitor in the capacitor hole.

11. The method for forming a memory device according to claim 1, wherein: The active regions are arranged in rows and columns.

12. The method for forming a memory device according to claim 1 or 11, wherein: The formation process of the plurality of active regions includes: forming a plurality of parallel first mask patterns extending in a first direction on the semiconductor substrate, with first and second openings alternately arranged between adjacent first mask patterns, the width of the first opening being greater than the width of the second opening; forming a plurality of parallel second mask patterns extending in a second direction on the first mask pattern, with sixth openings arranged between adjacent second mask patterns; etching the first mask pattern along the sixth opening using the second mask pattern as a mask, forming a plurality of third openings extending in the second direction in the first mask pattern, with the remaining first mask patterns forming a plurality of separate etching masks; etching the semiconductor substrate using the etching masks as a mask, forming a first trench corresponding to the first opening, a second trench corresponding to the second opening, and a third trench corresponding to the third opening in the semiconductor substrate, wherein an active region is formed between the first trench, the second opening, and the third trench, the first trench and the second trench being connected to the third trench, the depth of the second trench being less than the depth of the first trench, and the depth of the third trench outside the connection with the second trench being greater than the depth of the second trench.

13. The method for forming a memory device according to claim 12, wherein: The first mask pattern and the second mask pattern are formed by a self-aligned double patterning process.

14. The method for forming a memory device according to claim 13, wherein: The forming process of the first mask pattern includes: forming a first hard mask layer on the semiconductor substrate; forming a plurality of first strip-shaped structures extending in a first direction and arranged in parallel on the first hard mask layer; forming a first sacrificial spacer layer on the sidewalls and top surfaces of the first strip-shaped structures and on the surface of the first hard mask layer between the first strip-shaped structures; filling the first strip-shaped structures with the first filling layer; removing the first sacrificial spacer layer on the sidewall surfaces of the first strip-shaped structures to form a fourth opening between the first strip-shaped structures and the first filling layer; etching the first hard mask layer along the fourth opening to form a first opening in the first hard mask layer; forming a second filling layer to fill the first opening; forming a plurality of second strip-shaped structures extending in the first direction and arranged in parallel on the second filling layer, each of the second strip-shaped structures having a first sacrificial spacer layer and a first filling layer. The strip-shaped structure covers a second filling layer in a first opening and parts of the first hard mask layer on both sides of the first opening; a second sacrificial sidewall layer is formed on the sidewall and top surface of the second strip structure and on the surface of the first hard mask layer and the first filling layer between the second strip structures; a third filling layer is filled between the second strip structures; the second sacrificial sidewall layer on the sidewall surface of the second strip structure is removed to form a fifth opening between the second strip structure and the second filling layer, and the width of the fifth opening is smaller than the width of the fourth opening; the first hard mask layer between the first openings is etched along the fifth opening to form a second opening in the first hard mask layer, and the width of the second opening is smaller than the width of the first opening, and the remaining first hard mask layer between the second opening and the first opening is the first mask pattern.

15. A memory device, characterized in that: include: A semiconductor substrate having a plurality of active areas formed therein, the plurality of active areas being separated by a plurality of first trenches and second trenches extending along a first direction, and a plurality of third trenches extending along a second direction, the first trenches and the second trenches being connected to the third trenches, the first trenches and the second trenches being spaced apart in the first direction, the depth of the second trenches being less than the depth of the first trenches, and the depth of the third trenches outside the connection with the second trenches being greater than the depth of the second trenches; a bit line doping region in the semiconductor substrate located at the bottom of the second trench and at the bottom of the connection between the second trench and the third trench; a first isolation layer located in the first trench and the third trench, wherein a surface of the first isolation layer is lower than a surface of the active area; a gate dielectric layer surrounding the active area and located on a surface of the active area; a metal gate surrounding the active area and located on the surface of the gate dielectric layer on the sidewall of the active area, wherein the top surface of the metal gate is lower than the top surface of the active area; a source region located on a top surface of the active region; The metal gate fully fills the first trench, the third trench and the second trench, the metal gate is lower than the top surface of the active area, and the portion of the metal gate located in the third trench is cut off along the second direction.

16. The memory device according to claim 15, wherein: The width of the bit line doping region is greater than or equal to the width of the bottom of the second trench.

17. The memory device according to claim 15, wherein: The impurity ions doped in the bit line doping region are N-type impurity ions or P-type impurity ions.

18. The memory device according to claim 16, wherein: The type of impurity ions doped into the source region is the same as the type of impurity ions doped into the bit line doping region.

19. The memory device according to claim 15, wherein The metal gate is located on a surface of a gate dielectric layer on a sidewall of the active area and surrounds the active area. The metal gate does not completely fill the first trench, the third trench, and the second trench.

20. The memory device according to claim 19, wherein It also includes a second isolation layer covering the metal gate and filling the first trench, the third trench and the second trench; and a conductive connection structure located in the second isolation layer in the third trench, extending along the second direction and connecting the plurality of metal gates.

21. The memory device according to claim 15, wherein The invention further includes a capacitor located on the semiconductor substrate and connected to the source region.

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