Semiconductor structure, memory system and manufacturing method of semiconductor structure

Abstract

The embodiment of the invention provides a semiconductor structure, a memory, a memory system and a manufacturing method of the semiconductor structure. The semiconductor structure comprises a stacked structure which comprises a first stacked part and a second stacked part on a plane perpendicular to the stacking direction of the stacked structure, and the first stacked part comprises first dielectric layers and gate layers which are alternately stacked; and a contact structure extending in the stacking direction in the second stacking portion; each of the gate layer and the contact structure comprises a high dielectric constant layer and a conductive layer which are arranged from outside to inside.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a semiconductor structure, a memory, a memory system, and a method for manufacturing a semiconductor structure. Background Art

[0002] In the manufacturing process of semiconductor structures, people hope to simplify the process flow and reduce manufacturing costs, and pursue higher product yields. Summary of the Invention

[0003] The present application provides a semiconductor structure, a memory, a memory system, and a method for manufacturing a semiconductor structure that can at least partially solve the above-mentioned problems or other problems in the art.

[0004] In a first aspect, some embodiments of the present application provide a semiconductor structure. The semiconductor structure comprises: a stacked structure comprising a first stack portion and a second stack portion on a plane perpendicular to the stacking direction, the first stack portion comprising alternating first dielectric layers and gate layers; and a contact structure extending along the stacking direction within the second stack portion; wherein both the gate layer and the contact structure comprise a high-k dielectric constant layer and a conductive layer arranged from the outside inward.

[0005] In an exemplary embodiment, the contact structure includes a first contact portion extending in a stacking direction in the second stacking portion; and a second contact portion connected to the first contact portion and extending on a plane perpendicular to the stacking direction.

[0006] In an exemplary embodiment, the gate layer includes a first high dielectric constant layer and a first conductive layer from the outside to the inside, the first contact portion includes a second high dielectric constant layer and a second conductive layer from the outside to the inside, and the second contact portion includes a third high dielectric constant layer and a third conductive layer from the outside to the inside.

[0007] In an exemplary embodiment, the materials of the first high dielectric constant layer, the second high dielectric constant layer, and the third high dielectric constant layer are the same.

[0008] In an exemplary embodiment, the gate layer further includes a first adhesive layer located between the first high dielectric constant layer and the first conductive layer, the first contact portion further includes a second adhesive layer located between the second high dielectric constant layer and the second conductive layer, and the second contact portion further includes a third adhesive layer located between the third high dielectric constant layer and the third conductive layer.

[0009] In an exemplary embodiment, the materials of the first adhesive layer, the second adhesive layer, and the third adhesive layer are the same.

[0010] In an exemplary embodiment, the second high dielectric constant layer and the third high dielectric constant layer are connected, and the second adhesive layer and the third adhesive layer are connected.

[0011] In an exemplary embodiment, the contact structure further includes an insulating structure located inside the first contact portion.

[0012] In an exemplary embodiment, the semiconductor structure further includes at least one contact connection structure connected to an end portion of the first contact portion remote from the second contact portion.

[0013] In an exemplary embodiment, the contact structure further includes: a third contact portion located on a side of the insulation structure away from the second contact portion and connected to the first contact portion.

[0014] In an exemplary embodiment, the semiconductor structure further includes at least one contact connection structure connected to the third contact portion.

[0015] In an exemplary embodiment, the second stack portion includes first and second dielectric layers alternately stacked, and the second contact portion is located between adjacent first dielectric layers and connected to the gate layer.

[0016] In a second aspect, some embodiments of the present application provide a memory. The memory includes:

[0017] In a third aspect, some embodiments of the present application provide a memory system, comprising: a memory as described in any of the above embodiments; and a controller coupled to the memory and configured to control the memory to store data.

[0018] In a fourth aspect, some embodiments of the present application provide a method for manufacturing a semiconductor structure. The method includes: forming an initial stack structure comprising alternating first and second dielectric layers, the initial stack structure having a first region and a second region; forming a contact hole extending along a stacking direction of the initial stack structure, with at least a portion of the contact hole located within the second region; and replacing the second dielectric layer in the initial stack structure located within the first region with a gate layer, and forming a contact structure within the contact hole; wherein both the gate layer and the contact structure include a high dielectric constant layer and a conductive layer arranged from the outside inward.

[0019] In an exemplary embodiment, forming a contact hole extending along the stacking direction of the stacking structure includes: forming an initial contact hole extending along the stacking direction in the initial stacking structure; using the initial contact hole to remove a portion of a second dielectric layer located at the bottom thereof to form an epitaxial contact hole, the initial contact hole and the epitaxial contact hole serving as contact holes; wherein, forming a contact structure in the contact hole includes: forming a first contact portion of the contact structure on the side wall of the initial contact hole, and forming a second contact portion of the contact structure in the epitaxial contact hole, wherein materials of the first contact portion and the second contact portion both include a high dielectric constant material and a conductive material.

[0020] In an exemplary embodiment, the manufacturing method further includes: forming a gate line gap that penetrates the initial stacking structure; wherein, replacing the second dielectric layer in the initial stacking structure located in the first region with the gate layer includes: using the gate line gap to replace the second dielectric layer in the initial stacking structure located in the first region with the gate layer; and wherein, the manufacturing method further includes: removing a portion of the gate layer near the gate line gap.

[0021] In an exemplary embodiment, before removing a portion of the gate layer close to the gate line gap, the manufacturing method further includes: forming an insulating structure inside the first contact portion.

[0022] In an exemplary embodiment, before removing a portion of the gate layer near the gate line gap, the manufacturing method further includes: forming a mask layer exposing the gate line gap; wherein the mask layer is removed during the process of removing the portion of the gate layer near the gate line gap.

[0023] In an exemplary embodiment, the manufacturing method further includes forming at least one contact connection structure connected to an end portion of the first contact portion away from the second contact portion.

[0024] In an exemplary embodiment, before removing a portion of the gate layer near the gate line gap, the manufacturing method further includes: forming a mask layer exposing the gate line gap, wherein the mask layer is a conductive material; wherein, during the process of removing the portion of the gate layer near the gate line gap, the mask layer is retained; and removing a portion of the mask layer so that the retained mask layer covers the surface of the insulating structure and is connected to the first contact portion, and serves as the third contact portion of the contact structure.

[0025] In an exemplary embodiment, the manufacturing method further includes forming at least one contact connection structure connected to the third contact portion on a side away from the insulating structure.

[0026] In an exemplary embodiment, replacing the second dielectric layer in the initial stacking structure located in the first region with the gate layer includes: removing the second dielectric layer in the initial stacking structure located in the first region and forming a sacrificial gap; sequentially forming a first high dielectric constant layer and a first conductive layer in the sacrificial gap to form a gate layer; wherein, forming a first contact portion of the contact structure on the sidewall of the initial contact hole and forming a second contact portion of the contact structure in the epitaxial contact hole includes: sequentially forming a second high dielectric constant layer and a second conductive layer on the sidewall of the initial contact hole, and sequentially forming a third high dielectric constant layer and a third conductive layer in the epitaxial contact hole.

[0027] In an exemplary embodiment, the first high dielectric constant layer, the second high dielectric constant layer, and the third high dielectric constant layer are formed in the same thin film deposition process, and the first conductive layer, the second conductive layer, and the third conductive layer are formed in the same thin film deposition process. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings, in which:

[0029] Figure 1A is a schematic cross-sectional view of a semiconductor structure provided in an embodiment of the present application;

[0030] Figure 1B is a schematic top view of a semiconductor structure provided by an embodiment of the present application;

[0031] Figure 2 is a schematic cross-sectional view of a semiconductor structure provided by another embodiment of the present application;

[0032] Figure 3 is a schematic flow chart of a method for manufacturing a semiconductor structure provided in an embodiment of the present application;

[0033] Figures 4A to 21 is a schematic structural diagram of a semiconductor structure provided in an embodiment of the present application during the manufacturing process;

[0034] Figures 22 to 29 is a schematic cross-sectional view of a semiconductor structure during the manufacturing process provided by another embodiment of the present application;

[0035] Figure 30 is a schematic block diagram of a memory provided in an embodiment of the present application;

[0036] Figure 31 is a schematic block diagram of a system having a memory system provided by an embodiment of the present application; and

[0037] Figure 32A and Figure 32B This is a schematic block diagram of a memory system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely descriptions of exemplary embodiments of the present application and are not intended to limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0039] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another, and do not represent any limitation on the features, and especially do not represent any order of precedence. Therefore, without departing from the teachings of this application, the first stacking part discussed in this application can also be referred to as the second stacking part, and vice versa.

[0040] In the accompanying drawings, the thickness, size, and shape of components have been slightly adjusted for ease of illustration. The accompanying drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used to indicate approximations, not degrees, and are intended to account for the inherent variations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0041] It should also be understood that expressions such as "comprises," "including," "having," "includes," and / or "comprising" are open rather than closed expressions in this specification, indicating the presence of the stated features, elements, and / or components, but do not exclude the presence of one or more other features, elements, components, and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application." And, the term "exemplary" is intended to refer to an example or illustration.

[0042] Unless otherwise defined, all words used herein (including engineering terms and scientific and technological terms) have the same meaning as commonly understood by those skilled in the art to which this application belongs. It should also be understood that, unless otherwise specified in this application, words defined in commonly used dictionaries should be interpreted as having the same meaning as they do in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0043] It should be noted that, unless there is a conflict, the embodiments and features of the embodiments in this application may be combined with each other. In addition, unless explicitly limited or inconsistent with the context, the specific steps included in the method described in this application are not necessarily limited to the order described, but may be performed in any order or in parallel.

[0044] In addition, in the present application, when “connected” or “coupled” is used, it may indicate direct contact or indirect contact between corresponding components, unless otherwise clearly defined or inferred from the context.

[0045] The present application will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

[0046] Some embodiments of the present application provide a semiconductor structure. Figure 1A It is a cross-sectional schematic diagram of the semiconductor structure provided in an embodiment of the present application. Figure 1B is a schematic top view of a semiconductor structure provided by an embodiment of the present application. For example, Figure 1A The semiconductor structure shown is along Figure 1B Schematic cross-sectional views taken along lines AA' and BB' are shown.

[0047] It should be noted that the x-direction, y-direction, and z-direction in the various figures below illustrate the spatial relationships between components in a semiconductor structure. For example, the z-direction is the stacking direction of a stacked structure (or an initial stacked structure), and the x-direction and y-direction are two directions that intersect (e.g., are perpendicular to) each other on a plane that intersects (e.g., is perpendicular to) the stacking direction. The same concept will be used throughout this application to describe the spatial relationships between components in a semiconductor structure.

[0048] like Figure 1A and Figure 1B As shown, semiconductor structure 100 includes a stacked structure 111 and a contact structure 116. Stacked structure 111 includes a first stack portion 112 and a second stack portion 113 on a plane perpendicular to the z-direction. First stack portion 112 includes alternating first dielectric layers 114 and gate layers 115. Contact structure 116 extends along the z-direction within second stack portion 113. Gate layer 115 and contact structure 116 each include high-k dielectric constant layers 117, 121, and 124 and conductive layers 118, 122, and 125 arranged from the outside inward.

[0049] In this embodiment, the gate layer 115 and the contact structure 116 both include high dielectric constant layers 117, 121, 124 and conductive layers 118, 122, 125 arranged from the outside to the inside, which is beneficial to reducing the process complexity of the contact structure 116, improving manufacturing efficiency and reducing manufacturing costs, and is also beneficial to improving the yield of the semiconductor structure 100.

[0050] In some embodiments, as Figure 1B As shown, on a plane perpendicular to the z-direction, the first stacking portion 112 and the second stacking portion 113 in the stacking structure 111 are arranged adjacent to each other. For example, on a plane perpendicular to the z-direction, the first stacking portion 112 surrounds the second stacking portion 113 on both sides in the y-direction and on one side in the x-direction.

[0051] In some embodiments, as Figure 1AAs shown, the first dielectric layers 114 and gate layers 115 in the first stack portion 112 are alternately arranged along the z-direction. For example, each first dielectric layer 114 and each gate layer 115 in the first stack portion 112 extends laterally along the x-direction and the y-direction. The material of the first dielectric layer 114 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material. For example, the material of the first dielectric layer 114 includes silicon oxide (SiO2). The gate layer 115 includes a first high dielectric constant layer 117 and a first conductive layer 118 from the outside to the inside. The material of the first high dielectric constant layer 117 may include, but is not limited to, aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O3), and hafnium oxide (HfO2). The material of the first conductive layer 118 may include one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), or any other suitable metal material. For example, the material of the first conductive layer 118 includes tungsten (W). Alternatively, the material of the first conductive layer 118 may include a semiconductor conductive material such as polycrystalline silicon (poly-Si) or amorphous silicon (α-Si).

[0052] In some embodiments, as Figure 1A As shown, the second stack portion 113 includes alternately stacked first dielectric layers 114 and second dielectric layers 126. The first dielectric layers 114 and second dielectric layers 126 in the second stack portion 113 are alternately arranged along the z direction. For example, each first dielectric layer 114 and each second dielectric layer 126 in the second stack portion 113 extend laterally along the x direction and the y direction. For another example, each first dielectric layer 114 in the first stack portion 112 and each first dielectric layer 114 in the second stack portion 113 are respectively connected (for example, continuously extended) and are an integral structure. Each gate layer 115 in the first stack portion 112 and each second dielectric layer 126 in the second stack portion 113 are respectively connected. The material of the second dielectric layer 126 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material. The material of the second dielectric layer 126 may be different from the material of the first dielectric layer 114. For example, the material of the second dielectric layer 126 may include silicon nitride (Si3N4).

[0053] In some embodiments, the semiconductor structure 100 may further include a selection stack structure 130. The selection stack structure 130 may be located on one side (e.g., the surface) of a portion of the first stack portion 112 in the z direction. The selection stack structure 130 may include a first insulating layer 128, a selection gate layer 127, and a second insulating layer 129 sequentially arranged in the z direction. In other words, the first insulating layer 128 and the second insulating layer 129 are located on opposite surfaces of the selection gate layer 127 in the z direction. The materials of the first insulating layer 128 and the second insulating layer 129 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material. For example, the material of the first insulating layer 128 may include silicon oxide (SiO2). The material of the second insulating layer 129 may include silicon nitride (Si3N4). When the material of the first insulating layer 128 and the material of the first dielectric layer 114 are the same, there is no obvious interface between the two.

[0054] In some embodiments, the semiconductor structure 100 may further include a third insulating layer 131. The third insulating layer 131 may be located on one side (e.g., the surface) of the second stack portion 113 and a portion of the first stack portion 112 in the z direction. For example, the size of the stack structure 130 in the z direction may be the same as the size of the third insulating layer 131 in the z direction. The material of the third insulating layer 131 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material. For example, the material of the third insulating layer 131 includes silicon oxide (SiO2).

[0055] In some embodiments, the semiconductor structure 100 may further include a gate line isolation structure 138 extending (e.g., continuously extending) along the x-direction. For example, in the z-direction, a portion of the gate line isolation structure 138 penetrates the selection stack structure 130 and the first stack portion 112, and another portion of the gate line isolation structure 138 penetrates the third insulating layer 131 and the first stack portion 112. The material of the portion of the gate line isolation structure 138 that contacts the selection stack structure 130 and the first stack portion 112 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y) or any other suitable insulating material. As an example, the gate line isolation structure 138 may include a polysilicon body 1382 and an isolation insulating layer 1381. The isolation insulating layer 1381 may be located on the sidewalls of the polysilicon body 1382 and on the end surface away from the select stack structure 130, and may contact the select stack structure 130 and the first stack portion 112. The material of the isolation insulating layer 1381 may include silicon oxide (SiO2), and the material of the polysilicon body 1382 may include polycrystalline silicon (poly-Si). The gate line isolation structure 138 uses the above material combination to help optimize structural stress.

[0056] In some embodiments, the semiconductor structure 100 may further include a first protective layer 139 and a selection gate cut structure 140. The first protective layer 139 is located on the sidewall of the portion of the gate isolation structure 138 that passes through the selection gate layer 127 and the second insulating layer 129. The material of the first protective layer 139 may be different from the material of the second insulating layer 129. For example, in the case where the material of the second insulating layer 129 includes silicon nitride (Si3N4), the material of the first protective layer 139 may include silicon oxide (SiO2). The first protective layer 139 can prevent the second insulating layer 129 from being damaged, thereby improving the yield of the semiconductor structure 100. The selection gate cut structure 140 may pass through the selection gate layer 127 and extend along the x-direction (for example, continue to extend). The material of the selection gate cut structure 140 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material. The selection gate cut structure 140 can be used to electrically isolate the selection gate layer 127 located on both sides thereof.

[0057] In some embodiments, the semiconductor structure 100 may further include a channel structure 132 extending through the first stack portion 112 of the stack structure 111. The channel structure 132 may be a substantially columnar structure. For example, on a plane perpendicular to the z-direction, a plurality of channel structures 132 may be spaced apart along the x-direction and the y-direction. The channel structure 132 may include a blocking layer 1321, a charge trapping layer 1322, a tunneling layer 1323, and a first channel layer 1324, arranged sequentially from the outside to the inside. For example, the blocking layer 1321, the charge trapping layer 1322, the tunneling layer 1323, and the first channel layer 1324 may all extend through the first stack portion 112 of the stack structure 111, and the first channel layer 1324 may protrude from the first stack portion 112 of the stack structure 111. The blocking layer 1321, the charge trapping layer 1322, and the tunneling layer 1323 may be referred to as functional layers. For example, the materials of the blocking layer 1321, the charge trapping layer 1322, and the tunneling layer 1323 may include silicon oxide (SiO2), silicon nitride (Si3O4), and silicon oxide (SiO2) in sequence. The material of the first channel layer 1324 may include amorphous silicon (α-Si), polycrystalline silicon (poly-Si), or any other suitable semiconductor material. For example, the portion of the channel structure 132 surrounded by a gate layer 115 and a portion of the gate layer 115 constitute a memory cell. Multiple memory cells are arranged in series along the extension direction of the channel structure 132 (e.g., the z-direction) to form a memory string and share the first channel layer 1324.

[0058] In some embodiments, the semiconductor structure 100 may further include a selection channel structure 133 that penetrates the selection stack structure 130. The selection channel structure 133 may be a substantially columnar structure. The selection channel structure 133 may include a gate dielectric layer 1331 and a second channel layer 1332 sequentially arranged from the outside to the inside. For example, on a plane perpendicular to the z direction, a plurality of selection channel structures 133 may be spaced apart along the x direction and the y direction, and respectively connected to a plurality of channel structures 132. For example, the second channel layer 1332 in the selection channel structure 133 is connected to the first channel layer 1324 in the channel structure 132. The material of the gate dielectric layer 1331 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y), high dielectric constant material, or any other suitable insulating material. Among them, the high dielectric constant material may include, but is not limited to, aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O3), and hafnium oxide (HfO2). The material of the second channel layer 1332 may include amorphous silicon (α-Si), polycrystalline silicon (poly-Si), or any other suitable semiconductor material. For example, the portion of the select channel structure 133 surrounded by the select gate layer 127 and a portion of the select gate layer 127 constitute a select transistor. The select transistor may be connected to a memory string.

[0059] In some embodiments, the contact structure 116 may include a first contact portion 120 and a second contact portion 123. The first contact portion 120 extends along the z-direction in the second stack portion 113 of the stack structure 111. For example, the outer profile of the first contact portion 120 may be approximately a columnar structure. For another example, the dimension (e.g., outer diameter) of the first contact portion 120 on a plane perpendicular to the z-direction decreases along the negative z-direction. The second contact portion 123 is connected to the first contact portion 120 and extends on a plane perpendicular to the z-direction. For example, the outer profile of the second contact portion 123 may be approximately a disk-shaped structure. For another example, the second contact portion 123 may be located between adjacent first dielectric layers 114 and connected to (e.g., in contact with) the gate layer 115. Optionally, the second contact portion 123 extends laterally into the first stack portion 112 along the x-direction and y-direction to connect to (e.g., in contact with) the gate layer 115.

[0060] In some embodiments, the first contact portion 120 includes, from the outside inward, a second high-k dielectric constant layer 121 and a second conductive layer 122. For example, the second high-k dielectric constant layer 121 may be a generally tubular structure with both ends open. The second conductive layer 122 may also be a generally tubular structure with both ends open. The second conductive layer 122 may be disposed inside the second high-k dielectric constant layer 121. The second contact portion 123 may include, from the outside inward, a third high-k dielectric constant layer 124 and a third conductive layer 125. For example, the third conductive layer 125 may be a generally disk-shaped structure. The third high-k dielectric constant layer 124 surrounds the outside of the third conductive layer 125.

[0061] In some embodiments, the materials of the second high dielectric constant layer 121 and the third high dielectric constant layer 124 may include, but are not limited to, aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O3), and hafnium oxide (HfO2). The materials of the second conductive layer 122 and the third conductive layer 125 may include one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), or any other appropriate metal materials. As another option, the materials of the second conductive layer 122 and the third conductive layer 125 may include semiconductor conductive materials such as polycrystalline silicon (poly-Si) or amorphous silicon (α-Si). For example, the materials of the first high dielectric constant layer 117, the second high dielectric constant layer 121, and the third high dielectric constant layer 124 are the same. Optionally, the materials of the second conductive layer 122 and the third conductive layer 125 are the same. The materials of the second conductive layer 122 and the third conductive layer 125 both include tungsten (W).

[0062] In some embodiments, the second high dielectric constant layer 121 and the third high dielectric constant layer 124 are connected (e.g., in contact). If the second high dielectric constant layer 121 and the third high dielectric constant layer 124 are made of the same material, the two layers may be an integral structure without a distinct interface. Alternatively, the second conductive layer 122 and the third conductive layer 125 are connected (e.g., in contact). If the second conductive layer 122 and the third conductive layer 125 are made of the same material, the two layers may be an integral structure without a distinct interface.

[0063] In some embodiments, gate layer 115 may further include a first adhesion layer 119 positioned between first high-k dielectric layer 117 and first conductive layer 118. First contact portion 120 may further include a second adhesion layer 166 positioned between second high-k dielectric layer 121 and second conductive layer 122. Second contact portion 123 may further include a third adhesion layer 167 positioned between third high-k dielectric layer 124 and third conductive layer 125. First adhesion layer 119, second adhesion layer 166, and third adhesion layer 167 may improve the bonding performance between the high-k dielectric layer and the conductive layer. Materials for first adhesion layer 119, second adhesion layer 166, and third adhesion layer 167 may include, but are not limited to, titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). For example, first adhesion layer 119, second adhesion layer 166, and third adhesion layer 167 may be made of the same material.

[0064] In some embodiments, the second adhesive layer 166 in the first contact portion 120 is connected (e.g., in contact) with the third adhesive layer 167 in the second contact portion 123. If the second adhesive layer 166 and the third adhesive layer 167 are made of the same material, they can be an integral structure without a distinct interface.

[0065] In some embodiments, the contact structure 116 may further include an insulating structure 134 located inside the first contact portion 120. For example, the insulating structure 134 may be a substantially columnar structure, and the insulating structure 134 may be located inside the first contact portion 120 (e.g., the second high dielectric constant layer 121). In other words, the first contact portion 120 (e.g., the second high dielectric constant layer 121) surrounds the outside of the insulating structure 134. Optionally, an air gap may be provided inside the insulating structure 134. The material of the insulating structure 134 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material. For example, the material of the insulating structure 134 may include silicon oxide (SiO2).

[0066] In some embodiments, the semiconductor structure 100 further includes at least one (for example, two) contact connection structures 135. The contact connection structure 135 is connected to the end of the first contact portion 120 away from the second contact portion 123. For example, the semiconductor structure 100 may further include a fourth insulating layer 136 located on the end surface of the first contact portion 120 and the insulating structure 134 away from the second contact portion 123. The contact connection structure 135 may penetrate the fourth insulating layer 136 to the first contact portion 120. The contact connection structure 135 can be used to lead the contact structure 116 out from the z direction. It should be noted that the number and arrangement of the contact connection structures 135 are not specifically limited in this application. For example, on a plane perpendicular to the z direction, a plurality of contact connection structures 135 may be arranged in an annular pattern.

[0067] In some embodiments, the semiconductor structure 100 may further include a second protective layer 137. The second protective layer 137 may be located outside the first contact portion 120. For example, the second protective layer 137 may surround the first contact portion 120. The material of the second protective layer 137 may be different from the material of the second dielectric layer 126. For example, if the material of the second dielectric layer 126 includes silicon nitride (Si3N4), the material of the second protective layer 137 may include silicon oxide (SiO2). The second protective layer 137 can be used to prevent damage to the second dielectric layer 126, thereby improving the yield of the semiconductor structure 100.

[0068] In some embodiments, the semiconductor structure 100 may further include a semiconductor layer 141. The semiconductor layer 141 may be located on a side of the stacked structure 111 away from the selected stacked structure 130. The semiconductor layer 141 may extend laterally along the x-direction and the y-direction and may be connected to (e.g., in contact with) the first channel layer 1324 in the channel structure 132. The material of the semiconductor layer 141 may include one or more of polycrystalline silicon (poly-Si), amorphous silicon (α-Si), or any other suitable semiconductor material. When the semiconductor layer 141 and the first channel layer 1324 are made of the same material, there is no distinct interface between the two.

[0069] Figure 2 is a cross-sectional schematic diagram of a semiconductor structure provided by another embodiment of the present application. For example, Figure 2 The semiconductor structure 200 is shown along Figure 1B The cross-sectional view taken along line AA' and line BB' is shown. For the purpose of brevity, the same contents as those in the previous embodiment will not be repeated herein.

[0070] like Figure 2 As shown, semiconductor structure 200 may include a stack structure 211 and a contact structure 216. Stack structure 211 includes a first stack portion 212 and a second stack portion 213 on a plane perpendicular to the z-direction. First stack portion 212 includes alternating first dielectric layers 214 and gate layers 215. Contact structure 216 extends along the z-direction within second stack portion 213. Gate layer 215 and contact structure 216 each include high-k dielectric constant layers 217, 221, and 224 and conductive layers 218, 222, and 225 arranged from the outside inward.

[0071] In some embodiments, the contact structure 216 may include a first contact portion 220, a second contact portion 223, an insulating structure 234, and a third contact portion 242. The third contact portion 242 may be located on a side of the insulating structure 234 away from the second contact portion 223 and connected to the first contact portion 220. For example, the third contact portion 242 may be a generally disc-shaped structure. The third contact portion 242 covers the end surface of the first contact portion 220 away from the second contact portion 223 and the surface of the insulating structure 234 away from the second contact portion 223. In other words, the insulating structure 234 may be located in the space enclosed by the first contact portion 220, the second contact portion 223, and the third contact portion 242.

[0072] In some embodiments, the semiconductor structure 200 further includes at least one (e.g., two) contact connection structures 235. The contact connection structure 235 is connected to the third contact portion 242. For example, the semiconductor structure 200 may further include a fourth insulating layer 236 covering the third contact portion 242. The contact connection structure 235 may penetrate the fourth insulating layer 236 to the third contact portion 242. The contact connection structure 235 may be used to lead the contact structure 216 out in the z-direction. Providing the third contact portion 242 in the contact structure 216 helps reduce the process difficulty of the contact connection structure 235, increase the process window of the contact connection structure 235, and improve the electrical connection performance between the contact connection structure 235 and the contact structure 216.

[0073] Some embodiments of the present application also provide a method for manufacturing a semiconductor structure. Figure 3 FIG. 1 is a flow chart of a method for manufacturing a semiconductor structure provided in an embodiment of the present application. Figure 3 As shown, a method 300 for manufacturing a semiconductor structure (hereinafter referred to as manufacturing method 300 ) includes the following steps.

[0074] S310 , forming an initial stack structure including alternately stacked first dielectric layers and second dielectric layers, wherein the initial stack structure has a first region and a second region.

[0075] S320 , forming contact holes extending along the stacking direction of the initial stacking structure, wherein at least a portion of the contact holes is located in the second region.

[0076] S330, replacing the second dielectric layer in the initial stacked structure in the first region with a gate layer, and forming a contact structure in the contact hole, wherein both the gate layer and the contact structure include a high dielectric constant layer and a conductive layer arranged from the outside to the inside.

[0077] According to the manufacturing method of the semiconductor structure provided in the above embodiment, by forming a gate layer and a contact structure both including a high dielectric constant layer and a conductive layer arranged from the outside to the inside, it is beneficial to reduce the process complexity of the contact structure, improve manufacturing efficiency and reduce manufacturing costs, and also help improve the yield of the semiconductor structure.

[0078] Figures 4A to 21 This is a schematic diagram of the structure of the semiconductor structure provided in the embodiment of the present application during the manufacturing process. Figures 4A to 21 The manufacturing method 300 including steps S310 to S330 is exemplarily described.

[0079] S310

[0080] Figure 4A and Figure 4BThey are respectively a cross-sectional schematic diagram and a top view schematic diagram of the intermediate structure 400a after the initial stacking structure 411' is formed. Figure 4A The intermediate structure 400a is shown along Figure 4B Schematic cross-sectional views taken along lines AA' and BB' are shown.

[0081] like Figure 4A and Figure 4B As shown, the first dielectric layer 414 and the second dielectric layer 426 may be alternately formed by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof to form an initial stacked structure 411 ′.

[0082] In some embodiments, the initial stacked structure 411' may be formed on one side of the substrate 451. For example, the substrate 451 may include a semiconductor substrate. The material of the semiconductor substrate may include silicon (Si), germanium (Ge), gallium arsenide (GaAs), or indium phosphide (InP). For another example, the semiconductor substrate may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate. In some examples, the substrate 451 may be a composite layer structure. In other examples, the substrate 451 may be composed of a single material. For example, the substrate 451 may play a supporting role during the manufacturing process and may be removed in subsequent processes.

[0083] In this step, the initial stacking structure 411 ′ has a first region 401 (eg, Figure 4B gray area shown) and a second region 402 (e.g., Figure 4B The white area shown). On a plane perpendicular to the z-direction, the first region 401 and the second region 402 of the initial stacked structure 411' are arranged adjacent to each other. For example, on a plane perpendicular to the z-direction, the first region 401 surrounds the second region 402 on both sides in the y-direction and on one side in the x-direction. For example, the first region 401 can also be divided into sub-regions 4011 (e.g., Figure 4B The area within the dashed box in the gray area shown) and the sub-area 4012 (e.g., Figure 4B The sub-area 4011 and the sub-area 4022 are arranged along the x-direction, and the sub-area 4011 is located on both sides of the second area 402 in the y-direction, and the sub-area 4022 is located on one side of the second area 402 in the x-direction.

[0084] In some embodiments, after forming the initial stacked structure 411', a channel structure 432 may be formed that penetrates the initial stacked structure 411' and extends into the substrate 451. For example, there may be multiple channel structures 432. On a plane perpendicular to the z-direction, the multiple channel structures 432 are spaced apart along the x-direction and the y-direction.

[0085] In some embodiments, after forming the channel structure 432, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof may be used to sequentially form a first insulating layer 428, a select gate layer 427, and a second insulating layer 429 on a surface of the initial stacked structure 411' in the sub-region 4012 that is away from the substrate 451. A third insulating layer 431 is formed on a surface of the initial stacked structure 411' in the sub-region 4011 and the second region 402 that is away from the substrate 451. The first insulating layer 428, the select gate layer 427, and the second insulating layer 429 may be referred to as a select stacked structure 430.

[0086] In some embodiments, after forming the selection gate stack structure 430, a selection channel structure 433 may be formed that penetrates the selection gate stack structure 430. For example, there may be multiple selection channel structures 433. On a plane perpendicular to the z-direction, the multiple selection channel structures 433 may be arranged at intervals along the x-direction and the y-direction, and respectively connected to the multiple channel structures 432.

[0087] In some embodiments, the manufacturing method 300 may further include the step of forming a gate line gap 452 that penetrates the initial stacked structure 411'. For example, an etching process (e.g., dry etching and / or wet etching) may be used to form the gate line gap 452. The gate line gap 452 may extend within the first region 401 along the x-direction. In the case where a selective stacked structure 430 and a third insulating layer 431 are formed, the gate line gap 452 may also penetrate the selective stacked structure 430 and the third insulating layer 431. Optionally, in the z-direction, the gate line gap 452 may extend into the substrate 451. Thus, the substrate 451 may be exposed to the gate line gap 452. An oxide layer 453 may be formed on the surface of the substrate 451 exposed to the gate line gap 452. The oxide layer 453 may reduce the risk of damage to the substrate 451 during subsequent processing.

[0088] In some embodiments, before forming the gate line slit 452, a first protective layer 439 may be formed that penetrates the second insulating layer 429 and the select gate layer 427, so that the subsequently formed gate line slit 452 penetrates the first protective layer 439. The material of the first protective layer 439 may be different from that of the second insulating layer 429. For example, the material of the second insulating layer 429 may include silicon nitride (Si3N4), and the material of the first protective layer 439 may include silicon oxide (SiO2).

[0089] S320

[0090] Figure 5 The intermediate structure 400 b is shown after forming a first sacrificial layer 454 . Figure 6 The intermediate structure 400c is shown after the initial contact holes 456 are formed. Figure 7 The intermediate structure 400d is shown after forming the epitaxial contact holes 457 . Figure 8 The intermediate structure 400e is shown after forming a second sacrificial layer 459.

[0091] In some embodiments, as Figures 4A to 5 As shown, after forming the gate line gap 452, a first sacrificial layer 454 may be formed in the gate line gap 452. The material of the first sacrificial layer 454 may include polysilicon (poly-Si), carbon (C) or any other suitable easily removable material. For example, the material of the first sacrificial layer 454 includes polysilicon (poly-Si). Further, as Figure 6 As shown, a first mask layer 455 may be formed on a side of the selective stack structure 430 away from the substrate 451. The first mask layer 455 may cover the first sacrificial layer 454. It should be noted that the first mask layer 455 may include a composite layer structure or a single layer structure, which is not specifically limited in this application.

[0092] In some embodiments, continue with reference to Figure 6 , an initial contact hole 456 extending along the z-direction in the initial stacked structure 411' may be formed by an etching process (e.g., dry etching and / or wet etching). The initial contact hole 456 may be located in the second region 402. For example, the initial contact hole 456 may expose the second dielectric layer 426. Alternatively, the initial contact hole 456 may expose the first dielectric layer 414 (not shown). Further, as Figure 7As shown, an etching process (e.g., wet etching) can be used to remove a portion of the second dielectric layer 426 at the bottom of the initial contact hole 456 to form an epitaxial contact hole 457. The initial contact hole 456 and the epitaxial contact hole 457 can serve as a contact hole 458. At least a portion of the epitaxial contact hole 457 can be located within the second region 402. For example, the epitaxial contact hole 457 can extend into the sub-region 4011. In some examples, when the initial contact hole 456 exposes the second dielectric layer 426, an etching material (e.g., an etchant) can be directly contacted with the second dielectric layer 426 to remove a portion of the second dielectric layer 426, thereby forming the epitaxial contact hole 457. In other examples, when the initial contact hole 456 exposes the first dielectric layer 414 (not shown), the first dielectric layer 414 at the bottom of the initial contact hole 456 can be removed to expose the second dielectric layer 426, and then the exposed portion of the second dielectric layer 426 can be removed. Optionally, before forming the epitaxial contact hole 457, a second protective layer 437 may be formed on the sidewalls of the initial contact hole 456. The material of the second protective layer 437 may be different from the material of the second dielectric layer 426. During the process of forming the epitaxial contact hole 457, the second protective layer 437 may be used to prevent the second dielectric layer 426 exposed on the sidewalls of the initial contact hole 456 from being damaged by etching materials (e.g., etchants).

[0093] In some embodiments, after forming the contact hole 458, as shown in FIG. Figure 8 As shown, a second sacrificial layer 459 may be formed in the contact hole 458. The material of the second sacrificial layer 459 may include polysilicon (poly-Si), carbon (C), or any other suitable easily removable material. For example, the material of the second sacrificial layer 459 includes spin-on carbon (SOC).

[0094] S330

[0095] Figure 9 The intermediate structure 400 f is shown after forming the first sacrificial gap portion 460 . Figure 10 The intermediate structure 400g is shown after forming the third sacrificial layer 461 . Figure 11 The intermediate structure 400h is shown after the second sacrificial gap portion 462 . Figure 12 The intermediate structure 400 i is shown after forming the sacrificial gaps 463 and exposing the contact holes 458 . Figure 13 The intermediate structure 400 j is shown after formation of a gate layer 415 and a contact structure 416 .

[0096] In some embodiments, as Figure 8 and Figure 9As shown, an etching process (e.g., wet etching) can be used to remove the first sacrificial layer 454 in the gate line gap 452 in the sub-region 4011, thereby exposing the gate line gap 452 in the sub-region 4011. Furthermore, an etching process (e.g., wet etching) can be used to remove the second dielectric layer 426 in the initial stacked structure 411' in the sub-region 4011, thereby forming a first sacrificial gap portion 460. In the case where the oxide layer 453 is formed, the oxide layer 453 can reduce the risk of damaging the substrate 451 during the removal of the first sacrificial layer 454 in the gate line gap 452 in the sub-region 4011.

[0097] In some embodiments, as Figure 9 and Figure 10 As shown, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof may be used to form a third sacrificial layer 461 in the first sacrificial gap portion 460 and the gate line gap 452 located in the sub-region 4011. The material of the third sacrificial layer 461 may be different from the material of the first sacrificial layer 454. For example, when the material of the first sacrificial layer 454 includes polysilicon (poly-Si), the material of the third sacrificial layer 461 may include carbon (C).

[0098] In some embodiments, as Figure 10 and Figure 11 As shown, an etching (e.g., wet etching) process can be used to remove the first sacrificial layer 454 in the gate line gap 452 in the sub-region 4012, and the gate line gap 452 in the sub-region 4012 is exposed. Further, an etching (e.g., wet etching) process can be used to remove the second dielectric layer 426 in the initial stacked structure 411' in the sub-region 4012, and form a second sacrificial gap portion 462. In this step, the first protective layer 439 can be used to deal with the damage of the etching material (e.g., etchant) to the second insulating layer 429. In addition, the material of the first sacrificial layer 454 is different from the material of the third sacrificial layer 461, which can be used to ensure that the first region 401 (reference Figure 4B Similarly, when the oxide layer 453 is formed, the oxide layer 453 can reduce the risk of damaging the substrate 451 during the removal of the first sacrificial layer 454 in the gate line gap 452 in the sub-region 4012.

[0099] In some embodiments, as Figure 11 and Figure 12 As shown, an etching process (e.g., wet etching) can be used to remove the third sacrificial layer 461 in the first sacrificial gap portion 460 and the gate line gap 452 in the sub-region 4011, and remove the second sacrificial layer 459 in the contact hole 458. Figure 9) are connected to each second sacrificial gap portion 462 to form a sacrificial gap 463. The gate line gap 452 and the contact hole 458 located in the sub-regions 4011 and 4012 are exposed, and the epitaxial contact hole 457 in the contact hole 458 can be connected to a sacrificial gap 463.

[0100] In some embodiments, as Figure 12 and Figure 13 As shown, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to sequentially form high dielectric constant layers 417, 421, 424 and conductive layers 418, 422, 425 in the sacrificial gap 463 and the contact hole 458. The high dielectric constant layer 417 (hereinafter referred to as the first high dielectric constant layer 417) and the conductive layer 418 (hereinafter referred to as the first conductive layer 418) formed in the sacrificial gap 463 can constitute the gate layer 415. The high dielectric constant layers 421, 424 and the conductive layers 422, 425 formed in the contact hole 458 can constitute the contact structure 416. For example, the high dielectric constant layer and the conductive layer can also cover the sidewalls and bottom of the gate line gap 452, and can also extend to the side of the select stack structure 430 and the third insulating layer 431 away from the substrate 451.

[0101] In some embodiments, the step of forming the contact structure 416 may include: Figure 12 and Figure 13 As shown, a second high-k dielectric layer 421 and a second conductive layer 422 are sequentially formed on the sidewalls of the initial contact hole 456, and a third high-k dielectric layer 424 and a third conductive layer 425 are sequentially formed in the epitaxial contact hole 457. The second high-k dielectric layer 421 and the second conductive layer 422 may constitute the first contact portion 420 of the contact structure 416, and the third high-k dielectric layer 424 and the third conductive layer 425 may constitute the second contact portion 423. For example, the first high-k dielectric layer 417, the second high-k dielectric layer 421, and the third high-k dielectric layer 424 may be formed in the same thin-film deposition process, and the first conductive layer 418, the second conductive layer 422, and the third conductive layer 425 may be formed in the same thin-film deposition process. In other words, the gate layer 415 and the contact structure 416 may be formed in the same thin-film deposition process. The above process method is advantageous in reducing process complexity, improving manufacturing efficiency, and saving manufacturing costs.

[0102] In some embodiments, after forming the first high dielectric constant layer 417, the second high dielectric constant layer 421, and the third high dielectric constant layer 424, and before forming the first conductive layer 418, the second conductive layer 422, and the third conductive layer 425, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof may be used to form an adhesion layer (not shown) on the surfaces of the first high dielectric constant layer 417, the second high dielectric constant layer 421, and the third high dielectric constant layer 424.

[0103] After the above process, the initial stacking structure 411' is transformed into a stacking structure 411. Figure 4B ) is transformed into a first stacking portion 412, and the initial stacking structure 411' located in the second area 402 is transformed into a second stacking portion 413.

[0104] In some embodiments, the manufacturing method 300 further includes the steps described below. Figure 14 The intermediate structure 400k is shown after forming an initial insulating structure 434'. Figure 15 The intermediate structure 4001 is shown after forming the insulating structure 434 . Figure 16 The intermediate structure 400m is shown after forming an initial second masking layer 464'. Figure 17 Intermediate structure 400n is shown after forming a second masking layer 464. Figure 18 The intermediate structure 400 o is shown after the gate line slits 452 are exposed. Figure 19 The intermediate structure 400 p is shown after a portion of the gate layer 415 near the gate line gap 452 is removed. Figure 20 An intermediate structure 400q is shown after the gate line isolation structure 438 is formed. Figure 21 The intermediate structure 400 r is shown after the contact connection structure 435 has been formed.

[0105] In some embodiments, as Figure 13 and Figure 14 As shown, a thin film deposition process such as CVD, PVD, ALD or any combination thereof may be used to form an initial insulating structure 434' on the inner side of the gate line gap 452 and the first contact portion 420, and on the side of the stacked structure 430 and the third insulating layer 431 away from the substrate 451. Figure 15 As shown, a chemical mechanical polishing (CMP) process can be used to remove the portion of the initial insulating structure 434' located on the side of the selected stacked structure 430 and the third insulating layer 431 away from the substrate 451, and the remaining portion (hereinafter referred to as the insulating structure 434) can be located inside the gate line gap 452 and the first contact portion 420.

[0106] In some embodiments, as Figure 15 and Figure 16 As shown, a thin film deposition process such as CVD, PVD, ALD or any combination thereof may be used to form an initial second mask layer 464' on a side of the selected stack structure 430 and the third insulating layer 431 away from the substrate 451. The initial second mask layer 464' covers the insulating structure 434. The material of the initial second mask layer 464' may be the same as that of the conductive layers 418, 422, and 425. For example, the materials of the initial second mask layer 464' and the conductive layers 418, 422, and 425 all include tungsten (W). Further, as shown in FIG. Figure 16 and Figure 17 As shown, an etching (eg, dry etching and / or wet etching) process may be used to remove a portion of the initial second mask layer 464' covering the insulating structure 434 inside the gate line gap 452 to form a second mask layer 464. In other words, a second mask layer 464 may be formed to expose the gate line gap 452 (see FIG. Figure 12 ) of the second mask layer 464. It should be noted that the portion of the second mask layer 464 covering the insulating structure 434 inside the first contact portion 420 is not removed.

[0107] In some embodiments, as Figure 17 and Figure 18 As shown, an etching process (eg, wet etching) may be used to remove the insulating structure 434 inside the gate line gap 452 using the second mask layer 464 , so that the gate line gap 452 is exposed.

[0108] In some embodiments, as Figure 18 and Figure 19 As shown, an etching (e.g., wet etching) process can be used to remove a portion of the gate layer 415 near the gate line gap 452. Optionally, the second mask layer 464 can be removed during the process of removing the portion of the gate layer 415 near the gate line gap 452. In addition, when the high dielectric constant layers 417, 421, 424 and the conductive layers 418, 422, 425 cover the sidewalls and bottom of the gate line gap 452 and extend to the side of the selective stack structure 430 and the third insulating layer 431 away from the substrate 451, the portion can also be removed during the process of removing the portion of the gate layer 415 near the gate line gap 452. In this embodiment, since the insulating structure 434 has been formed inside the first contact portion 420, the already formed first contact portion 420 will not be damaged during the above-mentioned removal process.

[0109] In some embodiments, as Figure 19 and Figure 20As shown, a thin film deposition process such as CVD, PVD, ALD or any combination thereof may be used to sequentially form an isolation insulating layer 4381 and a polysilicon body 4382 in the gate line gap 452 to form a gate line isolation structure 438. For example, the isolation insulating layer 4381 may extend to a side of the selective stack structure 430 and the third insulating layer 431 away from the substrate 451 and serve as the fourth insulating layer 436 (refer to FIG. Figure 21 ) part.

[0110] In some embodiments, as Figure 20 and Figure 21 As shown, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to form another portion of the fourth insulating layer 436 on a side of the selected stack structure 430 and the third insulating layer 431 away from the substrate 451. The fourth insulating layer 436 can cover the polysilicon body 4382. Furthermore, an etching process and a thin film deposition process can be used to form at least one (e.g., two) contact connection structures 435 connected to the end of the first contact portion 420 away from the second contact portion 423.

[0111] In some embodiments, at least a portion of the substrate 451 may be removed, and at least a portion of the blocking layer 4321, the charge trapping layer 4322, and the tunneling layer 4323 in the channel structure 432 that protrudes from the first stack portion 412 may be removed, thereby exposing the first channel layer 4324. Next, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof may be used to form a semiconductor layer 141 connected to (e.g., in contact with) the first channel layer 4324 on a side of the first stack portion 412 away from the selected stack structure 430 (see FIG. 1 ). Figure 1A ).

[0112] Figures 22 to 29 : is a cross-sectional schematic diagram of a semiconductor structure provided in another embodiment of the present application during the manufacturing process. Figures 22 to 29 Shown Figure 15 The intermediate structure 4001 is shown as each intermediate structure 500a to 500h after subsequent processing. For the purpose of brevity, the same contents as the previous embodiment will not be repeated in this application.

[0113] Figure 22 Intermediate structure 500a is shown after forming an initial second masking layer 564'. Figure 23 Intermediate structure 500b is shown after forming a second masking layer 564 . Figure 24 The intermediate structure 500 c is shown after the gate line slits 552 are exposed. Figure 25 The intermediate structure 500d is shown after a portion of the gate layer 515 near the gate line gap 552 is removed. Figure 26The intermediate structure 500e is shown after the gate line isolation structure 538 is formed. Figure 27 The intermediate structure 500 f is shown after forming a third mask layer 565 . Figure 28 The intermediate structure 500g is shown after forming the third contact portion 542. Figure 29 The intermediate structure 500 h is shown after the contact connection structure 535 has been formed.

[0114] In some embodiments, as Figure 22 As shown, a thin film deposition process such as CVD, PVD, ALD or any combination thereof may be used to form an initial second mask layer 564' on a side of the selected stacked structure 530 and the third insulating layer 531 away from the substrate 551. The initial second mask layer 564' covers the insulating structure 534. The material of the initial second mask layer 564' may be the same as that of the conductive layers 518, 522, and 525. For example, the materials of the initial second mask layer 564' and the conductive layers 518, 522, and 525 all include tungsten (W). Further, as shown in FIG. Figure 22 and Figure 23 As shown, an etching (e.g., dry etching and / or wet etching) process may be used to remove a portion of the initial second mask layer 564' covering the insulating structure 534 inside the gate line gap 552 to form a second mask layer 564. In other words, a second mask layer 564 may be formed to expose the gate line gap 552 (e.g., the insulating structure 534 inside the gate line gap 522). For example, the thickness of the second mask layer 564 in the z direction in this embodiment may be greater than that of the second mask layer 464 in the previous embodiment (see Figure 17 It should be noted that the second mask layer 564 may cover a portion of the insulating structure 534 inside the first contact portion 520 without being removed.

[0115] In some embodiments, as Figure 23 and Figure 24 As shown, an etching process (eg, wet etching) may be used to remove the insulating structure 534 inside the gate line gap 552 using the second mask layer 564 , so that the gate line gap 552 is exposed.

[0116] In some embodiments, as Figure 24 and Figure 25 As shown, an etching (eg, wet etching) process may be used to remove a portion of the gate layer 515 near the gate line gap 552. Optionally, during the process of removing the portion of the gate layer 515 near the gate line gap 552, the second mask layer 564 may be retained.

[0117] In some embodiments, as Figure 25 and Figure 26As shown, a thin film deposition process such as CVD, PVD, ALD or any combination thereof may be used to sequentially form an isolation insulating layer 5381 and a polysilicon body 5382 in the gate line gap 552 to form a gate line isolation structure 538 .

[0118] In some embodiments, as Figure 26 and Figure 27 As shown, a third mask layer 565 covering the second mask layer 564 and the gate line isolation structure 538 can be formed by a thin film deposition process such as CVD, PVD, ALD or any combination thereof. The material of the third mask layer 565 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating materials.

[0119] In some embodiments, as Figure 27 and Figure 28 As shown, an etching process (e.g., dry etching) can be used to remove a portion of the third mask layer 565 and the second mask layer 564, so that the remaining third mask layer 565 and the second mask layer 564 cover the surface of the insulating structure 534 and are connected to (e.g., in contact with) the first contact portion 520. The remaining second mask layer 564 can serve as the third contact portion 542 of the contact structure 516. For example, the remaining third mask layer 565 can serve as the fourth insulating layer 536 (see Figure 29 Alternatively, when the high dielectric constant layer and the conductive layer extend to a side of the selective stacked structure 530 and the third insulating layer 531 away from the substrate 551, the portion may also be removed during the process of removing a portion of the second mask layer 564.

[0120] In some embodiments, as Figure 28 and Figure 29 As shown, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to form another portion of the fourth insulating layer 536 on a side of the selected stacked structure 530 and the third insulating layer 531 away from the substrate 551. The fourth insulating layer 536 can cover the polysilicon body 5382. Furthermore, an etching process and a thin film deposition process can be used to form at least one (e.g., two) contact connection structures 535 connected to the third contact portion 542 on a side away from the insulating structure 534. In this embodiment, forming the contact connection structure 535 connected to the third contact portion 542 helps to increase the process window and reduce the process difficulty.

[0121] In some embodiments, at least a portion of the substrate 551 may be removed, and at least a portion of the blocking layer 5321, the charge trapping layer 5322, and the tunneling layer 5323 in the channel structure 532 that protrudes from the first stack portion 512 may be removed, thereby exposing the first channel layer 5324. Next, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof may be used to form a semiconductor layer 241 connected to (e.g., in contact with) the first channel layer 5324 on a side of the first stack portion 512 away from the selected stack structure 530 (see FIG. 2 ). Figure 2 ).

[0122] Some embodiments of the present application also provide a memory. Figure 30 Schematic block diagram of the memory provided by the embodiment of the present application. Figure 30 As shown, the memory 60 may include a semiconductor structure 61 and a peripheral circuit 62. For example, the semiconductor structure 61 and the peripheral circuit 62 may be arranged in the z-direction to form the memory 60.

[0123] The semiconductor structure 61 may be implemented as the semiconductor structure described in any embodiment of the present application (eg, Figure 1A and Figure 1B The semiconductor structure 100 or Figure 2 ). In some embodiments, as described above, the semiconductor structure 61 may include a plurality of memory strings, each of which may include a plurality of memory cells. The semiconductor structure 61 may include a memory cell array to implement data storage. For example, the memory string may be a NAND memory string.

[0124] Peripheral circuitry 62 may be coupled to semiconductor structure 61. Peripheral circuitry 62 may include any suitable digital, analog, and / or mixed-signal peripheral circuitry for facilitating operation of the memory cell array in semiconductor structure 61. For example, peripheral circuitry 62 may include one or more of a page buffer, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output (I / O) circuitry, a charge pump, a voltage source or generator, a current or voltage reference, any portion (e.g., a subcircuit) of the aforementioned functional circuitry, or any active or passive component of the circuitry (e.g., a transistor, diode, resistor, or capacitor).

[0125] An embodiment of the present application also provides a memory system. Figure 31 is a schematic block diagram of a system with a memory system provided in an embodiment of the present application. Figure 32A and Figure 32B Schematic diagram of a memory system provided in an embodiment of the present application.

[0126] like Figure 31As shown, the system 11 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device (the electronic device has the memory system 12 located therein). Figure 31 As shown, system 11 may include a host 18 and a memory system 12 having one or more memories 14 and a controller 16. Host 18 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system-on-chip (SoC), such as an application processor (AP). Host 18 may be configured to send or receive data to or from memory 14.

[0127] The memory 14 may include the memory described in any embodiment of the present application (for example, Figure 30Memory 60 is shown. According to some embodiments, controller 16 is coupled to memory 14 and host 18 and is configured to control memory 14. Controller 16 can manage data stored in memory 14 and communicate with host 18. In some embodiments, controller 16 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, controller 16 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multi-media card (eMMC) used as a data storage device for mobile devices, such as smartphones, tablets, laptops, etc., and enterprise storage arrays. Controller 16 can be configured to control operations of memory 14, such as read, erase, and program operations. The controller 16 may also be configured to manage various functions related to data stored in or to be stored in the memory 14, including, but not limited to, bad block management, garbage collection, logical-to-physical address translation, wear leveling, and the like. In some embodiments, the controller 16 is further configured to process error correction code (ECC) associated with data read from or written to the memory 14. Any other appropriate functions may also be performed by the controller 16, such as formatting the memory 14. The controller 16 may communicate with an external device (e.g., the host 18) according to a specific communication protocol. For example, the controller 16 may communicate with the external device via at least one of various interface protocols, such as the USB protocol, the MMC protocol, the Peripheral Component Interconnect (PCI) protocol, the PCI Express (PCI-Express, PCI-E) protocol, the Advanced Technology Attachment (ATA) protocol, the Serial ATA protocol, the Parallel ATA protocol, the Small Computer Small Interface (SCSI) protocol, the Enhanced Small Disk Interface (ESDI) protocol, the Integrated Drive Electronics (IDE) protocol, the Firewire protocol, and the like.

[0128] The controller 16 and the one or more memories 14 can be integrated into various types of memory systems, for example, included in the same package (such as a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 12 can be implemented and packaged into different types of final electronic products. Figure 32AIn one example shown in FIG, the controller 16 and the single memory 14 may be integrated into a memory card 22. The memory card 22 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 22 may further include a memory card that connects the memory card 22 to a host (e.g., Figure 31 The host 18 in the memory card connector 24 is coupled. Figure 32B In another example shown in FIG, the controller 16 and the plurality of memories 14 may be integrated into an SSD 26. The SSD 26 may further include a processor that connects the SSD 26 to a host (e.g., Figure 31 In some embodiments, the SSD 26 has a storage capacity and / or an operating speed that is higher than that of the memory card 22.

[0129] The above description is merely an embodiment of the present application and an illustration of the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to the technical solutions formed by a specific combination of the above-mentioned technical features, but should also cover other technical solutions formed by any combination of the above-mentioned technical features or their equivalents without departing from the technical concept. For example, a technical solution formed by replacing the above-mentioned features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A semiconductor structure, characterized in that include: A stacked structure comprising a first stacked portion and a second stacked portion on a plane perpendicular to a stacking direction thereof, wherein the first stacked portion comprises alternately stacked first dielectric layers and gate layers; as well as a contact structure extending in the second stacking part along the stacking direction; Wherein, the gate layer and the contact structure both include a high dielectric constant layer and a conductive layer arranged from the outside to the inside.

2. The semiconductor structure according to claim 1, wherein The contact structure comprises: a first contact portion extending in the stacking direction in the second stack portion; and The second contact portion is connected to the first contact portion and extends on a plane perpendicular to the stacking direction.

3. The semiconductor structure according to claim 2, wherein: The gate layer includes a first high dielectric constant layer and a first conductive layer from outside to inside, the first contact portion includes a second high dielectric constant layer and a second conductive layer from outside to inside, and the second contact portion includes a third high dielectric constant layer and a third conductive layer from outside to inside.

4. The semiconductor structure according to claim 3, wherein: The first high dielectric constant layer, the second high dielectric constant layer, and the third high dielectric constant layer are made of the same material.

5. The semiconductor structure according to claim 3, wherein The gate layer further includes a first adhesive layer located between the first high dielectric constant layer and the first conductive layer, the first contact portion further includes a second adhesive layer located between the second high dielectric constant layer and the second conductive layer, and the second contact portion further includes a third adhesive layer located between the third high dielectric constant layer and the third conductive layer. The semiconductor structure according to claim 5 , wherein: The first adhesive layer, the second adhesive layer, and the third adhesive layer are made of the same material.

7. The semiconductor structure according to claim 5, wherein: The second high dielectric constant layer is connected to the third high dielectric constant layer, and the second adhesive layer is connected to the third adhesive layer.

8. The semiconductor structure according to any one of claims 2 to 7, wherein: The contact structure further includes an insulating structure located inside the first contact portion.

9. The semiconductor structure according to claim 8, wherein The semiconductor structure further includes at least one contact connection structure connected to an end of the first contact portion away from the second contact portion.

10. The semiconductor structure according to claim 8, wherein The contact structure further includes: The third contact portion is located on a side of the insulating structure away from the second contact portion and is connected to the first contact portion.

11. The semiconductor structure according to claim 10, wherein The semiconductor structure further comprises at least one contact connection structure connected to the third contact portion.

12. The semiconductor structure according to claim 2, wherein: The second stack portion includes the first dielectric layers and the second dielectric layers alternately stacked, and the second contact portion is located between adjacent first dielectric layers and connected to the gate layer.

13. A memory, characterized in that: include: The semiconductor structure according to any one of claims 1 to 12; as well as The peripheral circuit is coupled to the semiconductor structure.

14. A memory system, characterized in that: include: The memory as claimed in claim 13; as well as The controller is coupled to the memory and is used to control the memory to store data.

15. A method for manufacturing a semiconductor structure, characterized in that: include: forming an initial stacking structure including alternately stacked first and second dielectric layers, the initial stacking structure having a first region and a second region; forming contact holes extending in the stacking direction of the initial stacking structure, wherein at least a portion of the contact holes is located in the second region; as well as replacing the second dielectric layer in the initial stacked structure in the first region with a gate layer, and forming a contact structure in the contact hole; Wherein, the gate layer and the contact structure both include a high dielectric constant layer and a conductive layer arranged from the outside to the inside.

16. The manufacturing method according to claim 15, wherein: The contact holes formed in the stacked structure and extending along the stacking direction thereof include: forming an initial contact hole extending along the stacking direction in the initial stacking structure; Using the initial contact hole to remove a portion of the second dielectric layer at the bottom thereof to form an epitaxial contact hole, the initial contact hole and the epitaxial contact hole serving as the contact hole; Wherein, forming a contact structure in the contact hole comprises: A first contact portion of the contact structure is formed on the sidewall of the initial contact hole, and a second contact portion of the contact structure is formed in the epitaxial contact hole, wherein materials of the first contact portion and the second contact portion both include the high dielectric constant material and the conductive material.

17. The manufacturing method according to claim 16, wherein: The manufacturing method further comprises: forming a gate line gap penetrating the initial stacked structure; The step of replacing the second dielectric layer in the initial stacked structure in the first region with a gate layer includes: replacing the second dielectric layer in the initial stacked structure in the first region with the gate layer by using the gate line gap; and Wherein, the manufacturing method further comprises: A portion of the gate layer close to the gate line gap is removed.

18. The manufacturing method according to claim 17, wherein: Before removing a portion of the gate layer close to the gate line gap, the manufacturing method further includes: An insulating structure is formed inside the first contact portion.

19. The manufacturing method according to claim 18, wherein: Before removing a portion of the gate layer close to the gate line gap, the manufacturing method further includes: forming a mask layer exposing the gate line gaps; Wherein, in the process of removing a portion of the gate layer close to the gate line gap, the mask layer is removed.

20. The manufacturing method according to claim 19, wherein: The manufacturing method further comprises: At least one contact connection structure is formed at an end of the first contact portion away from the second contact portion and connected thereto.

21. The manufacturing method according to claim 18, wherein Before removing a portion of the gate layer close to the gate line gap, the manufacturing method further includes: forming a mask layer exposing the gate line gap, wherein the mask layer is a conductive material; wherein, in the process of removing a portion of the gate layer close to the gate line gap, the mask layer is retained; and A portion of the mask layer is removed, so that the remaining mask layer covers the surface of the insulating structure and is connected to the first contact portion, and serves as the third contact portion of the contact structure.

22. The manufacturing method according to claim 21, wherein: The manufacturing method further comprises: At least one contact connection structure is formed on a side of the third contact portion away from the insulating structure and connected thereto.

23. The manufacturing method according to claim 16, wherein: Replacing the second dielectric layer in the initial stacked structure in the first region with a gate layer includes: removing the second dielectric layer in the initial stacked structure in the first region and forming a sacrificial gap; forming a first high dielectric constant layer and a first conductive layer in sequence in the sacrificial gap to form the gate layer; Wherein, forming the first contact portion of the contact structure on the sidewall of the initial contact hole and forming the second contact portion of the contact structure in the epitaxial contact hole comprises: A second high dielectric constant layer and a second conductive layer are sequentially formed on the sidewalls of the initial contact hole, and a third high dielectric constant layer and a third conductive layer are sequentially formed in the epitaxial contact hole.

24. The manufacturing method according to claim 23, wherein: The first high dielectric constant layer, the second high dielectric constant layer and the third high dielectric constant layer are formed in the same thin film deposition process, and the first conductive layer, the second conductive layer and the third conductive layer are formed in the same thin film deposition process.

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