Solar cell and photovoltaic module

Abstract

The invention discloses a solar cell and a photovoltaic module, and relates to the field of photovoltaic technology. The solar cell includes a semiconductor substrate, a first semiconductor layer, a second semiconductor layer, a passivation layer, a plurality of first gate lines, and a second gate line. In the direction perpendicular to the first grid line or the second grid line, the distance between the hole edge close to the first edge and the hole edge close to the second edge in the first holes in the same group is W1, and the distance between the hole edge close to the third edge and the hole edge close to the fourth edge in the second holes in the same group is W2; the width of the first grid line is S1, and the width of the second grid line is S2; wherein | W1-W2 | < = 5 [mu] m, and S2 / W2 < = S1 / W1; or W2 is smaller than W1, and W2 is smaller than S2. Therefore, the shading area of the second grid line is reduced, the transmission efficiency between the second grid line and the second semiconductor layer is improved, and the overall power generation efficiency of the solar cell is improved.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic technology, and in particular to a solar cell and a photovoltaic module. Background Art

[0002] A solar cell is a device that converts sunlight into electrical energy. Specifically, when a solar cell is in operation, sunlight strikes the pn junction of the solar cell's semiconductor, forming new hole-electron pairs. Under the influence of the built-in electric field within the pn junction, the photogenerated holes flow to the p region, and the photogenerated electrons flow to the n region. Once the circuit is connected, current is generated.

[0003] The process of manufacturing the electrode grid lines of solar cells is generally done by printing or laser transfer of a paste followed by drying and curing. The paste may contain conductive particles such as silver, copper, and aluminum. For bifacial cells, current matching between the front and back grid lines, shading issues for the grid lines, and damage to the substrate caused by laser debonding are all technical issues that need to be balanced to improve the overall photoelectric conversion efficiency of the solar cell. Summary of the Invention

[0004] The purpose of this application is to provide a solar cell and a photovoltaic module to reduce the shading area and improve the photoelectric conversion efficiency of the solar cell.

[0005] In order to achieve the above objectives, this application provides the following technical solutions:

[0006] A solar cell comprising:

[0007] A semiconductor substrate having a backlight surface and a light-facing surface opposite to each other;

[0008] A first semiconductor layer is provided on the backlight side;

[0009] A second semiconductor layer is provided on the light-facing surface, and the conductivity type of the second semiconductor layer is opposite to that of the first semiconductor layer;

[0010] A passivation layer covering at least one side of the first semiconductor layer or the second semiconductor layer facing away from the semiconductor substrate; the passivation layer having a plurality of first openings and a plurality of second openings extending through the thickness of the passivation layer;

[0011] a plurality of first gate lines, at least some of which are electrically connected to the first semiconductor layer through a group of first openings; and the first gate lines have opposite first and second edges along a direction perpendicular to the first gate lines;

[0012] a plurality of second gate lines, at least some of which are electrically connected to the second semiconductor layer through a group of second openings; and the second gate lines have opposite third and fourth edges along a direction perpendicular to the second gate lines;

[0013] Along the direction perpendicular to the first gate line or the second gate line, the distance between the hole edge close to the first edge and the hole edge close to the second edge in the same group of first openings is W1, and the distance between the hole edge close to the third edge and the hole edge close to the fourth edge in the same group of second openings is W2; the width of the first gate line is S1, and the width of the second gate line is S2; wherein, │W1-W2│≤5μm, and S2 / W2≤S1 / W1; or, W2<W1 and W2<S2.

[0014] In the present application, │W1-W2│≤5μm, and S2 / W2≤S1 / W1. That is, the difference between the distance W1 between the hole edge close to the first edge and the hole edge close to the second edge in the first opening of the same group and the second opening W2 of the same group is less than or equal to 5μm, so that the groove widths of the passivation layer on the backlight side and the light-facing side are roughly equal, and at the same time, S2 / W2≤S1 / W1 is matched, that is, the ratio of the width S2 of the second grid line on the light-facing side to the groove width W2 is smaller than the ratio of the width S1 of the first grid line on the backlight side to the groove width W1. As a result, the width S2 of the second grid line on the light-facing side is smaller, while ensuring that the groove width W2 of the passivation layer on the light-facing side is equivalent to the groove width W1 on the backlight side, that is, S2 / W2<S1 / W1; or the width S2 of the second grid line on the light-facing side and the groove width W2 are both smaller than those on the backlight side, that is, S2 / W2=S1 / W1. In this way, the width S2 of the second grid line on the light-facing side is smaller, which can reduce the shading area of the second grid line; and the groove width W2 of the passivation layer on the light-facing side is slightly smaller than the groove width W1 on the backlight side, which can reduce the damage to the passivation layer caused by the groove process on the light-facing side, while also taking into account the transmission efficiency between the second grid line and the second semiconductor layer, thereby improving the overall power generation efficiency of the solar cell.

[0015] Alternatively, W2<W1, and W2<S2. That is, the groove width W2 of the passivation layer on the light-facing side is smaller than the groove width W1 on the backlight side, and the width of the matching second grid line is larger than the groove width W2 of the passivation layer on the light-facing side. This can reduce the groove width W2 of the passivation layer on the light-facing side, reduce damage to the passivation layer on the light-facing side caused by the groove process, and at the same time ensure a reasonable contact area between the second grid line and the second semiconductor layer, so that the second grid line and the second semiconductor layer have a low transmission resistance, thereby improving the overall power generation efficiency of the solar cell.

[0016] In one implementation, when |W1-W2|≤5 μm and S2 / W2≤S1 / W1, 1≤S1 / W1≤4, 0.1≤S2 / W2≤3. Preferably, 0.5≤S2 / W2≤1.

[0017] In one implementation, when W2<W1, W2<S2, and 1≤S1 / W1≤4, 1≤S2 / W2≤3.

[0018] In one implementation, 1≤S1 / W1≤3; and / or, 1≤S2 / W2≤2.

[0019] In one implementation, 15 μm≤W1≤200 μm; and / or, 15 μm≤W2≤150 μm.

[0020] In one implementation, W2<W1≤3W2.

[0021] In one implementation, the height of the second gate line is h2; 0.1≤h2 / S2≤0.8, and / or, 50 μm≤S2≤200 μm; 5 μm≤h2≤20 μm;

[0022] And / or, the height of the first gate line is h1; 0.25≤h1 / S1≤0.3, and / or, 50 μm≤S1≤200 μm; 5 μm≤h1≤15 μm.

[0023] In one implementation, each group of first openings is distributed in at least one row, and each row includes at least two first openings spaced apart and distributed along the extension direction of the first grid lines; or, each group of first openings is a strip-shaped hole extending along the extension direction of the first grid lines;

[0024] Alternatively, each group of second openings is distributed in at least one row, and each row includes at least two second openings spaced apart along the extension direction of the second grid lines; or, each group of second openings is a strip-shaped hole extending along the extension direction of the second grid lines.

[0025] In one implementation, each group of first openings is spaced apart, each group of second openings is spaced apart, and a spacing between adjacent openings in each group of second openings is smaller than a spacing between adjacent openings in each group of second openings.

[0026] In one implementation, the entire first semiconductor layer is disposed on the backlight surface; along a direction perpendicular to the first gate line, the width of the first semiconductor layer is D1; and 0.007≤W1 / D1≤0.15.

[0027] In one implementation, the first semiconductor layer is arranged on the backlight surface in a shape of a Chinese character "F" or a stripe; along the direction perpendicular to the first gate line, the width of the first semiconductor layer not corresponding to the first opening is W. 13 , 10μm≤W 13 ≤200μm; 0.08≤W1 / W 13 ≤2; and / or, along the direction perpendicular to the first gate line, the width of the isolation region between adjacent first semiconductor layers is W 14 , 100μm≤W 14 ≤1000μm; 0.15≤W1 / W 14 ≤1.2.

[0028] In one implementation, a first seed layer is disposed in the first opening, wherein a width of the first seed layer is S3 along a direction perpendicular to the first gate line; a height of the first seed layer is h3 along a thickness direction of the semiconductor substrate; 1.2≤S1 / S3≤20 and / or 1.2≤h1 / h3≤30;

[0029] And / or, a second seed layer is provided in the second opening, and the width of the second seed layer is S4 along the direction perpendicular to the second gate line; the height of the second seed layer is h4 along the thickness direction of the semiconductor substrate; 1.2≤S2 / S4≤20 and / or 1.2≤h2 / h4≤40.

[0030] In one implementation, the passivation layer has a heat-affected zone surrounding the first opening or the second opening; the heat-affected zone includes a plurality of holes and / or cracks, the holes and / or cracks are filled with a conductive material, and the conductive material is electrically connected to the first semiconductor layer or the second semiconductor layer.

[0031] In one implementation, the first gate line and / or the second gate line includes copper powder and organic matter; the copper powder includes at least flake particles and spherical particles.

[0032] In one implementation, the first grid line and / or the second grid line includes a main portion and a spreading portion arranged in a direction perpendicular to the first grid line or the second grid line;

[0033] The width of the spreading portion is 5%-50% of the width of the main portion; and / or, along the thickness direction of the semiconductor substrate, the height of the main portion is h0, the height of the spreading portion is h0', h0'≤1 / 3h0; and / or, the median value of the copper powder particle size contained in the spreading portion is smaller than the median value of the copper powder particle size contained in the main portion.

[0034] A photovoltaic module comprises a plurality of solar cells as described above and at least one interconnecting element, wherein the interconnecting element connects two adjacent solar cells in series or in parallel; the two adjacent solar cells are respectively a first solar cell and a second solar cell, and the interconnecting element is electrically connected to a first grid line of the first solar cell and extends to be electrically connected to a second grid line of the second solar cell.

[0035] Compared with the prior art, the beneficial effects of the photovoltaic module provided by the embodiment of the present application are the same as the beneficial effects of the above-mentioned solar cell, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0037] Figure 1A partial cross-sectional view of a solar cell provided in an embodiment of the present application;

[0038] Figure 2 A graph showing the relationship between the ratio of the gate line width to the passivation layer groove width and the series resistance provided in this application;

[0039] Figure 3 A graph showing the relationship between the groove width of the passivation layer on the backlight side and the cell efficiency provided in this application;

[0040] Figure 4 A graph showing the relationship between the groove width of the passivation layer on the light-facing side and the cell efficiency provided in this application;

[0041] Figure 5 A graph showing the relationship between the aspect ratio of the gate lines provided in this application and the current loss;

[0042] Figure 6 A partial schematic diagram of the light-facing surface of a solar cell provided in one embodiment of the present application;

[0043] Figure 7 A partial schematic diagram of the light-facing surface of a solar cell provided by another embodiment of the present application;

[0044] Figure 8 A partial schematic diagram of the light-facing surface of a solar cell provided by another embodiment of the present application;

[0045] Figure 9 A partial schematic diagram of the backlight surface of a solar cell provided in another embodiment of the present application;

[0046] Figure 10 A partial schematic diagram of the backlight surface of a solar cell provided in one embodiment of the present application;

[0047] Figure 11 A partial schematic diagram of the vicinity of a first grid line of a solar cell provided in one embodiment of the present application;

[0048] Figure 12 A partial schematic diagram of the vicinity of the second grid line of a solar cell provided in one embodiment of the present application;

[0049] Figure 13 A relationship diagram of the ratio of gate line width to seed layer width and series resistance is provided for an embodiment of the present application;

[0050] Figure 14 A relationship diagram between the ratio of gate line height to seed layer height and series resistance is provided for an embodiment of the present application;

[0051] Figure 15 A schematic diagram of a heat-affected zone formed around an opening provided in an embodiment of the present application;

[0052] Figure 16A schematic diagram of matching a first gate line with a first opening provided in an embodiment of the present application;

[0053] Figure 17 A schematic diagram of matching a first gate line with a first opening provided in another embodiment of the present application;

[0054] Figure 18 A schematic diagram of matching the second gate line and the second opening provided in one embodiment of the present application;

[0055] Figure 19 A schematic diagram of matching a second gate line with a second opening provided in another embodiment of the present application;

[0056] Figure 20 A schematic diagram of matching a second gate line with a second opening provided in another embodiment of the present application;

[0057] Figure 21 A schematic diagram of matching a second gate line with a second opening provided in another embodiment of the present application;

[0058] Figure 22 A schematic diagram of a first gate line or a second gate line provided in another embodiment of the present application.

[0059] Reference numerals:

[0060] 1-semiconductor substrate, 2-passivation layer, 2a-heat-affected zone, 2b-first opening, 2c-second opening, 3-first interface layer, 4-first semiconductor layer, 5-first seed layer, 6-first gate line, 7-second semiconductor layer, 7a-first region, 8-second gate line, 9-second seed layer, 101-main body, 102-spreading part. DETAILED DESCRIPTION

[0061] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0062] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0063] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of this application, "a plurality of" means two or more, unless otherwise specifically defined. "Several" means one or more, unless otherwise specifically defined.

[0064] In the description of this application, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "front", "rear", "left", "right", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the indicated device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to this application.

[0065] In the description of this application, it should be noted that unless otherwise clearly specified and limited, the terms "installed", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal connection of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0066] Please refer to Figure 1 , the solar cell provided by the embodiment of this application includes a semiconductor substrate 1, a first semiconductor layer 4, a first grid line 6, a second semiconductor layer 7, a second grid line 8, and a passivation layer 2.

[0067] Among them, the semiconductor substrate 1 includes an opposite backlight surface and a light-facing surface, that is, the two surfaces opposite along the thickness direction of the semiconductor substrate 1 are the backlight surface and the light-facing surface respectively.

[0068] The first semiconductor layer 4 is disposed on the backlight surface. Specifically, the first semiconductor layer 4 can be disposed on the backlight surface entirely or partially. When the first semiconductor layer 4 is disposed on the backlight surface partially, the first semiconductor layer 4 can be arranged at intervals on the backlight surface in a strip shape or a shape similar to a rich character; there is an isolation area between adjacent first semiconductor layers 4. The first semiconductor layer 4 is disposed on the backlight surface, and the back is a tunneling passivation structure with a relatively high current transmission capacity. Then, removing a part of the first semiconductor layer 4 has no impact on the performance of the solar cell, and the passivation effect in the area where the first semiconductor layer 4 is removed is better and there is no parasitic absorption, which is beneficial to improving the power generation efficiency. The first semiconductor layer 4 can be additionally formed on the semiconductor substrate 1 through deposition technology, or can be formed in the semiconductor substrate 1 through diffusion, ion implantation, etc.

[0069] The second semiconductor layer 7 is disposed on the light-facing surface. The second semiconductor layer 7 has an opposite conductivity type to the first semiconductor layer 4, so as to collect and conduct electrons and holes respectively, thereby facilitating the formation of photocurrent. Specifically, the second semiconductor layer 7 can be disposed entirely or partially on the light-facing surface. When the second semiconductor layer 7 is partially disposed on the light-facing surface, after subsequent process optimization, if the passivation performance and current transmission capacity of the light-facing surface allow, the second semiconductor layer can also be considered to be arranged in strips or a "F"-like pattern on the light-facing surface; adjacent second semiconductor layers 7 have isolation regions between them.

[0070] The passivation layer 2 covers at least the side of the first semiconductor layer 4 and the second semiconductor layer 7 facing away from the semiconductor substrate 1. Specifically, the passivation layer 2 covers both the backlight side and the light-facing side. When the first semiconductor layer 4 is partially disposed on the backlight side, the passivation layer 2 also covers the isolation region between adjacent first semiconductor layers 4. When the second semiconductor layer 7 is partially disposed on the light-facing side, the passivation layer 2 also covers the isolation region between adjacent second semiconductor layers 7. The passivation layer 2 protects the surface of the cell, preventing water vapor or oxygen from penetrating into the interior of the cell, thereby avoiding performance degradation of the cell due to oxidation or hydrolysis. Furthermore, the provision of the passivation layer 2 can reduce the surface recombination rate of the cell, thereby improving the photoelectric conversion efficiency of the cell. The passivation layer 2 can have a single-layer structure; alternatively, the passivation layer 2 can have a multi-layer structure. Specifically, the passivation layer 2 is at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer, or a composite film formed by stacking these layers. Exemplarily, the passivation layer 2 may be a double-layer structure including a silicon nitride layer and a silicon oxide layer.

[0071] The passivation layer 2 has multiple groups of first openings 2b and multiple groups of second openings 2c extending through the thickness thereof. At least a portion of the first gate lines 6 are electrically connected to the first semiconductor layer 4 via the group of first openings 2b. Specifically, the multiple groups of first openings 2b may correspond to a plurality of first gate lines 6, respectively. The first gate lines 6 are disposed on the passivation layer 2, and each first gate line 6 is electrically connected to the first semiconductor layer 4 via a group of first openings 2b. That is, a portion of the first gate line 6 is electrically connected to the first semiconductor layer 4 via the first openings 2b, so that the first gate lines 6 can be used to conduct carriers collected by the first semiconductor layer 4. At least a portion of the second gate lines 8 is electrically connected to the second semiconductor layer 7 through a group of second openings 2c. Specifically, multiple groups of second openings 2c can correspond to multiple second gate lines 8. The second gate lines 8 are disposed on the passivation layer 2, and each second gate line 8 is electrically connected to the second semiconductor layer 7 through a group of second openings 2c. That is, a portion of the second gate lines 8 is electrically connected to the second semiconductor layer 7 through the second openings 2c, so that the second gate lines 8 are used to conduct carriers collected by the second semiconductor layer 7. The first gate lines 6 and / or the second gate lines 8 can be formed using processes such as screen printing, electroplating, sputtering, or evaporation.

[0072] Among them, Figure 1 As shown, along the direction perpendicular to the first grid line 6, the first grid line 6 has a first edge and a second edge relative to each other, that is, the first edge and the second edge are arranged relative to each other along the width direction of the first grid line 6. Along the direction perpendicular to the first grid line 6, the distance between the hole edge close to the first edge and the hole edge close to the second edge in the first opening 2b of the same group is W1. Along the direction perpendicular to the second grid line 8, the second grid line 8 has a third edge and a fourth edge relative to each other, that is, the third edge and the fourth edge are arranged relative to each other along the width direction of the second grid line 8. Along the direction perpendicular to the second grid line 8, the distance between the hole edge close to the third edge and the hole edge close to the fourth edge in the second opening 2c of the same group is W2. The width of the first grid line 6 is S1, and the width of the second grid line 8 is S2.

[0073] In the present application, |W1-W2|≤5μm, and S2 / W2<S1 / W1. That is, the difference between the distance W1 between the hole edge close to the first edge and the hole edge close to the second edge in the same group of first openings 2b and the distance W2 between the hole edge close to the third edge and the hole edge close to the fourth edge in the same group of second openings 2c is less than or equal to 5μm, so that the groove widths of the passivation layer 2 on the backlight side and the light-facing side are roughly equal, and at the same time, S2 / W2<S1 / W1, that is, the ratio of the width S2 of the second gate line 8 on the light-facing side to the groove width W2 is smaller than the ratio of the width S1 of the first gate line 6 on the backlight side to the groove width W1. This makes the width S2 of the second grid line 8 on the light-facing side smaller, and at the same time ensures that the groove width W2 of the passivation layer 2 on the light-facing side is equivalent to the groove width W1 on the backlight side; in this way, when the light-facing side is the light-facing side, the smaller width S2 of the second grid line 8 can appropriately reduce the shading area of the second grid line 8, and at the same time, the groove width W2 of the passivation layer 2 on the light-facing side is roughly equal to the groove width W1 on the backlight side, thereby improving the transmission efficiency between the second grid line 8 and the second semiconductor layer 7, and thereby improving the overall power generation efficiency of the solar cell.

[0074] For example, |W1-W2| may be 0, 1 μm, 2 μm, 3 μm, 4 μm, or 5 μm.

[0075] Alternatively, W2<W1, and W2<S2. That is, the groove width W2 of the passivation layer 2 on the light-facing side is smaller than the groove width W1 on the backlight side, and the width of the second gate line 8 is matched to be larger than the groove width W2 of the passivation layer 2 on the light-facing side. In this way, the groove width W2 of the passivation layer 2 on the light-facing side can be appropriately reduced, while ensuring a reasonable contact area between the second gate line 8 and the second semiconductor layer 7, so that the second gate line 8 and the second semiconductor layer 7 have a lower transmission resistance, thereby improving the overall power generation efficiency of the solar cell.

[0076] In the present application, the first gate line 6 and / or the second gate line 8 can be formed using a non-burn-through paste to reduce the manufacturing cost of the gate line. The non-burn-through paste can include one or more of a low-temperature silver paste, a copper paste, an aluminum paste, a nickel paste, and a zinc paste. The non-burn-through paste refers to a paste that cannot directly penetrate the passivation layer 2 by sintering to achieve contact with the semiconductor layer. Generally speaking, the first gate line 6 or the second gate line 8 formed by the non-burn-through paste ultimately retains an adhesive material, such as an organic component.

[0077] In some embodiments, as Figure 1 As shown, if S1 / W1 is too large, the width of the first gridline 6 will be too wide, resulting in severe light blocking. If S1 / W1 is too small, the contact area between the first gridline 6 and the first semiconductor layer 4 will be small, resulting in large current transmission losses. Therefore, in this technical solution, both light blocking and transmission losses are taken into consideration, with 1≤S1 / W1≤4. This reduces the light blocking area of the first gridline 6 while ensuring low transmission losses between the first gridline 6 and the first semiconductor layer 4, thereby improving the power generation efficiency of the solar cell.

[0078] In one implementation, when |W1-W2|≤5 μm and S2 / W2≤S1 / W1, 1≤S1 / W1≤4, 0.1≤S2 / W2≤3. Preferably, 0.5≤S2 / W2≤1.

[0079] like Figure 2 As shown, from Figure 2 It can be seen that when S1 / W1 is preferably within a reasonable range of 1.25 to 3.5, the efficiency of the series resistance is low, which is beneficial to improving the power generation efficiency of the solar cell.

[0080] In one implementation, when W2<W1, W2<S2, and 1≤S1 / W1≤4, 1≤S2 / W2≤3.

[0081] For example, S1 / W1 may be 1.25, 1.5, 1.75, 2, 2.25, 2.75 or 3, etc.

[0082] In one implementation, when W2<W1 and W2<S2, 1≤S1 / W1≤4, 1≤S2 / W2≤3. The opening width of the light-facing surface is smaller than that of the backlight surface, which can minimize the damage to the light-facing surface. At the same time, the gate line widths of the light-facing surface and the backlight surface are both greater than or equal to the opening widths of the corresponding surfaces, which can take into account both process alignment and transmission loss. While minimizing the shading area of the second gate line 8, it is ensured that there is a low transmission loss between the first gate line 6 and the first semiconductor layer 4. Exemplarily, S2 / W2 can be 1, 1.3, 1.4, 1.5, 1.6, 1.9, 2.3, 2.6 or 3. S1 / W1 can be 1, 1.3, 1.7, 2, 2.5, 3, 3.5 or 4. Since there is no shading problem for the back gate line, this ratio can be appropriately widened.

[0083] In some embodiments, as Figure 1 As shown, 15 μm ≤ W1 ≤ 200 μm, so as to ensure that the contact area between the first gate line 6 and the first semiconductor layer 4 is within a reasonable range, thereby ensuring the current transmission efficiency and reducing the damage to the semiconductor substrate 1 during the groove forming process. Figure 3 As shown, from Figure 3 It can be seen that when W1 is within the reasonable range of 15μm to 150μm, the power generation efficiency of the solar cell is higher. For example, W1 can be 15μm, 20μm, 25μm, 30μm, 35μm, 40μm, 45μm, 50μm, 55μm, 60μm, 65μm, 70μm, 75μm, 80μm, 85μm, 90μm, 95μm, 100μm, 105μm, 110μm, 115μm, 120μm, 125μm, 130μm, 135μm, 140μm, 145μm or 150μm, etc.

[0084] In other embodiments, Figure 1 As shown, 15 μm ≤ W2 ≤ 150 μm, so as to ensure that the contact area between the second gate line 8 and the second semiconductor layer 7 is within a reasonable range, thereby ensuring the current transmission efficiency and reducing the damage to the semiconductor substrate 1 during the groove forming process. Figure 4 As shown, from Figure 4 It can be seen that when W2 is in the reasonable range of 15μm to 150μm, the power generation efficiency of the solar cell is higher. For example, W2 can be 15μm, 20μm, 25μm, 30μm, 35μm, 40μm, 45μm, 50μm, 55μm, 60μm, 65μm, 70μm, 75μm, 80μm, 85μm, 90μm, 95μm, 100μm, 105μm, 110μm, 115μm, 120μm, 125μm, 130μm, 135μm, 140μm, 145μm or 150μm, etc.

[0085] In other embodiments, W2<W1≤3W2. This configuration can further appropriately reduce the groove width W2 of the passivation layer 2 on the light-facing side, thereby reducing the width of the second gate line 8 and thus reducing the light-shielding area of the second gate line 8. At the same time, it can also prevent the difference between W1 and W2 from being too large, which may lead to a large current difference between the first gate line 6 and the second gate line 8, thereby affecting the overall power generation efficiency. For example, W1 can be equal to 1.1W2, 1.3W2, 1.5W2, 1.8W2, 2W2, 2.3W2, 2.5W2, 2.8W2, or 3W2, etc.

[0086] In some embodiments, │W1-W2│≤5μm, matching S2<S1, the groove widths of the passivation layer 2 on the backlight side and the light-facing side are approximately equal, and at the same time matching S2<S1, so that the width S2 of the second grid line 8 on the light-facing side is smaller; in this way, when the light-facing side is the light-facing side, the smaller width S2 of the second grid line 8 can appropriately reduce the shading area of the second grid line 8, and at the same time, the groove width W2 of the passivation layer 2 on the light-facing side is approximately equal to the groove width W1 on the backlight side, thereby improving the transmission efficiency between the second grid line 8 and the second semiconductor layer 7, thereby improving the overall power generation efficiency of the solar cell.

[0087] In other embodiments, 0.1≤h2 / S2≤0.8, when the aspect ratio of the second grid line 8 is greater than 0.8, the height of the second grid line 8 needs to be higher, resulting in more consumption of metal raw materials, and the second grid line 8 will block the light on its side, resulting in a decrease in light utilization, and is also not conducive to the welding effect of the welding strip; the width of the second grid line 8 is also required to be narrow, resulting in a larger contact resistance between the second grid line 8 and the second semiconductor layer 7, and a decrease in current transmission efficiency. When the aspect ratio of the second grid line 8 is less than 0.1, the width of the second grid line 8 is required to be wider, which will increase the shading area of the second grid line 8, reduce the light absorption utilization rate, and increase the metal composite loss; at the same time, the height of the second grid line 8 is required to be lower, which easily causes the second grid line 8 to be disconnected, affecting current transmission. Therefore, in order to balance the above two aspects, the present application has h2 / S2 of 0.1 to 0.8, so as to reduce the shading area and light loss, improve the light absorption utilization rate, ensure the welding effect of the welding strip, reduce the risk of grid breakage during printing and reduce metal composite loss. For example, h2 / S2 can be 0.1, 0.12, 0.15, 0.18, 0.2, 0.22, 0.25, 0.28, 0.3, 0.32, 0.35, 0.38, 0.4, 0.42, 0.45, 0.48, 0.5, 0.52, 0.55, 0.58, 0.6, 0.62, 0.65, 0.68, 0.7, 0.72, 0.75, 0.78 or 0.8, etc. Figure 5 As shown, from Figure 5It can be seen that the larger h2 / S2 is, the smaller the current loss is. However, considering that when the aspect ratio of the second gate line 8 is greater than 0.4, the product yield is low and the width of the second gate line 8 is too narrow, resulting in poor contact, so h2 / S2 is set to 0.4 in this solution.

[0088] In some embodiments, if the height of second gridline 8 is too high, it will lead to a large consumption of metal raw materials, and second gridline 8 will block the light from its side, resulting in reduced light utilization, and also detrimental to the welding effect of the welding ribbon; if the height of second gridline 8 is too small, it will easily cause second gridline 8 to break, affecting current transmission. In view of the above two situations, in this technical solution, the height h2 of second gridline 8 is set within a reasonable range of 5μm ≥ h2 ≥ 20μm, reducing the shading area and light loss while ensuring product yield.

[0089] Illustratively, the height h2 of the second gate line 8 may be 5 μm, 6 μm, 8 μm, 10 μm, 11 μm, 12 μm, 13 μm, 14 μm, 15 μm, 16 μm, 17 μm, 18 μm, 19 μm, or 20 μm.

[0090] In other embodiments, it is considered that if the second gate line 8 is too wide, the shading area and light loss will increase, and the light absorption utilization rate will be reduced; if the second gate line 8 is too narrow, the transmission resistance of the second gate line 8 will increase, and the photoelectric conversion efficiency will be reduced. In view of the above two situations, in this technical solution, the width S2 of the second gate line 8 is set within a reasonable range of 50μm≤S2≤200μm to reduce the shading area and light loss, improve the light absorption utilization rate, reduce the transmission resistance of the second gate line 8, and improve the current transmission efficiency. Exemplarily, the width S2 of the second gate line 8 can be 50μm, 60μm, 80μm, 100μm, 120μm, 140μm, 150μm, 180μm or 200μm, etc.

[0091] In other embodiments, Figure 1 As shown, the height of the first gate line 6 along the thickness direction of the semiconductor substrate 1 is h1. Similar to the design principle of the second gate line 8, in this technical solution, 0.2 ≤ h1 / S1 ≤ 0.3 is used to reduce the shading area and light loss, improve light absorption and utilization, reduce damage to the semiconductor substrate 1, and reduce the risk of gate breakage during printing. For example, h1 / S1 can be 0.2, 0.21, 0.22, 0.23, 0.24, 0.25, 0.26, 0.27, 0.28, 0.29, or 0.3, etc.

[0092] In some embodiments, the design principle is the same as that of the second gate line 8. In this technical solution, the width S1 of the first gate line 6 is set within a reasonable range of 50 μm ≤ S1 ≤ 200 μm to reduce the shading area and light loss, improve the light absorption utilization rate, reduce the transmission resistance of the first gate line 6, and improve the current transmission efficiency. Exemplarily, the width S1 of the first gate line 6 can be 50 μm, 60 μm, 80 μm, 100 μm, 120 μm, 140 μm, 150 μm, 180 μm or 200 μm, etc.

[0093] In some embodiments, the design principle of the second gate line 8 is the same. In this technical solution, the height h1 of the first gate line 6 is set within a reasonable range of 5μm≤h1≤15μm, thereby reducing the shading area and light loss while ensuring product yield. For example, the height h1 of the first gate line 6 can be 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, 11μm, 12μm, 13μm, 14μm, or 15μm.

[0094] In some embodiments, as Figure 6 As shown, in order to reduce the transmission resistance between the second semiconductor layer 7 and the second gate line 8, a full low sheet resistance doping layer (Low Sheet Resistance) can be formed, so that the doping concentration of the area where the second semiconductor layer 7 is electrically connected to the second gate line 8 is higher than the doping concentration of the remaining area. The second opening 2c can be set corresponding to the area of the second semiconductor layer 7 with a higher doping concentration, that is, the orthographic projection of the second opening 2c on the light-facing surface and the orthographic projection of the area of the second semiconductor layer 7 with a higher doping concentration on the light-facing surface at least partially overlap. In this technical solution, along the direction perpendicular to the second gate line 8, the width of the unopened area of the passivation layer 2 is W3; 0.006≤W2 / W3≤0.125. This setting can achieve a lower transmission resistance between the second semiconductor layer 7 and the second gate line 8, while preventing the groove width W2 of the second opening 2c from being too wide, thereby reducing damage to the semiconductor substrate 1. Illustratively, W2 / W3 may be 0.006, 0.01, 0.02, 0.03, 0.04, 0.05, 0.06, 0.07, 0.08, 0.09, 0.10, 0.11, 0.12 or 0.125, etc.

[0095] It should be noted that the width W3 of the unopened area of the passivation layer 2 refers to the width of the unopened area of the passivation layer 2 on one side of a group of second openings 2c along the direction perpendicular to the second gate line 8, for example Figure 6 The width of the unopened area of the passivation layer 2 on the left side of a group of second openings 2c.

[0096] In some embodiments, 1.2 mm ≤ W3 ≤ 2.5 mm, to ensure that the width of the unopened area of the passivation layer 2 on one side of the second opening 2 c remains within a reasonable range, thereby ensuring the passivation effect of the second semiconductor layer 7 while lowering the transmission resistance between the second semiconductor layer 7 and the second gate line 8, thereby improving the power generation efficiency of the solar cell. For example, W3 can be 1.2 mm, 1.3 mm, 1.4 mm, 1.5 mm, 1.6 mm, 1.7 mm, 1.8 mm, 1.9 mm, 2.0 mm, 2.1 mm, 2.2 mm, 2.3 mm, 2.4 mm, or 2.5 mm, etc.

[0097] In some embodiments, as Figure 7 and Figure 8 As shown, in order to reduce the transmission resistance between the second semiconductor layer 7 and the second gate line 8, an SE (Selective Emitter) structure can be formed. Specifically, the second semiconductor layer 7 includes a first region 7a and a second region, and the doping concentration of the first region 7a is greater than the doping concentration of the second region. The second opening 2c can be provided corresponding to the first region 7a of the second semiconductor layer 7 with a higher doping concentration, that is, the orthographic projection of the second opening 2c on the light-facing surface at least partially overlaps with the orthographic projection of the first region 7a of the second semiconductor layer 7 on the light-facing surface.

[0098] In some embodiments, as Figure 7 As shown, along a direction perpendicular to the second gridline 8, the distance W2 between the edge of the second opening 2c near the third edge and the edge of the second opening 2c near the fourth edge in the same group is less than or equal to the width of the first region 7a, and the orthographic projection of the edge of the second opening 2c on the light-facing surface overlaps with the orthographic projection of the first region 7a on the light-facing surface. In other words, the orthographic projection of the second opening 2c on the light-facing surface is located within the orthographic projection of the first region 7a on the light-facing surface. This arrangement ensures that the second gridline 8 is electrically connected to the first region 7a of the second semiconductor layer 7 with a higher doping concentration, further reducing the transmission resistance between the second gridline 8 and the second semiconductor layer 7, thereby improving the power generation efficiency of the solar cell.

[0099] In some embodiments, the doping concentration of the second region is lower than the doping concentration of the first region 7a, the passivation effect of the second region is better, and the recombination loss is less. Therefore, in this technical solution, along the direction perpendicular to the second gate line 8, the width of the portion of the second region that does not correspond to the second opening 2c is W5, 0.006≤W2 / W5≤0.12. Among them, the width of the portion of the second region that does not correspond to the second opening 2c can refer to the width of the overlap between the non-opening portion of the passivation layer 2 and the second region. Such a setting can ensure that the second semiconductor layer 7 has a second region of a reasonable width, so as to improve the carrier collection efficiency of the solar cell and reduce recombination.

[0100] Illustratively, W2 / W5 can be 0.006, 0.01, 0.02, 0.03, 0.04, 0.05, 0.06, 0.07, 0.08, 0.09, 0.1, 0.11 or 0.12, etc.

[0101] In some embodiments, the width of the portion of the second area that does not correspond to the second opening 2c is set within a reasonable range of 1.2mm≤W5≤2.5mm to ensure that the second semiconductor layer 7 has a second area of reasonable width to improve the carrier collection efficiency of the solar cell and reduce recombination. For example, W5 can be 1.2mm, 1.3mm, 1.4mm, 1.5mm, 1.6mm, 1.7mm, 1.8mm, 1.9mm, 2mm, 2.1mm, 2.2mm, 2.3mm, 2.4mm or 2.5mm, etc. It should be noted that the width W5 of the portion of the second area that does not correspond to the second opening 2c refers to the width of the portion of the second area on one side of a group of second openings 2c that does not correspond to the second opening 2c along the direction perpendicular to the second grid line 8, for example Figure 7 The second area on the left side of the group of second openings 2c does not correspond to the width of the second opening 2c portion.

[0102] In some embodiments, along the direction perpendicular to the second gate line 8, the width of the portion of the first region 7a that does not correspond to the second opening 2c is W6, and 0.008≤W2 / W6≤3. The width of the portion of the first region 7a that does not correspond to the second opening 2c may refer to the width of the overlap between the portion of the passivation layer 2 that does not have an opening and the first region 7a. In this technical solution, W2 / W6 is set within a reasonable range of 0.008 to 3, which can further ensure that the second gate line 8 is conductively connected to the first region 7a of the second semiconductor layer 7 with a higher doping concentration, which is beneficial to reducing the transmission loss between the second gate line 8 and the second semiconductor layer 7. It should be noted that the width W6 of the portion of the first region 7a that does not correspond to the second opening 2c refers to the sum of the widths of the portions of the first region 7a on both sides of a group of second openings 2c that do not correspond to the second openings 2c. The widths of the portions of the first region 7a on both sides of a group of second openings 2c that do not correspond to the second openings 2c may be the same or different; for example Figure 7 In the figure, the sum of the widths of the first areas 7a on the left and right sides of a group of second openings 2c that do not correspond to the second openings 2c is W6.

[0103] Illustratively, W2 / W6 can be 0.008, 0.01, 0.1, 0.5, 0.8, 1, 1.2, 1.5, 1.8, 2, 2.2, 2.5, 2.8 or 3, etc.

[0104] In some embodiments, along a direction perpendicular to the second gate line 8, 50 μm ≤ W6 ≤ 180 μm, to further ensure that the second gate line 8 is electrically connected to the first region 7 a of the second semiconductor layer 7 with a higher doping concentration, thereby reducing transmission loss between the second gate line 8 and the second semiconductor layer 7. For example, W6 can be 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, 110 μm, 120 μm, 130 μm, 140 μm, 150 μm, 160 μm, 170 μm, or 180 μm, etc.

[0105] In other embodiments, Figure 8 As shown, along a direction perpendicular to the second gate line 8, the distance W2 between the edge of the second opening 2c in the same group, which is close to the third edge, and the edge of the second opening 2c in the same group, which is close to the fourth edge, is greater than the width of the first region 7a, and the orthographic projection of the edge of the second opening 2c on the light-facing surface overlaps with the orthographic projection of the second region on the light-facing surface. In other words, the orthographic projection of the second opening 2c on the light-facing surface partially overlaps with the orthographic projections of both the second region and the first region 7a on the light-facing surface. This arrangement can appropriately reduce the total area of the second openings 2c in the same group, thereby reducing damage to the semiconductor substrate 1 during the opening process.

[0106] In some embodiments, the width of the first region 7a along the direction perpendicular to the second gate line 8 is W7, and 15 μm ≤ W7 ≤ 120 μm, so as to further reduce the transmission loss between the second gate line 8 and the second semiconductor layer 7. Exemplarily, W7 can be 15 μm, 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, 110 μm, or 120 μm, etc.

[0107] The width of the second region that does not correspond to the second opening 2c is W8, 1.2mm≤W8≤2.5mm, to ensure that the second semiconductor layer 7 has a second region of reasonable width, so as to improve the carrier collection efficiency of the solar cell and reduce recombination. For example, W8 can be 1.2mm, 1.3mm, 1.4mm, 1.5mm, 1.6mm, 1.7mm, 1.8mm, 1.9mm, 2mm, 2.1mm, 2.2mm, 2.3mm, 2.4mm or 2.5mm, etc. It should be noted that the width W8 of the second region that does not correspond to the second opening 2c refers to the width of the second region on one side of a group of second openings 2c that does not correspond to the second opening 2c, for example Figure 8 The second area on the left side of the group of second openings 2c does not correspond to the width of the second opening 2c portion.

[0108] In some embodiments, the width of the second region corresponding to the second opening 2c is W9, 10μm≤W9≤130μm. This setting can prevent W9 from being too large, which will increase the transmission resistance between the second gate line 8 and the second semiconductor layer 7, and can also prevent W9 from being too small, which will increase the recombination. For example, W9 can be 10μm, 20μm, 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, 90μm, 100μm, 110μm, 120μm or 130μm, etc. It should be noted that the width W9 of the second region corresponding to the second opening 2c refers to the sum of the widths of the second regions on both sides of a group of second openings 2c corresponding to the second opening 2c. The widths of the second regions on both sides of a group of second openings 2c corresponding to the second opening 2c can be the same or different; for example Figure 8 In the embodiment, the sum of the widths of the second areas on the left and right sides of a group of second openings 2c corresponding to the second openings 2c is W9.

[0109] In some embodiments, 0.006 ≤ W7 / W8 ≤ 0.1 to ensure that the second semiconductor layer 7 has a second region of reasonable width, thereby improving the carrier collection efficiency of the solar cell and reducing recombination. W7 / W8 can be 0.006, 0.01, 0.02, 0.03, 0.04, 0.05, 0.06, 0.07, 0.08, 0.09, or 0.1, etc.

[0110] In some embodiments, 0.08≤W7 / W9≤3, ensuring low transmission loss between the second gate line 8 and the second semiconductor layer 7, thereby improving the power generation efficiency of the solar cell. W7 / W9 can be 0.08, 0.1, 0.2, 0.5, 0.8, 1, 1.2, 1.5, 1.8, 2, 2.2, 2.5, 2.8, or 3.

[0111] In some embodiments, as Figure 9 As shown, when the entire first semiconductor layer 4 is provided on the backlight side, the width of the first semiconductor layer 4 along the direction perpendicular to the first gate line 6 is D1. In this technical solution, W1 / D1 is set within a reasonable range of 0.007≤W1 / D1≤0.15 to avoid excessive groove width of the passivation layer 2 on the backlight side, thereby ensuring the carrier collection efficiency of the first semiconductor layer 4. At the same time, it also ensures that there is an appropriate contact area and low contact resistance between the first gate line 6 and the first semiconductor layer 4, reducing the carrier transmission loss. Exemplary, W1 / D1 can be 0.007, 0.01, 0.02, 0.05, 0.08, 0.1, 0.12 or 0.15, etc.

[0112] In some embodiments, as Figure 10As shown, when the first semiconductor layer 4 is partially provided on the backlight surface, for example, when the first semiconductor layer 4 is arranged in a quasi-F shape on the backlight surface, the width of the first semiconductor layer 4 not corresponding to the first opening 2b in the direction perpendicular to the first gate line 6 is W 13 , that is, the width of the first semiconductor layer 4 corresponding to the ungrooved area is W 13 , 10μm≤W 13 ≤200μm. Such a setting can ensure that the first semiconductor layer 4 has a reasonable width to improve the carrier collection efficiency and reduce recombination. For example, W 13 It can be 10 μm, 30 μm, 50 μm, 80 μm, 100 μm, 120 μm, 150 μm, 180 μm or 200 μm, etc. It should be noted that the first semiconductor layer 4 does not correspond to the width W of the first opening 2b. 13 It means that the width of the first semiconductor layer 4 on both sides of a group of first openings 2b does not correspond to the first openings 2b, for example Figure 10 The first semiconductor layer 4 on the left and right sides of a group of first openings 2b does not correspond to the width of the first openings 2b. It can be understood that Figure 10 The black portion is the passivation layer 2, which may be removed or partially retained during the hole opening process.

[0113] In some embodiments, 0.08≤W1 / W 13 ≤2, so as to ensure the efficiency of collecting carriers in the first semiconductor layer 4 while taking into account the low transmission loss between the first semiconductor layer 4 and the first gate line 6. For example, W1 / W 13 It can be 0.08, 0.1, 0.2, 0.5, 0.8, 1, 1.2, 1.5, 1.8 or 2, etc.

[0114] Along the direction perpendicular to the first gate line 6, the width of the isolation region between adjacent first semiconductor layers 4 is W 14 , 100μm≤W 14 ≤1000 μm, that is, the width of the area not covered by the first semiconductor layer 4 is W 14 , so that sunlight can be irradiated to the semiconductor substrate 1 through the isolation region, thereby improving the light absorption rate and power generation rate. 14 It may be 100 μm, 200 μm, 300 μm, 400 μm, 500 μm, 600 μm, 700 μm, 800 μm, 900 μm or 1000 μm.

[0115] In some embodiments, if W1 / W 14If W1 / W is less than 0.15, the distance between the edges of the first openings 2b on both sides of the same group needs to be smaller, resulting in a larger contact resistance between the first gate line 6 and the first semiconductor layer 4, and a lower current transmission efficiency; at the same time, the width of the isolation region needs to be wider, resulting in poor lateral transmission and a lower open circuit voltage. 14 If the ratio is greater than 1.2, the distance between the edges of the first openings 2b in the same group must be larger, which in turn widens the first gate lines 6, blocking light and reducing light absorption, leading to increased metal recombination losses. Furthermore, the width of the isolation region must be narrow, which reduces the passivation effect. In view of these two factors, in this technical solution, 0.15 ≤ W1 / W14 ≤ 1.2 is used to ensure current transmission efficiency and increase open-circuit voltage while improving light absorption and reducing metal recombination losses.

[0116] Illustratively, W1 / W14 may be 0.15, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 1, 1.1 or 1.2, etc.

[0117] In some embodiments, as Figure 11 As shown, a first seed layer 5 is provided in the first opening 2b. The first seed layer 5 can achieve a good electrical connection between the first gate line 6 and the first semiconductor layer 4, and can prevent the metal elements in the first gate line 6 thereon from diffusing into the semiconductor substrate 1, thereby reducing recombination. The first gate line 6 can surround the top surface and partial side surface of the first seed layer 5 (such as Figure 1 As shown), alternatively, the first gate line 6 may also only contact the top surface of the first seed layer 5, that is, the first gate line 6 is formed on the top surface of the first seed layer 5, and the top surface is the side surface of the first seed layer 5 away from the semiconductor substrate.

[0118] The width of the first seed layer 5 can be greater than, less than, or equal to the width of the first opening 2b. Specifically, the width S3 of the first seed layer 5 is 10 μm to 80 μm to ensure a good electrical connection. For example, S3 can be 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, or 80 μm.

[0119] The height h3 of the first seed layer 5 is 0.5um-5um to ensure the barrier effect of the first seed layer 5. For example, h3 can be 0.5um, 0.1um, 1.5um, 2um, 2.5um, 3um, 3.5um, 4um, 4.5um or 5um.

[0120] The ratio of the width S1 of the first gate line 6 to the width S3 of the first seed layer 5 is 1.2 to 20, that is, 1.2≤S1 / S3≤20, to ensure a good electrical connection effect. For example, S1 / S3 can be 1.2, 1.5, 2, 5, 8, 10, 12, 15, 18 or 20. Figure 13 As shown, from Figure 13 It can be seen that when S1 / S3 is in the reasonable range of 1.2 to 20, the series resistance is low.

[0121] The ratio of the height h1 of the first gate line 6 to the height h3 of the first seed layer 5 is 1.2 to 30, that is, 1.2≤h1 / h3≤30, to prevent the first seed layer 5 from being too low in height and having too little contact area with the first gate line 6, resulting in high transmission resistance, and to avoid the first seed layer 5 being too high in height, which makes it difficult to process and form, and results in low yield. For example, h1 / h3 can be 1.2, 1.5, 2, 5, 8, 10, 12, 15, 18, 20, 22, 25, 28 or 30, etc. Figure 14 As shown, from Figure 14 It can be seen that when h1 / h3 is in the reasonable range of 1.2 to 30, the series resistance is low.

[0122] In other embodiments, Figure 12 As shown, a second seed layer 9 is disposed within the second opening 2c. The second seed layer 9 can achieve a good electrical connection between the second gate line 8 and the second semiconductor layer 7, and can prevent the metal elements in the second gate line 8 thereon from diffusing into the semiconductor substrate 1, thereby reducing recombination. The positional relationship between the second gate line 8 and the second seed layer 9 can be referred to the description of the first gate line 6 and the first seed layer 5 above, and will not be repeated here.

[0123] The width of the second seed layer 9 can be greater than, less than, or equal to the width of the second opening 2c. Specifically, the width S4 of the second seed layer 9 is 10 μm to 40 μm to ensure a good electrical connection. For example, S4 can be 10 μm, 20 μm, 30 μm, or 40 μm.

[0124] The height h4 of the second seed layer 9 is 0.5um-5um to ensure the barrier effect of the second seed layer 9. For example, h4 can be 0.5um, 0.1um, 1.5um, 2um, 2.5um, 3um, 3.5um, 4um, 4.5um or 5um.

[0125] The ratio of the width S2 of the second gate line 8 to the width S4 of the second seed layer 9 is 1.2 to 20, that is, 1.2≤S2 / S4≤20, to ensure a good electrical connection. For example, S2 / S4 can be 1.2, 1.5, 2, 5, 8, 10, 12, 15, 18 or 20.

[0126] The ratio of the height h2 of the second gate line 8 to the height h4 of the second seed layer 9 is 1.2 to 40, that is, 1.2≤h2 / h4≤40. This prevents the second seed layer 9 from being too low, resulting in too little contact area with the second gate line 8 and high transmission resistance, and also prevents the second seed layer 9 from being too high, making it difficult to process and form, and resulting in low yield. For example, h2 / h4 can be 1.2, 1.5, 2, 5, 8, 10, 12, 15, 18, 20, 22, 25, 28, 30, 32, 35, 38, or 40, etc.

[0127] In some embodiments, as Figure 15 As shown, the passivation layer 2 has a heat-affected zone 2a surrounding the first opening 2b or the second opening 2c. Specifically, during the laser grooving process of the passivation layer 2, the area near the edge of the opening is not removed but is affected by the heat of the laser, which is called the heat-affected zone 2a. The heat-affected zone 2a is formed around the first opening 2b or the second opening 2c. The shape of the first opening 2b and / or the second opening 2c can be circular, elliptical, rectangular, or other shapes. The surrounding shape of the heat-affected zone 2a also changes with the shape of the first opening 2b or the second opening 2c, and its annular shape can be a circular ring, an elliptical ring, a rectangular ring, etc.

[0128] In some embodiments, the width of the heat-affected zone 2a is L, 1 μm ≤ L ≤ 5 μm, so as to avoid the heat-affected zone 2a being too wide and reducing the passivation effect. For example, L can be 1 μm, 2 μm, 3 μm, 4 μm or 5 μm.

[0129] In some embodiments, during the laser drilling process, the laser energy at the edge is appropriately increased, for example, greater than 200 J / cm 2 , the passivation layer 2 material in the heat-affected zone 2a will be opened, and a plurality of holes and / or cracks will be formed. The purpose of such a setting is that if no holes and / or cracks are formed in the heat-affected zone 2a, the thermal damage to the semiconductor layer corresponding to the position of the heat-affected zone 2a cannot be repaired, and in this embodiment, the holes and / or cracks are filled with a conductive material, and the conductive material is electrically connected to the semiconductor layer. With such a setting, the gate line can be electrically connected to the semiconductor layer through the opening while also being electrically connected to the semiconductor layer through the conductive material, and the semiconductor layer at the position corresponding to the holes and / or cracks is also a heat concentration area with greater damage (heat concentration areas are prone to holes and / or cracks), and the conductive material can repair the damage at this position.

[0130] In some embodiments, as Figure 16 and Figure 17As shown, the first openings 2b of the same group corresponding to the same first gate line 6 can be distributed in at least one row, and each row includes at least two first openings 2b spaced apart along the extension direction of the first gate line 6. When each group of first openings 2b is provided in only one row, the multiple first openings 2b of the same group can be arranged in sequence along the extension direction of the first gate line 6; when a group of first openings 2b is provided in multiple rows, the multiple rows of first openings 2b are arranged in a direction perpendicular to the first gate line 6. For example, the multiple first openings 2b can be distributed in two rows, three rows or more rows. In this way, the multiple first openings 2b are distributed more evenly, and the positions where the first gate line 6 is electrically connected to the first semiconductor layer 4 are distributed more evenly, which is beneficial for the first gate line 6 to timely conduct the current at various positions of the first semiconductor layer 4 to avoid local overheating.

[0131] Among them, any adjacent first openings 2b do not overlap or partially overlap, which can be determined according to actual conditions.

[0132] like Figure 17 As shown, when a group of first openings 2b are arranged in multiple rows, the distance between the edges of the first openings 2b that are farthest apart along the direction perpendicular to the first grid lines 6 is W1. Figure 16-17 As shown, S1 may be greater than W1; S1 may also be equal to W1, which is not limited here.

[0133] In other embodiments, each group of first openings 2b includes continuously extending strip-shaped holes. Specifically, each group of first openings 2b may be one strip-shaped hole, or may include a plurality of strip-shaped holes arranged side by side.

[0134] In some embodiments, as Figure 18 and Figure 19 As shown, the same group of second openings 2c corresponding to the same second grid line 8 can be distributed in at least one row, with each row including at least two second openings 2c spaced apart along the extension direction of the second grid line 8. The arrangement of the second openings 2c can refer to the above description of the first openings 2b and will not be repeated here. In addition, any adjacent second openings 2c may not overlap or may partially overlap, which can be determined based on actual conditions.

[0135] In other embodiments, when |W1-W2|≤5μm, that is, W2 is close to W1, Figure 16 and Figure 18 Compared with the example, S2 is smaller than W2, and further satisfies 0.1≤S2 / W2<1, preferably, 0.5≤S2 / W2<1. With such a setting, the second gate line 8 can be designed to be narrower to reduce the light-shielding area of the light-facing surface. At the same time, the larger opening width can meet the alignment requirements, increase the process window, and improve the light absorption rate. At the same time, it will not cause the contact resistance of the first gate line 6 to increase, thereby ensuring the current transmission efficiency. This situation is a more preferred solution. Figure 17 and Figure 19Similarly, I will not elaborate on it.

[0136] In other embodiments, when |W1-W2|≤5μm, that is, W2 is close to W1, Figure 20 For example, S2 is close to or equal to W2, and further satisfies S2 / W2=1. In this way, the second gate line 8 is basically consistent with the opening width design, which satisfies the light-shielding problem on the light-facing surface. This situation places stricter requirements on the process window for laying the gate line on the opening. Figure 21 When a group of second openings 2c are arranged in multiple rows, the distance between the edges of the farthest first openings 2b along the direction perpendicular to the second grid lines 8 is W2, and the size relationship and effect are not further described.

[0137] In other embodiments, when |W1-W2|≤5μm, that is, W2 is close to W1, Figure 20 For example, S2 can be greater than W2, and further satisfy 1<S2 / W2≤3. In this way, the second gate line 8 is larger than the opening width. There are two ways to understand it. One is that S2 is not widened but W2 is reduced. This depends on the improvement of the conductivity of the subsequent barrier layer slurry or plating layer, and can meet the conductive contact requirements at a smaller slot width; the other is that S2 is appropriately widened to be greater than W2. In this case, the requirements for the gate line slurry laying process on the opening are more relaxed, the allowable process deviation can be larger, and the process window is larger.

[0138] In other embodiments, when W2 < W1 and W2 < S2, 1 ≤ S1 / W1 ≤ 4 and 1 ≤ S2 / W2 ≤ 3. The opening width of the light-facing side is smaller than that of the backlight side, thereby minimizing damage to the light-facing side. At the same time, the gate line widths of both the light-facing side and the backlight side are greater than or equal to the opening widths of the corresponding sides, thereby taking into account both process alignment and transmission loss. This minimizes the light-shielding area of the second gate line 8 while ensuring low transmission loss between the first gate line 6 and the first semiconductor layer 4.

[0139] In other embodiments, each group of second openings 2c includes continuously extending strip-shaped holes. Specifically, each group of second openings 2c may be one strip-shaped hole, or may include a plurality of strip-shaped holes arranged side by side.

[0140] In some embodiments, when each group of first openings 2b is distributed at intervals and each group of second openings 2c is also distributed at intervals, the spacing between adjacent openings in each group of second openings 2c is smaller than the spacing between adjacent openings in each group of first openings 2b, that is, the number of second openings 2c is greater and the density is greater, which is conducive to making the area of the second openings 2c smaller and reducing the width of the second gate line 8 to reduce the shading area, while ensuring lower transmission loss between the second gate line 8 and the second semiconductor layer 7.

[0141] In some embodiments, the first grid lines 6 and / or the second grid lines 8 are made of a copper paste material, and the first grid lines 6 and / or the second grid lines 8 after curing and forming include copper powder and organic matter. Copper has a good electrical conductivity and is inexpensive, so the first grid lines 6 and / or the second grid lines 8 in this technical solution include copper powder, which reduces manufacturing costs compared to the prior art in which the first grid lines 6 and / or the second grid lines 8 only include silver. In addition, the organic matter has good viscosity, and the particles contained in the copper powder can be adhered by the organic matter. The organic matter can also increase the adhesion between the first grid lines 6 and / or the second grid lines 8 and the backlight surface, preventing the first grid lines 6 and / or the second grid lines 8 from separating from the backlight surface.

[0142] Copper powder at least includes flaky particles and spherical particles. Wherein, the flaky particles are flat as a whole, and the edges of the flaky particles can be smooth edges, jagged edges or any irregular edges. Spherical particles can be spherical, ellipsoidal, quasi-spherical or quasi-ellipsoidal, etc. The contact area between the flaky particles and other conductive particles is large, which is conducive to the reduction of contact resistance, while the contact area between the spherical particles and organic matter is large, which is conducive to the molding of the grid line. Based on this, in the present technical solution, the copper powder includes flaky particles and spherical particles simultaneously, which can not only make the first grid line 6 and / or the second grid line 8 have suitable resistivity, but also facilitate the printing molding of the first grid line 6 and / or the second grid line 8.

[0143] In other embodiments, Figure 22 As shown, the first grid line 6 and / or the second grid line 8 may further include a main portion 101 and a spreading portion 102 arranged in a direction perpendicular to the first grid line 6 or the second grid line 8. The spreading portion 102 is formed on both sides of the main portion 101. That is, during the process of manufacturing the grid lines, after the slurry is printed or laser transferred and before the slurry is cured, the slurry (such as one or more organic substances in the slurry) diffuses toward the battery cell surfaces on both sides of the main portion 101, and the spreading portions 102 are formed on both sides of the main portion 101.

[0144] The width W of the spreading portion 102 21 The width W of the main body 101 20 The width of the spreading portion 102 is 5%-50% of the width of the main portion 101 to reduce the risk of leakage while ensuring the adhesion between the first gate line 6 and the backlight surface. For example, the width of the spreading portion 102 is 5%, 10%, 15%, 20%, 25%, 30%, 35%, 40%, 45% or 50% of the width of the main portion 101.

[0145] It should be noted that, in the foregoing, the width of the grid line is the sum of the widths of the main body 101 and the spreading portion 102 , while the height of the grid line is the same as the height of the main body 101 .

[0146] Along the thickness direction of the semiconductor substrate 1, the height of the main body 101 is h0, and the height of the spreading portion 102 is h0', where h0'≤1 / 3h0. This technical solution ensures that the height h0' of the spreading portion 102 and the height h0 of the main body 101 are in a reasonable ratio, thereby preventing the height of the spreading portion 102 from being too high, which would result in a decrease in the cross-sectional area of the main body 101 and an increase in the resistivity, thereby ensuring the overall current transmission efficiency of the gate line. Exemplarily, h0' is 1 / 3h0, 0.3h0, 0.25h0, 0.2h0, 0.15h0, or 0.1h0, etc.

[0147] In some embodiments, the median particle size of the copper powder contained in the spreading portion 102 is smaller than the median particle size of the copper powder contained in the main portion 101. The copper powder particle size may also be an equivalent diameter. That is, the particle size of the majority of the copper powder contained in the spreading portion 102 is smaller than the particle size of the majority of the copper powder contained in the main portion 101. This configuration allows the particle size of the copper powder contained in the spreading portion 102 to better match the thickness of the spreading portion 102, thereby improving the conductive performance of the spreading portion 102.

[0148] In actual application, the material of the semiconductor substrate 1 can be selected from materials such as silicon (Si) or germanium (Ge) or materials such as gallium arsenide (GaAs). Obviously, in terms of conductivity type, the semiconductor substrate 1 can be an intrinsic conductive substrate, an n-type conductive substrate or a p-type conductive substrate. Optionally, the semiconductor substrate 1 is a p-type conductive substrate or an n-type conductive substrate. Compared with the intrinsic conductive substrate, the p-type conductive substrate or the n-type conductive substrate has better conductivity, so that the final solar cell has a lower body resistivity, thereby improving the efficiency of the solar cell.

[0149] For example, the semiconductor substrate 1 can be a p-type substrate or an n-type substrate. The n-type substrate has the advantages of long minority carrier lifetime, no light decay, and good weak light performance.

[0150] The first semiconductor layer 4 may include doped polycrystalline silicon. Doped polycrystalline silicon layers have higher carrier transport properties. Therefore, when the first semiconductor layer 4 is a doped polycrystalline silicon layer, the carrier transport efficiency is higher, which helps improve the photoelectric conversion efficiency of the solar cell. Of course, the first semiconductor layer 4 can also be one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon.

[0151] The second semiconductor layer 7 may include doped polycrystalline silicon, or the second semiconductor layer 7 may also be one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon.

[0152] In some embodiments, a first interface layer 3 is provided between the first semiconductor layer 4 and the semiconductor substrate 1, and a second interface layer is provided between the second semiconductor layer 7 and the semiconductor substrate 1. The passivation contact structure composed of the interface layer and the semiconductor layer has an excellent interface passivation effect and can achieve selective collection of carriers, reduce the carrier recombination rate in the region where the semiconductor layer is formed on the surface of the semiconductor substrate 1, and further improve the photoelectric conversion efficiency of the solar cell. The material and thickness of the first interface layer 3 can be set according to the material of the first semiconductor layer 4 and actual requirements, and the material and thickness of the second interface layer can be set according to the material of the second semiconductor layer 7 and actual requirements, and are not specifically limited here.

[0153] For example, the first semiconductor layer 4 may be a doped polysilicon layer, the first interface layer 3 may be a tunneling oxide layer, the second semiconductor layer 7 may be a doped polysilicon layer, and the second interface layer may be a tunneling oxide layer.

[0154] In some embodiments, the light-facing surface of the semiconductor substrate 1 may be a velvet surface with multiple pyramid-like structures formed thereon. In the case where the light-facing surface is a light-facing surface, this helps increase the surface area of the light-facing surface, thereby improving the light trapping effect and light absorption rate of the light-facing surface. Of course, the light-facing surface may also be a polished surface.

[0155] The materials of the first semiconductor layer 4 and the second semiconductor layer 7 can be silicon (Si), germanium (Ge), silicon carbide (SiCx), or gallium arsenide (GaAs). In terms of conductivity type, the first semiconductor layer 4 can be an n-type doped layer, and the second semiconductor layer 7 can be a p-type doped layer; alternatively, the first semiconductor layer 4 can be a p-type doped layer, and the second semiconductor layer 7 can be an n-type doped layer.

[0156] An embodiment of the present invention further provides a method for manufacturing a solar cell. The method can be used to prepare the solar cell described in any of the above embodiments. The method for manufacturing a solar cell comprises the following steps:

[0157] S100: providing a semiconductor substrate 1, wherein the semiconductor substrate 1 has a backlight surface and a light-facing surface opposite to each other.

[0158] Prior to this step, in some embodiments, the semiconductor substrate 1 may be placed in a polishing and cleaning machine to remove the damaged layer of the semiconductor substrate 1 using a polishing solution. Furthermore, in this step, the morphology of the backlight side and the light-facing side of the semiconductor substrate 1 after polishing and cleaning may be adjusted by controlling parameters such as temperature, time, cleaning solution type, and cleaning solution concentration. It should be noted that in some examples, the polishing and cleaning step may be omitted.

[0159] S200: forming a first semiconductor layer 4 on the backlight surface of the semiconductor substrate 1;

[0160] The first semiconductor layer 4 can be additionally formed on the backlight surface of the semiconductor substrate 1 by a deposition technique, or can be formed within the semiconductor substrate 1 by diffusion, ion implantation, or the like.

[0161] S300: forming a second semiconductor layer 7 on the light-facing surface of the semiconductor substrate 1 , wherein the conductivity type of the second semiconductor layer 7 is opposite to that of the first semiconductor layer 4 ;

[0162] S400: forming a passivation layer 2 on a side of the first semiconductor layer 4 facing away from the semiconductor substrate 1 and on a side of the second semiconductor layer 7 facing away from the semiconductor substrate 1;

[0163] Specifically, the passivation layer 2 may be formed by deposition or the like. The material and structure of the passivation layer 2 may be referred to above and will not be described in detail here.

[0164] S500: opening a plurality of first openings 2b on the passivation layer 2 on the backlight side, and opening a plurality of second openings 2c on the passivation layer 2 on the light-facing side;

[0165] Specifically, a laser grooving process may be used to form multiple groups of first openings 2b and multiple groups of second openings 2c on the passivation layer 2. In some embodiments, after this step, the cell may be cleaned to remove dust particles generated during the grooving process.

[0166] S600: forming first gate lines 6 on the first passivation layer 2, each first gate line 6 being electrically connected to the first semiconductor layer 4 through a group of first openings 2b;

[0167] S700: forming second gate lines 8 on the second passivation layer 2, each second gate line 8 being electrically connected to the second semiconductor layer 7 through a group of second openings 2c;

[0168] The first grid lines 6 and / or the second grid lines 8 can be formed using processes such as screen printing, electroplating, sputtering, or evaporation. A relatively inexpensive conductive metal such as copper paste is added to the non-burn-through paste to reduce the manufacturing cost of the grid lines. In some embodiments, after this step, the cell can be dried to facilitate the rapid formation of the grid lines.

[0169] Along the direction perpendicular to the first gate line 6 or the second gate line 8, the distance between the hole edge close to the first edge and the hole edge close to the second edge in the first opening 2b of the same group is W1, and the distance between the hole edge close to the third edge and the hole edge close to the fourth edge in the second opening 2c of the same group is W2; the width of the first gate line 6 is S1, and the width of the second gate line 8 is S2; wherein, │W1-W2│≤5μm, and S2 / W2<S1 / W1; or, W2<W1, and S2>W2.

[0170] Compared with the prior art, the beneficial effects of the solar cell manufacturing method are the same as those of the above-mentioned solar cell, which will not be described in detail here.

[0171] In some embodiments, the width of the first opening 2b is 0.9 to 1.1 times the laser spot width, for example, 0.9, 0.92, 0.95, 0.98, 1, 1.02, 1.05, 1.08, or 1.1 times the laser spot width. When the width of the first opening 2b is greater than the laser spot width, a heat-affected zone 2a is formed around the first opening 2b to improve current transmission efficiency.

[0172] The width of the second opening 2c is 0.6 to 0.75 of the laser spot width, so as to appropriately reduce the size of the second opening 2c and, in turn, the width of the second grid line 8, thereby reducing the light shielding area and improving light absorption efficiency. For example, the width of the second opening 2c is 0.6, 0.62, 0.65, 0.68, 0.7, 0.72, or 0.75 of the laser spot width.

[0173] In addition, the present application also provides a photovoltaic assembly, which includes a plurality of solar cells provided in any of the above embodiments and at least one interconnecting member, wherein the interconnecting member connects two adjacent solar cells in series or in parallel. Specifically, the two adjacent solar cells are a first solar cell and a second solar cell, respectively, and the interconnecting member connects a first grid line of the first solar cell and extends to a second grid line of the second solar cell. Similarly, the interconnecting member is analogous to form an interconnection of multiple solar cells.

[0174] In some embodiments, when laser grooving is used and then electroplating or evaporating electrodes, the passivation layer can be structured by reasonably controlling the laser energy, and the passivation layer can be locally grooved more accurately, so that a passivation layer reserved portion exists at the groove position. The passivation layer reserved portion can protect the underlying layer structure from being damaged by the laser, maintain a good morphology and passivation effect, and at the same time is conducive to increasing the adhesion of the electrode and improving the electrode contact.

[0175] At the same time, the reserved portion of the passivation layer is used as the electrode growth point to improve the adhesion of the electrode to the battery surface, thereby improving the electrode contact stability. After the local grooves of the first protective layer are locally grooved by laser irradiation, an additional wet etching step can be added to clean the grooved locations. Of course, under appropriate laser energy conditions, this wet etching step can be omitted and a better groove morphology can be achieved. For example, under picosecond laser conditions, the laser energy density is adjusted to 2.6J / cm2.

[0176] Compared with the prior art, the beneficial effects of the photovoltaic module provided by the embodiment of the present application are the same as the beneficial effects of the above-mentioned solar cell and the method for manufacturing the solar cell, and are not described in detail here.

[0177] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0178] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A solar cell, characterized in that: include: A semiconductor substrate having a backlight surface and a light-facing surface opposite to each other; A first semiconductor layer is provided on the backlight surface; a second semiconductor layer, disposed on the light-facing surface, the second semiconductor layer having a conductivity type opposite to that of the first semiconductor layer; a passivation layer having a plurality of first openings and a plurality of second openings extending through the thickness of the passivation layer; a first gate line, at least a portion of which is electrically connected to the first semiconductor layer through a group of the first openings; and the first gate line has a first edge and a second edge opposite to each other in a direction perpendicular to the first gate line; a second gate line, at least a portion of the second gate line being electrically connected to the second semiconductor layer through a group of the second openings; and the second gate line having a third edge and a fourth edge opposite to each other in a direction perpendicular to the second gate line; Along a direction perpendicular to the first gate line or the second gate line, the distance between the edge of the first opening close to the first edge and the edge of the second opening close to the second edge in the same group is W1, and the distance between the edge of the third opening and the edge of the fourth opening in the same group is W2; the width of the first gate line is S1, and the width of the second gate line is S2; Where, │W1-W2│≤5μm, and S2 / W2≤S1 / W1; Alternatively, W2<W1 and W2<S2.

2. The solar cell according to claim 1, wherein When │W1-W2│≤5μm and S2 / W2≤S1 / W1, 1≤S1 / W1≤4, 0.1≤S2 / W2≤3; or, When W2<W1 and W2<S2, 1≤S1 / W1≤4, 1≤S2 / W2≤3.

3. The solar cell according to claim 1, wherein 15μm≤W1≤200μm; and / or, 15μm≤W2≤150μm.

4. The solar cell according to claim 1, wherein W2<W1≤3W2.

5. The solar cell according to claim 1, wherein The height of the second gate line is h2; 0.1≤h2 / S2≤0.8, and / or, 50μm≤S2≤200μm, 5μm≤h2≤20μm; And / or, the height of the first gate line is h1; 0.25≤h1 / S1≤0.3, and / or, 50 μm≤S1≤200 μm, 5 μm≤h1≤15 μm.

6. The solar cell according to claim 1, wherein Each group of first openings is distributed in at least one row, and each row includes at least two first openings spaced apart along the extending direction of the first grid lines; or each group of first openings is a strip-shaped hole extending along the extending direction of the first grid lines; Alternatively, each group of second openings is distributed in at least one row, and each row includes at least two second openings spaced apart along the extension direction of the second grid lines; or, each group of second openings is a strip-shaped hole extending along the extension direction of the second grid lines.

7. The solar cell according to claim 6, characterized in that The first openings in each group are spaced apart, the second openings in each group are spaced apart, and the spacing between adjacent openings in each group of the second openings is smaller than the spacing between adjacent openings in each group of the second openings.

8. The solar cell according to claim 1, wherein The entire first semiconductor layer is disposed on the backlight surface; along a direction perpendicular to the first gate line, the width of the first semiconductor layer is D1; 0.007≤W1 / D1≤0.

15.

9. The solar cell according to claim 1, wherein The first semiconductor layer is arranged on the backlight surface in a shape of a Chinese character "F" or a stripe; along the direction perpendicular to the first gate line, the width of the first semiconductor layer not corresponding to the first opening is W 13 , 10μm≤W 13 ≤200μm; 0.08≤W1 / W 13 ≤2; and / or, along the direction perpendicular to the first gate line, the width of the isolation region between adjacent first semiconductor layers is W 14 , 100μm≤W 14 ≤1000μm; 0.15≤W1 / W 14 ≤1.2。 10. The solar cell according to claim 1, wherein A first seed layer is disposed in the first opening, wherein the width of the first seed layer is S3 along a direction perpendicular to the first gate line; the height of the first seed layer is h3 along a thickness direction of the semiconductor substrate; 1.2≤S1 / S3≤20 and / or 1.2≤h1 / h3≤30; and / or, A second seed layer is provided in the second opening. The width of the second seed layer is S4 along the direction perpendicular to the second gate line. The height of the second seed layer is h4 along the thickness direction of the semiconductor substrate. 1.2≤S2 / S4≤20 and / or 1.2≤h2 / h4≤40.

11. The solar cell according to claim 1, wherein The passivation layer has a heat-affected zone surrounding the first opening or the second opening; the heat-affected zone includes a plurality of holes and / or cracks, the holes and / or cracks are filled with conductive material, and the conductive material is electrically connected to the first semiconductor layer or the second semiconductor layer.

12. The solar cell according to claim 1, wherein The first gate lines and / or the second gate lines include copper powder and organic matter; the copper powder includes at least flake particles and spherical particles.

13. The solar cell according to claim 12, wherein: The first grid line and / or the second grid line comprises a main portion and a spreading portion arranged in a direction perpendicular to the first grid line or the second grid line; The width of the spreading portion is 5%-50% of the width of the main portion; and / or, along the thickness direction of the semiconductor substrate, the height of the main portion is h0, the height of the spreading portion is h0', h0'≤1 / 3h0; and / or, the median value of the copper powder particle size contained in the spreading portion is smaller than the median value of the copper powder particle size contained in the main portion.

14. A photovoltaic module, characterized in that: The invention comprises a plurality of solar cells according to any one of claims 1 to 13 and at least one interconnecting member, wherein the interconnecting member connects two adjacent solar cells in series or in parallel; the two adjacent solar cells are respectively a first solar cell and a second solar cell, and the interconnecting member is electrically connected to a first grid line of the first solar cell and extends to be electrically connected to a second grid line of the second solar cell.

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