Solar cell and photovoltaic module

Abstract

The invention discloses a solar cell and a photovoltaic module, and relates to the field of photovoltaic technology, doping is carried out on a light-facing surface of a semiconductor substrate to form a first semiconductor layer, and the first semiconductor layer is provided with a first region and a second region; the passivation layer at least covers one side, deviating from the semiconductor substrate, of the first semiconductor layer; a first barrier layer and a first grid line, the first grid line is conductively connected with the first barrier layer, and the first grid line and the first barrier layer are arranged on one side, departing from the semiconductor substrate, of the first region; at least a part of the first barrier layer passes through the passivation layer and is conductively connected with at least a part of the first region; the surface doping concentration of the first region is a, the surface doping concentration of the second region is b, and a / b is greater than or equal to 2 and less than or equal to 20; the junction depth of the first region is c, the junction depth of the second region is d, and c-d is larger than or equal to 0.2 micrometer and smaller than or equal to 4 micrometers. Therefore, the manufacturing cost of the solar cell is reduced while the power generation efficiency of the solar cell is ensured.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic technology, and in particular to a solar cell and a photovoltaic module. Background Art

[0002] A solar cell is a device that converts sunlight into electrical energy. Specifically, when a solar cell is in operation, sunlight strikes the pn junction of the solar cell's semiconductor, forming new hole-electron pairs. Under the influence of the built-in electric field within the pn junction, the photogenerated holes flow to the p region, and the photogenerated electrons flow to the n region. Once the circuit is connected, current is generated.

[0003] As the photovoltaic industry's market and production capacity continue to expand, the industry's demand for silver paste has also surged. The price of silver paste has risen accordingly, costs have continued to rise, and profit margins have been increasingly squeezed. Summary of the Invention

[0004] The purpose of the present application is to provide a solar cell and a photovoltaic module to ensure the power generation efficiency of the solar cell while reducing the manufacturing cost of the solar cell.

[0005] In order to achieve the above objectives, this application provides the following technical solutions:

[0006] A solar cell comprising:

[0007] a semiconductor substrate containing a first conductivity type dopant element;

[0008] Doping the light-facing surface of the semiconductor substrate to form a first semiconductor layer, wherein the first semiconductor layer contains a second conductive type doping element opposite to the first conductive type doping element, and the first semiconductor layer includes a first region and a second region;

[0009] a passivation layer, covering at least a side of the first semiconductor layer facing away from the semiconductor substrate;

[0010] a first barrier layer and a first gate line, the first gate line being conductively connected to the first barrier layer, the first gate line and the first barrier layer being arranged on a side of the first region facing away from the semiconductor substrate; at least a portion of the first barrier layer passing through the passivation layer and conductively connected to at least a portion of the first region;

[0011] The surface doping concentration of the first region is a, the surface doping concentration of the second region is b, 2≤a / b≤20; the junction depth of the first region is c, the junction depth of the second region is d, 0.2μm≤cd≤4μm.

[0012] After research, the applicant discovered that if the doping concentration of the second region is too high, its passivation effect is poor and recombination is more severe, while a lower doping concentration in the second region affects the carrier transmission efficiency. The first region is conductively connected to the first barrier layer. If the doping concentration of the first region is too low, the transmission resistance is high, reducing the carrier transmission efficiency. If the doping concentration of the first region is too high, recombination is severe. As can be seen from the above, if a / b is larger, the passivation effect of the second region is better and the transmission resistance between the first region and the first barrier layer is lower, but the recombination in the second region is more severe. If a / b is smaller, the lateral transmission efficiency of the first semiconductor layer is higher, the transmission resistance between the first region and the first barrier layer is larger, and the current transmission efficiency is lower.

[0013] In addition, the significance of setting the difference range of junction depth between the first and second regions lies in that when a burn-through slurry is selected for the post-process, the slurry layer and the semiconductor layer are fused through high-temperature sintering to form an ohmic contact, which will also damage the first semiconductor layer to a certain depth. When a base metal barrier layer is selected for the post-process, the passivation layer on the semiconductor layer needs to be opened. In this case, the commonly used laser opening will inevitably remove a certain depth of the semiconductor layer while removing the passivation layer, causing damage to the substrate. Therefore, it is necessary to design the range of junction depth cd between the first and second regions. The larger the ratio, the larger the process window for damage caused by the thick process, that is, the greater the tolerance for the semiconductor depth damaged by sintering or laser opening, the better the conductivity between the first semiconductor layer and the first barrier layer. The smaller the cd, the higher the process requirements for removing damage to the first semiconductor layer, and the greater the processing difficulty.

[0014] Therefore, while designing the doping concentrations of the first and second regions, the junction depths of the first and second regions are also controlled. In this application, 2 ≤ a / b ≤ 20 is maintained, matching 0.2 μm ≤ cd ≤ 4 μm. This allows the doping concentration of the first region to be appropriately increased, resulting in a lower transmission resistance with the first barrier layer. Furthermore, the junction depth of the first region is deeper, reducing recombination in the first region. The doping concentration of the second region is lower, resulting in better passivation and less recombination. Furthermore, cd is kept within a reasonable range of 0.2 to 4 μm to reduce the process requirements for removing damage to the first semiconductor layer 2 and ensure good conductivity between the first region and the first barrier layer. The junction depth is defined as the distance X from the surface of the semiconductor substrate where the concentration of impurities of different conductivity types equals the concentration of impurities in the semiconductor substrate itself, forming a PN junction. This distance X is referred to as the PN junction depth, or simply junction depth, and is generally measured in microns.

[0015] Because the first gate line does not need to pass through the passivation layer to establish ohmic contact with the first semiconductor layer, the material of the first gate line can be formed from a non-burn-through paste. Therefore, the first gate line can be made of a relatively low-cost material to reduce costs. For example, the material of the first gate line can include metal elements such as copper and aluminum. To prevent the non-burn-through paste from damaging the passivation effect of the first semiconductor layer, a first barrier layer is also provided in the present application. The first barrier layer can separate the first gate line from the first semiconductor layer, thereby ensuring the passivation effect of the semiconductor layer while also ensuring electrical conductivity between the first gate line and the first semiconductor layer.

[0016] In one implementation, the first barrier layer includes silver or a base metal, is formed of a sintering paste, and is electrically connected to the first semiconductor layer by burning through the passivation layer.

[0017] In one implementation, the first barrier layer is formed of a non-fire-through paste: the passivation layer is provided with a first opening, and the first barrier layer is electrically connected to the first semiconductor layer through the first opening.

[0018] When the first barrier layer is formed from a burn-through paste including silver or a base metal, the temperature required during the burn-through process is relatively high, which can easily damage the first semiconductor layer. In addition, when the first barrier layer is formed from a non-burn-through paste or other plating methods, a laser grooving process is required to open a first opening in the passivation layer, and the laser grooving process can also cause damage to the first semiconductor layer. In order to ensure the normal efficiency of the solar cell, it is generally necessary to remove the damaged layer of the first semiconductor layer in the first opening area. In this way, when the first barrier layer is formed from a non-burn-through paste, after laser grooving, the damaged layer of the first semiconductor layer in the first opening area can be etched away.

[0019] In one implementation, 0.2μm≤c≤4μm; and / or, 0μm≤d≤1μm. It should be noted that the junction depth d of the second region can be 0. It can be understood that the junction depth of the second region can be reduced or even removed through processes such as laser etching or wet etching, that is, there is no PN junction below the non-gate line area, the purpose of which is to further reduce the metal recombination on the light-facing surface. At the same time, the passivation effect can also be achieved after the passivation layer is made in the subsequent process of this area. Of course, the backlight surface can also be set as above.

[0020] In one implementation, the width of the first region is greater than or equal to the width of the first gate line. In this way, the first region with a larger width range can provide a larger process window for the first gate line to be aligned and laid thereon, and a slight deviation of the first gate line can also meet the diversion requirements.

[0021] In one implementation, the width of the first area is 100-600 μm, which can meet the laying requirements of the first gate line. If the width of the first area is too narrow, the gate line alignment requirements are higher, and if the width of the first area is too large, the metal composite increases; and / or, the width of the second area is 100-900 μm. Under the premise that the distance between the gate lines is fixed, the second area is too wide, which means compressing the width of the first area, and the gate line alignment requirements are higher. If the second area is too narrow, it means that the width of the first area is too large, and the metal composite increases. Within the above width range, the technical goals of metal composite and gate line laying accuracy can be taken into account.

[0022] In one implementation, along the width direction of the first gate line, the width of the orthographic projection of the first opening on the light-facing surface is e, and the width of the orthographic projection of the first area on the light-facing surface is f; 10μm≤e≤100μm, and / or, 100μm≤f≤600μm, and / or, 1≤f / e≤50.

[0023] In one implementation, the first openings are arranged in multiple groups, each group of first openings is distributed in at least one row, and each row includes at least two first openings spaced apart along the extension direction of the first grid line; or, the first openings are strip-shaped holes extending along the extension direction of the first grid line.

[0024] In one implementation, the plurality of first openings in the same group do not overlap or partially overlap; and / or the first openings include circular holes, elliptical holes and / or polygonal holes.

[0025] In one implementation, the orthographic projection area of the first blocking layer on the light-facing surface is 4% to 70% of the orthographic projection area of the first grid line on the light-facing surface;

[0026] and / or, the height of the first barrier layer is 0.5% to 65% of the height of the first gate line;

[0027] And / or, the first barrier layer is disposed continuously or discontinuously along the extending direction of the first gate line.

[0028] In one implementation, the doping concentration of the first region gradually decreases in a direction toward the semiconductor substrate, or first increases and then decreases.

[0029] In one implementation, the doping concentration of the surface of the first region is 1E18 atom / cm 3 -8E18atom / cm 3 and / or, the maximum doping concentration of the first region is 5E18atom / cm 3 -9E23atom / cm 3 ;

[0030] and / or, along the thickness direction of the semiconductor substrate, the distance between the position with the highest doping concentration in the first region and the surface of the first region is 10 nm-500 nm;

[0031] And / or, the sheet resistance of the first region is 3 ohm / sq. to 200 ohm / sq.

[0032] In one implementation, the solar cell further includes a second semiconductor layer having a conductivity type opposite to that of the first semiconductor layer;

[0033] The second semiconductor layer is arranged on the backlight surface.

[0034] In one implementation, the second semiconductor layer is provided on the backlight side; the passivation layer also covers the side of the second semiconductor layer facing away from the semiconductor substrate;

[0035] The solar cell further includes a second barrier layer, at least a portion of which passes through the passivation layer and is conductively connected to the second semiconductor layer;

[0036] The second gate line is arranged on a side of the second barrier layer away from the semiconductor substrate, and the second gate line is conductively connected to the second barrier layer.

[0037] A photovoltaic module comprises a plurality of solar cells as described above and at least one interconnecting element, wherein the interconnecting element connects two adjacent solar cells in series or in parallel; the two adjacent solar cells are respectively a first solar cell and a second solar cell, the interconnecting element is electrically connected to a first grid line of the first solar cell and extends to be electrically connected to a second grid line of the second solar cell, wherein the polarity of the second grid line is opposite to that of the first grid line.

[0038] Compared with the prior art, the beneficial effects of the photovoltaic module provided by the embodiment of the present application are the same as the beneficial effects of the above-mentioned solar cell, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0040] Figure 1 A partial schematic diagram of a solar cell provided in an embodiment of the present application;

[0041] Figure 2 A partial schematic diagram of a solar cell provided in another embodiment of the present application;

[0042] Figure 3 A matching diagram of the passivation layer and the first barrier layer provided in an embodiment of the present application;

[0043] Figure 4A schematic diagram of a solar cell provided in an embodiment of the present application;

[0044] Figure 5 A schematic diagram of a solar cell provided in another embodiment of the present application;

[0045] Figure 6 A schematic diagram of the first barrier layer contacting the first semiconductor layer provided in one embodiment of the present application;

[0046] Figure 7 A schematic diagram of a first barrier layer in contact with a first semiconductor layer provided in another embodiment of the present application;

[0047] Figure 8 A schematic diagram of a first barrier layer in contact with a first semiconductor layer provided in another embodiment of the present application;

[0048] Figure 9 A schematic diagram of a first barrier layer in contact with a first semiconductor layer provided in another embodiment of the present application;

[0049] Figure 10 A schematic diagram of a first barrier layer extending into the first semiconductor layer provided in an embodiment of the present application;

[0050] Figure 11 A schematic diagram of a first barrier layer provided in an embodiment of the present application;

[0051] Figure 12 A schematic diagram of another first barrier layer provided in an embodiment of the present application;

[0052] Figure 13 A schematic diagram of another first barrier layer provided in an embodiment of the present application;

[0053] Figure 14 A schematic diagram of another first barrier layer provided in an embodiment of the present application;

[0054] Figure 15 A graph showing the doping concentration from the surface to the interior of the first region provided in an embodiment of the present application;

[0055] Figure 16 A cross-sectional view of a solar cell provided in accordance with another embodiment of the present application.

[0056] Reference numerals:

[0057] 1-semiconductor substrate, 2-first semiconductor layer, 2a-first region, 2b-second region, 3-passivation layer, 3a-first opening, 3b-aluminum oxide layer, 4-first barrier layer, 4a-alloy, 5-first gate line, 6-second semiconductor layer, 7-second barrier layer, 8-second gate line. DETAILED DESCRIPTION

[0058] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0059] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0060] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "multiple" means two or more, unless otherwise clearly and specifically defined. "Several" means one or more, unless otherwise clearly and specifically defined.

[0061] In the description of this application, it should be understood that the terms "up", "down", "front", "back", "left", "right", etc., indicating directions or positional relationships, are based on the directions or positional relationships shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, they should not be understood as limitations on this application.

[0062] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal communication between two components or the interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0063] In the manufacturing process of solar cells, the grid lines have always been highly dependent on silver. Currently, the electrode pattern is mainly formed by screen-printing silver paste to form silver grid lines. Silver grid lines are a major constraint on the cost reduction of solar cells or photovoltaic modules.

[0064] In view of the above, please refer to Figure 1-Figure 2The solar cell provided in the embodiment of the present application includes a semiconductor substrate 1, a first semiconductor layer 2, a passivation layer 3, a first barrier layer 4, and a first gate line 5. The semiconductor substrate 1 includes a light-facing surface and a backlight surface, that is, two surfaces facing each other along the thickness direction of the semiconductor substrate 1 are respectively the light-facing surface and the backlight surface. The semiconductor substrate 1 contains a first conductive type dopant element, which can be a Group III element, or a Group V element or a Group VI element.

[0065] The light-facing surface of the semiconductor substrate 1 is doped to form a first semiconductor layer 2. Specifically, the first semiconductor layer 2 can be formed within the light-facing surface of the semiconductor substrate 1 by diffusion, ion implantation, or other methods. The first semiconductor layer 2 includes a second conductivity type doping element opposite to the first conductivity type doping element. For example, when the first conductivity type doping element is a Group III element, the second conductivity type doping element is a Group V element or a Group VI element. Alternatively, when the second conductivity type doping element is a Group III element, the first conductivity type doping element is a Group V element or a Group VI element.

[0066] Specifically, the first semiconductor layer 2 can be disposed entirely on the light-facing surface, or partially on the light-facing surface, for example, in a strip-shaped arrangement. The first semiconductor layer 2 has a first region 2a and a second region 2b, wherein the first region 2a and the second region 2b can be distributed in a direction parallel to the light-facing surface of the semiconductor substrate 1.

[0067] The passivation layer 3 covers at least the side of the first semiconductor layer 2 facing away from the semiconductor substrate 1. The passivation layer 3 can be a single-layer structure or a multi-layer structure. The material of the passivation layer 3 can include one or more of silicon nitride, silicon oxynitride, silicon oxide, and aluminum oxide. It can passivate the surface of the first semiconductor layer 2, reduce its carrier recombination rate, and further improve the photoelectric conversion efficiency of the solar cell.

[0068] The first gate line 5 is conductively connected to the first barrier layer 4 and is disposed on a side of the first region 2a facing away from the semiconductor substrate 1. At least a portion of the first barrier layer 4 passes through the passivation layer 3 and is conductively connected to at least a portion of the first region 2a.

[0069] Multiple first gate lines 5 can extend along a first direction and be arranged along a second direction, that is, the length of the first gate lines 5 is arranged along the first direction. The first direction and the second direction intersect, that is, the first direction is different from the second direction, and the angle between the first direction and the second direction can be an acute angle or a right angle. The first direction can be one of the length and width directions of the battery body, and the second direction can be the other of the length and width directions of the battery body. In addition, the first gate lines 5 can be partially located on the side of the first barrier layer 4 facing away from the semiconductor substrate 1, that is, a portion of the first gate lines 5 is located on the side of the passivation layer 3 facing away from the semiconductor substrate 1, and another portion of the first gate lines 5 is located on the side of the first barrier layer 4 facing away from the semiconductor substrate 1; or, all of the first gate lines 5 are located on the side of the first barrier layer 4 facing away from the semiconductor substrate 1. The first gate lines 5 are conductively connected to the first barrier layer 4. The first gate lines 5 can directly contact the top surface and / or side surface of the first barrier layer 4 to achieve conductive connection, and the top surface of the first barrier layer 4 is the surface of the first barrier layer 4 facing away from the semiconductor substrate 1. The first barrier layer 4 functions to separate the first gate line 5 from the first semiconductor layer 2 , while ensuring electrical conductivity between the first gate line 5 and the first semiconductor layer 2 .

[0070] Among them, the surface doping concentration of the first region 2a of the first semiconductor layer 2 is a, that is, within the scope of the first region 2a, the surface of the first region 2a refers to the range from the outside of the first semiconductor layer 2 away from the semiconductor substrate 1 to the depth of 20nm inside thereof, the surface doping concentration a of the first region 2a refers to the doping concentration of any position within the first region 2a from the outside of the first semiconductor layer 2 away from the semiconductor substrate 1 to the depth of 20nm inside thereof, or the surface doping concentration a of the first region 2a refers to the average value of the doping concentrations of multiple positions within the first region 2a from the outside of the first semiconductor layer 2 away from the semiconductor substrate 1 to the depth of 20nm inside thereof. It should be noted here that there will be certain errors in the doping concentration test curves of multiple positions in the same doping region or the same square resistance region, and there will also be certain errors at the edge and center of the cell. The errors will often not exceed one order of magnitude, and the above test errors are allowed by this patent.

[0071] The surface doping concentration of second region 2b is b, which is the same as the surface doping concentration of first region 2a and is not further described. Carriers collected by first semiconductor layer 2 are sequentially transmitted through first region 2a, first barrier layer 4, and first gate line 5. The junction depth of first region 2a is c, and the junction depth of second region 2b is d.

[0072] After research, the applicant discovered that if the doping concentration of the second region 2b is too high, its passivation effect is poor and recombination is more severe, while the lower the doping concentration of the second region 2b, the carrier transmission efficiency is affected. The first region 2a is conductively connected to the first barrier layer 4. If the doping concentration of the first region 2a is too low, the transmission resistance is high, reducing the carrier transmission efficiency. If the doping concentration of the first region 2a is too high, recombination is severe. As can be seen from the above, if a / b is larger, the passivation effect of the second region 2b is better, the transmission resistance between the first region 2a and the first barrier layer 4 is lower, and the recombination of the second region 2b is more severe. The smaller a / b is, the higher the lateral transmission efficiency of the first semiconductor layer 2, the larger the transmission resistance between the first region 2a and the first barrier layer 4, and the lower the current transmission efficiency.

[0073] In addition, the significance of setting the difference range of junction depth between the first and second regions lies in that when a burn-through slurry is selected for the post-process, the slurry layer and the semiconductor layer are fused through high-temperature sintering to form an ohmic contact, which will also damage the first semiconductor layer to a certain depth. When a base metal barrier layer is selected for the post-process, the passivation layer on the semiconductor layer needs to be opened. In this case, the commonly used laser opening will inevitably remove a certain depth of the semiconductor layer while removing the passivation layer, causing damage to the substrate. Therefore, it is necessary to design the range of junction depth cd between the first and second regions. The larger the ratio, the larger the process window for damage caused by the thick process, that is, the greater the tolerance for the semiconductor depth damaged by sintering or laser opening, the better the conductivity between the first semiconductor layer and the first barrier layer. The smaller the cd, the higher the process requirements for removing damage to the first semiconductor layer, and the greater the processing difficulty. Therefore, the doping concentrations of the first region 2a and the second region 2b can be designed while controlling the junction depths of the first region 2a and the second region 2b. In this application, 2≤a / b≤20 is set, and 0.2μm≤cd≤4μm is matched. This allows the doping concentration of the first region 2a to be appropriately increased, resulting in a lower transmission resistance with the first barrier layer 4. At the same time, the junction depth of the first region 2a is deeper, reducing recombination in the first region 2a. The doping concentration of the second region 2b is lower, resulting in a better passivation effect and less recombination. At the same time, the junction depth of the second region 2b is smaller, reducing processing difficulty. Furthermore, cd is kept within a reasonable range of 0.2μm to 4μm to reduce the process requirements for removing damage to the first semiconductor layer 2 and ensure good conductivity between the first region 2a and the first barrier layer 4.

[0074] Wherein, a / b may be 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, or 20, etc. cd may be 0.2 μm, 0.5 μm, 0.8 μm, 1 μm, 1.2 μm, 1.5 μm, 1.8 μm, 2 μm, 2.2 μm, 2.5 μm, 2.8 μm, 3 μm, 3.2 μm, 3.5 μm, 3.8 μm, or 4 μm, etc. For example, a / b is 2.5 and cd is 0.7 μm; a / b is 15.8 and cd is 3.6 μm; a / b is 9.5 and cd is 1.4 μm; a / b is 4.3 and cd is 3.9 μm, etc.

[0075] Since the first gate lines 5 do not need to pass through the passivation layer 3 to establish ohmic contact with the first semiconductor layer 2, the material of the first gate lines 5 can be formed from a non-burn-through paste. Therefore, the first gate lines 5 can be formed from a relatively low-cost material to reduce costs. For example, the material of the first gate lines 5 can include metal elements such as copper and aluminum. In order to prevent the non-burn-through paste from damaging the passivation effect of the first semiconductor layer 2, a first barrier layer 4 is also provided in the present application. The first barrier layer 4 can separate the first gate lines 5 from the first semiconductor layer 2, thereby ensuring the passivation effect of the semiconductor layer while also ensuring electrical conductivity between the first gate lines 5 and the first semiconductor layer 2.

[0076] Considering that if the doping concentration of the first region 2a is too low, the transmission resistance is high, which reduces the carrier transmission efficiency. If the doping concentration of the first region 2a is too high, the recombination is serious. Therefore, in this technical solution, 5E18atom / cm 3 ≤a≤9E22atom / cm 3 To meet the transmission efficiency of the first region 2a while reducing the composite loss. For example, a can be 5E18 atoms / cm 3 、6E18 atom / cm 3 、7E18 atom / cm 3 、8E18 atom / cm 3 、9E18 atom / cm 3 、1E19atom / cm 3 、5E19 atom / cm 3 、9E20 atom / cm 3 、5E21 atom / cm 3 、8E21 atom / cm 3 、3E22 atom / cm 3 , 9E22 atoms / cm 3 wait.

[0077] Considering that the doping concentration of the second region 2b is too high, its passivation effect is poor and the recombination is more serious, while the lower the doping concentration of the second region 2b is, the lower the carrier transmission efficiency is. Therefore, in this technical solution, 1E18atom / cm 3 ≤b≤1E19atom / cm 3 , in order to improve the carrier transport efficiency of the second region 2b while ensuring the passivation effect of the second region 2b and reducing the recombination loss. For example, b can be 1E18 atoms / cm 3 、2E18 atom / cm 3 、3E18 atom / cm 3 、4E18 atom / cm 3 、5E18 atom / cm 3 、6E18 atom / cm 3 、7E18 atom / cm 3 、8E18 atom / cm 3 、9E18 atom / cm 3 or 1E19 atom / cm 3 wait.

[0078] Since the deeper the junction depth, the smaller the recombination, the deeper the junction depth, the higher the process requirements, the greater the manufacturing difficulty, and the greater the damage to the first semiconductor layer 2. In view of the above two situations, in this technical solution, 0.2μm≤c≤4μm; and / or, 0μm≤d≤1μm, so as to take into account the small recombination loss in the first region 2a and / or the second region 2b while reducing the processing difficulty and reducing the damage to the first semiconductor layer 2 during the processing. For example, c can be 0.2μm, 0.3μm, 0.5μm, 0.7μm, 0.8μm, 0.9μm, 1μm, 1.2μm, 1.5μm, 1.8μm, 2μm, 2.2μm, 2.5μm, 2.8μm, 3μm, 3.2μm, 3.5μm, 3.8μm or 4μm, etc. d can be 0, 0.05μm, 0.08μm, 0.1μm, 0.2μm, 0.3μm, 0.4μm, 0.5μm, 0.6μm, 0.7μm, 0.8μm, 0.9μm or 1μm, etc.

[0079] Understandably, 5E18 atoms / cm 3 ≤a≤9E22 atom / cm 3 Matching 0.4μm≤c≤4μm can appropriately increase the doping concentration of the first region 2a, lower the transmission resistance with the first barrier layer 4, and at the same time, the junction depth of the first region 2a is deeper, reducing the recombination of the first region 2a. 1E18 atom / cm 3 ≤b≤1E19atom / cm3 Matching with 0.3μm≤d≤1μm can make the doping concentration of the second region 2b lower, the passivation effect better and the recombination smaller. At the same time, the junction depth of the second region 2b is smaller, so as to reduce the processing difficulty and reduce the damage to the first semiconductor during the processing.

[0080] In order to ensure that the contact area between the first barrier layer 4 and the first gate line 5 is within a reasonable range, so that the transmission resistance between the first barrier layer 4 and the first gate line 5 is low and the transmission loss is small. In this technical solution, the orthographic projection area of the first barrier layer 4 on the light-facing surface is 4% to 70% of the orthographic projection area of the first gate line 5 on the light-facing surface. In this way, the contact resistance between the first barrier layer 4 and the first gate line 5 is small, while ensuring that the volume of the first barrier layer 4 is small and the cost is low. Optionally, the orthographic projection of the first barrier layer 4 on the light-facing surface is located inside the orthographic projection of the first gate line 5 on the light-facing surface. Alternatively, the orthographic projection of the first barrier layer 4 on the light-facing surface partially overlaps with the orthographic projection of the first gate line 5 on the light-facing surface.

[0081] Exemplarily, the orthographic projection area of the first blocking layer 4 on the light-facing surface is 4%, 5%, 10%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, 65% or 70% of the orthographic projection area of the first grid line 5 on the light-facing surface.

[0082] In some embodiments, if the first barrier layer 4 is too high, it can easily break during processing, making it difficult to form. If the first barrier layer 4 is too low, the contact area between the side surfaces of the first barrier layer 4 and the first gate lines 5 is too small, affecting current transmission efficiency. Therefore, in this technical solution, the height of the first barrier layer 4 along the thickness direction of the semiconductor substrate 1 is 0.5% to 65% of the height of the first gate lines 5. This balances the processing of the first barrier layer 4, facilitating forming with a high yield, while also ensuring the contact area between the side surfaces of the first barrier layer 4 and the first gate lines 5, reducing contact resistance and improving current transmission efficiency.

[0083] Illustratively, along the thickness direction of the semiconductor substrate 1 , the height of the first barrier layer 4 is 0.5%, 1%, 5%, 10%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50% or 65% of the height of the first gate line 5 .

[0084] In some embodiments, in order to save the raw materials of the first barrier layer 4, as Figure 2 As shown, when the first openings 3a are discontinuous along the extending direction of the first gate lines 5, that is, when a plurality of first openings 3a are arranged along the extending direction of the first gate lines 5, the first barrier layer 4 can be discontinuously provided along the extending direction of the first gate lines 5 to reduce the manufacturing cost of the first barrier layer 4. Alternatively, as Figure 1As shown, when the first opening 3a is a continuous strip hole along the extension direction of the first gate line 5, the first barrier layer 4 can also be continuously provided along the extension direction of the first gate line 5 to ensure current transmission efficiency and improve battery performance.

[0085] In some embodiments, the first barrier layer 4 comprises silver or a base metal. Silver has excellent electrical conductivity and direct contact with the first semiconductor layer 2 does not impair the passivation effect of the first semiconductor layer 2. The base metal may be aluminum, for example. In this technical solution, the first barrier layer 4 is electrically connected to the first semiconductor layer 2 by burning through the passivation layer 3.

[0086] In some embodiments, the first barrier layer 4 may be formed of a sintering paste and electrically connected to the first semiconductor layer 2 by burning through the passivation layer 3 .

[0087] In other embodiments, the first barrier layer 4 is formed of a non-burn-through paste. For example, the first barrier layer 4 includes nickel, which has a lower cost and can achieve good conductive contact with the first semiconductor layer 2. In addition, nickel has a strong ability to form alloys and has a strong plasticity, so the gap at the contact interface is smaller, thereby improving the conductive contact between the first barrier layer 4 and the first semiconductor layer 2.

[0088] Of course, the first barrier layer 4 may also include one or more elements of copper, chromium, lead, and tin, but the first barrier layer 4 contains a larger proportion of nickel and / or silver.

[0089] In the case where the first barrier layer 4 comprises nickel, as Figure 3 As shown, the passivation layer 3 is provided with a first opening 3a, and the first barrier layer 4 is electrically connected to the first semiconductor layer 2 through the first opening 3a to ensure electrical conductivity between the first semiconductor layer 2, the first barrier layer 4, and the first gate line 5. Along the width direction of the first gate line 5, the width of the orthographic projection of the first opening 3a on the light-facing surface is e, that is, the width of the first opening 3a is e.

[0090] In some embodiments, 10 μm ≤ e ≤ 100 μm. This configuration can prevent the width of the first opening 3a from being too wide, thereby avoiding severe damage to the semiconductor substrate 1 during processing. It can also prevent the width of the first opening 3a from being too narrow, thereby avoiding a situation where the contact area between the first semiconductor layer 2 and the first barrier layer 4 is too small, thereby avoiding increased transmission loss. For example, the width e of the orthographic projection of the first opening 3a on the light-facing surface can be 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, 55 μm, 60 μm, 65 μm, 70 μm, 75 μm, 80 μm, 85 μm, 90 μm, 95 μm, or 100 μm, etc.

[0091] In some embodiments, along the width direction of the first gate line 5, the width of the orthographic projection of the first region 2a on the light-facing surface is f, that is, the width of the first region 2a is f. 100μm≤f≤600μm, which can ensure that the width of the first region 2a is large enough, so that during the processing of the first opening 3a, it is easier to make the first opening 3a correspond to the first region 2a, reducing the precision requirement for the position of the first opening 3a, thereby facilitating the improvement of the processing efficiency of the first opening 3a; at the same time, it prevents the width of the first region 2a from being too wide, which increases the processing difficulty of the first region 2a, and avoids the waste of doping element raw materials. Exemplarily, the orthographic projection width f of the first region 2a on the light-facing surface can be 100μm, 150μm, 200μm, 260μm, 320μm, 350μm, 420μm, 480μm, 500μm, 550μm, 580μm or 600μm, etc.

[0092] In some embodiments, along the width direction of the first grid line 5, the width of the first region 2a is greater than or equal to the width of the first grid line 5, that is, the width of the orthographic projection of the first region 2a on the light-facing surface is greater than or equal to the width of the orthographic projection of the first grid line 5 on the light-facing surface. This also reduces the difficulty of aligning the first opening 3a with the first region 2a, reduces the precision requirement for the position of the first opening 3a, and improves processing efficiency.

[0093] In some embodiments, 1 ≤ f / e ≤ 50, to further ensure that during the processing of the first opening 3a, the first opening 3a is more easily aligned with the first area 2a, thereby reducing the precision requirement for the position of the first opening 3a, thereby improving the processing efficiency of the first opening 3a. For example, f / e can be 1, 5, 10, 15, 20, 25, 30, 35, 40, 45, or 50.

[0094] In some embodiments, the width of the second region 2b along the width direction of the first gate line 5 is 100-900 μm, that is, the width of the orthographic projection of the second region 2b on the light-facing surface is 100-900 μm. The doping concentration of the second region 2b is low, and the metal recombination loss is low, which ensures that the first semiconductor layer 2 uses the second region 2b to collect carriers with high efficiency, which is beneficial to improving the power generation efficiency of the solar cell. Exemplary, the width of the second region 2b is 100 μm, 200 μm, 300 μm, 400 μm, 500 μm, 600 μm, 700 μm, 800 μm or 900 μm, etc.

[0095] In some embodiments, the first openings 3a are arranged in multiple groups, and each group of first openings 3a corresponds to the same first gate line 5, that is, the first barrier layer 4 passing through the same group of first openings 3a is conductively connected to the same first gate line 5. Each group of first openings 3a is distributed in at least one column, and each column includes a plurality of first openings 3a spaced apart along the extension direction (length direction) of the first gate line 5. When each group of first openings 3a is provided with only one column, the plurality of first openings 3a in the same group can be arranged in sequence along the extension direction of the first gate line 5; when a group of first openings 3a is provided in multiple columns, the plurality of columns of first openings 3a are arranged in a direction perpendicular to the first gate line 5 (width direction), and each column of first openings 3a is arranged in sequence along the extension direction of the first gate line 5. For example, the plurality of first openings 3a in the same group can be distributed in two columns, three columns, or more columns. In this way, the multiple first openings 3a are distributed more evenly, and the positions where the first barrier layer 4 is electrically connected to the first semiconductor layer 2 are distributed more evenly, which helps the first barrier layer 4 to conduct the current at various positions of the first semiconductor layer 2 in time and avoid local overheating.

[0096] Multiple first openings 3a in the same group do not overlap or partially overlap, that is, two adjacent first openings 3a may overlap or not overlap; along the extension direction of the first gate line 5, two adjacent first openings 3a may overlap or not overlap, which can be determined according to actual conditions.

[0097] In other embodiments, the first openings 3a are strip-shaped holes extending continuously along the extension direction of the first gate lines 5. Specifically, each group of first openings 3a may include a single strip-shaped hole or a plurality of strip-shaped holes arranged side by side. This arrangement increases the area of conductive contact between the first barrier layer 4 and the first semiconductor layer 2, thereby reducing the transmission resistance between the first barrier layer 4 and the first semiconductor layer 2.

[0098] Of course, the shape of the first opening 3a may include a circular hole, an elliptical hole and / or a polygonal hole, which is not limited here.

[0099] In some embodiments, as Figure 4 As shown (illustrated within the oval frame), at least a portion of the first barrier layer 4 is in direct contact with the first semiconductor layer 2. Specifically, the first barrier layer 4 is partially in direct contact with the first semiconductor layer 2; alternatively, there is no other barrier layer between the first barrier layer 4 and the first semiconductor layer 2. This arrangement can further reduce the transmission resistance between the first barrier layer 4 and the first semiconductor layer 2, thereby improving the current transmission efficiency and the power generation efficiency of the battery.

[0100] In some embodiments, as Figure 5As shown (illustrated within the oval frame), an aluminum oxide layer 3b is provided between at least a portion of the first barrier layer 4 and the first semiconductor layer 2. Specifically, a relatively thin aluminum oxide layer 3b is partially provided between the first barrier layer 4 and the first semiconductor layer 2, or the first barrier layer 4 and the first semiconductor layer 2 are completely separated by the relatively thin aluminum oxide layer 3b (the relatively thin aluminum oxide does not affect the electrical conductivity between the first barrier layer 4 and the first semiconductor layer 2). During the laser drilling process, the deeper the first opening 3a, the greater the damage to the first semiconductor layer 2. Therefore, when the passivation layer 3 includes the aluminum oxide layer 3b, at least a portion of the aluminum oxide layer 3b is retained during the laser drilling process. When the aluminum oxide layer 3b is provided between the first barrier layer 4 and the first semiconductor layer 2, the depth of the first opening 3a is smaller, the laser damage is smaller, and the aluminum oxide layer 3b provides protection during the laser drilling process, thereby reducing laser damage to the first semiconductor layer 2.

[0101] In some embodiments, at least a portion of the metal element included in the first barrier layer 4 and / or the alloy 4 a formed by the metal element included in the first barrier layer 4 is in direct contact with the first semiconductor layer 2 .

[0102] Specifically, such as Figure 6 and Figure 8 As shown, the metal element contained in the first barrier layer 4 can be in direct contact with the first semiconductor layer 2. Figure 6 There is no other interlayer between the metal element contained in the first barrier layer 4 and the first semiconductor layer 2. Figure 8 There is a residual passivation layer 3 between a portion of the first barrier layer 4 and the first semiconductor layer 2 .

[0103] Or, as Figure 7 and Figure 9 As shown, the alloy 4a formed by the metal element included in the first barrier layer 4 is in direct contact with the first semiconductor layer 2. For example, when the first barrier layer 4 includes nickel, at least part of the nickel in the first barrier layer 4 forms a nickel-silicon alloy; for another example, when the first barrier layer 4 includes silver, at least part of the nickel in the first barrier layer 4 forms a silver-silicon alloy. Figure 7 The alloy 4a formed by the metal elements contained in the first barrier layer 4 is in direct contact with the first semiconductor layer 2. Figure 9 Part of the first semiconductor layer 2 is in direct contact with the metal element contained in the first barrier layer 4, and part of the first semiconductor layer 2 is in direct contact with the alloy 4a formed by the metal element contained in the first barrier layer 4. With this arrangement, the metal element contained in the first barrier layer 4 forms the alloy 4a, such as a nickel-silicon alloy, which has more stable performance.

[0104] In some embodiments, as Figure 10As shown, the metal elements included in the first barrier layer 4 form an alloy 4a. Ideally, the nickel-silicon contact is formed only on the surface of the semiconductor layer. However, since the subsequent copper paste drying also requires high-temperature treatment, the nickel-silicon alloy may continue to increase during the subsequent processing, and the alloy may extend into the semiconductor layer. Along the thickness direction of the semiconductor substrate 1, the extension distance of the alloy 4a within the first semiconductor layer 2 is less than or equal to 1.5μm. This facilitates better conductive contact between the alloy 4a and the first semiconductor layer 2, while ensuring the passivation effect of the first region 2a. Exemplary, the extension distance of the alloy 4a within the first semiconductor layer 2 is 0.1μm, 0.2μm, 0.3μm, 0.4μm, 0.5μm, 0.6μm, 0.7μm, 0.8μm, 0.9μm, 1.0μm, 1.1μm, 1.2μm, 1.3μm, 1.4μm, or 1.5μm, etc.

[0105] In some embodiments, as Figure 11 As shown, the first barrier layer 4 may comprise only metal elements, that is, the metal elements comprised in the first barrier layer 4 do not form an alloy 4a. For example, the first barrier layer 4 may comprise metal elements such as silver and nickel. In this manner, the first barrier layer 4 exhibits improved electrical conductivity, thereby reducing transmission loss.

[0106] Or, as Figure 12 As shown, first barrier layer 4 comprises a uniformly distributed metal mixture. A portion of the metal elements form an alloy 4a, and another portion of the metal elements within first barrier layer 4 are uniformly distributed. In other words, a portion of the metal elements within first barrier layer 4 do not form alloy 4a, while another portion does. Furthermore, the portion of first barrier layer 4 that does not form alloy 4a and the alloy 4a that does form are uniformly distributed. This improves the stability of first barrier layer 4 and makes it less susceptible to corrosion.

[0107] Or, as Figure 13 As shown, the alloy 4a formed by a portion of the metal elements included in the first barrier layer 4 is surrounded by another portion of the metal elements included in the first barrier layer 4. That is, the alloy 4a is formed in the area of the first barrier layer 4 close to the first semiconductor layer 2, so that the performance of the area of the first barrier layer 4 close to the first semiconductor layer 2 is more stable.

[0108] Or, as Figure 14 As shown, the first barrier layer 4 includes multiple stacked sub-barrier layers. The materials and thicknesses of the multiple sub-barrier layers can be the same or different and can be arbitrarily set according to the performance requirements of the solar cell. For example, the multiple sub-barrier layers include a nickel layer, a nickel-silicon alloy layer, a silver layer, a silver-silicon alloy layer, etc. This configuration can meet the performance requirements of various types of solar cells.

[0109] The applicant's research has found that if the surface doping concentration of the first region 2a is low, the area of the first opening 3a needs to be larger, and the required laser energy is higher, then the resulting heat-affected zone is larger. The heat-affected zone can refer to the damaged area of the first semiconductor layer 2, and the damage to the first semiconductor layer 2 is greater. If the surface doping concentration of the first region 2a is high, the required area of the first opening 3a is reduced, and the laser energy requirement is lower. However, the high doping concentration near the surface will lead to higher Auger recombination. After removing the damaged layer caused by the laser, the high doping concentration portion of the first region 2a may be removed, reducing the transmission efficiency. In short, the lower the doping concentration of the first region 2a, the larger the heat-affected zone caused by the laser opening process; and the higher the doping concentration of the first region 2a, the smaller the heat-affected zone generated during the laser opening process, and at the same time, the recombination of the first region 2a will increase, and the passivation effect will deteriorate.

[0110] In view of the above situation, in this technical solution, if Figure 15 As shown, along the direction toward the semiconductor substrate 1, from the outermost portion of the first region 2a away from the semiconductor substrate 1 to the inner portion thereof, the doping concentration of the first region 2a first increases and then decreases. In other words, from the outermost portion of the first region 2a away from the semiconductor substrate 1 to the inner portion thereof, the doping concentration of the first region 2a changes from low to high and then decreases. Specifically, the doping concentration of the first region 2a can change from low to high and then decrease within the range from the outermost portion of the first region 2a away from the semiconductor substrate 1 to a preset depth h0 within the inner portion thereof. This ensures that the doping concentration on the surface of the first region 2a is moderate, the area of the first opening 3a is moderate, and the heat-affected zone generated is relatively small. At the same time, after removing the damaged layer caused by the laser, the portion of the first region 2a with a higher doping concentration is exposed to contact the first barrier layer 4, thereby ensuring good conductive contact between the first region 2a and the first barrier layer 4. Optionally, h0 is greater than 10 nm, for example, h0 may be 15 nm, 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, 550 nm, 600 nm, 650 nm or 700 nm, etc.

[0111] In some embodiments, the doping concentration of the first region 2a gradually decreases along the direction toward the semiconductor substrate 1. In this way, when the surface concentration of the first region 2a is high, the concentration of the outermost surface of the first region 2a can be ensured to be at a high level after removing the damaged layer caused by the laser.

[0112] The doping concentration of the surface of the first region 2a can be 1E18atom / cm 3 -8E18atom / cm 3, to ensure that the area of the first opening 3a is moderate and the heat affected zone is relatively small. For example, the doping concentration of the surface of the first region 2a is 1E18atom / cm 3 、2E18atom / cm 3 、3E18atom / cm 3 、4E18atom / cm 3 、5E18atom / cm 3 、6E18atom / cm 3 、7E18atom / cm 3 or 8E18atom / cm 3 wait.

[0113] Optionally, the maximum doping concentration of the first region 2a is 5E18atom / cm 3 -9E22atom / cm 3 The maximum doping concentration of the first region 2a is the maximum doping concentration in the doping curve of the first region 2a measured along the first semiconductor layer 2 from the outside away from the semiconductor substrate 1 to the inside thereof. Multiple positions in the first region can be tested to obtain an average value of the maximum doping concentration.

[0114] When the doping concentration of the first region 2a increases and then decreases, the distance between the location with the highest doping concentration in the first region 2a and the surface of the first region 2a along the thickness direction of the semiconductor substrate 1 is 10 nm to 500 nm. This ensures that after the damaged layer caused by the laser in the first region 2a is removed, the location with the highest doping concentration in the first region 2a is exposed and can directly contact the first barrier layer 4, which is beneficial to improving the conductive efficiency. For example, the distance between the location with the highest doping concentration in the first region 2a and the surface of the first region 2a is 10 nm, 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, or 500 nm.

[0115] In some embodiments, the sheet resistance of the first region 2a is 3 ohms to 200 ohms to prevent excessive transmission loss in the first region 2a, which could affect battery performance. Furthermore, the sheet resistance of the first region 2a is prevented from being too low, which could result in significant recombination losses. For example, the sheet resistance of the first region 2a is 3 ohms, 5 ohms, 7 ohms, 10 ohms, 13 ohms, 50 ohms, 80 ohms, 110 ohms, 120 ohms, 130 ohms, 140 ohms, 150 ohms, 160 ohms, 170 ohms, 180 ohms, 190 ohms, or 200 ohms.

[0116] In actual application, the material of the semiconductor substrate 1 can be selected from materials such as silicon (Si) or germanium (Ge) or materials such as gallium arsenide (GaAs). Obviously, in terms of conductivity type, the semiconductor substrate 1 can be an intrinsic conductive substrate, an n-type conductive substrate or a p-type conductive substrate. Optionally, the semiconductor substrate 1 is a p-type conductive substrate or an n-type conductive substrate. Compared with the intrinsic conductive substrate, the p-type conductive substrate or the n-type conductive substrate has better conductivity, so that the final solar cell has a lower body resistivity, thereby improving the efficiency of the solar cell.

[0117] For example, the semiconductor substrate 1 can be a p-type substrate or an n-type substrate. The n-type substrate has the advantages of long minority carrier lifetime, no light decay, and good weak light performance.

[0118] The first semiconductor layer 2 may include doped polycrystalline silicon. Doped polycrystalline silicon layers have enhanced carrier transport properties. Therefore, when the first semiconductor layer 2 is a doped polycrystalline silicon layer, the carrier transport efficiency is higher, which helps improve the photoelectric conversion efficiency of the solar cell. Of course, the first semiconductor layer 2 may also be one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon.

[0119] The solar cell provided in the present application further includes a second semiconductor layer 6 . The conductivity type of the second semiconductor layer 6 is opposite to that of the first semiconductor layer 2 , so as to collect and conduct electrons and holes respectively, thereby facilitating the formation of photocurrent.

[0120] In the case of a bifacial solar cell, the second semiconductor layer 6 is disposed on the backlight side. The second semiconductor layer 6 can be disposed entirely or partially on the backlight side. When the second semiconductor layer 6 is partially disposed on the backlight side, the second semiconductor layer 6 can be arranged in strips or a "P"-like pattern at intervals on the backlight side.

[0121] The second semiconductor layer 6 may include doped polycrystalline silicon, or the second semiconductor layer 6 may also be one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon.

[0122] In the case where the solar cell is a bifacial cell, the second semiconductor layer 6 is provided on the backlight side. In this technical solution, the passivation layer 3 also covers the side of the second semiconductor layer 6 facing away from the semiconductor substrate 1, that is, the backlight side is also provided with a passivation layer 3 covering the side of the second semiconductor layer 6 facing away from the semiconductor substrate 1. The solar cell also includes a second barrier layer 7 and a second gate line 8, at least a portion of the second barrier layer 7 passes through the passivation layer 3 and is conductively connected to the second semiconductor layer 6, and the second gate line 8 is provided on the side of the second barrier layer 7 facing away from the semiconductor substrate 1, and the second gate line 8 is conductively connected to the second barrier layer 7. Among them, the technical features such as the material and structure of the second barrier layer 7 and the second gate line 8 can refer to the description of the first barrier layer 4 and the first gate line 5 above, and will not be repeated here.

[0123] In some embodiments, the passivation layer 3 is provided with second openings, and the second barrier layer 7 is electrically connected to the second semiconductor layer 6 through the second openings. The second openings are arranged in multiple groups, and at least part of the second barrier layer 7 is electrically connected to the second semiconductor layer 6 through a group of second openings. Figure 16 As shown, along the direction perpendicular to the first grid line 5, the first grid line 5 has a first edge and a second edge relative to each other, that is, the first edge and the second edge are arranged relative to each other along the width direction of the first grid line 5. Along the direction perpendicular to the second grid line 8, the distance between the hole edge close to the first edge and the hole edge close to the second edge in the second opening of the same group is W1. Along the direction perpendicular to the first grid line 5, the first grid line 5 has a third edge and a fourth edge relative to each other, that is, the third edge and the fourth edge are arranged relative to each other along the width direction of the first grid line 5. Along the direction perpendicular to the first grid line 5, the distance between the hole edge close to the third edge and the hole edge close to the fourth edge in the first opening of the same group is W2. The width of the second grid line 8 is S1, and the width of the first grid line 5 is S2.

[0124] In the present application, |W1-W2|≤5μm, and S2 / W2<S1 / W1. That is, the difference between the distance W1 between the hole edge close to the first edge and the hole edge close to the second edge in the same group of second openings and the distance W2 between the hole edge close to the third edge and the hole edge close to the fourth edge in the same group of first openings is less than or equal to 5μm, so that the groove width of the passivation layer 3 on the light-facing side and the backlight side is roughly equal, and at the same time, S2 / W2<S1 / W1, that is, the ratio of the width S2 of the first gate line 5 on the light-facing side to the groove width W2 is smaller than the ratio of the width S1 of the second gate line 8 on the backlight side to the groove width W1, thereby making the width S2 of the first grid line 5 on the light-facing side smaller, while ensuring that the groove width W2 of the passivation layer 3 on the light-facing side is equivalent to the groove width W1 on the backlight side; such a smaller width S2 of the first grid line 5 can appropriately reduce the shading area of the first grid line 5, while the groove width W2 of the passivation layer 3 on the light-facing side is roughly equal to the groove width W1 on the backlight side, thereby improving the transmission efficiency between the second grid line 8 and the second semiconductor layer 6, and thereby improving the overall power generation efficiency of the solar cell.

[0125] For example, |W1-W2| may be 0, 1 μm, 2 μm, 3 μm, 4 μm, or 5 μm.

[0126] Alternatively, W2<W1, and W2<S2. That is, the groove width W2 of the passivation layer 3 on the light-facing side is smaller than the groove width W1 on the backlight side, and the width S2 of the matching first grid line 5 is larger than the groove width W2 of the passivation layer 3 on the light-facing side. In this way, the groove width W2 of the passivation layer 3 on the light-facing side can be appropriately reduced, while ensuring a reasonable contact area between the first grid line 5 and the first semiconductor layer 2, so that the first grid line 5 and the first semiconductor layer 2 have a low transmission resistance, thereby improving the overall power generation efficiency of the solar cell.

[0127] In some embodiments, if S1 / W1 is too large, the width of the second gate line 8 will be too wide, resulting in severe shading; if S1 / W1 is too small, the contact area between the second gate line 8 and the second semiconductor layer 6 will be small, resulting in large current transmission losses. Therefore, in this technical solution, taking into account both shading and transmission losses, 1.25≤S1 / W1≤3 is used to reduce the shading area of the second gate line 8 while ensuring low transmission losses between the second gate line 8 and the second semiconductor layer 6, thereby improving the power generation efficiency of the solar cell. Exemplary, S1 / W1 can be 1.25, 1.5, 1.75, 2, 2.25, 2.75, or 3, etc.

[0128] In some implementations, 1.25≤S2 / W2≤2, taking into account both shading conditions and transmission loss, while minimizing the shading area of the first gate line 5, ensuring low transmission loss between the first gate line 5 and the first semiconductor layer 2. In this technical solution, S2 / W2 is in the range of 1.25 to 2, so that the width of the first gate line 5 is smaller than the groove width W2 of the passivation layer 3 on the light-facing surface, which is beneficial to reducing the shading area, improving the light absorption rate, and further improving the power generation efficiency of the solar cell. Exemplary, S2 / W2 can be 1.25, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9 or 2, etc.

[0129] In some embodiments, as Figure 16 As shown, 15μm≤W1≤150μm, so as to ensure that the contact area between the second gate line 8 and the second semiconductor layer 6 is within a reasonable range, thereby ensuring the current transmission efficiency and reducing the damage to the semiconductor substrate 1 during the groove forming process. Exemplarily, W1 can be 15μm, 20μm, 25μm, 30μm, 35μm, 40μm, 45μm, 50μm, 55μm, 60μm, 65μm, 70μm, 75μm, 80μm, 85μm, 90μm, 95μm, 100μm, 105μm, 110μm, 115μm, 120μm, 125μm, 130μm, 135μm, 140μm, 145μm or 150μm, etc.

[0130] In other embodiments, Figure 16As shown, 15μm≤W2≤150μm, so as to ensure that the contact area between the first gate line 5 and the first semiconductor layer 2 is within a reasonable range, thereby ensuring the current transmission efficiency and reducing the damage to the semiconductor substrate 1 during the groove forming process. Exemplarily, W2 can be 15μm, 20μm, 25μm, 30μm, 35μm, 40μm, 45μm, 50μm, 55μm, 60μm, 65μm, 70μm, 75μm, 80μm, 85μm, 90μm, 95μm, 100μm, 105μm, 110μm, 115μm, 120μm, 125μm, 130μm, 135μm, 140μm, 145μm or 150μm, etc.

[0131] In other embodiments, W2<W1≤3W2. This arrangement can further appropriately reduce the groove width W2 of the passivation layer 3 on the light-facing side, thereby reducing the width of the first gate line 5, thereby reducing the light-shielding area of the first gate line 5. At the same time, it can also prevent the difference between W1 and W2 from being too large, resulting in a large current difference between the first gate line 5 and the second gate line 8, which would affect the overall power generation efficiency. For example, W1 can be equal to 1.1W2, 1.3W2, 1.5W2, 1.8W2, 2W2, 2.3W2, 2.5W2, 2.8W2, or 3W2, etc.

[0132] In some embodiments, │W1-W2│≤5μm, matching S2<S1, the groove widths of the passivation layer 3 on the light-facing side and the backlight side are approximately equal, and at the same time matching S2<S1, so that the width S2 of the first gate line 5 on the light-facing side is smaller; in this way, the smaller width S2 of the first gate line 5 can appropriately reduce the shading area of the first gate line 5, and at the same time, the groove width W2 of the passivation layer 3 on the light-facing side is approximately equal to the groove width W1 on the backlight side, thereby improving the transmission efficiency between the first gate line 5 and the first semiconductor layer 2, thereby improving the overall power generation efficiency of the solar cell.

[0133] In other embodiments, Figure 16As shown, 0.1≤h2 / S2≤0.8, when the aspect ratio of the first gate line 5 is greater than 0.8, the height of the first gate line 5 needs to be higher, resulting in more consumption of metal raw materials, and the first gate line 5 will block the light on its side, resulting in a decrease in light utilization, and is also not conducive to the welding effect of the welding strip; the width of the first gate line 5 is also required to be narrow, resulting in a large contact resistance between the first gate line 5 and the first semiconductor layer 2, and a decrease in current transmission efficiency. When the aspect ratio of the first gate line 5 is less than 0.1, the width of the first gate line 5 is required to be wider, which will lead to an increase in the shading area of the first gate line 5, reduce the light absorption utilization rate, and increase the metal composite loss; at the same time, the height of the first gate line 5 is required to be lower, which easily causes the first gate line 5 to be disconnected, affecting current transmission. Therefore, in order to balance the above two aspects, the h2 / S2 of this application is 0.1~0.8 to reduce the shading area and light loss, improve the light absorption utilization rate, ensure the welding effect of the welding strip, reduce the risk of broken gates during printing and reduce metal composite losses. For example, h2 / S2 can be 0.1, 0.12, 0.15, 0.18, 0.2, 0.22, 0.25, 0.28, 0.3, 0.32, 0.35, 0.38, 0.4, 0.42, 0.45, 0.48, 0.5, 0.52, 0.55, 0.58, 0.6, 0.62, 0.65, 0.68, 0.7, 0.72, 0.75, 0.78 or 0.8, etc.

[0134] In other embodiments, Figure 16 As shown, the height of the second gate line 8 along the thickness direction of the semiconductor substrate 1 is h1. In this technical solution, 0.2≤S1 / h1≤0.3, thereby reducing the shading area and light loss, improving light absorption and utilization, reducing damage to the semiconductor substrate 1, and reducing the risk of gate breakage during printing. Exemplary, S1 / h1 can be 0.2, 0.21, 0.22, 0.23, 0.24, 0.25, 0.26, 0.27, 0.28, 0.29, or 0.3, etc.

[0135] In some embodiments, when each group of first openings 3a is distributed at intervals and each group of second openings is also distributed at intervals, the spacing between adjacent openings in each group of first openings 3a is smaller than the spacing between adjacent openings in each group of second openings, that is, the number of first openings 3a is greater and the density is higher, which is conducive to making the area of the first openings 3a smaller, and helping to reduce the width of the first gate line 5 to reduce the shading area, while ensuring lower transmission loss between the first gate line 5 and the first semiconductor layer 2.

[0136] In some embodiments, a first interface layer is provided between the first semiconductor layer 2 and the semiconductor substrate 1, and a second interface layer is provided between the second semiconductor layer 6 and the semiconductor substrate 1. The passivation contact structure composed of the interface layer and the semiconductor layer has an excellent interface passivation effect and can achieve selective collection of carriers, reduce the carrier recombination rate in the region where the semiconductor layer is formed on the surface of the semiconductor substrate 1, and further improve the photoelectric conversion efficiency of the solar cell. The material and thickness of the first interface layer can be set according to the material of the first semiconductor layer 2 and actual requirements, and the material and thickness of the second interface layer can be set according to the material of the second semiconductor layer 6 and actual requirements, and are not specifically limited here.

[0137] For example, the first semiconductor layer 2 may be a doped polysilicon layer, the first interface layer may be a tunneling oxide layer, the second semiconductor layer 6 may be a doped polysilicon layer, and the second interface layer may be a tunneling oxide layer.

[0138] In some embodiments, as Figure 4 and Figure 5 As shown, the passivation layer 3 also covers the side of the second semiconductor layer 6 facing away from the semiconductor substrate 1. The second semiconductor layer 6 includes a third region and a fourth region arranged in a direction parallel to the surface of the semiconductor substrate 1. The doping concentration of the third region is greater than the doping concentration of the fourth region. The solar cell also includes a second barrier layer 7 and a second gate line 8. At least a portion of the second barrier layer 7 passes through the passivation layer 3 and is conductively connected to the third region. The second gate line 8 is provided on the side of the second barrier layer 7 facing away from the semiconductor substrate 1. Based on this, the material, structure, and other characteristics of the second barrier layer 7 and the second gate line 8 can be referred to the description of the first barrier layer 4 and the first gate line 5 above, and will not be repeated here.

[0139] In some embodiments, as Figure 4 and Figure 5 As shown, the light-facing surface of the semiconductor substrate 1 can be a velvet surface with multiple pyramid-like structures formed on it. This helps increase the surface area of the light-facing surface, improve the light trapping effect and light absorption rate of the light-facing surface. Of course, the light-facing surface can also be a polished surface. In addition, the backlight surface of the semiconductor substrate 1 can be a polished surface, which has a lower surface roughness, facilitating subsequent processing and doping control, thereby helping to improve the production yield and the overall reliability of the solar cell. Of course, the backlight surface can also be a velvet surface.

[0140] The materials of the first semiconductor layer 2 and the second semiconductor layer 6 can be silicon (Si), germanium (Ge), silicon carbide (SiCx), or gallium arsenide (GaAs). In terms of conductivity type, the first semiconductor layer 2 can be an n-type doped layer, and the second semiconductor layer 6 can be a p-type doped layer; alternatively, the first semiconductor layer 2 can be a p-type doped layer, and the second semiconductor layer 6 can be an n-type doped layer.

[0141] An embodiment of the present invention further provides a method for manufacturing a solar cell. The method can be used to prepare the solar cell described in any of the above embodiments. The method for manufacturing a solar cell comprises the following steps:

[0142] S100: providing a semiconductor substrate 1, wherein the semiconductor substrate 1 has a light-facing surface and a backlight surface opposite to each other.

[0143] Prior to this step, in some embodiments, the semiconductor substrate 1 may be placed in a polishing and cleaning machine to remove the damaged layer of the semiconductor substrate 1 using a polishing solution. Furthermore, in this step, the morphology of the light-facing and backlight-facing surfaces of the semiconductor substrate 1 after polishing and cleaning can be adjusted by controlling parameters such as temperature, time, cleaning solution type, and cleaning solution concentration. It should be noted that in some examples, the polishing and cleaning step can be omitted.

[0144] S200: forming a first semiconductor layer 2 on the light-facing surface, wherein the first semiconductor layer 2 has a first region 2a and a second region 2b arranged in a direction parallel to the surface of the semiconductor substrate 1;

[0145] The first semiconductor layer 2 can be formed in the semiconductor substrate 1 by diffusion, ion implantation, etc. The doping concentration of the first region 2a is greater than the doping concentration of the second region 2b, so as to reduce the transmission resistance of the first region 2a and reduce the current transmission loss.

[0146] S300: forming a passivation layer 3 at least on a side of the first semiconductor layer 2 facing away from the semiconductor substrate 1;

[0147] Specifically, the passivation layer 3 may be formed by deposition or the like. The material and structure of the passivation layer 3 may be referred to above and will not be described in detail here.

[0148] S400: forming a first barrier layer 4, so that at least a portion of the first barrier layer 4 passes through the passivation layer 3 and is conductively connected to the first region 2a;

[0149] Specifically, the first barrier layer 4 may be formed by deposition or printing. The material and structure of the first barrier layer 4 may be referred to above and will not be described in detail here.

[0150] S500: forming a first gate line 5 on a side of the first barrier layer 4 facing away from the semiconductor substrate 1, wherein the first gate line 5 is conductively connected to the first barrier layer 4;

[0151] Specifically, the first grid lines 5 can be formed using processes such as screen printing, electroplating, sputtering, or evaporation. A relatively inexpensive conductive metal, such as copper paste, can be added to a non-burn-through slurry to reduce grid line manufacturing costs. In some embodiments, the cell can be dried after this step to facilitate rapid formation of the first grid lines 5. The material and structure of the first grid lines 5 can be found in the previous section and will not be further elaborated here.

[0152] The surface doping concentration of the first region 2a is a, and the surface doping concentration of the second region 2b is b, with 2≤a / b≤20. The junction depth of the first region 2a is c, and the junction depth of the second region 2b is d, with 0.2μm≤cd≤4μm. In this application, 2≤a / b≤20 is matched to 0.2μm≤cd≤4μm to appropriately increase the doping concentration of the first region 2a, lower the transmission resistance with the first barrier layer 4, and at the same time, the junction depth of the first region 2a is deeper, reducing recombination in the first region 2a. The doping concentration of the second region 2b is lower, with better passivation and less recombination. At the same time, the junction depth of the second region 2b is smaller, reducing processing difficulty. Furthermore, cd is kept within a reasonable range of 0.2μm to 4μm to reduce the process requirements for removing damage to the first semiconductor layer 2 and ensure good conductivity between the first region 2a and the first barrier layer 4.

[0153] In some embodiments, at least after forming the passivation layer 3 on the side of the first semiconductor layer 2 facing away from the semiconductor substrate 1 and before forming the first barrier layer 4, the manufacturing method of the solar cell also includes: forming a first opening 3a on the passivation layer 3; the first opening 3a is a through hole that penetrates the thickness of the passivation layer 3, so that the first barrier layer 4 can pass through the through hole and directly contact the first semiconductor layer 2, which can further reduce the transmission resistance and current transmission loss.

[0154] Alternatively, after forming the passivation layer 3 on at least the side of the first semiconductor layer 2 facing away from the semiconductor substrate 1 and before forming the first barrier layer 4, the solar cell manufacturing method further includes: forming an aluminum oxide layer 3b at the bottom of the first opening 3a. In this manner, the aluminum oxide layer 3b is disposed between at least a portion of the first barrier layer 4 and the first semiconductor layer 2. During the laser opening process, the aluminum oxide layer 3b provides protection, thereby reducing laser damage to the first semiconductor layer 2.

[0155] In some embodiments, forming the first opening 3a on the passivation layer 3 includes: using a laser to form the first opening 3a on the passivation layer 3, and the bottom of the first opening 3a has an aluminum oxide layer 3b. In this step, a laser opening process is used, which is simple to operate and helps improve processing efficiency.

[0156] Alternatively, forming the first opening 3a in the passivation layer 3 includes: using a laser to form a through hole through the thickness of the passivation layer 3, and etching away the damaged layer of the first semiconductor layer 2. The laser drilling through the passivation layer 3 inevitably causes damage to the first semiconductor layer 2. To improve the conductive effect, in this technical solution, the damaged layer of the first semiconductor layer 2 can also be etched away. Specifically, wet etching can be used to remove the damaged layer of the first semiconductor layer 2.

[0157] In some embodiments, at least before forming the passivation layer 3 on the side of the first semiconductor layer 2 facing away from the semiconductor substrate 1, the method for manufacturing a solar cell further includes: forming a second semiconductor layer 6 on the backlight side, or forming the second semiconductor layer 6 partially on the light-facing side, with the first semiconductor layer 2 and the second semiconductor layer 6 being alternately distributed. The second semiconductor layer 6 and the first semiconductor layer 2 have opposite conductivity types. The second semiconductor layer 6 can be additionally formed on the backlight side of the semiconductor substrate 1 using a deposition technique, or can be formed within the semiconductor substrate 1 by diffusion, ion implantation, or the like. In addition, the material and structure of the second semiconductor layer 6 can refer to the description above and will not be repeated here.

[0158] It should be noted that before forming the passivation layer 3, winding can be performed to remove the first semiconductor layer 2 on the side and backlight surface. After the de-plating is completed, acid washing is performed to remove the chemical solution remaining on the battery cell.

[0159] In addition, the present application also provides a photovoltaic assembly, which includes a plurality of solar cells as provided in any of the above embodiments and at least one interconnecting member, wherein the interconnecting member connects two adjacent solar cells in series or in parallel. Specifically, the two adjacent solar cells are a first solar cell and a second solar cell, respectively, and the interconnecting member connects the first grid line of the first solar cell and extends to connect to the second grid line 8 of the second solar cell. Similarly, the interconnecting member is analogous to form an interconnection of multiple solar cells. Compared with the prior art, the beneficial effects of the photovoltaic assembly provided by the embodiment of the present application are the same as the beneficial effects of the above-mentioned solar cell and the method for manufacturing the solar cell, which will not be elaborated here.

[0160] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0161] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A solar cell, characterized in that: include: a semiconductor substrate containing a first conductivity type dopant element; Doping the light-facing surface of the semiconductor substrate to form a first semiconductor layer, wherein the first semiconductor layer contains a second conductive type doping element opposite to the first conductive type doping element, and the first semiconductor layer includes a first region and a second region; a passivation layer, covering at least a side of the first semiconductor layer facing away from the semiconductor substrate; a first barrier layer and a first gate line, wherein the first gate line is conductively connected to the first barrier layer, and the first gate line and the first barrier layer are arranged on a side of the first region away from the semiconductor substrate; At least a portion of the first barrier layer is conductively connected to at least a portion of the first region through the passivation layer; The surface doping concentration of the first region is a, the surface doping concentration of the second region is b, 2≤a / b≤20; the junction depth of the first region is c, the junction depth of the second region is d, 0.2μm≤cd≤4μm.

2. The solar cell according to claim 1, wherein 0.2 μm≤c≤4 μm; and / or, 0 μm≤d≤1 μm.

3. The solar cell according to claim 1, wherein The width of the first region is greater than or equal to the width of the first gate line, and / or the width of the first region is 100-600 μm, and / or the width of the second region is 100-900 μm.

4. The solar cell according to claim 1, wherein Along the direction toward the semiconductor substrate, the doping concentration of the first region gradually decreases, or first increases and then decreases.

5. The solar cell according to claim 4, wherein The maximum doping concentration of the first region is 5E18atom / cm 3 -9E22atom / cm 3 ; And / or, when the doping concentration of the first region increases first and then decreases, along the thickness direction of the semiconductor substrate, the distance between the position with the highest doping concentration in the first region and the surface of the first region is 10 nm-500 nm.

6. The solar cell according to claim 1, wherein The first barrier layer includes silver or base metal, is formed of a sintering paste, and is electrically connected to the first semiconductor layer by burning through the passivation layer.

7. The solar cell according to claim 1, wherein The passivation layer is provided with a first opening, and the first barrier layer is electrically connected to the first semiconductor layer through the first opening.

8. The solar cell according to claim 7, characterized in that Along the width direction of the first gate line, the width of the orthographic projection of the first opening on the light-facing surface is e, and the width of the orthographic projection of the first region on the light-facing surface is f; 10μm≤e≤100μm, and / or, 100μm≤f≤600μm, and / or, 1≤f / e≤50.

9. The solar cell according to claim 7, wherein: The first openings are arranged in multiple groups, each group of first openings is distributed in at least one row, and each row includes at least two first openings spaced apart along the extension direction of the first grid lines; or, the first openings are strip-shaped holes extending along the extension direction of the first grid lines.

10. The solar cell according to claim 9, characterized in that The plurality of first openings in the same group do not overlap or partially overlap; and / or the first openings include circular holes, elliptical holes and / or polygonal holes.

11. The solar cell according to claim 1, wherein The orthographic projection area of the first blocking layer on the light-facing surface is 4% to 70% of the orthographic projection area of the first grid line on the light-facing surface; and / or, the height of the first barrier layer is 0.5% to 65% of the height of the first gate line; And / or, along the extension direction of the first gate line, the first barrier layer is disposed continuously or discontinuously.

12. A photovoltaic module, characterized in that: The invention comprises a plurality of solar cells according to any one of claims 1 to 11 and at least one interconnecting member, wherein the interconnecting member connects two adjacent solar cells in series or in parallel; the two adjacent solar cells are respectively a first solar cell and a second solar cell, the interconnecting member is electrically connected to a first grid line of the first solar cell and extends to be electrically connected to a second grid line of the second solar cell, and the polarity of the second grid line is opposite to that of the first grid line.

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