Display assembly, preparation method thereof and display equipment

Abstract

The invention provides a display assembly, a preparation method thereof and display equipment. The display assembly includes: a substrate; the light-emitting structures are arranged on the substrate at intervals, each light-emitting structure is provided with a top surface and at least one side wall, and the side walls of the adjacent light-emitting structures define a groove with a bottom surface; the passivation layer is arranged on the top surface of the light-emitting structure and the groove, and the passivation layer is provided with a through hole in the top surface of the light-emitting structure; the conductive filling layer is arranged in the through hole and on a part of the passivation layer in the groove; and the conductive interconnection layer is arranged on the conductive filling layer and the passivation layer which is not covered by the conductive filling layer and is used for realizing electrical interconnection of the light-emitting structures. By introducing the conductive filling layer, the circuit breaking risk between the light-emitting structures is effectively solved; the through hole is formed in the top surface of the passivation layer to form the ohmic contact position, an excellent ohmic contact layer can be formed, high resistance of contact between the transparent conductive layer and the N-type epitaxial layer is avoided, and the ohmic contact capacity of the display assembly is effectively improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device preparation, and in particular to a display component and a preparation method thereof, and a display device. Background Art

[0002] Display components using existing wafer bonding routes have high aspect ratios between the trenches of the light-emitting structures (>3:1, even reaching ultra-high aspect ratios of 10:1). This is limited by the poor step coverage of PVD during the traditional transparent conductive film deposition process. The step coverage capability in high aspect ratio graphics is typically less than 10%, resulting in various wiring anomalies during product manufacturing. These wiring anomalies can manifest visually in wafer-bonded products as uneven chip lighting, or even the inability to light up within a certain range. The driving voltage of the chips that can light up is also significantly greater than the theoretical device driving voltage of 2-3V. Undoubtedly, the reliability of such devices is extremely problematic, making them difficult to market.

[0003] Therefore, the existing technology needs to be improved and enhanced. Summary of the Invention

[0004] In view of the above-mentioned deficiencies in the prior art, the purpose of the present invention is to provide a display component and its preparation method and display device, aiming to solve the problem that various connection anomalies exist in the manufacturing process of the existing display components, resulting in uneven lighting of the display components or even failure to light up within a certain range.

[0005] The technical solutions of the present invention are as follows:

[0006] In a first aspect, a display assembly comprises:

[0007] substrate;

[0008] A plurality of light emitting structures are spaced apart and arranged on the substrate, wherein the light emitting structures have a top surface and at least one side wall, and the side walls of adjacent light emitting structures define a groove having a bottom surface;

[0009] a passivation layer, disposed on the top surface of the light emitting structure and the groove, and the passivation layer has a through hole formed on the top surface of the light emitting structure;

[0010] a conductive filling layer disposed in the through hole and on a portion of the passivation layer in the trench; and

[0011] The conductive interconnection layer is arranged on the conductive filling layer and the passivation layer not covered by the conductive filling layer, and is used to realize electrical interconnection of the light-emitting structures.

[0012] The following are preferred technical solutions of the present invention, but are not intended to limit the technical solutions provided by the present invention. Through the following preferred technical solutions, the objectives and beneficial effects of the present invention can be better achieved and realized.

[0013] As a preferred technical solution, the conductive filling layer of the display assembly is made by atomic layer deposition, which can well cover the step positions in the display assembly, with a step coverage rate greater than 90%.

[0014] As a preferred technical solution, in the display assembly, the conductive filling layer and the conductive interconnect layer are made of different materials, and the resistance of the conductive filling layer is lower than that of the conductive interconnect layer. The lower resistance of the conductive filling layer than that of the conductive interconnect layer achieves good electrical conductivity while reducing power consumption.

[0015] As a preferred technical solution, the display component, wherein the material of the conductive filling layer includes metal or alloy, such as Ru, Ti, TiN, ZnO, Cu, W, Ta, TaN, etc.; the material of the conductive interconnection layer is selected from any one of indium tin oxide, zinc aluminum oxide, fluorine-doped tin oxide, zinc oxide, indium gallium zinc oxide, tin oxide, cadmium telluride, titanium dioxide and zinc sulfate.

[0016] As a preferred technical solution, in the display assembly, the partial passivation layer in the groove includes a passivation layer located on the bottom surface of the groove and a partial passivation layer located on the sidewall of the groove.

[0017] As a preferred technical solution, the display assembly, wherein the light emitting structure includes a bonding layer, a current diffusion layer and an epitaxial layer sequentially arranged on the substrate;

[0018] The portion of the passivation layer located on the sidewall of the trench at least covers the bonding layer, the current diffusion layer and a portion of the epitaxial layer.

[0019] In a second aspect, a method for preparing a display assembly comprises the following steps:

[0020] Providing an epitaxial wafer and a substrate;

[0021] bonding the epitaxial wafer and the substrate to form an intermediate structure;

[0022] Etching the intermediate structure to obtain a plurality of light-emitting structures spaced apart on the substrate, wherein the light-emitting structure has a top surface and at least one sidewall, and the sidewalls of adjacent light-emitting structures define a groove having a bottom surface;

[0023] depositing a passivation layer on the top surface and the grooves of the light emitting structure;

[0024] A through hole is formed on the top surface of the passivation layer corresponding to the light emitting structure;

[0025] forming a conductive filling layer in the through hole and on a portion of the passivation layer in the trench; and

[0026] A conductive interconnection layer is formed on the conductive filling layer and the passivation layer not covered by the conductive filling layer.

[0027] As a preferred technical solution, the method for preparing the display assembly, wherein the step of bonding the epitaxial wafer and the substrate to form an intermediate structure comprises:

[0028] forming a first bonding layer on the substrate;

[0029] forming a second bonding layer on a side of the epitaxial wafer facing away from the growth substrate;

[0030] Bonding the substrate and the epitaxial wafer together through bonding the first bonding layer and the second bonding layer;

[0031] The growth substrate is peeled off to obtain the intermediate structure.

[0032] As a preferred technical solution, the method for preparing the display assembly, wherein the step of forming a conductive filling layer on a portion of the passivation layer in the through hole and in the groove comprises:

[0033] A conductive layer is formed in the through hole and on the passivation layer using an atomic layer deposition process;

[0034] A photoresist pattern is formed on the conductive layer; wherein the photoresist pattern is formed on the through hole and a portion of the passivation layer in the trench;

[0035] The conductive layer not blocked by the photoresist pattern is etched by a plasma etching process to form a conductive filling layer.

[0036] In a third aspect, a display device includes a driving circuit and the display component as described above, wherein the display component is electrically connected to the driving circuit.

[0037] Beneficial effects: The display assembly provided by the present invention provides a passivation layer, a conductive filling layer and a conductive interconnection layer in the grooves defined by the side walls of adjacent light-emitting structures, so that the connection will not be abnormal and the display module can be lit more evenly. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 is a partial cross-sectional view of a display assembly in one embodiment of the present application;

[0039] Figure 2 Schematic diagram of a process for preparing a display component in one embodiment of the present application;

[0040] Figure 3-Figure 10A schematic diagram of structural changes corresponding to a method for manufacturing a display assembly provided in an embodiment of the present invention;

[0041] Figure 11 Schematic diagram of a process for preparing a display component in another embodiment of the present application.

[0042] Explanation of the accompanying drawings: 10. Substrate; 11. Light-emitting structure; 20. Bonding layer; 21. First bonding layer; 22. Second bonding layer; 30. Current diffusion layer; 40. Epitaxial layer; 41. Photosensitive material; 42. Mesa; 43. Groove; 50. Growth substrate; 60. Hard mask; 61. Ohmic contact; 70. Passivation layer; 80. Conductive filling layer; 81. Photoresist pattern; 90. Conductive interconnect layer; 100. Lens layer. DETAILED DESCRIPTION

[0043] The present invention provides a method for manufacturing a display assembly and a method for manufacturing the same. To make the objectives, technical solutions, and effects of the present invention more clear and explicit, the present invention is further described below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only intended to illustrate the present invention and are not intended to limit the present invention.

[0044] The serial numbers assigned to the components herein, such as "first", "second", etc., are only used to distinguish the objects described and do not have any order or technical meaning. The "connection" and "coupling" mentioned in the present invention include direct and indirect connections (couplings) unless otherwise specified. In the description of the present invention, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation to the present invention.

[0045] In the present invention, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediary. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0046] Please refer to Figure 1 ,like Figure 1As shown, the display assembly provided by the present invention includes: a substrate 10 , a plurality of light emitting structures 11 arranged on the substrate 10 , and a passivation layer 70 , a conductive filling layer 80 and a conductive interconnection layer 90 formed on the surface of the light emitting structures 11 .

[0047] Specifically, a plurality of light emitting structures 11 are fixed on the substrate 10 in an interval arrangement, and the light emitting structure 11 has a top surface and at least one side wall, and the side walls of adjacent light emitting structures 11 define a groove 43 having a bottom surface. Figure 4 The light emitting structure 11 includes: a bonding layer 20 formed on the surface of the substrate 10, a current diffusion layer 30 formed on the surface of the bonding layer 20, and an epitaxial layer 40 formed on the surface of the current diffusion layer 30 (the epitaxial layer 40 is etched to form a mesa 42). The substrate 10 can be one of silicon, CMOS substrate, PCB substrate or glass substrate. The conductive filling layer 80 is made of metal or alloy. Figure 1 It can be seen that the two light-emitting structures 11 can be connected through the conductive filling layer 80 and the conductive interconnection layer 90, which effectively solves the risk of short circuit between the light-emitting structures, improves the yield of the display component, and improves the reliability of the device while solving the uneven lighting between the light-emitting structures.

[0048] In one implementation of this embodiment, the material of the current diffusion layer 30 is selected from any one of indium tin oxide, aluminum zinc oxide, fluorine-doped tin oxide, zinc oxide, indium gallium zinc oxide, tin oxide, cadmium telluride, titanium dioxide, and zinc sulfate; and the material of the conductive interconnect layer 90 is selected from any one of indium tin oxide, aluminum zinc oxide, fluorine-doped tin oxide, zinc oxide, indium gallium zinc oxide, tin oxide, cadmium telluride, titanium dioxide, and zinc sulfate. The thickness of the conductive interconnect layer 90 is 1500-5000 Å, for example, 1500 Å to 2000 Å, or 2000 Å to 2500 Å, or 2500 Å to 3000 Å, or 3000 Å to 3500 Å, or 3500 Å to 4000 Å, or 4000 Å to 4500 Å, or 4500 Å to 5000 Å.

[0049] In one implementation of this embodiment, the conductive filling layer 80 can be formed using an atomic layer deposition process. By using the atomic layer deposition process to prepare the conductive filling layer 80, a higher step coverage (>90%) can be achieved, allowing the conductive filling layer 80 to fully cover the bottom and sidewalls of the trench 43 without causing wiring anomalies.

[0050] In one implementation of this embodiment, the conductive filling layer 80 and the conductive interconnect layer 90 are made of different materials, and the resistance of the conductive filling layer 80 is lower than that of the conductive interconnect layer 90. The conductive filling layer 80 is made of a metal or alloy, such as Ru, Ti, TiN, ZnO, Cu, W, Ta, or TaN; while the conductive interconnect layer 90 is made of materials including, but not limited to, indium tin oxide, aluminum zinc oxide, fluorine-doped tin oxide, zinc oxide, indium gallium zinc oxide, tin oxide, cadmium telluride, titanium dioxide, and zinc sulfate. Compared to the resistance of the conductive interconnect layer 90, the conductive filling layer 80 has a lower resistance. This lower resistance not only achieves better connectivity but also reduces the power consumption of the entire display assembly.

[0051] In one implementation of this embodiment, Figure 1 As shown, the partial passivation layer in the groove 43 includes a passivation layer located on the bottom surface of the groove 43 and a partial passivation layer located on the side wall of the groove 43; and the partial passivation layer located on the side wall of the groove 43 at least covers the bonding layer 20, the current diffusion layer 30 and a portion of the epitaxial layer 40, that is, the passivation layer 70 achieves full coverage of the side wall of the light-emitting structure 11 and the groove formed by the side wall, thereby ensuring the performance of the display component.

[0052] In one implementation of this embodiment, Figure 1 and Figure 7 An ohmic contact position 61 (i.e., a through hole opened by the passivation layer 70 on the top surface of the light-emitting structure) is also provided at the end of the light-emitting structure 11, and a conductive filling layer 80 is also provided on the ohmic contact position. Since the metal free electron concentration forming the conductive filling layer 80 is high, an excellent ohmic contact layer can be formed under the condition of a suitable work function, thereby avoiding the high resistance of the contact between the conductive interconnect layer 90 and the epitaxial layer, and effectively improving the ohmic contact capability of the display component.

[0053] In one implementation of this embodiment, Figure 11 The display component further includes: a lens layer 100, which refers to a layer formed on the surface of the conductive interconnect layer 90 to increase the brightness of the device. This layer is defined as a lens layer.

[0054] Based on the same inventive concept, the present invention also provides a method for preparing a display assembly, such as Figure 2 As shown, the preparation method comprises the following steps:

[0055] S100, providing an epitaxial wafer and a substrate;

[0056] S200, bonding the epitaxial wafer and the substrate to form an intermediate structure;

[0057] S300, etching the intermediate structure to obtain a plurality of light-emitting structures spaced apart from each other on the substrate; wherein the light-emitting structure has a top surface and at least one sidewall, and the sidewalls of adjacent light-emitting structures define a groove having a bottom surface;

[0058] S400, depositing a passivation layer on the top surface of the light-emitting structure and the groove;

[0059] S500, opening a through hole on the top surface of the passivation layer corresponding to the light-emitting structure;

[0060] S600, forming a conductive filling layer on a portion of the passivation layer in the through hole and in the trench; and

[0061] S700 , fabricating a conductive interconnection layer on the conductive filling layer and the passivation layer not covered by the conductive filling layer.

[0062] In this embodiment, a conductive filling layer is formed on a portion of the passivation layer in the through hole and the groove, thereby effectively solving the risk of short circuit between the light-emitting structures and improving the reliability of the device while solving the problem of uneven lighting between the light-emitting structures.

[0063] In one implementation of this embodiment, step S200 specifically includes:

[0064] S210, forming a first bonding layer on the substrate;

[0065] S220, forming a second bonding layer on a side of the epitaxial wafer facing away from the growth substrate;

[0066] S230, bonding the substrate and the epitaxial wafer together by bonding the first bonding layer and the second bonding layer;

[0067] S240: Peeling off the growth substrate to obtain the intermediate structure.

[0068] Specifically, the first bonding layer 21 and the second bonding layer 22 can be deposited on the surface of the substrate 10 and the surface of the epitaxial layer 40 respectively by electron beam evaporation equipment or magnetron sputtering equipment, and the substrate 10 and the epitaxial layer 40 can be bonded by using a bonding device (such as Figure 3 After bonding, the growth substrate 50 is peeled off using a laser lift-off process to obtain an intermediate structure. The thickness of the bonding layer 20 formed after bonding is 2600-6000 Å. For example, it can be 2600 Å to 3000 Å, 3000 Å to 3500 Å, 3500 Å to 4000 Å, 4000 Å to 4500 Å, 4500 Å to 5000 Å, 5000 Å to 5500 Å, or 5500 Å to 6000 Å.

[0069] In one implementation of this embodiment, Figure 4 , a layer of photosensitive material (such as photoresist) 41 is coated on the surface of the epitaxial layer 40 of the intermediate structure to form a uniform covering layer. The desired etching pattern is projected onto the photoresist using a photolithography machine. Through the development process, the unprotected area of the photoresist is removed to expose the etching area. The exposed area is removed using a chemical etching method to form a mesa 42. The mesa 42 is cleaned to remove the residual photoresist and corrosion products. Combined Figure 5 On the surface of the mesa 42, a metal etching hard mask 60 is produced by using a photolithography process and an inductively coupled plasma (ICP) etching process. The bonding layer 20 and the current diffusion layer 30 are etched using an ICP / IBE inductively coupled plasma etcher to form grooves 43 between the light-emitting structures 11. The grooves 43 are used to separate adjacent light-emitting structures, thereby obtaining a plurality of light-emitting structures spaced apart on the substrate.

[0070] In one implementation of this embodiment, the hard mask 60 remaining on the light emitting structure is removed; a passvision (abbreviated as PV) layer, i.e., a passivation layer 70, is deposited on the top surface and the grooves of the light emitting structure using plasma enhanced / atomic layer PECVD / ALD deposition technology, such as Figure 6 As shown, the passivation layer 70 is used to protect the sidewalls of the light emitting structure.

[0071] In one implementation of this embodiment, the passivation layer at the end of the light emitting structure is removed by etching, and a through hole is formed on the passivation layer 70 to expose the epitaxial layer (forming the ohmic contact position 61). Figure 7 shown.

[0072] In one implementation of this embodiment, step S600 specifically includes:

[0073] S610, forming a conductive layer in the through hole and on the passivation layer by using an atomic layer deposition process;

[0074] S620, forming a photoresist pattern on the conductive layer; wherein the photoresist pattern is formed on the through hole and a portion of the passivation layer in the trench;

[0075] S630 , etching the conductive layer not blocked by the photoresist pattern using a plasma etching process to form the conductive filling layer.

[0076] ALD equipment is used to deposit metal or metal oxide, metal nitride, etc. in the through hole and on the passivation layer to form a conductive layer, a photoresist pattern 81 is made on the through hole and a portion of the passivation layer in the groove, and a plasma etching process is used to etch the conductive layer not blocked by the photoresist pattern to form the conductive filling layer 80. Figure 8As shown. Among them, the metal or compound includes (Ru, Ti, TiN, ZnO, Cu, W, Ta, TaN and other materials. By using ALD equipment to deposit the conductive filling layer 80, the step coverage capability can be improved, which can well solve the problem of graphic aspect ratio >3:1 in the existing wafer bonding project. The transparent conductive layer (such as ITO layer) deposited by the PVD equipment commonly used in the LED industry has a step coverage capability of <10% in graphics with high aspect ratios, resulting in abnormal connections between light-emitting structures, thereby improving the yield of the product. It is easy to understand that the conductive filling layer 80 deposited at the end of the light-emitting structure is in direct contact with the epitaxial layer in the light-emitting structure. Due to the high concentration of free electrons in the metal, an excellent ohmic contact layer can be formed under conditions with a suitable work function, avoiding the high resistance of the conductive interconnect layer 90 in contact with the epitaxial layer, and effectively improving the ohmic contact capability of the display component.

[0077] Combine Figure 9 The conductive filler layer 80 located on the sidewalls of the light-emitting structure is etched away using ICP / RIE / IBE to prevent the metal film from blocking visible light transmission, which could affect the external quantum efficiency of the display component and result in substandard device brightness. Because a photoresist pattern is formed within trench 43, the metal between pixels is protected by the photoresist during the etching process, forming a single piece. The subsequent ITO can contact the metal at its upper edge, forming a pathway, avoiding short circuits caused by step coverage issues in ITO deposits with high aspect ratio patterns.

[0078] like Figure 10 As shown, a conductive interconnect layer 90 can be deposited on the surface of the remaining conductive filling layer 80 and the exposed passivation layer using electron beam evaporation equipment or magnetron sputtering equipment, ensuring good wiring and good visible light transmittance of the sidewalls of the light-emitting structure. In other words, by depositing the conductive filling layer in areas prone to disconnection (grooves) before forming the conductive interconnect layer 90, good wiring is ensured, and the metal conductive layer on the sidewalls of the light-emitting structure where light is emitted is etched away without affecting the light transmittance of the sidewalls.

[0079] In one implementation of this embodiment, a lens layer 100 is further deposited on the surface of the conductive interconnect layer 90. The material used to form the lens layer can be silicon dioxide, amorphous silicon, aluminum oxide, silicon nitride, etc. Figure 11 A silicon dioxide layer of a certain thickness is deposited on the surface of the light-emitting structure, and the silicon dioxide layer is subjected to photolithography and etching to form a MicroLens pattern (i.e., lens layer 100), thereby obtaining a display component. The MicroLens pattern is then etched out through photolithography to increase the brightness of the display component.

[0080] Based on the same inventive concept, the present invention further provides a display device, comprising a driving circuit and the above-mentioned display component, wherein the display component is electrically connected to the driving circuit.

[0081] In summary, the present invention provides a display component, a preparation method thereof, and a display device. The display component includes: a substrate; a plurality of light-emitting structures arranged at intervals on the substrate, the light-emitting structure having a top surface and at least one sidewall, and the sidewalls of adjacent light-emitting structures define a groove having a bottom surface; a passivation layer arranged on the top surface of the light-emitting structure and the groove, and the passivation layer has a through hole on the top surface of the light-emitting structure; a conductive filling layer arranged in the through hole and on a portion of the passivation layer in the groove; and a conductive interconnection layer arranged on the conductive filling layer and the passivation layer not covered by the conductive filling layer, for realizing electrical interconnection of the light-emitting structures. By introducing the conductive filling layer, the risk of short circuit between the light-emitting structures is effectively solved. A through hole is opened on the top surface of the passivation layer to form an ohmic contact position. Due to the high concentration of free electrons in the metal, an excellent ohmic contact layer can be formed under the condition of a suitable work function, avoiding the high resistance of the contact between the transparent conductive layer and the epitaxial layer, and effectively improving the ohmic contact capability of the display component.

[0082] It should be understood that the application of the present invention is not limited to the above examples. For ordinary technicians in this field, they can make improvements or changes based on the above description. All these improvements and changes should fall within the scope of protection of the claims attached to this invention.

Claims

1. A display component, characterized in that: include: substrate; a plurality of light emitting structures disposed on the substrate at intervals, wherein the light emitting structures have a top surface and at least one sidewall, and the sidewalls of adjacent light emitting structures define a groove having a bottom surface; a passivation layer, disposed on the top surface of the light emitting structure and the groove, wherein the passivation layer has a through hole formed on the top surface of the light emitting structure; a conductive filling layer, disposed in the through hole and on a portion of the passivation layer in the trench; as well as The conductive interconnection layer is arranged on the conductive filling layer and the passivation layer not covered by the conductive filling layer, and is used to realize the electrical interconnection of the light-emitting structures.

2. The display assembly according to claim 1, wherein The conductive filling layer is made by adopting an atomic layer deposition process.

3. The display assembly according to claim 2, wherein: The conductive filling layer and the conductive interconnection layer are made of different materials, and the resistance of the conductive filling layer is smaller than the resistance of the conductive interconnection layer.

4. The display assembly according to claim 3, wherein: The material of the conductive filling layer includes metal or alloy; the material of the conductive interconnect layer is selected from any one of indium tin oxide, aluminum zinc oxide, fluorine-doped tin oxide, zinc oxide, indium gallium zinc oxide, tin oxide, cadmium telluride, titanium dioxide and zinc sulfate.

5. The display assembly according to claim 1, wherein: The partial passivation layer in the trench includes a passivation layer located on the bottom surface of the trench and a partial passivation layer located on the sidewall of the trench.

6. The display assembly according to claim 5, characterized in that The light emitting structure includes a bonding layer, a current diffusion layer and an epitaxial layer sequentially arranged on the substrate; Wherein, the portion of the passivation layer located on the sidewall of the trench at least covers the bonding layer, the current diffusion layer and a portion of the epitaxial layer.

7. A method for preparing a display component, characterized in that: The steps include: Providing an epitaxial wafer and a substrate; bonding the epitaxial wafer and the substrate to form an intermediate structure; Etching the intermediate structure to obtain a plurality of light-emitting structures spaced apart from each other on the substrate, wherein the light-emitting structure has a top surface and at least one sidewall, and the sidewalls of adjacent light-emitting structures define a groove having a bottom surface; depositing a passivation layer on the top surface of the light emitting structure and the groove; opening a through hole on the top surface of the passivation layer corresponding to the light emitting structure; forming a conductive filling layer on a portion of the passivation layer in the through hole and in the trench; and A conductive interconnection layer is fabricated on the conductive filling layer and the passivation layer not covered by the conductive filling layer.

8. The method for preparing a display assembly according to claim 7, wherein: The step of bonding the epitaxial wafer and the substrate to form an intermediate structure comprises: forming a first bonding layer on the substrate; forming a second bonding layer on a side of the epitaxial wafer facing away from the growth substrate; Bonding the substrate and the epitaxial wafer together through bonding the first bonding layer and the second bonding layer; The growth substrate is peeled off to obtain the intermediate structure.

9. The method for preparing a display assembly according to claim 7, wherein: The step of forming a conductive filling layer on a portion of the passivation layer in the through hole and in the trench comprises: Fabricating a conductive layer in the through hole and on the passivation layer using an atomic layer deposition process; Fabricating a photoresist pattern on the conductive layer; wherein the photoresist pattern is formed on the through hole and a portion of the passivation layer in the trench; The conductive layer not blocked by the photoresist pattern is etched by a plasma etching process to form the conductive filling layer.

10. A display device, characterized in that: The device comprises a driving circuit and a display component according to any one of claims 1 to 6, wherein the display component is electrically connected to the driving circuit.

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