Display panel and display device

Abstract

The invention discloses a display panel and a display device.The display panel comprises a substrate and a transistor, the display panel further comprises a shading structure, and the shading structure is located between a film layer where an active layer is located and a film layer where a gate electrode is located in the first direction; the shading structure comprises a first shading edge, the gate electrode comprises a first gate electrode edge, the orthographic projection of the first shading edge on the plane where the substrate is located is a first shading projection edge, and the orthographic projection of the first gate electrode edge on the plane where the substrate is located is a first gate electrode projection edge. The projection of the center of the active layer on the plane where the substrate is located is the projection center of the active layer. In the second direction, the first shading projection edge and the first gate electrode projection edge are located on the same side of the projection center of the active layer, and the first shading projection edge is located on the side, away from the projection center of the active layer, of the projection edge of the first gate electrode, so that the influence of visible light on the active layer can be blocked, and the illumination bias reliability of the transistor is improved; and the performance of the display panel is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In existing display panels, the gate electrode in the transistor can only block light in the vertical direction, and has a relatively weak ability to block lateral light along the length of the transistor channel. This results in more light entering the channel, causing the transistor's threshold voltage to drift significantly, affecting product use. Summary of the Invention

[0003] Embodiments of the present invention provide a display panel and a display device to block the influence of visible light on an active layer, improve the reliability of light bias voltage of transistors, and enhance the performance of the display panel.

[0004] In a first aspect, an embodiment of the present invention provides a display panel, comprising a substrate and a transistor located on one side of the substrate, wherein the transistor comprises an active layer, a gate electrode, and a source-drain electrode:

[0005] The gate electrode is located on at least one side of the active layer, and along a first direction, the gate electrode and the active layer at least partially overlap; the first direction is the thickness direction of the display panel;

[0006] The source-drain electrode is electrically connected to the active layer;

[0007] The display panel also includes a shading structure, and along the first direction, the shading structure is located between the film layer where the active layer is located and the film layer where the gate electrode is located; the shading structure includes a first shading edge, and the gate electrode includes a first gate electrode edge, the first shading edge has an orthographic projection on the plane where the substrate is located as the first shading projection edge, the first gate electrode edge has an orthographic projection on the plane where the substrate is located as the first gate electrode projection edge, and the center of the active layer is projected on the plane where the substrate is located as the active layer projection center; along the second direction, the first shading projection edge and the first gate electrode projection edge are located on the same side of the active layer projection center, and the first shading projection edge is located on the side of the first gate electrode projection edge away from the active layer projection center; the second direction is the length direction of the channel region in the active layer.

[0008] In a second aspect, an embodiment of the present invention further provides a display device, comprising the display module of the first aspect.

[0009] The technical solution provided by an embodiment of the present invention provides a light-shielding structure between the film layer where the active layer is located and the film layer where the gate electrode is located. Such a light-shielding structure can block visible light, thereby reducing the impact of visible light on the active layer. Specifically, along the second direction, that is, along the length direction of the channel region in the active layer, the first light-shielding projected edge and the first gate electrode projected edge are located on the same side of the active layer projected center, and the first light-shielding projected edge is located on the side of the first gate electrode projected edge away from the active layer projected center. In this way, the light-shielding structure can block lateral light, thereby reducing the light entering the channel region, blocking the impact of visible light on the active layer, improving the light bias reliability of the transistor, and enhancing the performance of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 Schematic diagram of a top view of a transistor on a substrate in the prior art;

[0011] Figure 2 for Figure 1 A schematic cross-sectional structure diagram of the corresponding transistor along the section line AA';

[0012] Figure 3 A schematic top view of a first transistor on a substrate provided by an embodiment of the present invention;

[0013] Figure 4 for Figure 3 A schematic cross-sectional structure diagram of the corresponding transistor along the section line BB';

[0014] Figure 5 A schematic cross-sectional view of a display panel provided by an embodiment of the present invention;

[0015] Figure 6 A schematic top view of a second transistor on a substrate provided by an embodiment of the present invention;

[0016] Figure 7 for Figure 6 A schematic diagram of a first cross-sectional structure of the corresponding transistor along the cross-sectional line CC';

[0017] Figure 8 A schematic top view of a third transistor on a substrate provided by an embodiment of the present invention;

[0018] Figure 9 for Figure 8 A schematic diagram of a first cross-sectional structure of the corresponding transistor along the cross-sectional line DD';

[0019] Figure 10 A schematic top view of a fourth transistor on a substrate provided by an embodiment of the present invention;

[0020] Figure 11 for Figure 10A schematic cross-sectional structure diagram of the corresponding transistor along the section line EE';

[0021] Figure 12 for Figure 8 A schematic diagram of a second cross-sectional structure of the corresponding transistor along the cross-sectional line DD';

[0022] Figure 13 for Figure 6 A schematic diagram of a second cross-sectional structure of the corresponding transistor along the cross-sectional line CC';

[0023] Figure 14 for Figure 6 A schematic diagram of a third cross-sectional structure of the corresponding transistor along the cross-sectional line CC';

[0024] Figure 15 A schematic top view of a fifth transistor on a substrate provided by an embodiment of the present invention;

[0025] Figure 16 for Figure 15 Schematic diagram of the cross-sectional structure of the corresponding transistor along the section line F-F'

[0026] Figure 17 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0027] The present invention will be further described in detail below with reference to the accompanying drawings and examples. It will be understood that the specific embodiments described herein are intended only to illustrate the present invention and are not intended to limit the present invention. It should also be noted that, for ease of description, the accompanying drawings only illustrate portions relevant to the present invention, not all structures.

[0028] Before introducing the technical solutions of the embodiments of the present invention in detail, the technical problems existing in the prior art are first explained.

[0029] Figure 1 FIG1 is a top view schematic diagram of a transistor on a substrate in the prior art. Figure 2 for Figure 1 The cross-sectional structure diagram of the corresponding transistor along the cross-sectional line AA' is as follows: Figure 1 and Figure 2 As shown, the visible light rays are Figure 2 As shown by the dotted arrow in the figure, in the width direction of the channel region (such as Figure 1 In the Y direction shown in FIG), the gate electrode 102' extends far beyond the channel region, thereby shielding most of the lateral light; however, in the length direction of the channel region (as shown in FIG), the gate electrode 102' extends far beyond the channel region, thereby shielding most of the lateral light. Figure 1In the X direction shown in the figure), the length of the channel region in the conventional design is controlled by top gate self-aligned injection, and the active layer 101' outside the channel region is conductorized by self-aligned injection. The transistor in the prior art can only block the light in the vertical direction through the gate electrode 102', and the lateral light blocking in the length direction of the channel region is relatively weak, that is, the lateral light can be incident on the active layer, which leads to more light entering the channel region, and it is easy to generate a large light leakage due to the light, affecting the display effect. Furthermore, when the active layer 101' of the transistor 10' includes an oxide active layer, the oxide active layer is more sensitive to light due to the low band gap width of the oxide active layer. There are more neutral oxygen vacancies in the oxide active layer, and under the action of light, electrons are more likely to jump to the conduction band, and the generated charged particles are trapped at the interface between the channel and the insulating layer under the action of the gate voltage, causing the threshold voltage to be severely negatively biased, affecting the performance of the display panel.

[0030] In order to solve the technical problems existing in the prior art, the technical solutions of the embodiments of the present invention are proposed, and the technical solutions of the embodiments of the present invention are described in detail below.

[0031] Figure 3 A schematic top view of a first transistor on a substrate provided by an embodiment of the present invention, Figure 4 for Figure 3 The corresponding cross-sectional structure diagram of the transistor along the section line BB', Figure 5 A cross-sectional schematic diagram of a display panel provided by an embodiment of the present invention is shown in FIG. Figure 3-Figure 5 As shown, the display panel 100 includes a substrate 20 and a transistor 10 located on one side of the substrate 20. The transistor 10 includes an active layer 101, a gate electrode 102, and a source-drain electrode 103. The gate electrode 103 is located on at least one side of the active layer 101 and extends along a first direction (e.g., Figure 4 ), the gate electrode 103 at least partially overlaps the active layer 101; the first direction Z is the thickness direction of the display panel; the source-drain electrode 103 is electrically connected to the active layer 101; the display panel 100 further includes a light shielding structure 30, along the first direction Z, the light shielding structure 30 is located between the film layer where the active layer 101 is located and the film layer where the gate electrode 102 is located; the light shielding structure 30 includes a first light shielding edge 301, the gate electrode 102 includes a first gate electrode edge 1021, the orthographic projection of the first light shielding edge 301 on the plane where the substrate 20 is located is the first light shielding projection edge 3011, the orthographic projection of the first gate electrode edge 1021 on the plane where the substrate 20 is located is the first gate electrode projection edge 10211, and the projection of the center of the active layer 101 on the plane where the substrate 20 is located is the active layer projection center O; along the second direction (as Figure 3The first light-shielding projection edge 3011 and the first gate electrode projection edge 10211 are located on the same side of the active layer projection center O, and the first light-shielding projection edge 3011 is located on the side of the first gate electrode projection edge 10211 away from the active layer projection center O; the second direction X is the length direction of the channel region in the active layer.

[0032] Specifically, such as Figure 5 As shown, the display panel includes a plurality of pixel circuits 200 arranged in an array, and the pixel circuit 200 is used to receive a scanning signal and be turned on or off under the action of the scanning signal to provide the data signal provided by the data signal line to the pixel unit, or stop providing the data signal to the pixel unit. Among them, the pixel circuit 200 may include one or more transistors 10. Taking the organic light-emitting display panel as an example, the pixel circuit may include at least two transistors 10 and at least one storage capacitor. For example, the pixel circuit may be a pixel circuit of a "2T1C" structure, or a pixel circuit of a "7T1C" structure, where "T" represents a thin film transistor and "C" represents a storage capacitor. The embodiment of the present invention does not limit the specific composition of the pixel circuit, and may be limited according to the requirements and the type of display panel.

[0033] For details, please refer to Figure 3-Figure 5 The transistor 10 includes an active layer 101, a gate electrode 102, and a source-drain electrode 103. The gate electrode 102 at least partially overlaps the active layer 101, and the region of the active layer 101 that overlaps with the gate electrode 102 is a channel region. The source-drain electrode 103 includes a source electrode and a drain electrode. The source electrode is provided corresponding to the source region of the active layer 101, and the drain electrode is provided corresponding to the drain region of the active layer 101. Under the action of the gate electrode signal, the channel region is turned on, changing from a non-conducting state to a conducting state, forming a path between the corresponding source electrode and drain electrode.

[0034] As a feasible embodiment, the gate electrode 102 can be located on the side of the active layer 101 close to the substrate 20, that is, the gate electrode 102 can be a bottom gate. In this way, the gate electrode 102 can serve as the lower light-shielding structure of the channel region, that is, it can block the light below the active layer 101 and vertically toward the active layer 10, thereby preventing the light from entering the channel region and causing threshold voltage drift.

[0035] As another feasible embodiment, the gate electrode 102 can also be located on the side of the active layer 101 away from the substrate 20, that is, the gate electrode 102 can be a top gate, so that the gate electrode 102 can serve as an upper light-shielding structure in the channel region, that is, it can block the light above the active layer 101 and vertically toward the active layer 10, to prevent the light from entering the channel region and causing threshold voltage drift.

[0036] As another feasible embodiment, the gate electrode 102 can be located on the side of the active layer 101 close to the substrate 20, and the gate electrode 102 can also be located on the side of the active layer 101 away from the substrate 20, that is, the gate electrode 102 includes a top gate and a bottom gate. In this way, on the one hand, the top and bottom double gates can be used to improve the shading effect of the channel region, and on the other hand, the gate control capability can be improved, thereby improving the performance of the display panel.

[0037] For further reference, Figure 5 The display panel may further include a first electrode 40, a second electrode 50, and a light-emitting layer located between the first electrode 40 and the second electrode 50. The first electrode 40 may be an anode, and the second electrode 50 may be a cathode. Holes provided by the first electrode 40 and electrons provided by the second electrode 50 recombine in the light-emitting layer to emit light, thereby realizing the display function of the display panel.

[0038] Specifically, Figure 6 A schematic top view of a second transistor on a substrate provided by an embodiment of the present invention, Figure 7 for Figure 6 The corresponding transistor is a schematic diagram of a first cross-sectional structure along the cross-sectional line CC'. Figure 8 A schematic top view of a third transistor on a substrate provided by an embodiment of the present invention, Figure 9 for Figure 8 The first cross-sectional structure diagram of the corresponding transistor along the cross-sectional line D-D' is as follows: Figure 3-Figure 9 As shown, along the first direction Z, the light shielding structure 30 is located between the film layer where the active layer 101 is located and the film layer where the gate electrode 102 is located. As a feasible embodiment, continue to refer to Figure 3 and Figure 4 The light shielding structure 30 is located between the film layer where the active layer 101 is located and the film layer where the second gate electrode 102-2 is located. In this way, the light shielding structure 30 can block the lateral light below the active layer 101. As another feasible embodiment, continue to refer to Figure 8 and Figure 9 The light shielding structure 30 is located between the film layer where the active layer 101 is located and the film layer where the first gate electrode 102-1 is located, so that the light shielding structure 30 can block the lateral light above the active layer 101. As another feasible embodiment, continue to refer to Figure 6 and Figure 7 The shading structure 30 is located between the film layer where the active layer 101 is located and the film layer where the second gate electrode 102-2 is located, and the shading structure 30 is also located between the film layer where the active layer 101 is located and the film layer where the first gate electrode 102-1 is located. In this way, the lateral light incident on the active layer 101 can be blocked. On the one hand, it can realize the diversified setting of the display panel, and on the other hand, it can improve the light blocking effect of the shading structure 30 on light.

[0039] For details, please refer to Figure 3-Figure 9 The light-shielding structure 30 includes a first light-shielding edge 301, and the gate electrode 102 includes a first gate electrode edge 1021. The orthographic projection of the first light-shielding edge 301 on the plane of the substrate 20 is a first light-shielding projected edge 3011. The orthographic projection of the first gate electrode edge 1021 on the plane of the substrate 20 is a first gate electrode projected edge 10211. The projection of the center of the active layer 101 on the plane of the substrate 20 is the active layer projected center O. Along the second direction X, the first light-shielding projected edge 3011 and the first gate electrode projected edge 10211 are located on the same side of the active layer projected center O, and the first light-shielding projected edge 3011 is located on the side of the first gate electrode projected edge 10211 away from the active layer projected center O. That is to say, along the second direction X, compared with the first gate electrode projection edge 10211, the first shading structure projection edge 3011 is farther away from the active layer projection center O, which is beneficial to blocking the lateral light through the shading structure 30, and then on the basis of preventing vertical light from entering the active layer on the gate electrode 102, the shading structure 30 can prevent lateral light from entering the active layer 101, and further reduce the light entering the channel region in the length direction of the channel region, which is beneficial to improving the light bias reliability of the transistor and improving the performance of the display panel.

[0040] The display panel provided by an embodiment of the present invention employs a light-shielding structure disposed between the film layer containing the active layer and the film layer containing the gate electrode. This light-shielding structure can block visible light, thereby reducing the impact of visible light on the active layer. Furthermore, a first light-shielding projected edge is located on the side of the first gate electrode projected edge away from the projected center of the active layer. This light-shielding structure can block lateral light, thereby reducing the amount of light entering the channel region, blocking the impact of visible light on the active layer, improving the reliability of the transistor's light bias, and enhancing the performance of the display panel.

[0041] Optional, continue to refer to Figure 3 and Figure 4 The shading structure 30 also includes a second shading edge 302, the orthographic projection of the second shading edge 302 on the plane where the substrate is located is a second shading projection edge 3021; along the second direction X, the second shading projection edge 3021 is located on the side of the first gate electrode projection edge 10211 close to the active layer projection center O.

[0042] Specifically, the second light-shielding edge 302 can be understood as the light-shielding edge located near the center of the active layer of the light-shielding structure 30. Along the second direction X, the second light-shielding projected edge 3021 is located on the side of the first gate electrode projected edge 10211 that is closer to the projected center O of the active layer. This prevents light from entering the active layer 101 from the position between the gate electrode 102 and the light-shielding structure 30, thereby further reducing the amount of light entering the channel region along the length direction of the channel region, thereby improving the light bias reliability of the transistor and enhancing the performance of the display panel.

[0043] Optional, continue to refer to Figure 3 and Figure 4 Along the second direction X, the distance between the second light-shielding projection edge 3021 and the first gate electrode projection edge 10211 is L1; along the first direction Z, the distance between the film layer where the light-shielding structure 30 is located and the film layer where the gate electrode 102 is located is L2; wherein, L1 is positively correlated with L2.

[0044] Specifically, along the first direction Z, the greater the distance between the film layer where the light-shielding structure 30 is located and the film layer where the gate electrode 102 is located, the weaker the light-shielding effect of the light-shielding structure 30 on the active layer 101, that is, the easier it is for light to pass through the gap between the light-shielding structure 30 and the gate electrode 102 and enter the active layer 101. By setting L1 and L2 to be positively correlated, that is, the larger L2 is, the larger L1 is, and the greater the distance between the film layer where the light-shielding structure 30 is located and the film layer where the gate electrode 102 is located, setting the distance between the second light-shielding projected edge 3021 and the first gate electrode projected edge 10211 to be greater along the second direction X, more lateral light is blocked by the light-shielding structure 30, thereby reducing the light entering the channel region, improving the light bias reliability of the transistor, and enhancing the performance of the display panel.

[0045] Optional, continue to refer to Figure 4 , along the first direction Z, the light shielding structure 30 overlaps with the active layer 101 .

[0046] Specifically, along the first direction Z, the shading structure 30 overlaps with the active layer 101, so that the shading structure 30 can block the light incident on the active layer 101, thereby reducing the light incident on the active layer 101, that is, reducing the light entering the channel area, which is beneficial to improving the light bias reliability of the transistor and improving the performance of the display panel.

[0047] Optional, continue to refer to Figure 4 , the length of the overlapping region between the light shielding structure 30 and the active layer 101 in the second direction X is greater than zero.

[0048] Specifically, the length of the overlapping area between the shading structure 30 and the active layer 101 in the second direction X is greater than zero. In this way, the shading structure 30 overlapping with the active layer 101 can block the light incident on the active layer 101, thereby reducing the light incident on the active layer 101, that is, reducing the light entering the channel area, which is beneficial to improving the light bias reliability of the transistor and improving the performance of the display panel.

[0049] Optional, continue to refer to Figure 4 The light-shielding structure 30 includes a first light-shielding section 30-1 and a second light-shielding section 30-2 arranged in the same layer. The first light-shielding section 30-1 and the second light-shielding section 30-2 both include a first light-shielding edge 301 and a second light-shielding edge 302, and there is an opening 60 between the two second light-shielding edges 302; along the first direction Z, the gate electrode 102 and the active layer 101 both at least partially overlap with the opening 60.

[0050] Specifically, the light shielding structure 30 is not integrally formed, but rather comprises two independent light shielding sections arranged in the same layer: a first light shielding section 30-1 and a second light shielding section 30-2, arranged along the second direction X. Along the second direction X, both first light shielding edges 301 of the first light shielding section 30-1 and the second light shielding section 30-2 are located away from the center of the active layer, and both second light shielding edges 302 of the first light shielding section 30-1 and the second light shielding section 30-2 are located closer to the center of the active layer. An opening 60 exists between the two second light shielding edges 302. Along the first direction Z, the gate electrode 102 and the active layer 101 at least partially overlap with the opening 60. In other words, along the second direction X, the two independent light shielding sections are located on either side of the active layer 101, respectively. This facilitates shielding light incident on the active layer 101 from both sides, thereby further reducing the amount of light entering the channel region and improving the light bias reliability of the transistor.

[0051] Optional, continue to refer to Figure 6 and Figure 7 The shading structure 30 includes a first shading substructure 31 and a second shading substructure 32 arranged in different layers. The first shading substructure 31 and the second shading substructure 32 both include a first shading section 30-1 and a second shading section 30-2. The area of the opening in the first shading substructure 31 is different from the area of the opening in the second shading substructure 32.

[0052] Specifically, the light-shielding structure 30 includes a first light-shielding substructure 31 and a second light-shielding substructure 32 arranged in different layers. That is, the first light-shielding substructure 31 and the second light-shielding substructure 32 can be respectively located on the upper and lower sides of the active layer 101, so as to form a sandwich structure of "first light-shielding substructure 31-active layer 101-second light-shielding substructure 32". This is conducive to blocking the lateral light incident on the left and right sides of the active layer 101 above the two branches of the first light-shielding substructure 31, and blocking the lateral light incident on the left and right sides of the active layer 101 below the two branches of the second light-shielding substructure 32, thereby further reducing the light incident on the active layer 101, that is, reducing the light entering the channel region. In addition, it is conducive to realizing a diversified setting of the light-shielding structure 30.

[0053] Furthermore, after forming the two light-shielding sections of the second light-shielding substructure 32, an active layer 101 is formed on the side of the second light-shielding substructure 32 away from the substrate 20. The active layer 101 fills the opening in the second light-shielding substructure 32. Then, two light-shielding sections of the first light-shielding substructure 31 are formed on the side of the active layer 101 away from the substrate 20. The first light-shielding substructure 31 partially covers the active layer 101. By setting the area of the opening in the first light-shielding substructure 31 to be different from the area of the opening in the second light-shielding substructure 32, that is, by setting the opening size in the first light-shielding substructure 31 to be different from the opening size in the second light-shielding substructure 32, this can reduce the difficulty of aligning the second light-shielding edge 302 of the first light-shielding substructure 31 with the second light-shielding edge 302 of the second light-shielding substructure 32. Furthermore, it can achieve flexible adjustment of the channel region size and length of the channel region by the light-shielding structure, thereby facilitating the flexible configuration of the display panel to meet different usage requirements.

[0054] It should be noted that Figure 6 and Figure 7 Only the technical solution in which the opening area in the first shading substructure 31 is smaller than the opening area in the second shading substructure 32 is shown. It can be understood that the opening area in the first shading substructure 31 can also be larger than the opening area in the second shading substructure 32, so that diversified settings of the shading structure and the channel area in the display panel can be achieved.

[0055] Optional, continue to refer to Figure 8 and Figure 9The gate electrode 102 includes a first gate electrode 102-1, which is located on a side of the active layer away from the substrate 20; along the first direction Z, the first gate electrode 102-1 at least partially overlaps with the active layer 101; the shading structure 30 includes a first shading substructure 31, which is located between the film layer where the first gate electrode 102-1 is located and the film layer where the active layer 101 is located; the first shading substructure 31 includes a first A shading edge 311, and the orthographic projection of the first A shading edge 311 on the plane where the substrate is located is a first A shading projection edge 3111. Along the second direction X, the first A shading projection edge 3111 and the first gate electrode projection edge 10211 are located on the same side of the active layer projection center O, and the first A shading projection edge 3111 is located on the side of the first gate electrode projection edge 10211 away from the active layer projection center O.

[0056] Specifically, the first gate electrode 102-1 is located on a side of the active layer away from the substrate 20, that is, the first gate electrode 102-1 is a top gate. In this way, the top gate can block light incident from above and perpendicular to the active layer 101. The first light-shielding substructure 31 is located between the film layer where the first gate electrode 102-1 is located and the film layer where the active layer 101 is located. In other words, the first light-shielding substructure 31 is located between the film layer where the top gate is located and the film layer where the active layer 101 is located. In this way, the first light-shielding substructure 31 located above the active layer 101 can block lateral light incident on the active layer 101, thereby reducing lateral light incident on the active layer 101 from above. This reduces the amount of light entering the channel region, improves the light bias reliability of the transistor, and enhances the performance of the display panel.

[0057] Optional, continue to refer to Figure 3 and Figure 4 The gate electrode 102 includes a second gate electrode 102-2, which is located on a side of the active layer 10 close to the substrate 20; along the first direction Z, the second gate electrode 102-2 at least partially overlaps with the active layer 101; the shading structure 30 includes a second shading substructure 32, which is located between the film layer where the second gate electrode 102-2 is located and the film layer where the active layer 101 is located; the second shading substructure 32 includes a first B shading edge 321, and the orthographic projection of the first B shading edge 321 on the plane where the substrate is located is a first B shading projection edge 3211. Along the second direction X, the first B shading projection edge 3211 and the first gate electrode projection edge 10211 are located on the same side of the active layer projection center O, and the first B shading projection edge 3211 is located on the side of the first gate electrode projection edge 10211 away from the active layer projection center O.

[0058] Specifically, the second gate electrode 102-2 is located on the side of the active layer 101 close to the substrate 20, that is, the second gate electrode 102-2 is a bottom gate, so that the bottom gate can block light below the active layer 101 and incident vertically toward the active layer 10. The second light-shielding substructure 32 is located between the film layer where the second gate electrode 102-2 is located and the film layer where the active layer 101 is located. In other words, the second light-shielding substructure 32 is located between the film layer where the bottom gate is located and the film layer where the active layer 101 is located. In this way, the second light-shielding substructure 32 located below the active layer 101 can block lateral light incident toward the active layer 101, thereby reducing lateral light incident on the active layer 101 from below. In addition, the position of the light-shielding structure 30 can be flexibly set.

[0059] Optional, Figure 10 A schematic top view of a fourth transistor on a substrate provided by an embodiment of the present invention, Figure 11 for Figure 10 The cross-sectional structure diagram of the corresponding transistor along the cross-sectional line EE' is as follows: Figure 10 and Figure 11 As shown, the display panel further includes an etching protection structure 70 ; the etching protection structure 70 is located between the film layer where the active layer 101 is located and the film layer where the first light-shielding substructure 31 is located, and the opening 60 in the first light-shielding substructure 31 exposes at least a portion of the etching protection structure 70 .

[0060] Specifically, the etching protection structure 70 is located between the film layer where the active layer 101 is located and the film layer where the first light-shielding substructure 31 is located. The provision of the etching protection structure 70 can protect the active layer 101. Specifically, after the active layer 101 is prepared, the etching protection structure 70 is prepared on the upper surface of the active layer 101, so that the etching protection structure 70 covers at least a portion of the upper surface of the active layer 101. A first light-shielding sublayer is then prepared on the upper surface of the etching protection structure 70, and the first light-shielding sublayer is patterned to form a first light-shielding subsection 30-1 and a second light-shielding subsection 30-2. An opening 60 is provided between the first light-shielding subsection 30-1 and the second light-shielding subsection 30-2. The provision of the etching protection structure 70 can prevent damage to the upper surface of the active layer 101 during the etching process of the first light-shielding substructure 31, thereby protecting the stability of the active layer 101 and improving the film stability of the display panel.

[0061] Optional, continue to refer to Figure 9 , along the second direction X, the length of the first gate electrode 102 - 1 is greater than the length of the active layer 101 .

[0062] Specifically, along the second direction X, the length of the first gate electrode 102-1 is greater than the length of the active layer 101, that is, the first gate electrode 102-1 can cover a larger area. In this way, the first gate electrode 102-1 can better control the electric field distribution and reduce the risk of breakdown voltage, thereby increasing the voltage resistance of the transistor, improving the reliability of the display panel, and extending the service life of the display panel.

[0063] Optional, continue to refer to Figure 9 The light-shielding structure 30 includes at least one light-shielding substructure, and the at least one light-shielding substructure includes a conductive light-shielding substructure 300 . The at least one conductive light-shielding substructure 300 is electrically connected to the source-drain electrode 103 and the active layer 101 , respectively.

[0064] Specifically, the light-shielding structure 30 includes a first light-shielding substructure 31 as an example. The first light-shielding substructure 31 includes a conductive light-shielding substructure 300, that is, the light-shielding structure 30 has both light-shielding performance and conductive performance. In this way, the conductive light-shielding substructure 300 is electrically connected to the source and drain electrodes 103 and the active layer 101 respectively, and then under the action of the gate electrode signal, the channel region can be turned on.

[0065] As a comparative example, in the prior art, the length of the channel region is controlled by top-gate self-aligned injection, while the region outside the channel region is made conductive by oxide self-aligned injection, thereby achieving conduction in the channel region. However, in the embodiments of the present invention, by providing a conductive light-shielding substructure 300 electrically connected to the source-drain electrodes 103 and the active layer 101, the ion implantation process can be eliminated. This not only simplifies the display panel manufacturing process, but also allows the conductive light-shielding substructure 300 to directly serve as the source and drain regions, rather than forming a highly doped region in the semiconductor layer through ion implantation. This ensures conductivity and, in turn, the stability of the electrical connection between the conductive light-shielding substructure 300 and the source-drain electrodes 103 and the active layer 101.

[0066] Optional, Figure 12 for Figure 8 The second cross-sectional structure diagram of the corresponding transistor along the cross-sectional line D-D' is shown in FIG. Figure 9 and Figure 12 The conductive light-shielding substructure 300 is electrically connected to the source-drain electrode 103 through the connecting via 80 ; the conductive light-shielding substructure 300 is electrically connected to the active layer 101 through the connecting via 90 , or the conductive light-shielding substructure 300 directly contacts the active layer 101 .

[0067] As a feasible implementation method, continue to refer to Figure 9The conductive light-shielding substructure 300 is electrically connected to the source-drain electrode 103 through the connecting via 80, and the conductive light-shielding substructure 300 directly contacts the active layer 101. In this way, the connection between the conductive light-shielding substructure 300 and the active layer 101 is simple. As another feasible embodiment, continue to refer to Figure 12 The conductive light-shielding substructure 300 is electrically connected to the source-drain electrode 103 through the connecting via 80, and the conductive light-shielding substructure 300 is electrically connected to the active layer 101 through the connecting via 90. This can ensure the stability of the electrical connection between the conductive light-shielding substructure 300 and the active layer 101 and the source-drain electrode 103, respectively, on the one hand, and ensure the diversity of the electrical connection on the other hand.

[0068] Optional, continue to refer to Figure 7 The light-shielding structure 30 includes a first light-shielding substructure 31 and a second light-shielding substructure 32 arranged in different layers. The first light-shielding substructure 31 and the second light-shielding substructure 32 both include a conductive light-shielding substructure 300 ; the first light-shielding substructure 31 is electrically connected to the second light-shielding substructure 32 .

[0069] Specifically, the first shading substructure 31 and the second shading substructure 32 both include a conductive shading substructure 300, which can ensure the shading effect on the active layer 101 on the one hand, and on the other hand, through the electrical connection between the first shading substructure 31 and the second shading substructure 32, the shading structure 30 can be electrically connected to the source and drain electrodes 103 and the active layer 101 respectively. In addition, the electrical connection between the first shading substructure 31 and the second shading substructure 32 can be understood as the first shading substructure 31 and the second shading substructure 32 being arranged in parallel. The parallel arrangement of the first shading substructure 31 and the second shading substructure 32 can reduce the connection resistance and ensure the accuracy of signal transmission between the source and drain electrodes 103.

[0070] Optional, Figure 13 for Figure 6 The second cross-sectional structure diagram of the corresponding transistor along the cross-sectional line CC' is shown in FIG. Figure 7 and Figure 13 , the first light-shielding substructure 31 directly contacts the second light-shielding substructure 32 ; or, the first light-shielding substructure 31 is electrically connected to the second light-shielding substructure 32 through a connecting via.

[0071] Specifically, as a feasible implementation method, continue to refer to Figure 7 The first light-shielding substructure 31 directly contacts the second light-shielding substructure 32. On the one hand, the connection method between the first light-shielding substructure 31 and the second light-shielding substructure 32 is simple, and the preparation process is simple. On the other hand, it can ensure that there is a large contact area between the first light-shielding substructure 31 and the second light-shielding substructure 32, thereby ensuring the electrical connection effect between the two and reducing the connection resistance.

[0072] As another possible implementation, continue to refer to Figure 13 The first light-shielding substructure 31 is electrically connected to the second light-shielding substructure 32 through the connecting vias, so that a diversified setting of the electrical connection between the first light-shielding substructure 31 and the second light-shielding substructure 32 can be achieved.

[0073] Optional, Figure 14 for Figure 6 The third cross-sectional structure diagram of the corresponding transistor along the cross-sectional line CC' is as follows: Figure 14 As shown, the shading structure 30 includes a first shading substructure 31 and a second shading substructure 32 arranged in different layers, and the first shading substructure 31 and the second shading substructure 32 both include a conductive shading substructure 300; the first shading substructure 31 is electrically connected to the source and drain electrodes 103 and the active layer 101 respectively; the second shading substructure 32 is independently arranged with the first shading substructure 31.

[0074] Specifically, the first light-shielding substructure 31 is electrically connected to the source-drain electrode 103 and the active layer 101, respectively. This ensures conduction in the channel region while also providing light shielding for the active layer 101. Furthermore, the second light-shielding substructure 32 is independently configured from the first light-shielding substructure 31, enabling a variety of light-shielding configurations.

[0075] Optional, continue to refer to Figure 4 , the second light-shielding substructure 32 is electrically connected to the fixed potential signal line.

[0076] Specifically, the fixed potential signal line can be a positive power signal line and a negative power signal line, wherein the positive power signal line can provide a fixed positive voltage to the pixel driving circuit in the display panel, and the negative power signal line can provide a negative voltage to the cathode of the light emitting element.

[0077] Specifically, the second shading substructure 32 is electrically connected to the fixed potential signal line. This can, on the one hand, prevent the second shading substructure 32 from coupling with other unit signals due to potential floating and interfering with the normal conduction of the transistor. On the other hand, the second shading substructure 32 is electrically connected to the fixed potential signal line, which can be understood as the second shading substructure 32 being connected in parallel with the fixed potential signal line, reducing the impedance of the fixed potential signal line during transmission, and ensuring the accuracy of the fixed potential signal in the fixed potential signal.

[0078] Optional, Figure 15 A schematic top view of a fifth transistor on a substrate provided by an embodiment of the present invention, Figure 16 for Figure 15 The corresponding cross-sectional structure diagram of the transistor along the cross-sectional line F-F' is as follows: Figure 15 and Figure 16As shown, the shading structure 30 includes a first shading substructure 31 and a third shading substructure 33 arranged in different layers. The first shading substructure 31 includes a conductive shading substructure 300 and is electrically connected to the source and drain electrodes 103 and the active layer 101 respectively; the third shading substructure 33 includes an insulating shading structure 330.

[0079] Specifically, the first light-shielding substructure 31 includes a conductive light-shielding substructure 300 electrically connected to the source / drain electrodes 103 and the active layer 101, respectively. This ensures conduction in the channel region and provides light shielding for the active layer 101. The third light-shielding substructure 33 includes an insulating light-shielding structure 330, further ensuring the light-shielding effect of the insulating light-shielding structure 330 on the active layer 101. This reduces light entering the channel region, blocks visible light from affecting the active layer, improves the reliability of the transistor's light bias voltage, and enhances the performance of the display panel. Furthermore, this allows for diverse configurations of the display panel.

[0080] Optional, continue to refer to Figure 4 The active layer 101 includes an oxide active layer. Since the active layer 101 has a high electron mobility, it is beneficial to improve the switching speed of the transistor, thereby achieving a high refresh rate of the display panel.

[0081] Optional, continue to refer to Figure 4 The active layer 101 includes at least one of indium gallium zinc oxide, indium gallium zinc tin oxide, indium gallium oxide and indium zinc tin oxide. These oxides are all high-mobility oxides. These oxides have high electron mobility and can increase the switching speed of the transistor, thereby achieving a high refresh rate of the display panel.

[0082] Optional, specific, continue to refer to Figure 5 The display panel further includes a pixel circuit 200, which includes a driving transistor; the active layer 101 of the driving transistor includes an oxide active layer.

[0083] Specifically, the active layer 101 of the driving transistor includes an oxide active layer. Since the oxide active layer has a high electron mobility, the response speed of the driving transistor is fast, thereby achieving a high refresh rate of the display panel.

[0084] Based on the same inventive concept, an embodiment of the present invention further provides a display device, Figure 17 A schematic structural diagram of a display device provided by an embodiment of the present invention is shown in FIG. Figure 17As shown, the display device 1000 includes the display panel 100 in the above embodiment. Therefore, the display device 1000 provided by the embodiment of the present invention also has the beneficial effects described in the above embodiment, which will not be repeated here. For example, the display device can be an electronic device such as a mobile phone, a computer, a smart wearable device (for example, a smart watch), and an in-vehicle display device, which is not limited in the embodiment of the present invention.

[0085] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will appreciate that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, combinations, and substitutions are possible for those skilled in the art without departing from the scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the scope of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that: The device comprises a substrate and a transistor located on one side of the substrate, wherein the transistor comprises an active layer, a gate electrode, and a source-drain electrode. The gate electrode is located on at least one side of the active layer, and along a first direction, the gate electrode and the active layer at least partially overlap; the first direction is the thickness direction of the display panel; The source-drain electrode is electrically connected to the active layer; The display panel also includes a shading structure, and along the first direction, the shading structure is located between the film layer where the active layer is located and the film layer where the gate electrode is located; the shading structure includes a first shading edge, and the gate electrode includes a first gate electrode edge, the first shading edge has an orthographic projection on the plane where the substrate is located as the first shading projection edge, the first gate electrode edge has an orthographic projection on the plane where the substrate is located as the first gate electrode projection edge, and the center of the active layer is projected on the plane where the substrate is located as the active layer projection center; along the second direction, the first shading projection edge and the first gate electrode projection edge are located on the same side of the active layer projection center, and the first shading projection edge is located on the side of the first gate electrode projection edge away from the active layer projection center; the second direction is the length direction of the channel region in the active layer.

2. The display panel according to claim 1, wherein: The light shielding structure further includes a second light shielding edge, wherein the orthographic projection of the second light shielding edge on the plane where the substrate is located is a second light shielding projection edge; Along the second direction, the second light-shielding projection edge is located on a side of the first gate electrode projection edge close to the projection center of the active layer.

3. The display panel according to claim 2, wherein: Along the second direction, the distance between the second light-shielding projection edge and the first gate electrode projection edge is L1; Along the first direction, the distance between the film layer where the light shielding structure is located and the film layer where the gate electrode is located is L2; Among them, L1 and L2 are positively correlated.

4. The display panel according to claim 1, wherein: Along the first direction, the light shielding structure overlaps with the active layer.

5. The display panel according to claim 4, wherein: A length of an overlapping region between the light-shielding structure and the active layer in the second direction is greater than zero.

6. The display panel according to claim 2, wherein: The light-shielding structure includes a first light-shielding sub-section and a second light-shielding sub-section provided in the same layer, the first light-shielding sub-section and the second light-shielding sub-section both include a first light-shielding edge and a second light-shielding edge, and an opening exists between the two second light-shielding edges; Along the first direction, the gate electrode and the active layer at least partially overlap with the opening.

7. The display panel according to claim 6, wherein: The light-shielding structure includes a first light-shielding substructure and a second light-shielding substructure arranged in different layers, and the first light-shielding substructure and the second light-shielding substructure both include the first light-shielding subsection and the second light-shielding subsection; The area of the opening in the first light-shielding substructure is different from the area of the opening in the second light-shielding substructure.

8. The display panel according to claim 1, wherein: The gate electrode includes a first gate electrode, the first gate electrode is located on a side of the active layer away from the substrate; along the first direction, the first gate electrode at least partially overlaps with the active layer; The light-shielding structure includes a first light-shielding substructure, and the first light-shielding substructure is located between the film layer where the first gate electrode is located and the film layer where the active layer is located; The first light-shielding substructure includes a first A light-shielding edge, the orthographic projection of the first A light-shielding edge on the plane where the substrate is located is the first A light-shielding projection edge. Along the second direction, the first A light-shielding projection edge and the first gate electrode projection edge are located on the same side of the active layer projection center, and the first A light-shielding projection edge is located on the side of the first gate electrode projection edge away from the active layer projection center.

9. The display panel according to claim 1, wherein: The gate electrode includes a second gate electrode, and the second gate electrode is located on a side of the active layer close to the substrate; along the first direction, the second gate electrode at least partially overlaps with the active layer; The light-shielding structure includes a second light-shielding substructure, and the second light-shielding substructure is located between the film layer where the second gate electrode is located and the film layer where the active layer is located; The second light-shielding substructure includes a first B light-shielding edge, the orthographic projection of the first B light-shielding edge on the plane where the substrate is located is the first B light-shielding projection edge. Along the second direction, the first B light-shielding projection edge and the first gate electrode projection edge are located on the same side of the active layer projection center, and the first B light-shielding projection edge is located on the side of the first gate electrode projection edge away from the active layer projection center.

10. The display panel according to claim 8, wherein The display panel further includes an etching protection structure; The etching protection structure is located between the film layer where the active layer is located and the film layer where the first light-shielding substructure is located, and the opening in the first light-shielding substructure exposes at least a portion of the etching protection structure.

11. The display panel according to claim 8, wherein Along the second direction, a length of the first gate electrode is greater than a length of the active layer.

12. The display panel according to claim 1, wherein The light-shielding structure includes at least one layer of light-shielding substructure, at least one layer of the light-shielding substructure includes a conductive light-shielding substructure, and at least one layer of the conductive light-shielding substructure is electrically connected to the source-drain electrode and the active layer respectively.

13. The display panel according to claim 12, wherein: The conductive light-shielding substructure is electrically connected to the source-drain electrode through a connecting via; The conductive light-shielding substructure is electrically connected to the active layer through a connecting via, or the conductive light-shielding substructure directly contacts the active layer.

14. The display panel according to claim 12, wherein: The light-shielding structure includes a first light-shielding substructure and a second light-shielding substructure arranged in different layers, and both the first light-shielding substructure and the second light-shielding substructure include the conductive light-shielding substructure; The first light-shielding substructure is electrically connected to the second light-shielding substructure.

15. The display panel according to claim 14, wherein: The first light-shielding substructure directly contacts the second light-shielding substructure; Alternatively, the first light-shielding substructure is electrically connected to the second light-shielding substructure through a connecting via.

16. The display panel according to claim 12, wherein: The light-shielding structure includes a first light-shielding substructure and a second light-shielding substructure arranged in different layers, and both the first light-shielding substructure and the second light-shielding substructure include the conductive light-shielding substructure; The first light-shielding substructure is electrically connected to the source-drain electrode and the active layer respectively; The second light-shielding substructure and the first light-shielding substructure are independently provided.

17. The display panel according to claim 16, wherein: The second light-shielding substructure is electrically connected to the fixed-potential signal line.

18. The display panel according to claim 12, wherein: The light-shielding structure includes a first light-shielding substructure and a third light-shielding substructure arranged in different layers, the first light-shielding substructure includes the conductive light-shielding substructure and is electrically connected to the source-drain electrode and the active layer respectively; The third light-shielding substructure includes an insulating light-shielding structure.

19. The display panel according to claim 1, wherein The active layer includes an oxide active layer.

20. The display panel according to claim 19, wherein The active layer includes at least one of indium gallium zinc oxide, indium gallium zinc tin oxide, indium gallium oxide, and indium zinc tin oxide.

21. The display panel according to claim 19, wherein The display panel further includes a pixel circuit, wherein the pixel circuit includes a driving transistor; The active layer of the driving transistor includes the oxide active layer.

22. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 21.

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