Member for semiconductor device manufacturing and method for manufacturing same

Abstract

A method for manufacturing a member for manufacturing a semiconductor device includes: (a) a step of forming a recess in a surface of an insulating material layer; (b) a step for forming a first electroless Ni plating layer on the surface of the insulating material layer and the inner surface of the recess by electroless nickel plating; (c) a step for forming a Cu plating layer on the first electroless Ni plating layer; (d) a step in which the Cu plating layer and the first electroless Ni plating layer formed on the surface of the insulating material layer are removed to form a wiring layer including the Cu plating layer in the recess; and (e) a step for forming a second electroless Ni plating layer by electroless nickel plating on the exposed surface of the wiring layer, the first electroless Ni plating layer containing nickel and boron, and the boron content of the first electroless Ni plating layer being 0.3-1.0 mass% based on the mass of the first electroless Ni plating layer.

Description

Technical Field

[0001] The present invention relates to a component for manufacturing a semiconductor device and a method for manufacturing the same. Background Art

[0002] To achieve higher density and higher performance in semiconductor packaging, a method of mounting chips with different performances mixed in one package has been proposed, and cost-effective high-density interconnection technology between chips has become important (see, for example, Patent Document 1).

[0003] Package-on-package, which connects different packages by stacking them on top of each other via flip-chip mounting, is widely adopted in smartphones and tablet terminals (for example, see Non-Patent Documents 1 and 2). As methods for achieving even higher density mounting, packaging technologies using organic substrates with high-density wiring (organic interposers), fan-out packaging technologies with through-molded vias (TMVs) (FO-WLP), packaging technologies using silicon or glass interposers, packaging technologies using through-silicon vias (TSVs), and packaging technologies that use chips embedded in substrates for inter-chip transmission have been proposed.

[0004] In particular, in organic interposers and FO-WLPs, when semiconductor chips are mounted in parallel, a fine wiring layer is required for high-density conduction (see, for example, Patent Document 2).

[0005] Previous technical literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application No. 2012-529770

[0008] Patent Document 2: U.S. Patent Application Publication No. 2001 / 0221071

[0009] Non-patent literature

[0010] Non-patent document 1: Application of Through Mold Via (TMV) as PoP Base Package, Electronic Components and Technology Conference (ECTC), 2008

[0011] Non-patent document 2: Advanced Low Profile PoP Solution with Embedded WaferLevelPoP (eWLB-PoP) Technology, ECTC, 2012 Summary of the Invention

[0012] Technical issues to be solved by the invention

[0013] In build-up substrates, wafer-level packaging (WLP), fan-out PoP bottom packaging, etc., an organic interposer having a stack of multiple organic insulating layers (organic insulating stack) is sometimes used. For example, when a plurality of fine wirings with a line width and spacing of 5 μm or less are arranged in the organic insulating stack, the wiring is formed using a trench method. The trench method refers to a method in which grooves (trench) formed on the surface of the organic insulating layer are formed into a metal layer that becomes the wiring by plating or the like. Therefore, the shape of the wiring formed on the organic insulating layer is formed along the shape of the groove.

[0014] When forming fine wiring within an organic insulating laminate using the trench method, a highly conductive metal material, such as copper, is sometimes used to minimize costs and minimize increases in wiring resistance. When wiring is formed using such a metal material, it can diffuse within the organic insulating laminate. This can cause short circuits between wirings through the diffused metal material, raising concerns about the insulation reliability of the organic interposer.

[0015] The present invention provides a component for manufacturing a semiconductor device having a fine wiring layer with sufficiently high insulation reliability and a method for manufacturing the same.

[0016] Means for solving technical problems

[0017] One aspect of the present invention relates to a method for manufacturing a component for manufacturing a semiconductor device. The method comprises: (a) forming a recess on the surface of an insulating material layer; (b) forming a first electroless Ni plating layer on the surface of the insulating material layer and the inner surface of the recess by electroless nickel plating; (c) forming a Cu plating layer on the first electroless Ni plating layer; (d) removing the Cu plating layer and the first electroless Ni plating layer formed on the surface of the insulating material layer to form a wiring layer including the Cu plating layer in the recess; and (e) forming a second electroless Ni plating layer on the exposed surface of the wiring layer by electroless nickel plating, wherein the first electroless Ni plating layer contains nickel and boron, and the boron content of the first electroless Ni plating layer is 0.3 to 1.0% by mass based on the mass of the first electroless Ni plating layer.

[0018] One aspect of the present invention relates to a component for manufacturing semiconductor devices. The component comprises: an insulating material layer; a recessed portion formed on a surface of the insulating material layer; a first electroless Ni plating layer formed to cover the inner surface of the recessed portion; a Cu plating layer formed on the surface of the first electroless Ni plating layer and filling the recessed portion; and a second electroless Ni plating layer formed to cover the exposed surface of the Cu plating layer. The first electroless Ni plating layer contains nickel and boron, and the boron content of the first electroless Ni plating layer is 0.3 to 1.0% by mass based on the mass of the first electroless Ni plating layer.

[0019] Effects of the Invention

[0020] According to the present invention, a component for manufacturing a semiconductor device having a fine wiring layer with sufficiently high insulation reliability and a method for manufacturing the same are provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 (a) is a cross-sectional view schematically showing a state where an insulating material layer is formed on a support body, Figure 1 (b) is a cross-sectional view schematically showing a state where a recessed portion is formed in the insulating material layer. Figure 1 (c) is a cross-sectional view schematically showing a state in which a palladium catalyst adsorption layer is formed on the surface of the insulating material layer by pretreatment. Figure 1 (d) is a cross-sectional view schematically showing a state where a first electroless Ni plating layer is formed on an insulating material by electroless nickel plating.

[0022] Figure 2 (a) is a cross-sectional view schematically showing a state where a Cu plating layer is formed on a first electroless Ni plating layer, Figure 2 (b) is a cross-sectional view schematically showing a state where the wiring layer is exposed by surface polishing. Figure 2 (c) is a cross-sectional view schematically showing a state in which a second electroless Ni plating layer is formed so as to cover the exposed wiring layer.

[0023] Figure 3 This is a SEM image showing the groove pattern according to Example 1.

[0024] Figure 4 (a) is a SEM image showing a Ni—B seed layer (first electroless Ni plating layer) formed on the surface of the insulating material layer and the inner surface of the trench. Figure 4 (b) Yes Figure 4 (a) A partial enlarged view.

[0025] Figure 5 (a) is a plan view schematically showing the structure of the interdigitated electrodes according to the embodiment and the comparative example. Figure 5(b) is a cross-sectional view schematically showing a sample used for the electrical insulation evaluation. DETAILED DESCRIPTION

[0026] The following describes embodiments of the present invention in detail with reference to the accompanying drawings. In the following description, identical or equivalent components are denoted by the same reference numerals, and duplicate descriptions are omitted. Furthermore, positional relationships, such as up, down, left, and right, are based on those shown in the drawings unless otherwise specified. Furthermore, the dimensional ratios in the drawings are not limited to those shown.

[0027] When terms such as "left," "right," "front," "back," "upper," "lower," "above," and "below" are used in this specification and claims, these are for illustrative purposes only and do not necessarily imply constant relative positions. Furthermore, the term "layer" encompasses not only structures that form a shape across the entire surface but also structures that form a shape across a portion of the surface when viewed in a plan view.

[0028] This embodiment is particularly preferred in packages requiring refinement and multi-pinning, particularly packages requiring an interposer for co-loading heterogeneous chips. More specifically, the manufacturing method of this embodiment is preferred in packages having a trench structure with a line width of 20 μm or less (e.g., 0.5 to 10 μm in finer cases) and a pitch of 20 μm or less (e.g., 0.5 to 10 μm in finer cases).

[0029] The method for manufacturing a member for manufacturing a semiconductor device according to this embodiment includes the following steps.

[0030] Step (I) of forming an insulating material layer 1 on a support S

[0031] Step (II) of forming recessed portion 1a on surface of insulating material layer 1

[0032] Step (III) of modifying the surface of the insulating material layer 1 including the recessed portion 1a

[0033] Step (IV) of forming the palladium adsorption layer 3 on the surface including the recessed portion 1 a of the modified insulating material layer 1

[0034] Step (V) of forming the first electroless Ni plating layer 5 on the surface including the recessed portion 1a of the insulating material layer 1 on which the palladium adsorption layer 3 is formed by electroless nickel plating

[0035] Step (VI) of forming the Cu plating layer 7 on the first electroless Ni plating layer 5 by electrolytic copper plating

[0036] Step (VII) of forming the wiring layer 8 including the Cu plating layer 7 formed in the recessed portion 1a by removing the Cu plating layer 7, the first electroless Ni plating layer 5, and the palladium adsorption layer 3 in the region other than the recessed portion 1a formed in the surface of the insulating material layer 1 (on the upper surface of the insulating material layer 1).

[0037] Step (VIII) of forming the second electroless Ni plating layer 9 on the exposed surface 8a of the wiring layer 8 by electroless nickel plating

[0038] According to the above-described manufacturing method, the diffusion of copper contained in the wiring layer 8 can be prevented by the first electroless Ni plating layer 5 and the second electroless Ni plating layer 9, thereby making it possible to manufacture a component for manufacturing a semiconductor device having a fine wiring layer with sufficiently high insulation reliability. Each step is described below.

[0039] <Step (I) of forming an insulating material layer on a support>

[0040] First, a step (I) of forming an insulating material layer 1 on a support S of a semiconductor device manufacturing component is performed ( Figure 1 (a) The support S is not particularly limited and may be a silicon plate, a glass plate, an SUS plate, a substrate containing glass cloth, a sealing resin containing a semiconductor element, or the like, and is preferably a substrate formed of a highly rigid material.

[0041] The thickness of the support S is preferably in the range of 0.2 mm to 2.0 mm. When it is thinner than 0.2 mm, handling becomes difficult, and when it is thicker than 2.0 mm, material costs increase. The support S can be wafer-shaped or plate-shaped. The size is not particularly limited, but wafers with a diameter of 200 mm, 300 mm, or 450 mm, or rectangular panels with a side of 300 to 700 mm are preferably used.

[0042] From the perspective of being able to easily form fine recesses 1a through a photolithographic process in the later-described step (II), a photosensitive resin material is preferably used as the material constituting the insulating material layer 1. As the photosensitive insulating material, liquid or film-like photosensitive insulating materials can be cited. From the perspective of film thickness flatness and cost, film-like photosensitive insulating materials are preferred. Furthermore, from the perspective of being able to form fine wiring, the photosensitive insulating material preferably contains a filler (filling material) having an average particle size of 500 nm or less (more preferably 50 to 200 nm). The filler content of the photosensitive insulating material is preferably 0 to 70 parts by mass, more preferably 0 to 50 parts by mass, relative to 100 parts by mass of the photosensitive insulating material excluding the filler.

[0043] When using a film-like photosensitive insulating material, the lamination process is preferably performed at a low temperature, preferably a photosensitive insulating film that can be laminated at 40°C to 120°C. A photosensitive insulating film that can be laminated at a temperature below 40°C tends to have high viscosity at room temperature (approximately 25°C), resulting in poor workability. A photosensitive insulating film laminated at a temperature above 120°C tends to warp significantly after lamination.

[0044] The thermal expansion coefficient of the insulating material layer 1 after curing is preferably 80×10 -6 / K or less, and more preferably 70×10 -6 / K or less. In addition, it is preferably 20×10 -6 / K or above.

[0045] The thickness of the insulating material layer 1 is preferably 10 μm or less, more preferably 5 μm or less, and even more preferably 3 μm or less. When the thickness of the insulating material layer 1 is within this range, for example, in step (II) described later, recessed portions 1a having a fine trench structure are easily formed. From the perspective of insulation reliability, the thickness of the insulating material layer 1 is preferably 1 μm or greater.

[0046] <Step (II) of forming recessed portions in insulating material layer>

[0047] Next, step (II) of forming the recessed portion 1a on the surface of the insulating material layer 1 is performed ( Figure 1 (b)). In this embodiment, the recess 1a refers to a portion that is recessed in the thickness direction of the insulating material layer 1 relative to the surface of the insulating material layer 1, and includes the inner wall (side surface and bottom surface, etc.) of the recessed portion. Figure 1 As shown in (b), the recess 1a is preferably formed up to the surface of the support body S, that is, it is preferably composed of a side surface formed by the insulating material layer 1 and a bottom surface formed by the surface of the support body S. The recess 1a is preferably a groove structure, in which case the opening width (line width) is, for example, 0.5 to 20 μm, and in a more minute case, it can also be 0.5 to 5 μm. By setting the opening width of the recess 1a to the above range, there is a tendency to easily provide a semiconductor device that achieves high density. That is, it is easy to manufacture a semiconductor device with a fine wiring layer with good yield and low cost. In addition, the opening shape of the recess 1a can be, for example, circular or elliptical, and the opening size in this case can also be equivalent to the area of a circle with a diameter of 5 to 50 μm (a diameter of 5 to 10 μm in a more minute case).

[0048] The method for forming the recess 1a can include laser ablation, photolithography, imprinting, etc., but from the perspective of refinement and cost, it is preferred to form an insulating material layer 1 formed of a photosensitive resin material in step (I), and form the recess 1a by a photolithography process (exposure and development). As the exposure method of the photosensitive resin material, a conventional projection exposure method, a contact exposure method, a direct drawing exposure method, etc. can be used, and as the development method, an alkaline aqueous solution of sodium carbonate or TMAH (tetramethylammonium hydroxide) is preferably used. After the recess 1a is formed in the insulating material layer 1, the insulating material can be further heated and cured. It is carried out under the conditions of a heating temperature of 100°C to 200°C and a heating time of 30 minutes to 3 hours.

[0049] <Surface Modification Step (III)>

[0050] Next, step (III) (not shown) of modifying the surface of the insulating material layer 1 including the recessed portion 1a is performed. In this embodiment, modification refers to making the surface of the insulating material layer 1 more susceptible to adsorption of the palladium catalyst prior to step (IV). Because this treatment is performed prior to step (IV), this modification treatment may be referred to as "pretreatment" below.

[0051] As a modification method, any of the following pretreatments in the wet method and pretreatments in the dry method can be used. As the pretreatment liquid (modification liquid) used in the pretreatment in the wet method, for example, a pretreatment liquid containing at least one selected from the group consisting of silane coupling agents containing polyethers, glycol ethers, amines, amides, urea groups, triazines, melamines, imidazoles, triazoles, benzotriazoles, etc. in the molecule can be cited. The type of solvent used in these pretreatment liquids is not particularly limited and can be selected from commonly used organic solvents and water. One type can be used alone or two or more types can be used in combination. In addition, for the purpose of improving the wettability of the surface of the insulating material layer 1, a surfactant can also be included. In addition, in order to improve the modification effect, pretreatment can be carried out with an aqueous solution containing sodium hypophosphite, potassium hypophosphite, calcium hypophosphite, etc. In addition, as a modification method based on pretreatment in a wet method other than these, roughening treatment based on acid or alkali can be cited. On the other hand, examples of pretreatment in the dry method include surface modification by plasma treatment, corona treatment, ultraviolet treatment, and the like.

[0052] Even in the above-mentioned modification methods, it is preferred to perform a pretreatment in a wet method, that is, modification of the surface of the insulating material layer 1 using a pretreatment solution (modification solution) containing a silane coupling agent as the pretreatment. Specific implementation methods of the wet method include spraying, dipping, spin coating, and printing, in which the pretreatment solution is brought into contact with the surface of the insulating material layer 1. Dipping is preferred because it allows for efficient treatment.

[0053] In order to improve the reactivity between the components of the pretreatment liquid and the insulating material layer 1, the surface of the insulating material layer 1 may be activated before performing the pretreatment for these modifications. Examples of activation methods include ultraviolet irradiation, electron beam irradiation, ozone water treatment, corona discharge treatment, and plasma treatment. However, ultraviolet irradiation is preferred because it does not require vacuum equipment and does not generate waste liquid.

[0054] Examples of UV lamps used for activation include high-pressure mercury lamps, low-pressure mercury lamps, and vacuum ultraviolet excimer lamps. Low-pressure mercury lamps or excimer lamps are preferred due to their high activation effect. Activation is preferably performed in air, more preferably in an oxygen atmosphere. Activation is preferably performed at 25°C to 100°C. To further accelerate reactivity, 40°C to 100°C is more preferred, and 60°C to 100°C is even more preferred.

[0055] The contact angle between the surface of the insulating material layer 1 after activation and pure water is preferably 40 degrees or less, more preferably 20 degrees or less, and even more preferably 10 degrees or less.

[0056] Pretreatment is preferably performed at 25°C to 80°C. To further accelerate reactivity, it is more preferably performed at 40°C to 80°C, and even more preferably at 60°C to 80°C. Pretreatment is preferably performed for 5 minutes to 30 minutes. To further accelerate reactivity, it is more preferably performed for 10 minutes to 30 minutes, and even more preferably for 15 minutes to 30 minutes. After contact with the pretreatment solution used in the pretreatment, the pretreatment solution may be washed with water or an organic solvent to remove excess pretreatment solution.

[0057] After the pretreatment, heat treatment may be performed to enhance the bonding strength between the insulating material layer 1 and the silane coupling agent, a component of the pretreatment solution. The heat treatment temperature is preferably 80°C to 200°C. To further accelerate reactivity, the temperature is more preferably 120°C to 200°C, and even more preferably 120°C to 180°C. The heat treatment time is preferably 5 minutes to 60 minutes, more preferably 10 minutes to 60 minutes, and even more preferably 20 minutes to 60 minutes. Furthermore, the pretreatment and heat treatment may be repeated multiple times.

[0058] <Step (IV) of Forming a Palladium Adsorption Layer>

[0059] Next, a step (IV) of forming a palladium adsorption layer 3 on the surface of the modified insulating material layer 1 including the recessed portion 1a is performed ( Figure 1 (c) In this embodiment, the palladium adsorption layer 3 is a layer formed by adsorbing palladium onto the surface of the insulating material layer 1 including the recessed portion 1a, and then activating the palladium so that the palladium functions as a catalyst. This layer serves as a catalyst for the electroless nickel plating reaction performed in the subsequent step. A method for forming the palladium adsorption layer 3 is described below.

[0060] First, palladium is deposited on the surface of the pretreated insulating material layer 1. The palladium can be a commercially available aqueous palladium solution for electroless plating, such as a solution of palladium-tin colloid dispersed in water (palladium-tin colloid solution), an aqueous palladium ion solution, or a palladium nanoparticle dispersion solution. The temperature of the aqueous solution used for palladium deposition is set between 25°C and 80°C, and the immersion time for deposition is between 1 minute and 60 minutes. After deposition, the excess palladium can be removed by washing with water or an organic solvent.

[0061] After the palladium is attached, it is activated to make the palladium function as a catalyst. The reagent for activating the palladium can be a commercially available activator (activation treatment solution). The temperature of the activator used to activate the palladium is 25°C to 80°C, and the time for activation is between 1 minute and 60 minutes. After the activation of the palladium, in order to remove the excess activator, it can be washed with water or an organic solvent.

[0062] <Step (V) of Forming the First Electroless Ni Plating Layer>

[0063] Next, a step (V) of forming a first electroless Ni plating layer 5 by electroless nickel plating is performed on the surface including the recessed portion 1a of the insulating material layer 1 on which the palladium adsorption layer 3 is formed ( Figure 1 (d) The first electroless Ni plating layer 5 serves as a seed layer (a power supply layer for electrolytic copper plating) for electrolytic copper plating to be performed in a subsequent step in order to form the Cu plating layer 7 .

[0064] As electroless nickel plating, electroless pure nickel plating (purity 99% or more), electroless nickel-phosphorus plating (phosphorus content: 1% to 13% by mass), and electroless nickel-boron plating (boron content: 0.3% to 1.0% by mass) can be cited, but from the perspective of the management stability of the plating bath, electroless nickel-boron plating is preferred. The boron content of the first electroless Ni plating layer 5 is preferably 0.3 to 1.0% by mass. If this value is less than 0.3% by mass, there is a tendency that the electrical properties become insufficient due to the magnetization characteristics and the reliability becomes insufficient. On the other hand, if it is greater than 1% by mass, there is a tendency that the electrical conductivity decreases and the electrical properties become insufficient. This value is preferably 0.3 to 0.8% by mass, and more preferably 0.3 to 0.5% by mass. The nickel content of the first electroless Ni plating layer 5 is, for example, 98.0 to 99.7% by mass, or 99.5 to 99.7% by mass.

[0065] The electroless nickel plating solution may be a commercially available plating solution, for example, TOP CHEM ALLOY B-1 (OKUNO CHEMICAL INDUSTRIES CO., LTD.) can be used. The electroless nickel plating is performed in an electroless nickel plating solution at 60°C to 90°C.

[0066] The thickness of the first electroless Ni plating layer 5 is preferably 20 to 400 nm, more preferably 40 to 300 nm, and even more preferably 60 to 250 nm. A thickness of 20 nm or greater for the first electroless Ni plating layer 5 facilitates a sufficient copper diffusion suppression effect. Furthermore, a thickness of 400 nm or less for the first electroless Ni plating layer 5 facilitates thinning the overall thickness when manufacturing a semiconductor device by multiplying wiring layers.

[0067] The first electroless Ni plating layer 5 preferably satisfies the following conditions.

[0068] 0.3≤Ta / T≤1.0

[0069] Ta represents the thickness of the first electroless Ni plating layer 5 formed on the inner surface of the recess 1a, and T represents the thickness of the first electroless Ni plating layer 5 formed on the surface of the insulating material layer 1. The inner surface of the recess 1a refers to the bottom and side surfaces of the recess 1a. If the Ta / T value is less than 0.3, resistance to Cu ion migration tends to be insufficient. On the other hand, if it is greater than 1.0, electrical conductivity of the wiring tends to be insufficient. This value is more preferably 0.6 to 1.0, and even more preferably 0.8 to 1.0.

[0070] After electroless nickel plating, in order to remove excess plating solution, it can be washed with water or an organic solvent. In addition, after electroless nickel plating, in order to improve the adhesion between the first electroless Ni plating layer 5 and the insulating material layer 1, thermal curing (annealing: aging curing treatment based on heating) can be performed. Regarding the thermal curing temperature, it is preferably heated at 80°C to 200°C. In order to further accelerate the reactivity, it is more preferably 120°C to 200°C, and further preferably heated at 120°C to 180°C. The thermal curing time is preferably 5 minutes to 60 minutes, more preferably 10 minutes to 60 minutes, and further preferably 20 minutes to 60 minutes.

[0071] <Step (VI) of forming a Cu plating layer>

[0072] Next, a step (VI) of forming a Cu plating layer 7 by electrolytic copper plating on the first electroless Ni plating layer 5 is performed ( Figure 2(a)). Specifically, a first electroless Ni plating layer 5 formed by electroless nickel plating is used as a seed layer, and a Cu plating layer 7 is formed on the first electroless Ni plating layer 5 by electrolytic copper plating. At the same time, the Cu plating layer 7 is filled in the recess 1a whose inner wall is covered by the first electroless Ni plating layer 5. In this embodiment, electrolytic copper plating is used as a method for forming the Cu plating layer 7, but other methods, for example, electroless copper plating can be selected.

[0073] The thickness of the Cu plating layer 7 (excluding the region where the recessed portion 1 a is formed) is preferably 1 to 10 μm, more preferably 1 to 5 μm, and even more preferably 1 to 3 μm.

[0074] By filling the recess 1a with the Cu plating layer 7, in the next step (VII), only the Cu plating layer 7, the first electroless Ni plating layer 5, and the palladium (palladium adsorption layer) remaining thereunder, formed on the surface of the insulating material layer 1, in the area outside the recess 1a, are removed. This allows the surface of the insulating material layer 1 and the wiring layer 8 (composed of the Cu plating layer 7, the first electroless Ni plating layer 5, and the palladium adsorption layer 3) formed within the recess 1a to be flush with each other. When filling the recess 1a with the Cu plating layer 7 by electrolytic copper plating, it is preferable to use so-called fill plating, in which the amount of electrolytic copper plating deposited (plating thickness) within the recess 1a is greater than that on the surface of the insulating material layer 1.

[0075] In addition, the recess 1a does not necessarily need to be filled with the Cu plating layer 7. The Cu plating layer 7 may also be formed along the inner wall (side surface and bottom surface) of the recess 1a. In this case, in the next step (VII), after removing the Cu plating layer 7 formed in the area other than the recess 1a on the surface of the insulating material layer 1, the first electroless Ni plating layer 5, and the palladium (palladium adsorption layer) remaining thereunder, the surface of the insulating material layer 1 is then cut to expose the Cu plating layer 7 formed on the bottom surface of the recess 1a. This allows the surface of the insulating material layer 1 and the wiring layer 8 formed in the recess 1a to be flush with each other.

[0076] <Step (VII) of forming a wiring layer including a Cu plating layer>

[0077] Next, a step (VII) is performed to form a wiring layer 8 including the Cu plating layer 7 formed in the recessed portion 1a by removing the Cu plating layer 7, the first electroless Ni plating layer 5, and the palladium adsorption layer 3 in the region other than the recessed portion 1a formed in the surface of the insulating material layer 1 ( Figure 2(b)). That is, by removing the Cu plating layer 7, the first electroless Ni plating layer 5, and the palladium (palladium adsorption layer 3) remaining thereunder formed on the upper surface of the insulating material layer 1, a portion of the Cu plating layer 7, the first electroless Ni plating layer 5, and the palladium adsorption layer 3 remains within the recess 1a. As a result, a wiring layer 8 composed of the Cu plating layer 7, the first electroless Ni plating layer 5, and the palladium adsorption layer 3 is formed within the recess 1a.

[0078] When removing the Cu plating layer 7, the first electroless Ni plating layer 5, and the palladium remaining thereunder formed on the upper surface of the insulating material layer 1, it is preferred that the treatment be performed so that the surface of the insulating material layer 1 and the wiring layer 8 within the recess 1a are flush with each other. In other words, after step (VII), it is preferred that step (VII) be performed so that the surface of the insulating material layer 1 and the wiring layer 8 within the recess 1a are flat. The removal treatment in step (VII) may target only the Cu plating layer 7, the first electroless Ni plating layer 5, and the palladium remaining thereunder formed on the upper surface of the insulating material layer 1, or may also target a portion of the upper surface side of the insulating material layer 1.

[0079] As the removal process in operation (VII), the process based on back grinding method, fly cutting (fly cutting) method and chemical mechanical polishing (CMP) etc. can be enumerated, among these, can adopt 1 kind alone, also can use more than 2 kinds.For example, in fly cutting method, the grinding device based on diamond drill bit can be used.As a specific example, the automatic leveling machine (Automatic Surface Planer) (DISCO Corporation system, product name " DAS8930 ") corresponding to 300mm wafer can be used.In addition, the removal process based on fly cutting method is the process of uniformly grinding the entire surface from the upper surface side of Cu plating layer 7, and the ground surface becomes flat, therefore also referred to as planarization process.

[0080] <Step (VIII) of Forming the Second Electroless Ni Plating Layer>

[0081] Next, a step (VIII) is performed of forming a second electroless Ni plating layer 9 by electroless nickel plating on the exposed surface 8a of the wiring layer 8 formed by the removal treatment in the above step (VII) ( Figure 2 (c)). Thus, a wiring board 10 (a component for manufacturing a semiconductor device) is manufactured. For example, by sequentially subjecting the exposed surface 8a of the wiring layer 8 to degreasing, water washing, sulfuric acid cleaning, palladium catalysis, and nickel plating, the second electroless nickel plating layer 9 can be formed only on the exposed surface 8a. As the plating solution for the electroless nickel plating, a commercially available alternative electroless plating solution can be used.

[0082] As electroless nickel plating, electroless pure nickel plating (purity 99% or more by mass), electroless nickel-phosphorus plating (phosphorus content: 1% to 13% by mass) and electroless nickel-boron plating (boron content: 0.3% to 1.0% by mass) can be cited. Among these, from the viewpoint of selectively forming the electroless plating film on Cu, electroless nickel-phosphorus plating is preferred. The phosphorus content of the second electroless Ni plating layer 9 is preferably 1 to 13% by mass. If this value is less than 1% by mass, there is a tendency that the electrical properties become insufficient and the reliability becomes insufficient due to the magnetization characteristics. On the other hand, if it is greater than 13% by mass, there is a tendency that the electrical conductivity decreases and the electrical properties become insufficient. This value is preferably 1 to 10% by mass, more preferably 1 to 8% by mass. The nickel content of the second electroless Ni plating layer 9 is, for example, 88 to 99% by mass, or 92 to 99% by mass.

[0083] The electroless nickel plating solution may be a commercially available plating solution. For example, a medium-phosphorus type (phosphorus content: 7% to 9% by mass) electroless nickel plating solution (manufactured by Sanmei Co., Ltd., product names "ICP Nicoron GM-SB-M" and "ICP Nicoron GMSD") may be used. Electroless nickel plating is performed in the electroless nickel plating solution at a temperature of 60°C to 90°C.

[0084] By covering the exposed surface 8a of the wiring layer 8 with the second electroless Ni plating layer 9, the diffusion of copper contained in the wiring layer 8 can be sufficiently suppressed. Therefore, the wiring substrate 10 is useful in manufacturing a semiconductor device having a fine wiring layer with sufficiently high insulation reliability. The thickness of the second electroless Ni plating layer 9 is preferably 50 to 500 nm, more preferably 100 to 400 nm, and further preferably 150 to 300 nm. By having a thickness of the second electroless Ni plating layer 9 of 50 nm or more, it is easy to obtain a sufficient copper diffusion suppression effect. On the other hand, by having a thickness of the second electroless Ni plating layer 9 of 500 nm or less, it is easy to make the overall thickness thinner when the wiring layer is multilayered to manufacture a semiconductor device.

[0085] Wiring substrate 10 includes: insulating material layer 1; recess 1a; first electroless Ni plating layer 5 formed to cover the inner surface of recess 1a; Cu plating layer 7 filling recess 1a; and second electroless Ni plating layer 9 formed to cover the exposed surface of Cu plating layer 7. Wiring layer 8 is formed by first electroless Ni plating layer 5 and Cu plating layer 7.

[0086] As mentioned above, the component (wiring board) for manufacturing a semiconductor device has been described. However, the present invention is not necessarily limited to the above-mentioned embodiment, and can be modified appropriately without departing from the scope of the present invention.

[0087] For example, in the above embodiment, a method for manufacturing a wiring substrate 10 having a single wiring layer is illustrated, but a wiring substrate having a multilayered wiring layer can be manufactured instead of the wiring substrate 10, and used to manufacture a semiconductor device. The multilayered wiring layer can be formed by repeating the step (XI) of forming an insulating material layer in a manner covering the insulating material layer 1 and the second electroless Ni plating layer 9 after the above step (VIII) more than once, and a series of steps from the above step (II) to the above step (VIII). The same material as the above-mentioned insulating material layer 1 can be used for the formation of the insulating material layer in step (XI), preferably a photosensitive insulating material. The insulating material layer can be formed in the same manner as the insulating material layer 1. The thickness of the insulating material layer is preferably 10 μm or less, more preferably 5 μm or less, and even more preferably 3 μm or less.

[0088] In the above embodiment, the insulating material layer is illustrated as a single layer. However, the insulating material layer may also have a laminated structure. Specifically, the insulating material layer is formed through the following steps and comprises a first insulating layer and a second insulating layer formed on the surface of the first insulating layer. A recess may be formed in the second insulating layer. In this case, the bottom surface of the recess is formed by the surface of the first insulating layer.

[0089] (a1) A step of curing the first insulating layer by exposing the first insulating layer composed of a negative photosensitive resin composition to light.

[0090] (a2) A step of forming a second insulating layer made of a negative-type photosensitive resin composition on the surface of the cured first insulating layer.

[0091] (a3) A step of exposing a region of the second insulating layer where the recess is to be formed.

[0092] (a4) A step of forming a recess by developing the exposed second insulating layer.

[0093] The present invention relates to the following inventions.

[0094] [1] A method for manufacturing a component for manufacturing a semiconductor device, comprising:

[0095] (a) forming a recessed portion on the surface of the insulating material layer;

[0096] (b) forming a first electroless Ni plating layer on the surface of the insulating material layer and the inner surface of the recess by electroless nickel plating;

[0097] (c) forming a Cu plating layer on the first electroless Ni plating layer;

[0098] (d) forming a wiring layer including the Cu plating layer in the recess by removing the Cu plating layer and the first electroless Ni plating layer formed on the surface of the insulating material layer; and

[0099] (e) forming a second electroless Ni plating layer on the exposed surface of the wiring layer by electroless nickel plating;

[0100] The first electroless Ni plating layer contains nickel and boron,

[0101] The boron content of the first electroless Ni plating layer is 0.3 to 1.0 mass % based on the mass of the first electroless Ni plating layer.

[0102] [2] The method for manufacturing a component for manufacturing a semiconductor device according to [1], wherein:

[0103] The second electroless Ni plating layer contains nickel and phosphorus,

[0104] The phosphorus content of the second electroless Ni plating layer is 1 to 13% by mass based on the mass of the second electroless Ni plating layer.

[0105] [3] The method for manufacturing a semiconductor device manufacturing component according to [1] or [2], wherein:

[0106] The first electroless Ni plating layer formed in the step (b) satisfies the following conditions.

[0107] 0.3≤Ta / T≤1.0

[0108] Ta represents the thickness of the first electroless Ni plating layer formed on the inner surface of the recessed portion, and T represents the thickness of the first electroless Ni plating layer formed on the surface of the insulating material layer.

[0109] [4] The method for manufacturing a member for manufacturing a semiconductor device according to any one of [1] to [3], wherein:

[0110] (a) The process includes:

[0111] (a1) curing the first insulating layer by exposing the first insulating layer composed of a negative photosensitive resin composition to light;

[0112] (a2) forming a second insulating layer composed of a negative photosensitive resin composition on the surface of the cured first insulating layer;

[0113] (a3) exposing a region of the second insulating layer where the recess is to be formed; and

[0114] (a4) A step of forming the recess by developing the exposed second insulating layer.

[0115] [5] A component for manufacturing a semiconductor device, comprising:

[0116] Insulation material layer;

[0117] a recess formed on a surface of the insulating material layer;

[0118] a first electroless Ni plating layer formed so as to cover the inner surface of the recess;

[0119] a Cu plating layer formed on the surface of the first electroless Ni plating layer and filling the recess; and

[0120] a second electroless Ni plating layer formed so as to cover the exposed surface of the Cu plating layer;

[0121] The first electroless Ni plating layer contains nickel and boron,

[0122] The boron content of the first electroless Ni plating layer is 0.3 to 1.0 mass % based on the mass of the first electroless Ni plating layer.

[0123] [6] The component for manufacturing a semiconductor device according to [5], wherein:

[0124] The second electroless Ni plating layer contains nickel and phosphorus. The phosphorus content of the second electroless Ni plating layer is 1 to 13% by mass based on the mass of the second electroless Ni plating layer.

[0125] [7] The component for manufacturing a semiconductor device according to [5] or [6], wherein:

[0126] The recessed portion is a groove having an opening width of 0.5 to 3 μm.

[0127] [8] The component for manufacturing a semiconductor device according to any one of [5] to [7], wherein

[0128] The thickness of the insulating material layer is less than 10 μm.

[0129] Example

[0130] Hereinafter, the present invention will be described based on examples. However, the present invention is not limited to the following examples.

[0131] (Example 1)

[0132] A layer of negative photosensitive insulating material (2 μm thick) was formed on the surface of a silicon wafer. The entire surface of the layer was exposed to broadband i-rays using a high-pressure mercury lamp and then heated on a hot plate at 85°C. After development with 2.38% TMAH (Tetra-methyl ammonium hydrooxide), a first insulating layer was formed by thermal curing. Next, a layer of the same photosensitive insulating material as the first insulating layer was formed on the surface of the first insulating layer (2 μm thick). Exposure was performed using an i-ray stepper in such a manner as to form a groove pattern in the layer. After exposure, heating was performed on a hot plate. After development with 2.38% TMAH, a second insulating layer having a groove pattern was formed by thermal curing. Thus, an insulating material layer (4 μm thick) consisting of the first insulating layer and the second insulating layer was obtained. The L / S (width / space) of the groove pattern was set to 1.2 μm / 1.2 μm (reference Figure 3 ).

[0133] A Ni-B seed layer (first electroless Ni plating layer) with a thickness of 200 nm was formed on the surface of the second insulating layer and the inner surface of the groove (the side and bottom of the groove) by an electroless Ni-B plating process (refer to Figure 4 (a) and Figure 4 (b)). The boron content of the Ni-B seed layer is 0.4% by mass, and the nickel content is 99.6% by mass. The contents mentioned here are based on the mass of the Ni-B seed layer. Figure 4 In (b), “Ni—B seed layer” represents a Ni—B seed layer, and “Dielectiric” represents a dielectric layer (insulating material layer).

[0134] Next, a Cu plating layer with a thickness of 5 μm was formed on the Ni-B seed layer by electrolytic Cu plating. Thus, the interior of the groove pattern was filled with the Cu plating layer. Afterwards, the excess Cu plating layer and the Ni-B seed layer were ground by CMP, and a portion of the surface of the second insulating layer was ground. After grinding, a metal cover (second electroless Ni plating layer) with a thickness of 200 nm was formed on the surface of the exposed Cu plating layer by an electroless Ni-P plating process. The phosphorus content in the metal cover is 5% by mass, and the nickel content is 95% by mass. The contents mentioned here are all based on the mass of the metal cover. A photosensitive insulating material layer (thickness 3 μm) was formed in a manner covering the metal cover. After the above process, Figure 5 (a) and Figure 5 (b) The interdigitated electrodes of the structure shown are formed on the surface of the silicon wafer. Figure 5 “Cu pad” in (a) represents a Cu pad. Figure 5In (b), “photosensitive dielectric” means a photosensitive dielectric layer (photosensitive insulating material layer), and “damascene wiring” means damascene wiring.

[0135] (Example 2)

[0136] Interdigitated electrodes were formed on the surface of a silicon wafer in the same manner as in Example 1, except that the L / S (width / space) of the groove pattern was set to 1.5 μm / 1.5 μm instead of 1.2 μm / 1.2 μm.

[0137] (Comparative Example 1)

[0138] Interdigitated electrodes were formed on the surface of the silicon wafer in the same manner as in Example 2 except that no metal cap was formed on the surface of the Cu plating layer.

[0139] (Comparative Example 2)

[0140] Interdigitated electrodes were formed on the surface of the silicon wafer in the same manner as in Example 2 except that a Ti / Cu seed layer was formed as the seed layer instead of the Ni—B seed layer.

[0141] (Comparative Example 3)

[0142] Interdigitated electrodes were formed on the surface of the silicon wafer in the same manner as in Example 2, except that neither the Ni—B seed layer nor the metal cap was formed and the interior of the groove pattern was filled with a Cu plating layer by electroless Cu plating.

[0143] [Electrical insulation test]

[0144] The electrical insulation properties of the interdigitated electrodes of Example 2 and Comparative Examples 1 to 3 were evaluated by b-HAST (biased-Highly Accelerated Stress Test). The b-HAST conditions were an applied voltage of 3.3 V, a temperature of 130°C, and a relative humidity of 85%. As a result, in Example 2, the resistance value of 10 8 On the other hand, in Comparative Examples 1 and 3, the resistance value became 10Ω or more after several hours. 6 Ω or less. In Comparative Example 2, the resistance value becomes 10 after about 60 hours. 6 Ω or less.

[0145] STEM analysis of a cross-section of the interdigitated electrode from Example 2 after 200 hours of b-HAST revealed no Cu dendrites or other structures between the wiring. Furthermore, EDX mapping confirmed that no Cu or Ni elements were detected in the photosensitive insulating material between the wirings, and that no ion migration of these elements occurred during the 200 hours of b-HAST.

[0146] Explanation of symbols

[0147] S-support, 1-insulating material layer, 1a-recessed portion, 3-palladium adsorption layer, 5-first electroless Ni plating layer, 7-Cu plating layer, 8-wiring layer, 8a-exposed surface, 9-second electroless Ni plating layer, 10-wiring substrate (component for manufacturing semiconductor devices).

Claims

1. A method for manufacturing a component for semiconductor device manufacturing, comprising: (a) forming a recessed portion on the surface of the insulating material layer; (b) forming a first electroless Ni plating layer on the surface of the insulating material layer and the inner surface of the recess by electroless nickel plating; (c) forming a Cu plating layer on the first electroless Ni plating layer; (d) forming a wiring layer including the Cu plating layer in the recess by removing the Cu plating layer and the first electroless Ni plating layer formed on the surface of the insulating material layer; and (e) forming a second electroless Ni plating layer on the exposed surface of the wiring layer by electroless nickel plating; The first electroless Ni plating layer contains nickel and boron, The boron content of the first electroless Ni plating layer is 0.3 to 1.0 mass % based on the mass of the first electroless Ni plating layer.

2. The method for manufacturing a semiconductor device manufacturing component according to claim 1, wherein: The second electroless Ni plating layer contains nickel and phosphorus, The phosphorus content of the second electroless Ni plating layer is 1 to 13% by mass based on the mass of the second electroless Ni plating layer.

3. The method for manufacturing a member for manufacturing a semiconductor device according to claim 1 or 2, wherein: The first electroless Ni plating layer formed in step (b) satisfies the following conditions: 0.3≤Ta / T≤1.0 Ta represents the thickness of the first electroless Ni plating layer formed on the inner surface of the recessed portion, and T represents the thickness of the first electroless Ni plating layer formed on the surface of the insulating material layer.

4. The method for manufacturing a member for manufacturing a semiconductor device according to claim 1 or 2, wherein: (a) The process includes: (a1) curing the first insulating layer by exposing the first insulating layer composed of a negative photosensitive resin composition to light; (a2) forming a second insulating layer composed of a negative photosensitive resin composition on the surface of the cured first insulating layer; (a3) exposing a region of the second insulating layer where the recess is to be formed; and (a4) A step of forming the recess by developing the exposed second insulating layer.

5. A component for manufacturing a semiconductor device, comprising: Insulation material layer; a recess formed on a surface of the insulating material layer; a first electroless Ni plating layer formed so as to cover the inner surface of the recess; a Cu plating layer formed on the surface of the first electroless Ni plating layer and filling the recess; and a second electroless Ni plating layer formed so as to cover the exposed surface of the Cu plating layer; The first electroless Ni plating layer contains nickel and boron, The boron content of the first electroless Ni plating layer is 0.3 to 1.0 mass % based on the mass of the first electroless Ni plating layer.

6. The component for manufacturing a semiconductor device according to claim 5, wherein: The second electroless Ni plating layer contains nickel and phosphorus, The phosphorus content of the second electroless Ni plating layer is 1 to 13% by mass based on the mass of the second electroless Ni plating layer.

7. The component for manufacturing a semiconductor device according to claim 5 or 6, wherein: The recessed portion is a groove having an opening width of 0.5 to 3 μm.

8. The component for manufacturing a semiconductor device according to claim 5 or 6, wherein: The thickness of the insulating material layer is less than 10 μm.

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