Storage device, operation method of storage device, and storage system

Abstract

The invention provides a storage device, an operating method of the storage device, and a storage system. A storage device according to some example embodiments includes: a non-volatile memory including a first memory including a plurality of partitions configured to sequentially store data based on a write pointer, the write pointer indicating a location at which the data is to be written, and a second memory configured to store preliminary data to be written in the plurality of partitions; and a storage controller configured to receive a plurality of operation requests, each of the plurality of operation requests including a logical block address, a write command, and write data, and if a position of a first logical block address corresponding to a first operation request among the plurality of operation requests does not match a write pointer, the first logical block address corresponding to the first operation request; and if yes, storing first write data corresponding to the first operation request in a second memory as first preliminary data.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0019064 filed on February 7, 2024, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The inventive concept relates to a storage device, an operating method of a storage device, and a storage system. Background Art

[0003] As a non-volatile memory, flash memory can retain data even in the absence of applied power. Recently, storage devices including flash memory, such as solid-state drives (SSDs) and memory cards, are becoming widely used.

[0004] Typically, non-volatile memory devices store data based on random access. This random access is accompanied by frequent garbage collection (GC) operations across the entire area, which reduces the useful life of the storage device. Because a large over-provisioning (OP) area is allocated for frequent garbage collection, wear leveling, and bad block management, the available storage capacity of the storage device can be reduced. To prevent this, recent technologies have been developed for dividing a non-volatile memory device's memory blocks into multiple partitions and sequentially storing related data within the partitions. Summary of the Invention

[0005] The inventive concept provides a storage device capable of sequentially writing data into a nonvolatile memory.

[0006] According to some example embodiments, a storage device includes: a non-volatile memory, including: a first memory including a plurality of partitions configured to sequentially store data based on a write pointer indicating a location where the data is to be written, and a second memory configured to store preliminary data to be written in the plurality of partitions; and a storage controller configured to receive a plurality of operation requests, each of the plurality of operation requests including a logical block address, a write command, and write data, and if a position of a first logical block address corresponding to a first operation request among the plurality of operation requests does not match the write pointer, storing the first write data corresponding to the first operation request in the second memory as first preliminary data.

[0007] According to some example embodiments, a storage system includes: a host device configured to send multiple operation requests, each of the multiple operation requests including a logical block address, a write command, and write data; a storage device including: a first memory including multiple partitions configured to sequentially store data, and a second memory configured to store preliminary data to be written into the multiple partitions, based on a determination that a first operation request among the multiple operation requests cannot be processed, storing first write data corresponding to the first operation request in the second memory as first preliminary data, and writing the first preliminary data to a location corresponding to a write pointer in response to receiving a synchronization command from the host device, the write pointer indicating a location in the first memory where the data is to be written.

[0008] An operating method of a storage system according to some example embodiments includes: receiving an operation request for writing write data to a location corresponding to a first logical block address in a plurality of partitions, the plurality of partitions being configured to sequentially store data using a write pointer indicating a location of the data to be written, determining a target partition to be written among the plurality of partitions and a target write pointer indicating a location to be written in a target area based on the first logical block address, and determining whether to process the operation request based on a position of a current write pointer of the target partition and a position of the target write pointer, storing the write data as preliminary data in a second memory if the operation request cannot be processed, receiving a synchronization command including the first logical block address, and reading the preliminary data and writing the preliminary data to a location corresponding to the current write pointer of the target partition. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A storage system according to some example embodiments is shown.

[0010] Figure 2 A memory controller according to some example embodiments is shown.

[0011] Figure 3 Shown is a partial configuration of a memory device according to some example embodiments.

[0012] Figure 4 is a block diagram illustrating an example of a nonvolatile memory according to some example embodiments.

[0013] Figure 5 A memory cell array according to some example embodiments is illustrated.

[0014] Figure 6 An operating method of a storage system according to some example embodiments is illustrated.

[0015] Figure 7 An operating method of a storage system according to some example embodiments is illustrated.

[0016] Figure 8 An operating method of a storage system according to some example embodiments is illustrated.

[0017] Figure 9 An operating method of a storage system according to some example embodiments is illustrated.

[0018] Figure 10 A storage system according to some example embodiments is shown.

[0019] Figure 11 A storage system according to some example embodiments is shown. DETAILED DESCRIPTION

[0020] In the following detailed description, only some exemplary embodiments of the present invention are shown and described simply by way of illustration. As those skilled in the art will appreciate, the described exemplary embodiments may be modified in various different ways without departing from the spirit or scope of the present invention.

[0021] Therefore, the drawings and description are to be considered illustrative in nature and not restrictive. Throughout the specification, like reference numerals denote like elements. In the flowcharts described in this specification with reference to the drawings, the order of operations may be changed, some operations may be combined, some operations may be divided, and certain operations may not be performed.

[0022] In the description, unless a clear expression (such as "one" or "single") is used, expressions described in the singular in this specification may be interpreted as singular or plural. Although terms including ordinal numbers (such as "first" and "second") may be used to describe various components, these components are not limited to the above terms. These terms are only used to distinguish one component from another.

[0023] Figure 1 A storage system according to some example embodiments is shown. Figure 2 A memory controller according to some example embodiments is shown. Figure 3 Shown is a partial configuration of a memory device according to some example embodiments.

[0024] In some example embodiments, the storage system 10 may be included in a user device (such as a personal computer, laptop computer, server, media player, digital camera, etc.), but example embodiments are not limited thereto. In some example embodiments, the storage system 10 may be included in an automotive device (such as a navigation device, black box, automotive electronic device, etc.), but example embodiments are not limited thereto. In some example embodiments, the storage system 10 may be included in a mobile system (such as a mobile phone, smartphone, tablet personal computer (PC), wearable device, healthcare device, or Internet of Things (IoT) device), but example embodiments are not limited thereto.

[0025] like Figure 1 As shown in , the storage system 10 includes a host device 100 and a storage device 200 .

[0026] The host device 100 controls the overall operation of the memory system 10 .

[0027] The host device 100 may communicate with the storage device 200 through various interfaces. For example, the host device 100 may communicate with the storage device 200 through various interfaces such as Universal Serial Bus (USB), MultiMediaCard (MMC), PCI Express (PCI-E), AT Attachment (ATA), Serial AT Attachment (SATA), Parallel AT Attachment (PATA), Small Computer System (SCSI), Serial Attached SCSI (SAS), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Non-Volatile Memory Express (NVMe), etc., but example embodiments are not limited thereto.

[0028] The host device 100 may provide, transfer, or send a logical block address LBA and a request signal REQ representing the logical address to the memory device 200. In some example embodiments, the host device 100 may exchange data DQ with the memory device 200 (e.g., the host device 100 may transfer, transfer, or send the data DQ to the memory device 200 and may receive the data DQ from the memory device 200).

[0029] In some example embodiments, the logical block address LBA may include a logical unit number LUN. The logical unit number may include information about a logical unit number of the storage device 200 to which the request signal REQ is transmitted or sent.

[0030] In some example embodiments, the request signal REQ may include a task tag, an initiator ID (ID), a command set type, an expected data transfer length, and the like, but example embodiments are not limited thereto. The task tag may include a unique tag value maintained for task-related transfers. The initiator ID may include information regarding the ID of the host device 100 that transmits or sends the request signal REQ. The expected data transfer length may include information regarding the number of bits to be transmitted or sent to complete a small computer system interface (SCSI) command request.

[0031] In some example embodiments, the host device 100 may transfer, provide, or send a request signal REQ including a write command, a logical block address LBA to which data DQ is to be written, and the data DQ to the memory device 200. The memory device 200 may write the data DQ to a location corresponding to the logical block address LBA in response to the request signal REQ and the logical block address LBA.

[0032] In some example embodiments, the host device 100 may transfer, provide, or send a plurality of operation requests to the memory device 200. For example, the operation request may include a request signal REQ and a logical block address LBA including a write command.

[0033] The storage device 200 may be accessible by the host device 100. For example, the storage device 200 may be implemented in the form of a solid state drive (SSD), a smart SSD, an embedded multimedia card (eMMC), an embedded universal flash memory (UFS) memory device, a UFS memory card, a compact flash (CF), a secure digital (SD), a micro secure digital (Micro-SD), a mini secure digital (Mini-SD), extreme digital (xD), a memory stick, or the like, but example embodiments are not limited thereto.

[0034] In some example embodiments, the storage device 200 may be connected to the host device 100 through a block-accessible interface including a bus such as a Serial Advanced Technology Attachment (SATA) bus, a Small Computer System Interface (SCSI) bus, a Non-Volatile Memory Express (NVMe), a Serial Attached SCSI (SAS) bus, UFS, and eMMC, but example embodiments are not limited thereto.

[0035] The memory device 200 may include a nonvolatile memory (NVM) 400 and a memory controller 300. The memory device 200 may store or process data DQ in response to a request signal REQ from the host device 100.

[0036] The nonvolatile memory 400 may include multiple dies or multiple chips including a memory cell array. For example, the nonvolatile memory 400 may include multiple chips, and each of the multiple chips may include multiple dies. In some example embodiments, the nonvolatile memory 400 may also include multiple channels, each channel including multiple chips.

[0037] The nonvolatile memory 400 may include a NAND flash memory. In some example embodiments, the nonvolatile memory 400 may include an electrically erasable programmable read-only memory (EEPROM), a phase-change random access memory (PRAM), a resistive RAM (ReRAM), a resistive random access memory (RRAM), a nano-floating gate memory (NFGM), a polymer random access memory (PoRAM), a magnetic random access memory (MRAM), a ferroelectric random access memory (FRAM), or the like, but example embodiments are not limited thereto. Hereinafter, in the following description, the nonvolatile memory 400 will be described assuming that the nonvolatile memory 400 is a NAND flash memory device.

[0038] In some example embodiments, the nonvolatile memory 400 may include a user memory 4031 and a reserved memory 4033 .

[0039] The user memory 4031 may be divided into a plurality of partitions. The storage controller 300 may sequentially write data to the user memory 4031. Random writes may be disabled within the user memory 4031. A write pointer may indicate the location where the next data will be written in each partition. In some example embodiments, as data is written to each partition, the corresponding write pointer may be updated.

[0040] In some example embodiments, the storage device 200 may be implemented based on various standards such as Zoned Name Space (ZNS), Zoned Block Device (ZBD), etc., but example embodiments are not limited thereto.

[0041] The reserved memory 4033 may store preliminary data. The preliminary data may be data to be written to the user memory 4031. For example, the storage controller 300 may read the preliminary data stored in the reserved memory 4033 and write the read preliminary data to the user memory 4031. In some example embodiments, the size of the reserved memory 4033 may be set in advance. For example, the storage device 200 may set the size of the reserved memory 4033 based on a set feature command received from the host device 100.

[0042] In some example embodiments (such as Figure 1), one storage device 200 is illustrated as including one nonvolatile memory 400, but the inventive concept is not limited thereto, and the storage device 200 may include a plurality of nonvolatile memories.

[0043] The memory controller 300 may control operations of the memory device 200 .

[0044] The memory controller 300 may provide an address ADDR, a command CMD, a control signal CTRL, etc. to the nonvolatile memory 400 in response to a logical block address LBA and a request signal REQ received from the host device 100 .

[0045] In some example embodiments, the address ADDR may include a user memory address for the user memory 4031 and a reserved memory address for the reserved memory 4033. The memory controller 300 may provide, transfer, or send a signal to the nonvolatile memory 400 to write data to or read data from the nonvolatile memory 400. In some example embodiments, the memory controller 300 and the nonvolatile memory 400 may exchange data DATA.

[0046] and Figure 1 Refer to it together Figure 2 In some example embodiments, the memory controller 300 may include a host interface (I / F) 311 , a partition management circuit 301 , a flash translation layer (FTL) 303 , a reserved memory management circuit 305 , a processor 307 , a buffer memory 309 , and a memory interface 313 .

[0047] The host interface 311 may transfer, provide, or send data packets to the host device 100 and receive data packets from the host device 100. The data packets transferred, provided, or sent from the host device 100 to the host interface 311 may include data or commands to be written to the nonvolatile memory 400. The data packets transferred, provided, or sent from the host interface 311 to the host device 100 may include responses to data or commands read from the nonvolatile memory 400.

[0048] The partition management circuit 301 may manage a write pointer (WP) position of each of the plurality of partitions in the user memory 4031. In some example embodiments, the partition management circuit 301 may determine whether to process the request signal REQ based on current states of the plurality of partitions.

[0049] Reference Figure 3In some example embodiments, the partition management circuit 301 may generate a match signal SIG_MATCH indicating whether the request signal REQ can be processed based on the results of the write pointer comparison operation and the data size comparison operation. For example, the request signal REQ may include a write command. The partition management circuit 301 may transmit, provide, or send the match signal SIG_MATCH to the processor 307.

[0050] In some example embodiments, the partition management circuit 301 may generate a match signal SIG_MATCH indicating whether the positions of the write pointers match.

[0051] For example, the partition management circuit 301 may obtain or alternatively determine, based on the logical block address (LBA) received from the host device 100, a partition address indicating a target partition to be written to among multiple partitions in the user memory 4031 and the position of a target write pointer to be written to the corresponding partition. The partition management circuit 301 may perform a write pointer comparison operation. The partition management circuit 301 may determine whether the position of the target write pointer matches the position of the current write pointer of the target partition. For example, the logical block address (LBA) may indicate a first partition among multiple partitions in the user memory 4031 and a first position of a target write pointer for the first partition. The partition management circuit 301 may compare the first position of the target write pointer with the second position of the current write pointer of the first partition.

[0052] In some example embodiments, the partition management circuit 301 may generate a match signal SIG_MATCH based on a result of the data size comparison operation.

[0053] For example, the partition management circuit 301 may compare the size of the data DQ received from the host device 100 with the size of the remaining storage space of the target partition in the user memory 4031. For example, the first size of the data DQ received from the host device 100 and the second size of the remaining storage space of the target partition may be compared. For example, the remaining storage space of the target partition may include at least one writable block.

[0054] For example, when the first position of the target write pointer matches the second position of the current write pointer of the target partition, and the first size of the data DQ is less than or equal to the second size of the remaining storage space in the target partition, the partition management circuit 301 may generate a match signal SIG_MATCH indicating that writing is possible. For example, when the first position of the target write pointer and the second position of the current write pointer of the target partition are different from each other, or the first size of the data DQ is greater than the second size of the remaining storage space in the target partition, the partition management circuit 301 may generate a match signal SIG_MATCH indicating that writing is not possible.

[0055] However, the inventive concept is not limited thereto, and the partition management circuit 301 may determine whether the memory device 200 can perform a write operation through various comparison operations.

[0056] The FTL 303 may include firmware or software that manages data writes, data reads, and sub-block and / or block erase operations of the non-volatile memory 400. The firmware of the FTL 303 may be executed by the processor 307. In some example embodiments, the FTL 303 may be implemented by various hardware automation circuits configured to perform the various maintenance operations described above. For example, the FTL 303 may be implemented as hardware, and the various maintenance operations described above may be performed by the hardware.

[0057] The FTL 303 may perform various maintenance operations to efficiently use the nonvolatile memory 400. For example, the FTL 303 may perform several functions such as address mapping, wear leveling, and garbage collection.

[0058] The FTL 303 may change a logical block address (LBA) received from the host device 100 into a physical address for storing data in the user memory 4031. For example, the FTL 303 may use a user address mapping table UM_MT to map the logical block address LBA and the user memory address UM_ADDR from the host device 100. The FTL 303 may include the user address mapping table UM_MT, and in some example embodiments, the user address mapping table UM_MT may include mapping information between the logical block address LBA and the user memory address UM_ADDR.

[0059] According to some example embodiments, wear leveling may be an operation of preventing or reducing excessive degradation of a specific block, or alternatively, a desired block, by balancing the frequency or amount of use of a plurality of memory blocks included in the nonvolatile memory 400. For example, the wear leveling operation may be implemented by firmware or hardware that balances erase counts of physical blocks.

[0060] According to some example embodiments, garbage collection may be an operation of copying valid data from blocks in the nonvolatile memory 400 to new blocks and erasing existing blocks so that the existing blocks can be reused, in order to ensure available capacity within the nonvolatile memory 400 .

[0061] In some example embodiments, the FTL 303 may store data required for performing operations of the FTL 303. For example, the FTL 303 may store block information of the nonvolatile memory 400, a garbage collection level for performing garbage collection on the nonvolatile memory 400, a user address mapping table UM_MT for converting a logical block address LBA of the host device 100 into a physical address of the user memory 4031, an address mapping table managed by garbage collection or a wear leveling operation, etc. However, the present inventive concept is not limited thereto, and data for performing operations of the FTL 303 may be stored in the buffer memory 309 or the nonvolatile memory 400.

[0062] The reserved memory management circuit 305 may perform various operations to use the reserved memory 4033. For example, the reserved memory management circuit 305 may perform an address mapping operation.

[0063] The reserved memory management circuit 305 may change the logical block address LBA received from the host device 100 into a physical address for storing the data DATA in the reserved memory 4033. The reserved memory management circuit 305 may use a reserved address mapping table RM_MT to map the logical block address LBA and the reserved memory address RM_ADDR from the host device 100. The reserved memory management circuit 305 may include the reserved address mapping table RM_MT including mapping information between the reserved memory address RM_ADDR into which the data DATA is written and the logical block address LBA.

[0064] In some example embodiments, the reserved memory address RM_ADDR may be set according to the size of the reserved memory 4033 set by the host device 100. The reserved memory management circuit 305 may generate a reserved address mapping table RM_MT based on the size of the reserved memory 4033.

[0065] The processor 307 may control the overall operation of the storage controller 300. The processor 307 may control the storage controller 300 by executing firmware loaded on the FTL 303. In some example embodiments, the processor 307 may include a central processing unit (CPU), a controller, or an application specific integrated circuit (ASIC), but example embodiments are not limited thereto.

[0066] The processor 307 may execute various firmware or software executed on the storage controller 300. The processor 307 may use the buffer memory 309 as an operating memory of the processor 307. In some example embodiments, the processor 307 may use the non-volatile memory 400 as an operating memory of the processor 307. For example, the processor 307 may control data read operations from the non-volatile memory 400 and data write operations to the non-volatile memory 400 by executing firmware.

[0067] In some example embodiments, the processor 307 may determine processing of the request signal REQ received from the host device 100 based on the match signal SIG_MATCH.

[0068] In some example embodiments, when the processor 307 receives a match signal SIG_MATCH indicating that write is possible from the partition management circuit 301, the processor 307 may write the data DATA into the user memory 4031. For example, the processor 307 may refer to the user address mapping table UM_MT of the FTL 303 and write the data DATA into the user memory address UM_ADDR corresponding to the logical block address LBA.

[0069] In some example embodiments, when the processor 307 receives a match signal SIG_MATCH indicating that writing is not possible from the partition management circuit 301, the processor 307 may temporarily write the data DATA into the reserved memory 4033 as preliminary data P_DATA. For example, the processor 307 may refer to the reserved address mapping table RM_MT of the reserved memory management circuit 305 and write the data DATA into the reserved memory address RM_ADDR corresponding to the logical block address LBA.

[0070] In some example embodiments, the processor 307 may generate a failure signal indicating that the request signal REQ received from the host device 100 cannot be processed. The failure signal may include a logical block address LBA and a reason for the write failure. Here, the logical block address LBA may be the logical block address corresponding to the request signal REQ that cannot be processed. In some example embodiments, the reason for the write failure may include a write pointer mismatch, insufficient storage space, etc., but example embodiments are not limited thereto. The processor 307 may transmit, provide, or send the failure signal to the host device 100.

[0071] The host device 100 may generate a synchronization command based on the failure signal. In some example embodiments, the synchronization command may be a signal instructing the storage device 200 to move and store the preliminary data P_DATA in the user memory 4031. In some example embodiments, the synchronization command may be a signal to change the position of the target write pointer to the position of the current write pointer in the target partition. The synchronization command may include a logical block address (LBA), etc., but example embodiments are not limited thereto. For example, in some example embodiments, the synchronization command may also include a task tag, an IID, an expected data transfer length, etc.

[0072] The host device 100 may transmit, provide, or send a synchronization command to the storage device 200. The processor 307 may read the preliminary data P_DATA in response to receiving the synchronization command from the host device 100 and write the read data to the user memory 4031. For example, the processor 307 may read the preliminary data P_DATA stored in the reserved memory address RM_ADDR corresponding to the logical block address LBA based on the reserved address mapping table RM_MT. Thereafter, in some example embodiments, the processor 307 may write the read preliminary data P_DATA to the user memory 4031.

[0073] For example, the storage device 200 may receive a request signal including a write command for writing first data to a first logical block address. Hereinafter, the request signal including the write command is referred to as a write request. In some example embodiments, the processor 307 may determine that writing the first data has failed based on a match signal SIG_MATCH received from the partition management circuit 301, and write the first data to the reserved memory 4033. For example, the processor 307 may write the first data to the reserved memory 4033 based on the reserved address mapping table RM_MT of the reserved memory management circuit 305. The processor 307 may generate a fail signal including the first logical block address and transmit, provide, or send the fail signal to the host device 100.

[0074] In some example embodiments, if the failure signal includes a cause of write failure indicating a write pointer mismatch, the synchronization command may include a logical block address LBA. For example, the host device 100 may generate a synchronization command including the first logical block address in response to receiving the failure signal. The host device 100 may transmit, provide, or send the synchronization command to the storage device 200. The processor 307 may read the first data in response to receiving the synchronization command. For example, the processor 307 may read the first data stored at a first reserved memory address corresponding to the first logical block address based on the reserved address mapping table RM_MT. Thereafter, the processor 307 may write the first data to the location of the current write pointer of the target partition indicated by the first logical block address.

[0075] In some example embodiments, if the failure signal includes a reason for the write failure indicating insufficient storage space, the synchronization command may include a new logical block address LBA. For example, the host device 100 may generate a synchronization command including the new second logical block address. The host device 100 may transmit, provide, or send the synchronization command to the storage device 200. In some example embodiments, the partition management circuit 301 may derive or optionally determine a partition address indicating a new target partition based on the new second logical block address and the new target write pointer.

[0076] The processor 307 may read the first data in response to receiving the synchronization command. For example, the processor 307 may read the first data stored in the first reserved memory address corresponding to the first logical block address based on the reserved address mapping table RM_MT. In some example embodiments, the processor 307 determines whether the first data can be written to the new target partition indicated by the second logical block address, and if so, the processor 307 may write the first data to the location of the current write pointer in the new target partition. Referring again to Figure 2 The buffer memory 309 may store commands and data executed and processed by the memory controller 300. The buffer memory 309 may temporarily store data stored in the nonvolatile memory 400, or may temporarily store data to be stored in the nonvolatile memory 400.

[0077] The buffer memory 309 may be implemented as a volatile memory such as a dynamic random access memory (DRAM), a static RAM (SRAM), etc. However, example embodiments are not limited thereto, and in some example embodiments, the buffer memory 309 may be implemented by various types of non-volatile memories including resistive non-volatile memories such as magnetic RAM (MRAM), phase change RAM (PRAM), or resistive RAM (ReRAM), etc., flash memory, nano-floating gate memory (NFGM), polymer random access memory (PoRAM), or ferroelectric random access memory (FRAM), etc.

[0078] In some example embodiments, the buffer memory 309 may store code data required for initial startup of the storage device 200. The buffer memory 309 may buffer logical block addresses LBA, request signals REQ, data DATA, commands, etc. received from the host 100, but example embodiments are not limited thereto. The signals buffered in the buffer memory 309 may be transmitted, provided, or sent to the nonvolatile memory 400 via the memory interface 313 and used, for example, by the nonvolatile memory 400. For example, the data buffered in the buffer memory 309 may be written to the nonvolatile memory 400.

[0079] Although the buffer memory 309 is illustrated as being provided or located inside the memory controller 300 , example embodiments of the inventive concepts are not limited thereto, and in some example embodiments, the buffer memory 309 may be provided or located outside the memory controller 300 .

[0080] The memory interface 313 may provide signal transmission and reception of the nonvolatile memory 400. For example, the memory interface 313 may transmit, provide, or send command and control signals to the nonvolatile memory 400 together with data to be written to the nonvolatile memory 400. For example, the memory interface 313 may also receive data read from the nonvolatile memory 400. According to some example embodiments, the memory interface 313 may be implemented to comply with a standard protocol such as Toggle or ONFI.

[0081] Figure 4 is a block diagram illustrating an example of a nonvolatile memory according to some example embodiments. Figure 5 Memory cell arrays according to some example embodiments are shown.

[0082] Reference Figure 4 , the nonvolatile memory 400 includes a control logic 401 , a memory cell array 403 , an address decoder 405 , a voltage generator 407 , a page buffer circuit 409 , and a data input / output circuit 411 .

[0083] The control logic 401 can be Figure 2 The memory controller 300 receives a command CMD and an address ADDR and may control an erase operation, a write operation, and a read operation of the nonvolatile memory 400 based on the command CMD and the address ADDR.

[0084] For example, the control logic 401 may generate a control signal CTRL_vol for the control voltage generator 407 and a control signal for controlling the page buffer circuit 409 based on the command CMD, and may generate a row address X_ADDR and a column address Y_ADDR based on ADDR. The control logic 401 may provide the row address X_ADDR to the address decoder 405 and the column address Y_ADDR to the page buffer circuit 409.

[0085] The memory cell array 403 is connected to the address decoder 405 via a plurality of string select lines SSL, a plurality of word lines WL, and a plurality of ground select lines GSL. In some example embodiments, the memory cell array 403 is connected to the page buffer circuit 409 via a plurality of bit lines BL. The memory cell array 403 may include a plurality of memory cells connected to the plurality of word lines WL and the plurality of bit lines BL. In some example embodiments, the memory cell array 403 may be formed in a two-dimensional (2D) array structure or a three-dimensional (3D) vertical array structure.

[0086] The memory cell array 403 may include a user memory 4031 and a reserve memory 4033 .

[0087] Reference Figure 5In some example embodiments, the user memory 4031 may include a first partition Z1 to an Nth partition ZN. N may be any natural number. A logical area may include an address recognizable by the host device 100. For example, each of the plurality of partitions Z1 to ZN may include a corresponding partition address. A partition ZN may include a plurality of logical block addresses LBA. In some example embodiments, a plurality of blocks having adjacent addresses ADDR may be included in a partition ZN. The first partition Z1 to the Nth partition ZN may be independent of each other. According to some example embodiments, a physical area may include the location or address of a memory block in the non-volatile memory 400. The logical area and the physical area may have a mapping relationship.

[0088] In some example embodiments, for example, Figure 5 As shown in , the storage space of the first partition Z1 may correspond to the 11th logical block address LBA11 to the 1mth logical block address LBA1m. The storage space of the second partition Z2 may correspond to the 21st logical block address LBA21 to the 2mth logical block address LBA2m. The storage space of the Nth partition ZN may correspond to the n1th logical block address LBAn1 to the nmth logical block address LBAnm. Although each of the 1st partition Z1 to the Nth partition ZN is shown as corresponding to m logical block addresses, example embodiments of the present inventive concept are not limited thereto, and in some example embodiments, each of the 1st partition Z1 to the Nth partition ZN may correspond to any number of logical block addresses.

[0089] The memory controller 300 may manage data to be logically and physically sequentially stored in the user memory 4031 corresponding to a write request received from the host device 100. For example, the memory controller 300 may support sequential writing.

[0090] The memory controller 300 may use a write pointer to sequentially store data in the user memory 4031. The write pointer may include information about a location within the memory device 200 where the data is to be written. Figure 5 In some example embodiments, the first partition Z1 may include a first write pointer WP11 indicating a logical block address LBA12. The second partition Z2 may include a second write pointer WP22 indicating a logical block address LBA23. The Nth partition ZN may include an Nth write pointer WPN1 indicating a logical block address LBAn2.

[0091] According to some example embodiments, the logical block addresses may each correspond to sequential sub-blocks or sequential programming units (e.g., units for performing programming on memory cells) within a block, while sequentially maintaining the logical block addresses. The correspondence between the logical block addresses and the memory blocks may be modified and implemented in various different ways by a person of ordinary skill in the art to which the present inventive concept pertains.

[0092] In some example embodiments, a memory block may be a unit for executing an operation request. The user memory 4031 may receive a write request or a read request from the memory controller 300. For example, a write request may include a write command CMD, an address ADDR, and data DATA. For example, a read request may include a read command CMD and an address ADDR. The user memory 4031 may perform a task corresponding to the operation request. For example, when receiving a write request, the user memory 4031 may write the received data DATA to the block corresponding to the address ADDR. For example, when receiving a read request, the user memory 4031 may read data stored in the memory block corresponding to the address ADDR.

[0093] In some example embodiments, the user memory 4031 may be a triple-level cell (TLC) area.

[0094] The reserved memory 4033 may include a plurality of logical block addresses LBAk1 to LBAk1. Figure 5 As shown in , the reserved memory 4033 may correspond to L logical block addresses. In some example embodiments, L may be a multiple of m.

[0095] In some example embodiments, the retention memory 4033 may be a single-level cell (SLC) area.

[0096] Refer again Figure 4 In some example embodiments, the address decoder 405 may be connected to the memory cell array 403 through a plurality of string selection lines SSL, a plurality of word lines WL, and a plurality of ground selection lines GSL.

[0097] The voltage generator 407 may generate a voltage VS required for the operation of the nonvolatile memory 400 based on a power supply voltage and a control signal CTRL_vol. For example, the voltage generator 407 may generate the voltage signal VS for the operation of the nonvolatile memory 400 based on the power supply voltage and the control signal CTRL_vol. The voltage VS may be applied to a plurality of string select lines SSL, a plurality of word lines WL, and a plurality of ground select lines GSL via the address decoder 405. In some example embodiments, the voltage generator 407 may generate an erase voltage required for an erase operation based on the power supply voltage and the control signal CTRL_vol. The erase voltage VERS may be applied directly to the memory cell array 403 or may be applied via the bit lines BL. For example, in some example embodiments, the voltage generator 407 may generate an erase voltage signal for an erase operation and transmit, send, or provide the erase voltage signal directly to the memory cell array 403. In some example embodiments, the voltage generator 407 may generate the erase voltage signal and transmit, send, or provide the erase voltage signal to the memory cell array 403 via the bit lines BL.

[0098] The page buffer circuit 409 may be connected to the memory cell array 403 through a plurality of bit lines BL. The page buffer circuit 409 may include a plurality of page buffers. In some example embodiments, one bit line BL may be connected to one page buffer. In some example embodiments, two or more bit lines BL may be connected to one page buffer.

[0099] The page buffer circuit 409 may store write data DATA to be written to the memory cell array 403 or read data DATA detected from the memory cell array 403. For example, the page buffer circuit 409 may operate as a write driver or a sense amplifier according to an operation mode of the nonvolatile memory 400.

[0100] The data input / output circuit 411 may be connected to the page buffer circuit 409 through the data line DL. The data input / output circuit 411 may provide, transfer, or send write data DATA to the memory cell array 403 through the page buffer circuit 409, or provide, transfer, or send read data DATA output from the memory cell array 403 to the outside (e.g., the outside) through the page buffer circuit 409.

[0101] Although, for example, in Figures 1 to 5 In the embodiment, the retention memory 4033 is described as being included in the nonvolatile memory 400 , but example embodiments of the inventive concept are not limited thereto, and in some example embodiments, the retention memory 4033 may also be included in the memory controller 300 .

[0102] Figure 6 The operating method of the storage system according to some example embodiments is shown. For example, Figure 6 Showing that according to Figure 1 An example embodiment in which a storage device fails to process a write request due to a mismatch in a write pointer.

[0103] First, the host device 100 transmits, provides, or sends a write request Write REQ to the storage device 200 ( S1001 ).

[0104] The write request Write REQ may include a write command, write data, and a logical block address. The write request Write REQ may include first data and a first logical block address.

[0105] The memory controller 300 determines whether the write request has failed ( S1003 ).

[0106] For example, in S1003, the storage controller 300 may obtain or optionally determine the partition address of the target partition to be written among multiple partitions of the user memory 4031 in the storage device 200 and the position of the target write pointer to be written in the corresponding partition based on the logical block address.

[0107] In some example embodiments, in S1003 , the storage controller 300 may detect or alternatively determine a position of a current write pointer of a target partition of a logical block address.

[0108] For example, the storage controller 300 may obtain or alternatively determine a target write pointer indicating the partition address and the first position of the first partition based on the first logical block address. In some example embodiments, the storage controller 300 may detect or alternatively determine that the position of the current write pointer of the first partition corresponding to the partition address is the second position. The storage controller 300 may compare the first position of the target write pointer with the second position of the current write pointer of the first partition.

[0109] In some example embodiments, if the first location and the second location are the same, the storage controller 300 may determine that the write request is successful ("No" in S1003). In some example embodiments, if the first location and the second location are different, the storage controller 300 may determine that the write request has failed ("Yes" in S1003).

[0110] For example, if the memory controller 300 determines that the write request is successful (No in S1003 ), the memory controller 300 transfers, provides, or sends a write command to the user memory 4031 ( S1021 ).

[0111] For example, the memory controller 300 may write data to a location corresponding to a logical block address of the user memory 4031 .

[0112] For example, the memory controller 300 may write the first data into a location corresponding to the first logical address of the user memory 4031 .

[0113] Thereafter, the memory controller 300 transmits, provides, or sends a write completion response to the host device 100 ( S1025 ).

[0114] In some example embodiments, if the memory controller 300 determines that the write request has failed (“Yes” in S1003 ), the memory controller 300 transfers, provides, or sends a write command to the reserved memory 4033 ( S1005 ).

[0115] For example, the storage controller 300 may determine the reserved memory address corresponding to the logical block address in the write request based on a reserved address mapping table including mapping information between the logical block address and the reserved memory address. The storage controller 300 may transmit, provide, or send the write command, write data, and the reserved memory address to the reserved memory 4033.

[0116] For example, the memory controller 300 may determine a first reserved memory address corresponding to the first logical block address, and control the reserved memory 4033 to write the first data into the first reserved memory address of the reserved memory 4033 .

[0117] Data is written into the reserve memory 4033 ( S1007 ).

[0118] For example, in response to receiving a write command from the memory controller 300 , the reserved memory 4033 may store the first data received from the memory controller 300 in a location corresponding to the first reserved memory address as preliminary data.

[0119] The memory controller 300 transmits, provides, or sends a fail signal (eg, a write fail response) to the host device 100 ( S1009 ).

[0120] The failure signal may include a logical block address and a reason for the write failure. For example, the failure signal may include a reason for the write failure due to a mismatch between a first logical block address and a write pointer corresponding to a first reserved memory address for writing preliminary data.

[0121] The host device 100 generates a synchronization command in response to receiving the write failure response ( S1011 ).

[0122] For example, the host device 100 may generate a synchronization command based on the failure signal. For example, upon receiving a failure signal indicating a write pointer mismatch, the host device 100 may generate a synchronization command including the received logical block address. For example, the synchronization command may also include a task tag, an IID, an expected data transfer length, etc., but example embodiments are not limited thereto.

[0123] The host device 100 transfers, provides, or sends a synchronization command to the storage device 200 ( S1013 ).

[0124] The memory controller 300 transfers, provides, or sends the read command to the reserved memory 4033 ( S1015 ).

[0125] The memory controller 300 may read preliminary data written in the reserved memory address corresponding to the logical block address in the synchronization command based on the reserved address mapping table.

[0126] For example, the memory controller may read first data stored in a first reserved memory address corresponding to a first logical block address.

[0127] The reserve memory 4033 reads data corresponding to the read command ( S1017 ).

[0128] The reserve memory 4033 transfers, provides, or sends the read data to the memory controller 300 ( S1019 ).

[0129] The memory controller 300 transfers, provides, or sends a rewrite command to the user memory 4031 ( S1021 ).

[0130] For example, the storage controller 300 may obtain the position of the current write pointer of the target partition corresponding to the logical block address. The storage controller 300 may write the read data according to the current write pointer position of the target partition in the user memory 4031.

[0131] For example, the memory controller 300 may rewrite the first data to the second location of the current write pointer of the first partition corresponding to the first logical block address.

[0132] Thereafter, the memory controller 300 transmits, provides, or sends a write completion response to the host device 100 ( S1025 ).

[0133] Figure 7 An operating method of a storage system according to some example embodiments is illustrated.

[0134] First, the storage device 200 receives a write request ( S2001 ).

[0135] A write request may include a write command, write data, and a logical block address.

[0136] The storage device 200 determines whether the write request has failed ( S2003 ).

[0137] For example, in S2003 , the storage device 200 may compare a first position of a write pointer of a logical block address in the write request and a second position of currently written data in a target partition corresponding to the logical block address.

[0138] In some example embodiments, if it is determined that the write request is successful (No in S2003 ), the storage device 200 may perform operations of storing the received data in the user memory 4031 and transmitting, providing, or sending a write completion response ( S2013 ).

[0139] In some example embodiments, if it is determined that the write request has failed (“Yes” in S2003 ), the storage device 200 stores the received data in the reserved memory 4033 ( S2005 ).

[0140] The storage device 200 transmits, provides, or sends a fail signal to the host device 100 ( S2007 ).

[0141] The fail signal may include a logical block address and a reason for the write failure. The host device 100 may generate a synchronization command based on the fail signal.

[0142] The storage device 200 receives the synchronization command ( S2009 ).

[0143] The synchronization command may include a logical block address. The storage device 200 may read the preliminary data written in the reservation memory 4033 based on the synchronization command.

[0144] The storage device 200 rewrites the data stored in the reserve memory 4033 to the user memory 4031 ( S2011 ).

[0145] The storage device 200 may rewrite the read data to the user memory 4031 .

[0146] The storage device 200 transmits, provides, or sends a write completion response ( S2013 ).

[0147] Figure 8 The operating method of the storage system according to some example embodiments is shown. For example, Figure 8 An example embodiment is shown in which a write failure occurs due to insufficient storage space in the user memory 4031 within the storage device 200 .

[0148] First, the host device 100 transmits, provides, or sends a write request to the storage device 200 ( S3001 ).

[0149] The write request may include a write command, write data, and a logical block address. The write request may include first data and a first logical block address.

[0150] The memory controller 300 determines whether the write request has failed ( S3003 ).

[0151] For example, the storage controller 300 may obtain or alternatively determine, based on the logical block address, a partition address indicating a target partition to be written to among multiple partitions of the user memory 4031 in the storage device 200 and a position of a target write pointer to be written to the corresponding partition. In some example embodiments, the storage controller 300 may detect the position of a current write pointer of the target partition of the logical block address.

[0152] Thereafter, in some example embodiments, the storage controller 300 may compare the size of the data received from the host device 100 with the size of the remaining storage space in the target partition.

[0153] For example, the storage controller 300 may obtain or optionally determine the location of the target partition and the target write pointer based on the logical block address received from the host device 100. The storage controller 300 may determine whether the location of the current write pointer and the location of the target write pointer of the target partition are the same. In some example embodiments, if the locations of the current write pointer and the target write pointer are the same, the storage controller 300 may compare the size of the data and the size of the remaining storage space in the target partition. In some example embodiments, if the size of the data is greater than the size of the remaining storage space, the storage controller 300 may determine that the write request has failed ("Yes" in S3003).

[0154] For example, the storage controller 300 may determine whether the first position of the first partition is the same as the position of the current write pointer of the first partition. If the storage controller 300 determines that the first position and the position of the current write pointer are the same, the storage controller 300 may compare the size of the first data with the size of the remaining storage space in the first partition.

[0155] For example, if the size of the first data is less than or equal to the size of the remaining storage space in the first partition, the storage controller 300 may determine that the write request is successful ("No" in S3003). In some example embodiments, if the size of the first data is greater than the size of the remaining storage space in the first partition, the storage controller 300 may determine that the write request has failed ("Yes" in S3003).

[0156] If the memory controller 300 determines that the write request is successful (No in S3003 ), the memory controller 300 transfers, provides, or sends a write command to the user memory 4031 ( S3023 ).

[0157] For example, the memory controller 300 may write the first data into a location corresponding to the first logical address of the user memory 4031 ( S3025 ).

[0158] Thereafter, the memory controller 300 transmits, provides, or sends a write completion response to the host device 100 ( S3027 ).

[0159] In some example embodiments, if the memory controller 300 determines that the write request has failed (“Yes” in S3003 ), the memory controller 300 transfers, provides, or sends a write command to the reserved memory 4033 ( S3005 ).

[0160] The memory controller 300 may determine the reserved memory address corresponding to the logical block address in the write request based on the reserved address mapping table including mapping information between the logical block address and the reserved memory address. The memory controller 300 may transmit, provide, or send the write command, write data, and the reserved memory address to the reserved memory 4033 (S3005).

[0161] For example, the memory controller 300 may determine that the first reserved memory address corresponds to the first logical block address, and control the reserved memory 4033 to write the first data into the first reserved memory address of the reserved memory 4033 ( S3007 ).

[0162] Data is written into the reserve memory 4033 ( S3007 ).

[0163] The memory controller 300 transmits, provides, or sends a failure signal indicating a write failure response to the host device 100 ( S3009 ).

[0164] The failure signal may include a logical block address corresponding to the preliminary data and a reason for the write failure. For example, the failure signal may include a first logical block address corresponding to a first reserved memory address for writing the preliminary data and a reason for the write failure due to insufficient storage space.

[0165] The host device 100 generates a synchronization command ( S3011 ).

[0166] For example, the host device 100 may generate a synchronization command based on the failure signal. In some example embodiments, upon receiving the failure signal indicating insufficient storage space, the host device 100 may generate a synchronization command including a new logical block address (S3011). The new logical block address may indicate a target partition different from the target partition of the logical block address transmitted, sent, or provided to the storage device 200 in operation S3001. For example, the host device 100 may generate a synchronization command (S3011) including a logical block address different from the logical block address of the previously transmitted, provided, or sent write request (S3001).

[0167] For example, based on the failure signal, the host device 100 may generate a second logical block address including a partition address indicating a second partition different from the first partition and a corresponding write pointer. The host device 100 may generate a synchronization command including the second logical block address (S3011). For example, the synchronization command may also include a task tag, an IID, an expected data transfer length, etc.

[0168] The host device 100 transfers, provides, or sends the generated synchronization command to the storage device 200 ( S3013 ).

[0169] The memory controller 300 determines whether the write request has failed ( S3015 ).

[0170] The storage controller 300 may obtain or optionally determine the location of the new target partition and the new target write pointer based on the new logical block address of the synchronization command. The storage controller 300 may determine whether the location of the current write pointer of the new target partition and the location of the new target write pointer are the same. In some example embodiments, if the locations of the current write pointer and the new target write pointer are the same, the storage controller 300 may compare the size of the data DQ with the size of the remaining storage space of the new target partition. In some example embodiments, if the size of the data DQ is greater than the size of the remaining storage space, the storage controller 300 may determine that the write request has failed ("Yes" in S3015).

[0171] In some example embodiments, if the memory controller 300 determines that the write request is successful (No in S3015 ), the memory controller 300 transfers, provides, or sends a read command to the reserved memory 4033 ( S3017 ).

[0172] In some example embodiments, if the memory controller 300 determines that the write request has failed (“Yes” in S3015 ), operation S3005 may be performed again.

[0173] The reserve memory 4033 reads data corresponding to the read command ( S3019 ).

[0174] The reserved memory 4033 transfers, provides, or sends the read data to the memory controller 300 ( S3021 ).

[0175] The memory controller 300 transfers, provides, or sends a rewrite command to the user memory 4031 ( S3023 ).

[0176] Thereafter, the memory controller 300 transmits, provides, or sends a write completion response to the host device 100 ( S3027 ).

[0177] Figure 9 An operating method of a storage system according to some example embodiments is illustrated.

[0178] First, the storage device 200 receives a write request ( S4001 ).

[0179] A write request may include a write command, write data, and a logical block address.

[0180] The storage device 200 determines whether the write request has failed ( S4003 ).

[0181] For example, the storage device 200 may compare a first position of a write pointer of a logical block address in a write request with a second position of currently written data in a target partition corresponding to the logical block address. In some example embodiments, if the first position and the second position are the same, the storage device 200 may compare the size of the data DQ received from the host device 100 with the size of the remaining storage space in the target partition.

[0182] In some example embodiments, if it is determined that the write request is successful (No in S4003 ), the storage device 200 stores the received data in the user memory 4031 and transmits, provides, or sends a write completion response ( S4027 ).

[0183] In some example embodiments, if it is determined that the write request has failed (“Yes” in S4003 ), the storage device 200 stores the received data in the reserved memory 4033 ( S4005 ).

[0184] The storage device 200 transmits, provides, or sends a fail signal to the host device 100 ( S4009 ).

[0185] The fail signal may include a logical block address and a reason for the write failure. The host device 100 may generate a synchronization command based on the fail signal.

[0186] The storage device 200 receives the synchronization command ( S4013 ).

[0187] The host device 100 may generate a synchronization command including a new logical block address based on the fail signal. For example, if the host device 100 receives a fail signal indicating insufficient storage space, the host device 100 may generate a synchronization command including a new logical block address.

[0188] The storage device 200 determines whether the write request has failed ( S4015 ).

[0189] In some example embodiments, if it is determined that the write request has failed (“Yes” in S4015 ), the storage device 200 may perform operation S4009 again.

[0190] In some example embodiments, if it is determined that the write request is successful (No in S4015 ), the storage device 200 rewrites the data stored in the reserve memory 4033 to the user memory 4031 ( S4023 ).

[0191] The storage device 200 may rewrite the read data to the user memory 4031 ( S4023 ).

[0192] The storage device 200 transmits, provides, or sends a write completion response to the host 100 ( S4027 ).

[0193] Figure 10 A storage system according to some example embodiments is shown.

[0194] For example, Figure 10 Show reference Figures 1 to 9 The storage system described ( Figure 1 10) is a system compliant with the Universal Flash Storage (UFS) standard promulgated by the Joint Electron Device Engineering Council (JEDEC) according to some example embodiments.

[0195] Reference Figure 10 The UFS system 30 may include a UFS host device 1000 , a UFS device 1050 , and a UFS interface 500 .

[0196] The UFS host device 1000 and the UFS device 1050 may be interconnected through a UFS interface 500. In some example embodiments, the UFS host device 1000 may be implemented as part of an application processor, but example embodiments are not limited thereto.

[0197] The UFS host device 1000 may include a UFS host controller 1001 , an application 1003 , a UFS driver 1005 , a host memory 1007 , and a UFS interconnect (UIC) layer 1009 .

[0198] The UFS device 1050 may include a UFS device controller 1051 , a nonvolatile memory device 1053 , a storage interface 1055 , a device memory 1057 , a UIC layer 1059 , and a regulator 1069 .

[0199] The nonvolatile memory 1053 may include a plurality of storage units 1061 and a retention memory 1063 .

[0200] The plurality of memory cells 1061 may include V-NAND flash memory in a 2D structure or a 3D structure, but example embodiments of the inventive concept are not limited thereto, and, in some example embodiments, each of the plurality of memory cells 1061 may also include other types of nonvolatile memories (such as PRAM and / or RRAM).

[0201] In some example embodiments, the plurality of storage units 1061 may be divided into a plurality of partitions to enforce sequential writes. Random writes may be prohibited within the plurality of storage units 1061. A write pointer may indicate the location where the next data will be written in each partition. As data is written to each partition, the corresponding write pointer may be updated.

[0202] The reserve memory 1063 may store preliminary data to be stored in the plurality of storage units 1061 .

[0203] The UFS device controller 1051 and the nonvolatile memory device 1053 may be interconnected through a storage interface 1055. The storage interface 1055 may be implemented to comply with a standard protocol such as Toggle or ONFI, but example embodiments are not limited thereto.

[0204] The application 1003 of the UFS host device 1000 may be a program that communicates with the UFS device 1050 to use functions of the UFS device 1050. The application 1003 may transmit, provide, or send an input-output request (IOR) to the UFS driver 1005 of the host device 1000 for input / output to the UFS device 1050. The input / output request may refer to a data read request, a write request, and / or an erase request, but example embodiments of the present inventive concept are not limited thereto.

[0205] The UFS driver 1005 can manage the UFS host controller 1001 through the UFS-HCI (Host Controller Interface). The UFS driver 1005 can convert input / output requests generated by the application 1003 into UFS commands defined by the UFS standard and transmit, provide, or send the converted UFS commands to the UFS host controller 1001. One input / output request can be converted into multiple UFS commands. UFS commands can essentially be commands defined by the SCSI (Small Computer System Interface) standard, but example embodiments are not limited thereto and, in some example embodiments, may be commands exclusive to the UFS standard.

[0206] The UFS host controller 1001 can transmit, provide, or send the UFS command converted by the UFS driver 1005 to the UIC layer 1059 of the UFS device 1050 through the UIC layer 1009 of the UFS host device 1000 and the UFS interface 500. For example, the UFS host register 111 of the UFS host controller 1001 can be used as a command queue (CQ). The UIC layer 1009 on the UFS host device 1000 side may include MIPI M-PHY and MIPI UniPro, and the UIC layer 1059 on the UFS device 1050 side may also include MIPI M-PHY and MIPI UniPro.

[0207] The UFS interface 500 may include a line for transmitting, providing, or sending a reference clock REF_CLK, a line for transmitting, providing, or sending a hardware reset signal RESET_n to the UFS device 1050 , a pair of lines for transmitting, providing, or sending a pair of differential input signals DIN_T and DIN_C, and a pair of lines for transmitting, providing, or sending a pair of differential output signals DOUT_T and DOUT_C.

[0208] The UFS device 1050 may generate clocks of various frequencies using a phase-locked loop (PLL) or the like based on a reference clock provided from the UFS host device 1000. In some example embodiments, the UFS host device 1000 may set a value of a data rate between the UFS host device 1000 and the UFS device 1050 based on the frequency value of the reference clock. For example, the value of the data rate may be determined based on the frequency value of the reference clock.

[0209] The UFS device controller 1051 may include a plurality of logic units 1052 , a partition management circuit 1065 , and a reserved memory management circuit 1067 .

[0210] The partition management circuit 1065 may manage a write pointer (WP) position of each of the plurality of partitions within the plurality of storage units 1061. In some example embodiments, the partition management circuit 1065 may compare the position of a target write pointer of a target partition in a command received from the UFS host device 1000 with the position of a current write pointer of the target partition within the plurality of storage units 1061. In some example embodiments, the partition management circuit 1065 may compare the size of data received from the UFS host device 1000 with the size of remaining storage space in the target partition.

[0211] The reserved memory management circuit 1067 may perform address mapping operations for the reserved memory 1063 .

[0212] The UFS interface 500 may support multiple channels, and each channel may be implemented as a differential pair. For example, the UFS interface 500 may include one or more receive channels and one or more transmit or send channels. Figure 10 In the embodiment, a pair of lines that transmit, provide or send a pair of differential input signals DIN_T and DIN_C may constitute a receiving channel, and a pair of lines that transmit, provide or send a pair of differential output signals DOUT_T and DOUT_C may constitute a transmitting or sending channel. Figure 10 One transmission or sending channel and one reception channel are shown, but example embodiments are not limited thereto and the number of transmission or sending channels and reception channels may be modified.

[0213] The receiving channel and the transmitting or sending channel can transmit, provide, or send data via a serial communication method, and communication between the UFS host device 1000 and the UFS device 1050 is possible in a full-duplex manner using a structure in which the receiving channel and the transmitting or sending channel are separated. For example, even while receiving data from the UFS host device 1000 via the same transmitting or sending channel, the UFS device 1050 can transmit, provide, or send data to the UFS host device 1000 via the transmitting or sending channel. In some example embodiments, control data (such as commands from the UFS host device 1000 to the UFS device 1050) and user data that the UFS host device 1000 wishes to store in or retrieve from the non-volatile storage device 1053 of the UFS device 1050 can be transmitted, provided, or sent via the same channel. Therefore, in addition to a pair of receiving channels and a pair of transmitting or sending channels, there may be no need or advantage in providing separate channels for data transmission between the UFS host device 1000 and the UFS device 1050.

[0214] Figure 11 A storage system according to some example embodiments is shown.

[0215] According to some example embodiments, Figure 11 The system 2000 may be a mobile system such as a mobile phone, a smart phone, a tablet personal computer (PC), a wearable device, a healthcare device, or an Internet of Things (IoT) device. However, Figure 11 Example embodiments of system 2000 are not necessarily limited to mobile systems and, in some example embodiments, may include a personal computer, a laptop computer, a server, a media player, or an automotive device (eg, a navigation device).

[0216] Reference Figure 11 , the system 2000 may include a main processor 2100, memories 2200a and 2200b, and storage devices 2300a and 2300b. In some example embodiments, the system 2000 may include at least one of an image capture device 2410, a user input device 2420, a sensor 2430, a communication device 2440, a display 2450, a speaker 2460, a power supply 2470, and a connection interface 2480.

[0217] The main processor 2100 may control the overall operation of the system 2000. In some example embodiments, the main processor 2100 may be implemented with a general-purpose processor, a dedicated processor, or an application processor, but example embodiments are not limited thereto.

[0218] The main processor 2100 may include one or more CPU cores 2110 and may also include a controller 2120 for controlling memories 2200a and 2200b and / or storage devices 2300a and 2300b. According to some example embodiments, the main processor 2100 may also include an accelerator 2130, which is a dedicated circuit for high-speed data operations (such as artificial intelligence (AI) data operations). The accelerator 2130 may include a graphics processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU), but example embodiments are not limited thereto, and in some example embodiments, the accelerator 2130 may also be implemented as a separate chip that is physically independent of other components of the main processor 2100.

[0219] The memories 2200a and 2200b may serve as main memory devices of the system 2000 and may include volatile memory (such as SRAM and / or DRAM). However, example embodiments are not limited thereto, and in some example embodiments, the memories 2200a and 2200b may also include non-volatile memory (such as flash memory, PRAM, and / or RRAM). The memories 2200a and 2200b may also be implemented in the same package as the main processor 2100.

[0220] Memory devices 2300a and 2300b can function as nonvolatile memory devices that store data regardless of whether power is supplied to them, and can have relatively large storage capacities compared to memories 2200a and 2200b. Memory devices 2300a and 2300b may include memory controllers 2310a and 2310b (STRG CTRL) and nonvolatile memories (NVMs) 2320a and 2320b that store data under the control of memory controllers 2310a and 2310b. Nonvolatile memories 2320a and 2320b may include 2-dimensional (2D) or 3-dimensional (3D) V-NAND (Vertical NAND) flash memory, or may include other types of nonvolatile memory, such as PRAM and / or RRAM.

[0221] The storage devices 2300a and 2300b may be included in the system 2000 while being physically separated from the main processor 2100, or may be implemented in the same package as the main processor 2100. In some example embodiments, the storage devices 2300a and 2300b may have the same shape as a solid-state device (SSD) or a memory card, so that the storage devices 2300a and 2300b can be combined through an interface (such as the connection interface 2480) to be attached to and detached from other components of the system 2000. The storage devices 2300a and 2300b may be configured as devices applying a standard convention (such as Universal Flash Storage (UFS), Embedded MultiMediaCard (eMMC), or Non-Volatile Memory Express (NVMe)), but example embodiments are not limited thereto.

[0222] The image capturing device 2410 may obtain a still image or a video and may be a camera, a camcorder, and / or a webcam, but example embodiments are not limited thereto.

[0223] The user input device 2420 may receive various types of data input from a user of the system 2000 and may include a touch pad, a keypad, a keyboard, a mouse, and / or a microphone, but example embodiments are not limited thereto.

[0224] The sensor 2430 may detect various types of physical quantities that may be obtained from an external entity of the system 2000 and may convert the detected physical quantities into electrical signals. The sensor 2430 may be a temperature sensor, a pressure sensor, a brightness sensor, a position sensor, an acceleration sensor, a biosensor, and / or a gyro sensor, but example embodiments are not limited thereto.

[0225] The communication device 2440 may transmit, provide, or send signals to and receive signals from other devices existing outside the system 2000 according to various communication protocols. The communication device 2440 may include an antenna, a transceiver, and / or a modem.

[0226] Display 2450 and speaker 2460 may be used as output devices for outputting visual and auditory information to a user of system 2000 .

[0227] The power supply device 2470 may appropriately convert power supplied from a battery (not shown) built in the system 2000 and / or an external power source, and may supply the power to each component of the system 2000 .

[0228] The connection interface 2480 may provide a connection between the system 2000 and an external device that is connected to the system 2000 and can exchange data with the system 2000. The connection interface 2480 may be implemented through various interface methods such as Advanced Technology Attachment (ATA), Serial ATA (SATA), external SATA (e-SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI Express (PCIe), NVM Express (NVMe), IEEE 1394, Universal Serial Bus (USB), Secure Digital (SD) card, MultiMedia Card (MMC), Embedded MultiMedia Card (eMMC), Universal Flash Storage (UFS), Embedded Universal Flash Storage (eUFS), Compact Flash (CF) card interface, etc., but example embodiments are not limited thereto.

[0229] Storage devices 2300a and 2300b may correspond to reference Figures 1 to 9 Description Figure 1 The storage device 200 and the reference Figure 10 The UFS device 1050 described in the FIG. 2 is a main processor 2100. Figure 1 The host device 100 described or referenced Figure 10 A UFS host 1000 is described.

[0230] The memory devices 2300a and 2300b can sequentially write the request signals received from the main processor 2100 in the memory devices 2300a and 2300b into the nonvolatile memories 2320a and 2320b. The memory devices 2300a and 2300b can ensure sequential writing of the nonvolatile memories 2320a and 2320b without allocating additional resources for storing data corresponding to the request signals.

[0231] Meanwhile, in a conventional storage device comprising a plurality of partitions that sequentially store data, when a write request comprising data is received from a host device and the storage device cannot write the received data due to a mismatch in a write pointer or insufficient storage space, the storage device invalidates the received data and transmits information about the current position of the write pointer to the host device. Because the received data is invalidated by the storage device, the host device must retransmit the data to be written to the storage device together with a write request including the updated position of the write pointer. In other words, conventionally, when the storage device fails to write the data that the host device wants to write, the host device must retransmit the data to the storage device multiple times. Therefore, in conventional storage devices, there is a high overhead ratio in the transmission / reception of signals between the host device and the storage device.

[0232] Meanwhile, according to some example embodiments of the present inventive concept, when a write request received from a host device cannot be written due to a write pointer mismatch or insufficient storage space, storage devices 2300a and 2300b may store the received data included in the write request in a separate reserved memory. Storage devices 2300a and 2300b may communicate, provide, or send the reason for the write failure (e.g., the reason why the received data cannot be processed) and the address corresponding to the received data that was not written to the host device. The host device may generate a synchronization command to control storage devices 2300a and 2300b to write the data stored in the reserved memory of storage devices 2300a and 2300b to the appropriate location based on the reason for the write failure.

[0233] For example, in some example embodiments, the host device may transmit, provide, or send a synchronization command to storage devices 2300a and 2300b. In response to receiving the synchronization command, storage devices 2300a and 2300b may read data stored in any memory (e.g., data stored in reserved memory) and rewrite the data to an appropriate location. Since the data is stored in any memory (e.g., reserved memory) of storage devices 2300a and 2300b, the host device may not need to transmit, provide, or send the data again to storage devices 2300a and 2300b. Therefore, in some example embodiments, the overhead of signals transmitted, provided, or sent and received between the host device and storage devices 2300a and 2300b may be reduced.

[0234] One or more of the elements disclosed above may include one or more processing circuits (such as hardware including logic circuits, a hardware / software combination (such as a processor executing software), or a combination thereof) or be implemented in one or more processing circuits. For example, the processing circuits may more specifically include, but are not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0235] Any or all elements described with reference to the accompanying drawings may communicate with any or all other elements described with reference to the accompanying drawings. For example, any element may communicate with any or all other elements in the drawings in a unidirectional and / or bidirectional and / or broadcast manner to transmit and / or exchange and / or receive information (such as, but not limited to, data and / or commands) via a bus (such as a wireless and / or wired bus) in a serial and / or parallel manner. The information may be encoded in various formats (such as analog and / or digital).

[0236] Although some example embodiments of the present inventive concept have been described in detail, it will be understood that the present inventive concept is not limited to the disclosed example embodiments, but on the contrary is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A storage device comprising: Non-volatile memory, including: a first memory including a plurality of partitions configured to sequentially store data based on a write pointer, the write pointer indicating a location where the data is to be written, and a second memory configured to store preliminary data to be written into the plurality of partitions; and Storage controller, configured as: receiving a plurality of operation requests, each of the plurality of operation requests including a logical block address, a write command, and write data, and If a position of a first logical block address corresponding to a first operation request among the plurality of operation requests does not match a write pointer, first write data corresponding to the first operation request is stored in the second memory as first preliminary data.

2. The storage device according to claim 1, wherein The storage controller includes a partition management circuit configured to determine a target partition to be written among the plurality of partitions and a target write pointer indicating a first location to be written in the target partition based on a logical block address, and The partition management circuit is configured to perform a first comparison operation to compare a first position of a target write pointer with a second position of a current write pointer of the target partition.

3. The storage device according to claim 2, wherein: The partition management circuit is configured to perform a second comparison operation to compare a first size of the first write data with a second size of a remaining storage space of the target partition. The storage device according to claim 3 , wherein: The partition management circuit is configured to generate a match signal indicating whether the first operation request can be processed based on results of the first comparison operation and the second comparison operation.

5. The storage device according to claim 4, wherein: The memory controller includes a processor configured to determine processing of the first operation request based on the match signal, a mapping table between the logical block address and the second memory address of the second memory, and a mapping table between the logical block address and the first memory address of the first memory. The storage device according to claim 5 , wherein: The processor is configured to write the first write data as first preliminary data to a second memory address corresponding to the first logical block address when the match signal indicates that the first operation request cannot be processed.

7. The storage device according to claim 6, wherein: The processor is configured to generate a failure signal indicating that the first operation request cannot be processed based on the first logical block address, a result of the first comparison operation, and a result of the second comparison operation. The storage device according to claim 7 , wherein: The memory controller is configured to receive a synchronization command generated based on the fail signal, read the first preliminary data stored in the second memory address, and write the first preliminary data to a location corresponding to a current write pointer of the target partition.

9. The storage device according to claim 1, wherein The second memory includes a single-level cell region, and the first memory includes a triple-level cell region.

10. A storage system comprising: a host device configured to send a plurality of operation requests, each of the plurality of operation requests including a logical block address, a write command, and write data; as well as A storage device comprising: a first memory including a plurality of partitions configured to sequentially store data, and The second memory is configured as: storing preliminary data to be written into the plurality of partitions, and Storage controller, configured as: Based on a determination that a first operation request among the plurality of operation requests cannot be processed, first write data corresponding to the first operation request is stored in a second memory as first preliminary data, and In response to receiving a synchronization command from the host device, first preliminary data is written to a location corresponding to a write pointer indicating a location in the first memory where data is to be written. The storage system according to claim 10 , wherein: The host device is configured to send a set feature command to set a size of the second memory, and the memory controller is configured to generate a reserved address mapping table including mapping information between logical block addresses and second memory addresses of the second memory based on the set feature command.

12. The storage system according to claim 10, wherein: The memory controller is configured to, in response to a determination that the first operation request cannot be processed, generate a fail signal indicating that the first operation request cannot be processed based on the first logical block address.

13. The storage system according to claim 12, wherein: The host device is configured to generate a synchronization command based on the fail signal to instruct the storage device to read the preliminary data stored in the second memory and store the preliminary data in the first memory.

14. The storage system according to claim 10, wherein: The storage controller is configured to determine a target partition to be written among the plurality of partitions and a target write pointer indicating a location to be written in a target area based on the logical block address.

15. The storage system according to claim 14, wherein: The storage controller is configured to determine that the first operation request cannot be processed if a first position of a target write pointer corresponding to the first operation request and a second position of a current write pointer of the target partition are different.

16. The storage system according to claim 15, wherein: The synchronization command includes a first logical block address, And the storage controller is configured to read the first preliminary data in response to receiving the synchronization command, and write the first preliminary data to a location corresponding to a current write pointer of the target partition.

17. The storage system according to claim 14, wherein: The storage controller is configured to determine that the first operation request cannot be processed if a first size of the first write data is greater than a second size of a remaining storage space of the target partition.

18. The storage system according to claim 17, wherein: The synchronization command includes a second logical block address different from the first logical block address, And the storage controller is configured to read the first preliminary data in response to receiving the synchronization command and write the first preliminary data to a location corresponding to a current write pointer of the target partition corresponding to the second logical block address.

19. A method for operating a storage system, comprising: receiving an operation request for writing write data to a location corresponding to a first logical block address in a plurality of partitions, the plurality of partitions being configured to sequentially store data based on a write pointer indicating a location where the data is to be written; determining a target partition to be written among the plurality of partitions and a target write pointer indicating a location to be written in the target area based on the first logical block address, and determining whether the operation request can be processed based on a position of a current write pointer of the target partition and a position of the target write pointer; If the operation request cannot be processed, storing the write data as preliminary data in the second memory; receiving a synchronization command including a first logical block address; as well as The preliminary data is read and written to a location corresponding to the current write pointer of the target partition.

20. The method for operating a storage system according to claim 19, wherein: The step of determining whether the operation request can be processed includes: if a first size of the written data is larger than a second size of the remaining storage space of the target partition among the plurality of partitions, determining that the operation request cannot be processed, The step of receiving a synchronization command includes: receiving a synchronization command including a second logical block address different from the first logical block address, And the step of writing preliminary data includes: writing the preliminary data to a position of a current write pointer of the target partition corresponding to the second logical block address.

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