Control unit and memory device including the same

Abstract

The invention discloses a control unit and a storage device including the same. According to the embodiment of the invention, the time and scheme for processing the command can be adjusted based on the address of the region in the memory for performing the operations such as data storage and the address of the command transmitted by the host device; therefore, the operation performance of the storage device including the memory is improved by improving the efficiency of command processing while the data storage state of the memory is maintained.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2024-0019388, filed on February 8, 2024, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate to a control unit and a storage device including the control unit. Background Art

[0004] The storage device may include at least one memory for storing data. The storage device may write data to the memory or read data from the memory in response to a command received from an external source.

[0005] The processing of commands may be delayed based on the operating state of the memory. As a result, the latency between receiving a command and processing it may increase. This increased latency can negatively impact the performance of the memory device. Summary of the Invention

[0006] An embodiment of the present disclosure provides a method for enhancing operation performance of a storage device by adjusting a timing and a method of processing a command received from an external device based on an operation state of a memory included in the storage device.

[0007] An embodiment of the present disclosure may provide a storage device, which includes: at least one memory; and a control unit that communicates between the at least one memory and a host device and controls the at least one memory, wherein the control unit includes: a memory controller that controls the operation of the at least one memory; a data saving operation manager that manages the data saving operation of the at least one memory; and a buffer manager that receives a command transmitted by the host device and stores the command in a buffer memory if the address of the command is included in the address area where the data saving operation is being performed, and provides the command to the memory controller if the address is not included in the address area.

[0008] An embodiment of the present disclosure may provide a storage device comprising: at least one memory; and a control unit that controls the at least one memory and, during a first period of time when a data saving operation is being performed on a first memory area of the at least one memory, controls an operation of writing data to a second memory area of the at least one memory or an operation of reading data written to the second memory area.

[0009] An embodiment of the present disclosure may provide a control unit comprising: a first interface for communicating with a host device; a second interface for communicating with a memory, controlling the operation of the memory and outputting information about a data saving operation of the memory; and a buffer manager for acquiring a command received through the first interface and, if an address according to the command is included in an address area in which a data saving operation is being performed, storing the command in a buffer memory, and providing the command to the second interface if the address is not included in the address area.

[0010] According to an embodiment of the present disclosure, the timing and method of processing commands are adjusted based on the operating state of the memory included in the storage device and the type of command received from the external device. This adjustment reduces the delay time associated with command processing and improves the operating performance of the storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a diagram showing a schematic configuration of a storage device according to an embodiment of the present disclosure;

[0012] Figure 2 is a diagram illustrating a schematic configuration of a control unit included in a storage device according to an embodiment of the present disclosure;

[0013] Figure 3 is a view showing a configuration of a control unit according to an embodiment of the present disclosure;

[0014] Figures 4 to 7 is a view illustrating an operating method of a storage device according to an embodiment of the present disclosure; and

[0015] Figures 8 to 10 is a view illustrating an operating method of a control unit according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0016] Examples or embodiments of the present disclosure are described below with reference to the accompanying drawings, in which specific examples or embodiments that can be implemented are shown by way of diagrams, and in the drawings, the same reference numerals and symbols may be used to represent the same or similar components even if they are shown in different drawings. In addition, in the following description of the examples or embodiments of the present disclosure, when it is determined that a detailed description of well-known functions and components incorporated herein may make the subject matter in certain embodiments of the present disclosure less clear, the description will be omitted. Terms such as "including," "having," "comprising," "consisting of," and "formed of" used herein are generally intended to allow for the addition of other components unless these terms are used with the term "only." As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0017] Terms such as "first," "second," "A," "B," "(A)," or "(B)" may be used herein to describe elements of the present disclosure. Each of these terms is not used to define the nature, order, sequence, or quantity of the elements, but is only used to distinguish the corresponding element from other elements.

[0018] When referring to a first element being “connected or coupled to” a second element or “contacting or overlapping” the second element, it should be understood that the first element may not only be “directly connected or coupled to” the second element or “directly contact or overlap” the second element, but also that a third element may be “interposed” between the first and second elements, or that the first and second elements may be “connected or coupled to” or “contact or overlap” each other via a fourth element. Here, the second element may be included in at least one of the two or more elements that are “connected or coupled to” or “contact or overlap” each other.

[0019] When time relative terms such as “after,” “subsequently,” “next,” “before,” etc. are used to describe a process or operation of an element or configuration, or a flow or step in an operation, process, or manufacturing method, unless these terms are used with the terms “directly” or “immediately,” these terms may be used to describe non-continuous or non-sequential processes or operations.

[0020] In addition, when referring to any dimension, relative size, etc., even if no relevant description is given, it should be considered that the numerical value or corresponding information (e.g., degree, range, etc.) of the element or feature includes the tolerance or error range that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.). In addition, the term "may" fully encompasses all meanings of the word "can".

[0021] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0022] Figure 1 is a diagram showing a schematic configuration of a storage device 100 according to an embodiment of the present disclosure;

[0023] Reference Figure 1 , the storage device 100 may include at least one memory 110. The storage device 100 may further include a control unit 120 that controls the operation of the memory 110.

[0024] The memory 110 may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, etc., but the embodiments of the present disclosure are not limited thereto. The memory 110 may include nonvolatile memory such as NAND flash memory, three-dimensional (3D) NAND flash memory, NOR flash memory, etc.

[0025] Furthermore, the memory 110 may be one of various types of memory, such as resistive RAM, phase change memory, magnetoresistive memory, ferroelectric memory, spin injection magnetization reversal memory, and the like. Furthermore, in some cases, the memory 110 may be a processing-in-memory (PIM) that includes arithmetic or data processing functions. In this disclosure, the memory 110 may also be referred to as a memory device.

[0026] The memory 110 may include a plurality of memory blocks. Each of the plurality of memory blocks may include a plurality of memory cells. The plurality of memory blocks may be divided into a plurality of memory banks, which are units controlled by the control unit 120.

[0027] The control unit 120 may receive a command from an external device and control the operation of the memory 110 based on the received command. In addition, the control unit 120 may control the operation of the memory 110 based on the command generated therein.

[0028] The control unit 120 may transmit a command or address for controlling the operation of the memory 110 to the memory 110. The control unit 120 may control, for example, an operation of writing data to the memory 110. The control unit 120 may control an operation of reading data from the memory 110. Data may be transmitted and received between the control unit 120 and the memory 110.

[0029] The control unit 120 may control a data saving operation (eg, a refresh operation or a patrol scrub operation) or an erase operation on data stored in the memory 110 according to the type of the memory 110 .

[0030] The control unit 120 may control the operation of the memory 110 based on a command received from the external host device 200 .

[0031] For example, the host device 200 may be a computer, an ultra-mobile PC (UMPC), a workstation, a personal digital assistant (PDA), a tablet computer, a mobile phone, a smartphone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a smart TV, a digital audio recorder, a digital audio player, a digital video recorder, a digital video player, a storage device constituting a data center, one of various electronic devices constituting a telematics network, a radio frequency identification (RFID) device, a mobile device capable of traveling under human control or autonomously (e.g., a vehicle, a robot, or a drone), etc. Alternatively, the host device 200 may be a virtual / augmented reality device that provides two-dimensional (2D) or three-dimensional (3D) virtual reality images or augmented reality images. The host device 200 may be any of various electronic devices that require a storage device 100 capable of storing data.

[0032] The host device 200 may include at least one operating system. The operating system may generally manage and control the functions and operations of the host device 200 and may control the interaction between the host device 200 and the storage device 100. Depending on the mobility of the host device 200, the operating system may be categorized as a general-purpose operating system or a mobile operating system.

[0033] The control unit 120 and the host device 200 may be independent devices. In some cases, the control unit 120 and the host device 200 may be integrated and implemented as a single device, or some components or functions of the control unit 120 may be implemented as included in the host device 200. Hereinafter, for ease of description, the control unit 120 and the host device 200 are described as independent devices.

[0034] The control unit 120 can communicate with the host device 200 and control the memory 110. The control unit 120 can adjust the timing and scheme for processing commands based on the operating state of the memory 110 and the type of command transmitted from the host device 200. Through the control of the control unit 120, the efficiency of the host device 200 in processing commands can be improved, and the operating performance of the storage device 100 can be prevented from being reduced due to the operating state of the memory 110.

[0035] Figure 2 is a view illustrating a schematic configuration of a control unit 120 included in the storage device 100 according to an embodiment of the present disclosure.

[0036] Reference Figure 2, the storage device 100 may include at least one memory 110 and a control unit 120 that controls the memory 110. The storage device 100 may include a plurality of memories 110. The control unit 120 may control the plurality of memories 110, and may include components for controlling each of the plurality of memories 110 and components for performing common functions.

[0037] The control unit 120 may include components for communicating with the host device 200. The control unit 120 may include components for communicating with and controlling the memory 110.

[0038] The control unit 120 may be implemented as a single chip or a package including multiple chips. When the control unit 120 is implemented by multiple chips, each of the multiple chips may be divided functionally or may be divided according to the memory 110 to be controlled.

[0039] The control unit 120 may include a host interface 121 and a memory interface 122 .

[0040] The host interface 121 facilitates communication between the control unit 120 and the host device 200. The host interface 121 may be a Compute Express Link (CXL) interface. The host device 200 may be configured as a CXL root port, and the storage device 100 may be configured as a CXL endpoint. Because the host device 200 communicates with the storage device 100 via the CXL interface, a low-latency, high-bandwidth access environment can be achieved within the communication architecture with the mass storage device 100.

[0041] Furthermore, in some cases, host interface 121 may be one of various interfaces other than a CXL interface.

[0042] For example, the host interface 121 may support at least one of various interface protocols such as a Universal Serial Bus (USB) protocol, a MultiMediaCard (MMC) protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI-Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer Interface (SCSI) protocol, an Enhanced MiniDisk Interface (ESDI) protocol, and an Integrated Drive Electronics (IDE) protocol, but the embodiments of the present disclosure are not limited thereto.

[0043] The memory interface 122 may facilitate communication with the memory 110. The memory interface 122 may include components for controlling or managing the operation of the memory 110. In some cases, the memory interface 122 refers to the physical layer responsible for communicating with the memory 110, and the components for controlling and managing the memory 110 may be implemented separately from the memory interface 122.

[0044] In the present disclosure, the host interface 121 may be referred to as a first interface, and the memory interface 122 may be referred to as a second interface.

[0045] The control unit 120 may further include a buffer manager 123 and a buffer memory 124 .

[0046] The buffer manager 123 may communicate with the host interface 121 and receive a command and / or data transmitted by the host device 200 through the host interface 121 .

[0047] The buffer manager 123 may transfer data to the host device 200 through the host interface 121. In some cases, the data may be transferred directly from the memory interface 122 to the host device 200 through the host interface 121, bypassing the buffer manager 123.

[0048] The buffer manager 123 may communicate with the memory interface 122 and obtain information about an operating state of the memory 110 .

[0049] The buffer manager 123 may control a timing and a method of processing a command transmitted by the host device 200 based on the command received through the host interface 121 and information on an operating state of the memory 110 received through the memory interface 122 .

[0050] When the buffer manager 123 directly processes a command based on the type of the command transmitted by the host device 200 and the operating state of the memory 110 , the buffer manager 123 may transmit the received command to the memory interface 122 .

[0051] The memory interface 122 may control the operation of the memory 110 based on a command transferred through the buffer manager 123 .

[0052] When the buffer manager 123 does not directly process a command transmitted by the host device 200, the buffer manager 123 may store the received command in the buffer memory 124. The buffer manager 123 may manage the commands stored in the buffer memory 124 and monitor the operating state of the memory 110.

[0053] When buffer manager 123 is ready to process a command stored in buffer memory 124 , buffer manager 123 may provide the command to memory interface 122 .

[0054] The memory interface 122 may receive a command from the buffer memory 124 and control the operation of the memory 110 based on the received command.

[0055] The timing and method of processing commands may be adjusted under the control of the buffer manager 123 , and the processing efficiency of commands may be improved according to the operating state of the memory 110 .

[0056] When a command transmitted from the host device 200 is stored in the buffer memory 124, the buffer manager 123 may transmit a response signal to the host device 200 through the host interface 121 to confirm that the command is stored in the buffer memory 124. Since the control circuit 120 manages command processing within the memory device 100 and transmits a response signal to the host device 200, a delay caused by data processing between the host device 200 and the memory device 100 may be reduced.

[0057] The buffer manager 123 may adjust the timing and method of processing commands transmitted by the host device 200 based on various operating states of the memory 110. For example, the buffer manager 123 may control the method of processing commands based on an operation of saving data stored in the memory 110.

[0058] In an embodiment, the control unit 120 may be implemented by one or more processors, memory devices, or a combination thereof. Specifically, some components of the control unit 120, such as the host interface 121, the memory interface 122, and the buffer manager 123, may use (multiple) processors to perform certain functions. However, the embodiment is not limited to this configuration.

[0059] Figure 3 is a view showing a configuration of the control unit 120 according to an embodiment of the present disclosure.

[0060] Reference Figure 3 , the storage device 100 may include a memory 110 and a control unit 120 . The control unit 120 may include a host interface 121 , a memory interface 122 , a buffer manager 123 , and a buffer memory 124 .

[0061] The buffer memory 124 and the buffer manager 123 may be separate or integrated into the buffer manager 123. The buffer memory 124 may be a cache memory or an SRAM, but is not limited thereto.

[0062] The memory interface 122 may include a memory controller 122 a and a data retention management manager (DRM) 122 b .

[0063] The control unit 120 may include a memory controller 122a and a data saving operation manager 122b to correspond to each memory 110 included in the storage device 100. The memory controller 122a and the data saving operation manager 122b may be implemented separately or integrated in some cases.

[0064] The memory controller 122 a may control operations of the memory 110 , including writing data to or reading data from the memory 110 .

[0065] In some cases, the memory controller 122 a may control an operation of saving data stored in the memory 110 or an operation of erasing data stored in the memory 110 .

[0066] The data saving operation manager 122b may manage an operation of saving data stored in the memory 110. The data saving operation may refer to an operation such as a refresh operation or a patrol scrubbing operation, which involves rewriting data stored in the memory 110.

[0067] An operation of rewriting data stored in at least a partial area of the memory 110 may be performed at predetermined intervals or times. The data saving operation manager 122b may manage the timing of data saving operations on the memory 110, affected areas, and related information.

[0068] Information related to the data saving operation managed by the data saving operation manager 122 b may be provided to the buffer manager 123 .

[0069] The buffer manager 123 may identify the operating state of the memory 110 based on the information received from the data saving operation manager 122b. The buffer manager 123 may control the timing and method of processing commands transmitted by the host device 200 based on the information about the progress of the data saving operation on the memory 110.

[0070] The data stored in the memory 110 may be saved through the data saving operation, thereby ensuring minimization of delay due to command processing by the host device 200 .

[0071] Figures 4 to 7 is a diagram illustrating an operating method of the storage device 100 according to an embodiment of the present disclosure. Figures 4 to 7 An example in which a single memory 110 is included in the storage device 100 is shown, but embodiments of the present disclosure are also applicable to a case in which a plurality of memories 110 are included.

[0072] Reference Figure 4 , the memory 110 may include a plurality of memory regions MR1, MR2, ..., MRn. A memory region may refer to a memory block having a predetermined size. The size of a memory region may correspond to a unit for performing a data saving operation.

[0073] The memory 110 may perform a data saving operation at predetermined intervals or at a designated time.

[0074] Although the data saving operation is described as a refresh operation in this example, the data saving operation may include various operations performed to save data stored in the memory 110 .

[0075] Although this example illustrates a scheme in which the buffer manager 123 processes commands transmitted by the host device 200 during a data saving operation of the memory 110 , embodiments of the present disclosure may also be applicable to other operations of the memory 110 other than the data saving operation that require commands to be kept on standby.

[0076] A refresh operation may be performed on a first memory region MR1 among a plurality of memory regions MR1 , MR2 , . . . , MRn included in the memory 110 .

[0077] Refresh operations can be managed by a data storage operation manager 122b, which controls the timing and memory region of refresh operations. Memory controller 122a can control refresh operations of memory 110 based on refresh information provided by data storage operation manager 122b. Alternatively, memory 110 can perform refresh operations in response to signals transmitted by memory controller 122a.

[0078] Alternatively, the refresh operation may be managed by the memory controller 122a. In this case, the memory controller 122a may control the refresh operation and provide relevant information about the refresh operation to the data saving operation manager 122b.

[0079] When the refresh operation of the first memory region MR1 of the memory 110 starts, the data saving operation manager 122 b may transmit a start signal of the refresh operation to the buffer manager 123 , as indicated by ①.

[0080] The data saving operation manager 122 b may transmit a start signal and an end signal of the refresh operation to the buffer manager 123 .

[0081] The data saving operation manager 122 b may transmit a start signal of the refresh operation to the buffer manager 123 together with information about a memory area on which the refresh operation is being performed.

[0082] The information about the memory region where the refresh operation is being performed may include address information about the corresponding memory region.

[0083] Alternatively, the information about the memory area in which the refresh operation is being performed may include start address information of the corresponding memory area. The refresh operation may be performed in units of a predetermined memory area size.

[0084] Information about the size of the memory area where the refresh operation is performed may be transmitted together with the start address information to the buffer manager 123. Alternatively, information about the size of the memory area where the refresh operation is performed may be pre-stored in the buffer manager 123 without being transmitted by the data saving operation manager 122b.

[0085] When transmitting the end signal of the refresh operation to the buffer manager 123 , the data saving operation manager 122 b may or may not transmit address information about the memory area on which the refresh operation has been completed to the buffer manager 123 .

[0086] The buffer manager 123 may receive information about the refresh operation from the data saving operation manager 122 b .

[0087] The buffer manager 123 may receive a command transmitted by the host device 200 , as shown in ②.

[0088] The host interface 121 may transfer commands received from the host device 200 to the buffer manager 123. At least some of the commands received through the host interface 121 may be transferred to the memory interface 122 through the buffer manager 123, rather than being directly transmitted to the memory interface 122.

[0089] The host interface 121 may transmit a command transmitted by the host device 200 together with an address associated with the command to the buffer manager 123 .

[0090] The address associated with the command may be a logical address. The host interface 121 may include a decoder that converts the logical address transmitted by the host device 200 into a physical address of the memory 110 or an address managed by the memory controller 122a.

[0091] If the buffer manager 123 receives a command from the host interface 121 , the buffer manager 123 may compare an address associated with the command with the address of the memory region where the refresh operation is being performed, received from the data saving operation manager 122 b .

[0092] The buffer manager 123 may control a method of processing a command based on a comparison result between an address associated with the command and an address of a memory region where a refresh operation is being performed.

[0093] Reference Figure 5 , shows an example in which the address of the command received by the buffer manager 123 corresponds to the address of the first memory region MR1 on which the refresh operation is being performed.

[0094] If the address associated with the command transmitted by the host device 200 corresponds to the address of the first memory region MR1 , the buffer manager 123 may transmit the command to the buffer memory 124 , as shown in ③.

[0095] The buffer manager 123 may store the command and its corresponding address in the buffer memory 124. The buffer manager 123 may store data in the buffer memory 124 according to the type of the command.

[0096] For example, when the command transmitted by the host device 200 is a write command, the buffer manager 123 may store the command, address, and write data in the buffer memory 124, as shown in FIG.<EX 1> shown.

[0097] The buffer manager 123 may set a valid flag of a command stored in the buffer memory 124 .

[0098] For example, the buffer manager 123 may set the valid flag of the command stored in the buffer memory 124 to a first value. The command with the valid flag set to the first value may indicate that the command needs to be processed once the refresh operation of the first memory region MR1 including the address associated with the command is completed.

[0099] When storing a write command in buffer memory 124 , buffer manager 123 may check whether the address associated with the write command matches any address of a previously stored write command in buffer memory 124 .

[0100] When the address associated with the write command received from the host device 200 is already stored in the buffer memory 124, that is, when the address associated with the write command matches any one of the addresses stored in the buffer memory 124, the buffer manager 123 can set the valid flag of the received write command to a first value and store it in the buffer memory 124.

[0101] The buffer manager 123 may change the valid flag of the write command already stored in the buffer memory 124 to a second value. The command with the valid flag set to the second value may be considered invalid, indicating that the command does not need to be processed after the refresh operation is completed.

[0102] Optionally, when the address associated with the write command received from the host device 200 is already stored in the buffer memory 124, the buffer manager 123 may overwrite the data of the stored write command with the write data of the received write command and maintain the valid flag of the stored write command as the first value.

[0103] When the buffer manager 123 stores the write command, address, and write data in the buffer memory 124, the buffer manager 123 may transmit a response signal to the host device 200 through the host interface 121, as shown in (4). After receiving the response signal, the host device 200 may recognize that the write command has been processed and may transmit the next necessary command to the storage device 100 without delay.

[0104] As another example, when the command transmitted by the host device 200 is a read command, the buffer manager 123 may store the read command and its corresponding address in the buffer memory 124, such as<EX 2> shown.

[0105] The buffer manager 123 may set a valid flag of the read command stored in the buffer memory 124 to a first value.

[0106] Buffer manager 123 may check whether the address associated with the read command matches any address already stored in buffer memory 124 .

[0107] If the address associated with the read command matches the address associated with the write command stored in the buffer memory 124, the buffer manager 123 may provide the data of the stored write command to the host device 200. Specifically, the buffer manager 123 may check a valid flag of the stored write command and provide the data of the stored write command to the host device 200 if the valid flag is set to a first value.

[0108] As described above, when providing data to the host device 200 in response to a read command, the buffer manager 123 may choose not to store the read command in the buffer memory 124. Alternatively, the buffer manager 123 may store the read command in the buffer memory 124 and set the valid flag of the read command to a second value.

[0109] If the address associated with the command transmitted by the host device 200 corresponds to the address of the first memory region MR1 undergoing a refresh operation, the buffer manager 123 may store the command in the buffer memory 124 or process the command based on the command and data already stored in the buffer memory 124, as described above.

[0110] Even when receiving a command for the first memory region MR1 undergoing a refresh operation, the buffer manager 123 can reduce an average delay time required to process the command.

[0111] The buffer memory 124 may have a size capable of storing commands from the host device 200 during a period in which a refresh operation is ongoing.

[0112] For example, the size of buffer memory 124 may correspond to the product of the duration of the first period during which the refresh operation of the first memory region MR1 is ongoing and the data transmission speed between the host device 200 and the storage device 100 (specifically, the control unit 120). Specifically, the size of buffer memory 124 is less than or equal to this product. Alternatively, considering the data transmission efficiency between the host device 200 and the storage device 100 (e.g., 0.8), the size of buffer memory 124 may be adjusted to a value obtained by multiplying this product by the data transmission efficiency.

[0113] In this way, by appropriately sizing the buffer memory 124, the processing and management of commands received during the period when the refresh operation is ongoing may be facilitated.

[0114] Once the refresh operation is completed or the memory area undergoing the refresh operation is changed, the buffer manager 123 may process the commands stored in the buffer memory 124 .

[0115] For example, Figure 6 As shown, the refresh operation on the first memory region MR1 of the memory 110 may be completed.

[0116] There may be a predetermined time interval between the completion of the refresh operation of the first memory region MR1 and the start of the next refresh operation.Alternatively, the refresh operation of the first memory region MR1 may end and then the refresh operation of the second memory region MR2 may begin.

[0117] A duration for performing the refresh operation of the first memory region MR1 may be referred to as a first period, and a duration for performing the refresh operation of the second memory region MR2 may be referred to as a second period.

[0118] When the first period ends, the data saving operation manager 122b may transmit an end signal of the refresh operation of the first memory region MR1 to the buffer manager 123. Similarly, when the second period starts, the data saving operation manager 122b may transmit a start signal of the refresh operation of the second memory region MR2 to the buffer manager 123. There may be a time interval between the first period and the second period, or the first period and the second period may be continuous.

[0119] If the buffer manager 123 receives an end signal of the refresh operation for the first memory region MR1 , the buffer manager 123 may process commands related to the first memory region MR1 stored in the buffer memory 124 .

[0120] The buffer manager 123 may provide the command associated with the address of the first memory region MR1 among the commands whose valid flags are set to the first value and stored in the buffer memory 124 to the memory controller 122 a , as shown in ⑤.

[0121] When the command stored in the buffer memory 124 is a write command, the buffer manager 123 may provide the write command, its corresponding address, and write data stored in the buffer memory 124 to the memory controller 122 a. When the command stored in the buffer memory 124 is a read command, the buffer manager 123 may provide the read command and its corresponding address stored in the buffer memory 124 to the memory controller 122 a.

[0122] After receiving the command from the buffer manager 123 , the memory controller 122 a may control an operation corresponding to the command of the first memory region MR1 , as shown in ⑥ .

[0123] The memory controller 122 a may control an operation of writing data into the first memory region MR1 in response to a write command stored in the buffer memory 124 .

[0124] Alternatively, the memory controller 122a may control an operation of reading data from the first memory region MR1 in response to a read command stored in the buffer memory 124. The memory controller 122a may provide the read data to the host interface 121 through the buffer manager 123 or may directly provide the read data to the host interface 121.

[0125] When the command stored in the buffer memory 124 is provided to the memory controller 122 a , the buffer manager 123 may change the valid flag of the command stored in the buffer memory 124 to a second value.

[0126] Alternatively, when the memory controller 122 a completes processing of the command, the buffer manager 123 may change the valid flag of the command stored in the buffer memory 124 to a second value.

[0127] When the refresh operation of the first memory region MR1 is completed, a command with respect to the first memory region MR1 is processed, thereby minimizing a delay time of the command processing.

[0128] Furthermore, since a command for the first memory region MR1 is processed during the second period while a refresh operation of another memory region (eg, the second memory region MR2) is in progress, delay caused by command processing can be reduced even during the refresh operation.

[0129] Furthermore, when an address associated with a command transmitted by the host device 200 corresponds to a memory area other than a memory area undergoing a refresh operation, the command can be processed without delay.

[0130] For example, refer to Figure 7 The buffer manager 123 may receive information about a refresh operation for the first memory region MR1 from the data saving operation manager 122b, as shown in ①. In addition, the buffer manager 123 may receive a command transmitted by the host device 200 through the host interface 121, as shown in ②.

[0131] The buffer manager 123 may check whether the address associated with the received command corresponds to the first memory region MR1 undergoing a refresh operation.

[0132] For example, when the address associated with the received command corresponds to the second memory region MR2 where no refresh operation is being performed, the buffer manager 123 may provide the received command to the memory controller 122 a , as shown in ③ ′.

[0133] The buffer manager 123 may provide the received command directly to the memory controller 122 a without utilizing the buffer memory 124 , or may first route the command through the buffer memory 124 before providing it to the memory controller 122 a .

[0134] The buffer manager 123 may provide the received command and its corresponding address to the memory controller 122a. Depending on the type of command, the buffer manager 123 may also provide relevant data to the memory controller 122a.

[0135] The memory controller 122 a may control the operation of the memory 110 based on a command received from the buffer manager 123 .

[0136] During a first period in which a refresh operation of the first memory region MR1 is being performed, the memory controller 122 a may control an operation of the second memory region MR2 , as indicated by ④ ′.

[0137] The memory controller 122a may control an operation of writing data to the second memory region MR2 during the first period. Alternatively, the memory controller 122a may control an operation of reading data from the second memory region MR2 during the first period.

[0138] Once the memory controller 122a completes processing of the command, it may transmit a response signal for the write command or data corresponding to the read command to the host device 200, as shown in FIG5 ′. The memory controller 122a may transmit the signal directly to the host interface 121 or route the signal through the buffer manager 123.

[0139] During a first period in which a refresh operation of the first memory region MR1 is in progress, a command for a memory region other than the first memory region MR1 (eg, the second memory region MR2 ) may be processed.

[0140] Even during a refresh operation of the memory 110, commands transmitted by the host device 200 can be processed without waiting. This method helps maintain the preservation state of the data stored in the memory 110 while reducing the delay in processing commands by the host device 200, thereby improving the operating performance of the storage device 100 including the memory 110.

[0141] The buffer manager 123 included in the control unit 120 may be implemented to manage command processing and facilitate communication between the host interface 121 and the memory interface 122 , as described in the above examples. The buffer manager 123 may be integrated into the host interface 121 or the memory interface 122 .

[0142] The buffer manager 123 may refer to a component within the control unit 120 that receives and processes a command from the host device 200 and information about a data saving operation of the memory 110 .

[0143] Figures 8 to 10 is a view illustrating an operating method of the control unit 120 according to an embodiment of the present disclosure.

[0144] Reference Figure 8 , the buffer manager 123 included in the control unit 120 may receive refresh start information related to a refresh operation of the memory 110 ( S800 ).

[0145] The buffer manager 123 may use the refresh start information to identify a memory region undergoing a refresh operation. The buffer manager 123 may predict the duration of the refresh operation based on the refresh start information.

[0146] The buffer manager 123 may receive a command input from the host device 200 and continuously acquire real-time information on a refresh operation ( S810 ).

[0147] A command transmitted from the host device 200 to the memory device 100 may be input to the buffer manager 123 through the host interface 121 .

[0148] The buffer manager 123 may check whether the address associated with the received command corresponds to a memory region undergoing a refresh operation or matches any address stored in the buffer memory 124 ( S820 ).

[0149] If the address associated with the received command corresponds to a memory area undergoing a refresh operation, the buffer manager 123 may transfer the command to the buffer memory 124 (S830). In addition, if the address associated with the received command matches any address stored in the buffer memory 124 and corresponds to a command in a valid state, the buffer manager 123 may transfer the received command to the buffer memory 124.

[0150] If the address associated with the received command does not correspond to the memory region undergoing a refresh operation, the buffer manager 123 may transmit the received command to the memory controller 122 a ( S840 ), where the command is executed.

[0151] The buffer manager 123 can manage commands received from the host device 200 and transmit the commands to the memory controller 122a for processing even during a refresh operation. This improves the operating performance of the memory device 100.

[0152] The buffer manager 123 may control the timing and method of processing commands based on the memory region undergoing the refresh operation and the address associated with the command.

[0153] When the address associated with the command corresponds to a memory region undergoing a refresh operation, buffer manager 123 may process the command based on factors such as the type of command, whether a corresponding command stored in buffer memory 124 is valid, or other relevant conditions.

[0154] For example, refer to Figure 9 , the buffer manager 123 receives refresh start information (S900). The buffer manager 123 may store a buffer point corresponding to the start position of the refresh operation in the buffer memory 124 based on the refresh start information (S910). Then, the buffer manager 123 manages commands received after the refresh operation starts based on the start position.

[0155] After storing the buffer point in the buffer memory 124, the buffer manager 123 receives a command transmitted by the host device 200 (S920). When the address associated with the received command corresponds to the memory area undergoing a refresh operation, the buffer manager 123 may check whether the address associated with the received command matches any address associated with a command previously stored in the buffer memory 124 (S930). In other words, at S930, the buffer manager 123 checks whether the address associated with the received command is already stored in the buffer memory 124.

[0156] When the address associated with the received command matches the address stored in the buffer memory 124 ( S930 : YES), the buffer manager 123 may check whether the received command is a write command ( S941 ).

[0157] If the received command is a write command (S941: Yes), the buffer manager 123 may store the received command in the buffer memory 124, set its valid flag to a first value, and change the valid flag of the command previously stored in the buffer memory 124 to a second value, thereby invalidating it (S951). In some cases, the buffer manager 123 may overwrite the previously stored command with the received command.

[0158] On the other hand, if the received command is a read command (S941: No), the buffer manager 123 may read the data corresponding to the write command stored in the buffer memory 124 and provide it to the host device 200. The buffer manager 123 may not store the received read command in the buffer memory 124, or may store it and set the valid flag to a second value, thereby managing it as an invalid command (S952). In this case, the address associated with the write command stored in the buffer memory 124 and the address associated with the received command match.

[0159] When the address associated with the received command does not match any address stored in the buffer memory 124 ( S930 : No), the buffer manager 123 may check whether the received command is a write command ( S942 ).

[0160] If the received command is a write command ( S942 : YES), the buffer manager 123 may store the received command in the buffer memory 124 and set its valid flag to a first value ( S953 ).

[0161] If the received command is a read command (S942: No), the buffer manager 123 may retain it in the buffer memory 124 until the refresh operation is completed (S954). Similar to the write command, the buffer manager 123 may store the read command and its address in the buffer memory 124, set its valid flag to the first value, and manage it as a valid command.

[0162] The buffer manager 123 may manage commands using the buffer memory 124 and, after a refresh operation is completed, process the commands stored in the buffer memory 124 .

[0163] For example, refer to Figure 10 , the buffer manager 123 may receive end information indicating the end of the refresh operation after the refresh operation is completed ( S1000 ).

[0164] After receiving the refresh operation completion information, the buffer manager 123 may identify a command corresponding to the memory area for which the refresh operation is completed, the command being selected from commands stored between the start buffer point and the current buffer point, the command having a valid flag set to a first value (S1010).

[0165] The buffer manager 123 may transmit data related to the valid command to the memory controller 122 a ( S1020 ). The memory controller 122 a may perform an operation specified by the valid command on the memory area where the refresh operation is completed.

[0166] According to an embodiment of the present disclosure, the buffer manager 123 of the control unit 120 manages refresh operation information and processes commands transmitted by the host device 200. This enables the refresh operation of the memory 110 to be performed and reduces delay in command processing by the host device 200.

[0167] This approach enhances the operational performance of the storage device 100 while preserving the data stored in the memory 110 .

[0168] In addition, the buffer manager 123 can obtain information about the operation of the memory 110 (except for the refresh operation) and adjust the timing and method of processing commands transmitted by the host device 200 based on the address of the ongoing operation. This improves the operating performance of the memory device 100 by improving the processing efficiency of commands and maintaining the state of the memory 110.

[0169] Based on the embodiments of the disclosed technology, the operation delay time of the memory system can be significantly reduced or minimized. In addition, the overhead associated with calling specific functions can be reduced or minimized. Although various embodiments of the disclosed technology have been described with specific details for illustrative purposes, it will be understood by those skilled in the art that various modifications, additions, and substitutions can be made based on the content disclosed or described in this disclosure without departing from the spirit and scope of the disclosure as defined in the appended claims.

Claims

1. A storage device comprising: at least one memory; as well as a control unit that facilitates communication between the at least one memory and a host device and controls the at least one memory, Wherein, the control unit includes: a memory controller to control the operation of the at least one memory; a data saving operation manager to manage data saving operations of the at least one memory; and A buffer manager receives a command transmitted by the host device, stores the command in a buffer memory when an address associated with the command corresponds to a memory area in which the data saving operation is being performed, and provides the command to the memory controller when the address does not correspond to the memory area, the memory area being included in the at least one memory.

2. The storage device according to claim 1, wherein After receiving a valid command from the buffer manager, the memory controller performs an operation of writing data to a target memory area corresponding to an address associated with the valid command or an operation of reading data from the target memory area while the data saving operation is in progress.

3. The storage device according to claim 1, wherein When the data saving operation is completed, the buffer manager provides the commands stored in the buffer memory to the memory controller. The storage device according to claim 1 , wherein: When the command is stored in the buffer memory, the buffer manager transmits a response signal to the host device. The storage device according to claim 1 , wherein: When the command is a write command, the buffer manager stores the command, an address associated with the command, and data corresponding to the command in the buffer memory. The storage device according to claim 1 , wherein: When the command is a write command and an address associated with the command matches an address associated with a write command pre-stored in the buffer memory, the buffer manager sets a valid flag of the command to a first value, stores the valid flag in the buffer memory, and changes the valid flag of the pre-stored write command to a second value, wherein the first value indicates valid and the second value indicates invalid.

7. The storage device according to claim 1, wherein When the command is a write command and an address associated with the command matches an address associated with a write command pre-stored in the buffer memory, the buffer manager overwrites the pre-stored write command with the command transmitted by the host device.

8. The storage device according to claim 1, wherein When the command is a read command, the buffer manager stores the command and an address associated with the command in the buffer memory.

9. The storage device according to claim 1, wherein When the command is a read command and an address associated with the command matches an address associated with a write command pre-stored in the buffer memory, the buffer manager provides data corresponding to the pre-stored write command to the host device.

10. The storage device according to claim 1, wherein When storing the command in the buffer memory, the buffer manager sets a valid flag of the command to a first value indicating valid. The storage device according to claim 10 , wherein: When providing the command to the memory controller, the buffer manager changes a valid flag of the command to a second value indicating invalidity.

12. The storage device according to claim 1, wherein The buffer manager receives a start signal and an end signal of the data saving operation from the data saving operation manager.

13. The storage device according to claim 1, wherein The buffer manager receives information about the memory area and a start signal of the data saving operation from the data saving operation manager.

14. The storage device according to claim 1, wherein The size of the buffer memory is less than or equal to a size corresponding to a product of a duration of a first period during which the data saving operation is ongoing and a data transmission speed between the host device and the control unit.

15. A storage device comprising: at least one memory; as well as A control unit controls the at least one memory to write data into or read data from a second memory area of the at least one memory during a first period in which a data saving operation on a first memory area of the at least one memory is in progress. The storage device according to claim 15 , wherein: Upon receiving a command directed to the first memory area during the first period, the control unit stores the command in a buffer memory and sets a valid flag of the command to a first value.

17. The storage device according to claim 16, wherein: After the first period ends, during a second period in which a data saving operation for the second memory area is in progress, the control unit controls an operation of writing data into or reading data from the first memory area based on a command stored in the buffer memory.

18. The storage device according to claim 17, wherein: The control unit changes the valid flag of the command stored in the buffer memory to a second value during the second period.

19. A control unit comprising: a first interface for communicating with a host device; a second interface in communication with the memory, controlling the operation of the memory and outputting information regarding data saving operations being performed on the memory; as well as A buffer manager receives a command through the first interface, stores the command in a buffer memory when an address associated with the command corresponds to a memory area in which the data saving operation is being performed, and provides the command to the second interface when the address does not correspond to the memory area.

20. The control unit according to claim 19, wherein During a period in which a data saving operation for a first memory area of the memory is in progress, the second interface controls an operation of writing data to or reading data from a second memory area of the memory based on the command.

Images