Apparatus and method

Abstract

Apparatus and methods are disclosed. Some aspects of the present disclosure relate to an apparatus comprising memory circuitry, machine-readable instructions, and processor circuitry to execute the machine-readable instructions, the method comprises the following steps: obtaining a physical layout of a first processor circuit system comprising a plurality of processor cores, and thermal information of the plurality of processor cores; and determining a first processor core of the plurality of processor cores for executing the first workload based on the physical layout of the first processor circuitry and the thermal information of the plurality of processor cores.

Description

Background Art

[0001] The task scheduler is an important component in the computing environment. It arranges the distribution of computing tasks to the appropriate processing units to ensure efficient execution and resource utilization. The scheduler can operate at various levels within the system (such as the operating system thread level and the application level) and can be designed to optimize the performance and responsiveness of the computing system. For the scheduler, adapting to the specific characteristics and configuration of the underlying hardware may be a challenge. This limitation may lead to less than ideal task distribution, thereby affecting the overall performance and efficiency of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Some examples of apparatus and / or methods will be described below by way of example only and with reference to the accompanying drawings, in which:

[0003] Figure 1 A block diagram illustrating an example of an apparatus or device;

[0004] Figure 2 A block diagram illustrating an example of an apparatus or device;

[0005] Figure 3 Graph illustrating temperature measurement distribution across processor circuitry including multiple processor cores by a core adjacency unaware scheduler;

[0006] Figure 4 Graph illustrating temperature measurement distribution across processor circuitry including multiple processor cores by a core adjacency aware scheduler;

[0007] Figure 5 The diagram shows the Figure 3 system and Figure 4 Comparison of the core temperature of the system;

[0008] Figure 6 A flowchart illustrating an example of a method; and

[0009] Figure 7 A flow chart illustrating an example of a method is shown. DETAILED DESCRIPTION

[0010] Some examples are now described in more detail with reference to the accompanying drawings. However, other possible examples are not limited to the features of these embodiments described in detail. Other examples may include modifications of features and equivalents and substitutes of features. In addition, the terms used in this article to describe certain examples should not limit other possible examples.

[0011] Throughout the description of the drawings, the same or similar reference numerals refer to the same or similar elements and / or features, which may be the same or implemented in a modified form while providing the same or similar functions. For clarity, the thickness of lines, layers and / or regions in the drawings may also be exaggerated.

[0012] When two elements A and B are combined using "or", it is understood that this discloses all possible combinations, i.e., only A, only B, and A and B, unless otherwise explicitly defined in individual cases. As alternative wording for the same combination, "at least one of A and B" or "A and / or B" can be used. This applies equally to combinations of more than two elements.

[0013] If singular forms such as "a", "an" and "the" are used and the use of only a single element is neither explicitly nor implicitly defined as mandatory, further examples may also use several elements to implement the same functionality. If a functionality is described below as being implemented using multiple elements, further examples may use a single element or a single processing entity to implement the same functionality. It is further understood that when the terms "include", "including", "comprise" and / or "comprising" are used, they describe the presence of specified features, integers, steps, operations, elements, components and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0014] In the following description, specific details are set forth, but examples of the technology described herein can be implemented without these specific details. Well-known circuits, structures, and techniques are not shown in detail to avoid obscuring the understanding of this description. "An example / example," "various examples / examples," "some examples / examples," etc. may include features, structures, or characteristics, but not every example necessarily includes these specific features, structures, or characteristics.

[0015] Some examples may have some, all, or none of the features described for other examples. "First," "second," "third," and the like describe common elements and indicate different instances of the same element being referenced. Such adjectives do not imply that the elements so described must be in a given order, either temporally or spatially, in ranking, or in any other manner. "Connected" may indicate that elements are in direct physical or electrical contact with each other, and "coupled" may indicate that elements cooperate or interact with each other, but these elements may or may not be in direct physical or electrical contact.

[0016] As used herein, the terms "operate," "execute," or "run" are used interchangeably when referring to software or firmware in connection with a system, device, platform, or resource, and may refer to software or firmware stored in one or more computer-readable storage media accessible to the system, device, platform, or resource, even if the instructions contained in the software or firmware are not being actively executed by the system, device, platform, or resource.

[0017] The specification may use the phrases "in an example / example," "in various examples," "in some examples / examples," and / or "in various examples / examples," each of which may refer to one or more of the same or different examples. Furthermore, the terms "comprising," "including," "having," and the like as used with respect to examples of the present disclosure are synonymous.

[0018] Task schedulers (e.g., operating system (OS) thread-level and application-level schedulers) can assign work to computing resources. Current schedulers may not be aware of the physical layout of the processor cores or their thermal characteristics. This can result in greater power consumption by the cooling system, reduced core performance, and / or greater component degradation due to inefficient distribution of workloads that increase die temperature.

[0019] Some approaches to part degradation include using a scheduler that assigns work using a round-robin methodology, as this may create more even wear on the cores. However, this is a blind approach, as it may not account for core layout or core temperature, which may result in greater thermal degradation if a core is heated more frequently by neighboring cores.

[0020] Some schedulers may consider many parameters (such as non-uniform memory access, or NUMA affinity) when assigning work to cores. According to the present disclosure, the scheduler can add the physical layout of the (processor) cores and their thermal characteristics to the parameters considered. The proposed scheduler can assign work to cores that are physically farther away and therefore less susceptible to performance limitations from thermal throttling.

[0021] Figure 1 The figure shows a block diagram of an example of an apparatus 100 or device 100. The apparatus 100 includes circuitry configured to provide the functionality of the apparatus 100. For example, Figure 1 The apparatus 100 includes interface circuitry 120, processor circuitry 130, and (optionally) memory circuitry 140. For example, the processor circuitry 130 may be coupled to the interface circuitry 120 and, optionally, to the memory circuitry 140.

[0022] For example, processor circuitry 130 may be configured to provide the functionality of apparatus 100 in conjunction with interface circuitry 120. Interface circuitry 120 may be configured to exchange information with other components internal or external to apparatus 100 and memory circuitry 140, for example. Likewise, apparatus 100 may include apparatus configured to provide the functionality of apparatus 100.

[0023] The components of the apparatus 100 are defined as component means that may correspond to or be implemented by corresponding structural components of the apparatus 100. For example, Figure 1 Device 100 includes: means for processing 130, which may correspond to or be implemented by processor circuitry 130; means for communicating 120, which may correspond to or be implemented by interface circuitry 120; and (optionally) means for storing information 140, which may correspond to or be implemented by storage circuitry 140. Hereinafter, the functionality of device 100 will be illustrated with respect to device 100. Therefore, features described in conjunction with device 100 may also apply to the corresponding device 100.

[0024] Generally speaking, the functionality of the processor circuitry 130 or means for processing 130 may be implemented by the processor circuitry 130 or means for processing 130 executing machine-readable instructions. Thus, any features attributed to the processor circuitry 130 or means for processing 130 may be defined by one or more of the plurality of machine-readable instructions. The apparatus 100 or device 100 may include machine-readable instructions (e.g., within the storage circuitry 140 or means for storing information 140).

[0025] The interface circuitry 120 or means for communicating 120 may correspond to one or more inputs and / or outputs for receiving and / or transmitting information within a module, between modules, or between modules of different entities, which may be in the form of digital (bit) values according to a specified code. For example, the interface circuitry 120 or means for communicating 120 may include circuitry configured to receive and / or transmit information.

[0026] For example, the processor circuit system 130 or the means for processing 130 may be implemented using one or more processing units, one or more processing devices, or any means for processing, such as a processor, a computer, or a programmable hardware component operable with correspondingly adapted software. In other words, the functions of the processor circuit system 130 or the means for processing 130 described may also be implemented using software, which is then executed on one or more programmable hardware components. Such hardware components may include general-purpose processors, digital signal processors (DSPs), microcontrollers, and the like.

[0027] For example, the storage circuit system 140 or the device for storing information 140 may include at least one element from the group of computer-readable storage media, such as magnetic or optical storage media, such as a hard drive, flash memory, floppy disk, random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or network storage device. For example, the storage circuit system 140 may store (UEFI) BIOS.

[0028] Processor circuitry 130 is configured to obtain a physical layout of a first processor circuitry including a plurality of processor cores and thermal information of the plurality of processor cores. Processor circuitry 130 is configured to determine a first processor core among the plurality of processor cores for executing a first workload based on the physical layout of the first processor circuitry and the thermal information of the plurality of processor cores.

[0029] In some examples, the first processor circuitry may be the same as processor circuitry 130. In this case, for example, circuitry 130 may obtain the physical layout of the first processor circuitry from memory circuitry 140. For example, a first processor core of processor circuitry 130 may execute a first workload.

[0030] In some examples, the first processor circuitry may be different from processor circuitry 130. In this case, for example, circuitry 130 may obtain the physical layout of the first processor circuitry from another device including the first processor circuitry via interface circuitry 120. For example, the determined first processor core is transmitted to the first processor circuitry via interface circuitry 120.

[0031] The physical layout of the first processor circuitry including multiple processor cores can be a spatial representation of the processor cores within the first processor circuitry. In some examples, the physical layout of the first processor circuitry can be a spatial representation that also includes other components of the first processor circuitry, such as interconnects, memory controllers, power management, I / O interfaces, etc. In some examples, the physical layout of the first processor circuitry can be a two-dimensional (2D) or three-dimensional spatial representation of the components of the first processor circuitry. That is, the physical layout can include components arranged in a plane or in stacked layers to represent their spatial locations within the first processor circuitry.

[0032] In some examples, the physical layout includes at least the spatial positioning of the processor cores within the processor circuitry. In some examples, the physical layout includes at least the spatial positioning of the processor cores relative to each other within a two-dimensional plane within the processor circuitry (see Figure 3 and Figure 4 ). For example, the physical layout of the space can

[0033] In some examples, the physical layout of the first processor circuit system can be determined during the manufacturing process of the first processor circuit system (e.g., a silicon manufacturing company). In another example, the physical layout of the first processor circuit system can be determined by applying a power-intensive workload to a processor core of the first processor circuit system, measuring the corresponding temperature distribution of the processor core (and in some examples, also measuring the corresponding temperature distribution of other components), and inferring the physical layout based on this. This will be explained in more detail below. For example, the physical layout of the first processor circuit system can be determined by circuit system 130 or by another device and can be transmitted to circuit system 130.

[0034] In some examples, the thermal information for the plurality of processor cores may include a temperature measurement for each of the plurality of cores.Apparatus 100 (eg, circuitry 130 ) may include a sensor for measuring the temperature of the plurality of processor cores.

[0035] In some examples, thermal information for the plurality of processor cores may include a thermal throttle threshold for each of the plurality of cores. The thermal throttle threshold for a processor core may indicate a maximum temperature limit above which the core will reduce its performance to prevent overheating. In some examples, thermal information for the plurality of processor cores may include a heat dissipation value for each of the plurality of cores. The heat dissipation value for each core may indicate the amount of heat that each core can emit during a specific time period, that is, how quickly the processor core can cool down.

[0036] Processor circuitry 130 is configured to determine a first processor core from the plurality of processor cores to execute a first workload based on the physical layout of the first processor circuitry and thermal information about the plurality of processor cores. In other words, the workload is assigned to a particular processor core taking into account (possibly among other factors) current temperature measurements of the processor cores and their corresponding spatial locations within the physical layout of the processor circuitry.

[0037] In some examples, a workload can be a task, a process, an application, or a virtual machine. That is, a workload can refer to a single task, which is a specific operation or a small sequence of operations, or a workload can refer to a process, which is an executing program that contains one or more tasks. A workload can also refer to an application, which can be a complete software program designed for an end user. In some examples, a workload can refer to a virtual machine, which is a simulation of a computer system that provides the functionality of a physical computer, allowing multiple instances to run on a single physical hardware resource. In some examples, the processor circuit system 130 can be configured to assign a first workload to a first processor core. The first processor core can then execute the first workload.

[0038] Such temperature-based scheduling of workloads as described in the present disclosure can result in heat generated by the workload being more evenly distributed across the first processor circuitry. Consequently, a cooling system for the first processor circuitry can require less energy, which results in improved energy efficiency. Furthermore, thermal degradation of the first processor circuitry, or thermal degradation of parts thereof, can be more evenly distributed, which increases the lifespan of the first processor circuitry. Furthermore, when a processor core reaches a thermal throttling threshold, it can reduce its clock speed or power consumption to reduce heat generation that causes performance loss. Therefore, due to temperature-based scheduling of workloads as described in the present disclosure, a processor core can be less likely to reach its thermal throttling threshold, which can result in better performance.

[0039] In some examples, a pre-existing scheduling algorithm may be used in which current temperature measurements of the processor cores and their corresponding spatial locations within the physical layout of the processor circuitry are integrated as additional factors for deciding which processor core should execute the first workload.

[0040] Determine the processor core

[0041] For example, circuitry 130 may be configured to determine a first processor core from among the plurality of processor cores for executing a first workload only among processor cores of the processor circuitry that are not currently executing any workload. For example, circuitry 130 may be configured to determine a processor core for a new workload (i.e., one in which execution may not have yet been initiated).

[0042] In some examples, circuitry 130 can be configured to determine a first processor core among the plurality of processor cores for executing a first workload, wherein the first processor core has the lowest temperature measurement among the plurality of processor cores of the processor circuitry. In some examples, circuitry 130 can be configured to determine a first processor core among the plurality of processor cores for executing the first workload, wherein the first processor core has a temperature below a predetermined value. For example, the first processor core is selected because it has a temperature below 40° C., 50° C., 60° C., etc.

[0043] In some examples, the circuit system 130 can be configured to determine a first processor core among the plurality of processor cores for executing a first workload, wherein the first processor core has a temperature that is lower than an average temperature of the plurality of processor cores. The average temperature of the plurality of processor cores can generally refer to a representative value that summarizes the temperatures across the plurality of processor cores. For example, the average temperature of the plurality of processor cores can refer to a mean (the sum of all core temperatures divided by the number of cores), other statistical measures such as a median (the middle value when ranking the core temperatures), or a mode (the most common temperature value), etc.

[0044] In some examples, processor circuitry 130 can be configured to determine a partitioning of the physical layout of the first processor circuitry into a plurality of regions, wherein each of the plurality of regions includes one or more processor cores from the plurality of processor cores. For example, the physical layout can be divided into a plurality of regions of equal size. For example, each of the plurality of regions includes the same number of processor cores from the plurality of processor cores. For example, each of the plurality of regions includes between 2 and 10 processor cores from the plurality of processor cores.

[0045] In another example, one or more regions may include different amounts of processor cores.

[0046] In some examples, the processor circuit system 130 can be configured to determine that the first processor core is part of a first region among multiple regions. The first region may have the lowest average processor core temperature measurement. For example, after the physical layout of the first processor circuit system is divided into multiple regions, each region including one or more processor cores, the average temperature for each region is determined. For example, the average temperature can refer to the mean temperature of all processor cores in a region (the average value is to be understood as described above). The region with the lowest average temperature can be referred to as the first region. If there is more than one processor core in the first region, then in some examples, the first processor core is randomly selected among the processor cores in the first region. In another example, the first processor core is determined to be the processor core in the first region with the lowest processor core temperature measurement.

[0047] Identify the second processor core

[0048] In some examples, processor circuitry 130 can be configured to determine a second processor core from among the plurality of processor cores to execute a second workload based on the physical layout of the first processor circuitry, based on thermal information about the plurality of processor cores, and / or based on the first processor core determined to execute the first workload. In some examples, processor circuitry 130 can be configured to determine the second processor core based on a spatial location within the physical layout of the first processor circuitry determined to execute the first workload. In other words, the assignment of the second workload to the second processor core can be further based on a previously completed assignment of the first workload to the first processor core (or vice versa).

[0049] For example, the second processor core may be determined in such a manner that a predetermined spatial relationship within the physical layout of the first processor circuitry is maintained between the first processor core and the second processor core. For example, the second processor core may be determined in such a manner that a predetermined distance (i.e., a predetermined number of processor cores) exists between the first processor core and the second processor core.

[0050] In some examples, the first processor core and / or the second processor core are determined such that the first processor core and the second processor core are not adjacent processor cores within the physical layout of the first processor circuitry. For example, the first processor cores may not share a plane (in the case of a 3D layout) nor an edge or corner. In some cases, they may share a corner and not be considered adjacent.

[0051] In some examples, the first processor core and / or the second processor core are determined such that the first processor core has a predetermined spacing from the second processor core, and a predetermined number of processor cores are located between the first processor core and the second processor core. The predetermined number of processor cores located between the first processor core and the second processor core can be counted as the number of processor cores that must be traversed to get from the first processor core to the second processor core.

[0052] In some examples, the first processor core and / or the second processor core are determined such that there is a maximum possible spacing between the first processor core and the second processor core within the physical layout. The maximum possible spacing can refer to a maximum distance measurement between the two processor cores (which can be from the center of the first processor core to the center of the second processor core), or it can refer to a maximum number of processor cores between the two processor cores.

[0053] For example, the first processor core is first determined to execute the first workload, and then the second processor core is determined so as to satisfy the above conditions. If the second processor core is first determined to execute the second workload, the first processor core is determined so as to satisfy the above conditions.

[0054] In the event that the first processor core is first determined to execute the first workload, the processor circuitry 130 may be configured to determine that the second processor core is part of a second region of the plurality of regions, the second region having the second lowest average processor core temperature measurement. The plurality of regions and corresponding average temperatures may be determined as described above. The first processor core may have been determined to be part of the first region having the lowest average processor core temperature measurement.

[0055] As described with respect to the first region, in some examples, the second processor core is randomly selected among the processor cores in the second region. In another example, the second processor core is selected as the processor core in the second region having the lowest processor core temperature measurement.

[0056] Further details and aspects are mentioned in conjunction with the examples described below. Figure 1 The examples shown in may include those in conjunction with the concepts presented or described below (e.g., Figure 2-Figure 7 ) One or more optional additional features corresponding to one or more aspects mentioned in one or more examples described.

[0057] Redistribute workload

[0058] Figure 2 The figure shows a block diagram of an example of an apparatus 200 or device 200. The apparatus 200 includes circuitry configured to provide the functionality of the apparatus 200. For example, Figure 2 Device 200 includes interface circuitry 220, processor circuitry 230, and (optionally) memory circuitry 240. For example, processor circuitry 230 may be coupled to interface circuitry 220, and optionally to memory circuitry 240. For example, processor circuitry 230 may be configured to provide the functionality of device 200 in conjunction with interface circuitry 220. For example, interface circuitry 220 may be configured to exchange information with other components within or external to device 200 and memory circuitry 240. Similarly, device 200 may include a device configured to provide the functionality of device 200.

[0059] Device 200 and interface circuitry 220, processor circuitry 230, and memory circuitry 240 may be the same as or different from device 100 and its circuitry.

[0060] In some examples, circuitry 230 can be configured to move the executed workload from the current processor core to another processor core within the processing circuitry if the current processor core may be thermally throttled due to high temperature, for example, where the current processor core and the other processor core are physically far apart within the physical layout and are therefore less likely to be affected by the temperature of an adjacent core.

[0061] In some examples, the processor circuit system 230 can be configured to obtain a physical layout of a first processor circuit system including multiple processor cores and thermal information of the multiple processor cores. Further, the processor circuit system 230 can be configured to identify a first processor core among the multiple processor cores that is executing a first workload based on the thermal information of the first processor core. For example, the first processor core is identified as the processor core with the highest current temperature among the multiple processor cores. In another example, the first processor core is identified as the first processor core that exceeds its predefined thermal throttle threshold. In another example, the first processor core is identified as the processor core that exceeds its predefined thermal throttle threshold the most as a percentage or in absolute temperature.

[0062] Furthermore, the processor circuitry 230 may be configured to determine a second processor core from among the plurality of processor cores for executing the first workload based on the physical layout of the first processor circuitry and thermal information about the plurality of processor cores. The second processor core may be determined as described above (with respect to the first processor core or the second processor core described above). For example, the second processor core may be the processor core with the lowest temperature measurement.

[0063] In another example, the second processor core may be determined such that a predetermined spatial relationship within the physical layout of the first processor circuitry is maintained between the first processor core and the second processor core (see above for different examples in this regard). For example, the second processor core may be determined such that a predetermined distance (i.e., a predetermined number of processor cores) exists between the first processor core and the second processor core.

[0064] In some examples, the temperature measurement of the first core is higher than the temperature measurement of the second core.

[0065] Furthermore, the processor circuitry 230 may be configured to assign the first workload to the second processor core. In other words, the first workload that is executed by one processor core and causes temperature-related thermal difficulties is reallocated to another processor core that is in a more favorable thermal state.

[0066] This temperature-based redistribution of workloads as described in the present disclosure can result in more even distribution of heat generated by the workload across the first processor circuitry. Consequently, the cooling system of the first processor circuitry can require less energy, resulting in increased energy efficiency. Furthermore, thermal degradation of the first processor circuitry, or components thereof, can be more evenly distributed, which increases the lifespan of the first processor circuitry. Furthermore, temperature-based rescheduling of workloads as described in the present disclosure increases performance because processor cores that may have reached a thermal throttling threshold are freed.

[0067] Example of determining a physical layout of a first processor circuitry

[0068] As described above, the physical layout of a first processor circuit system comprising multiple (processor) cores can be obtained as described in the following method: Inferring the concept of the physical layout of a processor circuit system comprising multiple processor cores can include (one, some, or all of) the following four stages: Stage 1: Collect temperature data (of multiple cores) by heating one core at a time using a power-intensive workload. When a particular core runs this power-intensive workload, all other cores may be idle. Stage 2: Use the collected temperature data and perform a linear regression between the heated core and all other cores. Stage 3: Perform a cluster analysis on the regression data to determine nearby cores for each heated core. Stage 4: Associate the nearby cores of each heated core to determine the physical layout of the processor circuit system on the die. These four stages are described in more detail below.

[0069] The first stage of the disclosed technique for inferring the physical layout of a processor circuitry comprising multiple processor cores may include collecting thermal telemetry data from each processor in the system under test. Thus, for example, publicly available performance registers may be used to monitor core temperatures. For example, the following procedure may be performed in this regard: 1. Collect all individual core temperatures (of all processor cores in the processor circuitry) at predetermined time intervals (e.g., every 200 milliseconds, etc.). 2. Bind a power-intensive workload to one core. This may cause the core to heat up over time. 3. Stop collecting core temperatures. 4. Repeat steps 1, 2, and 3 for each core in the processor circuitry (system).

[0070] In the second stage of the disclosed technique for inferring the physical layout of a processor circuit system including multiple processor cores, a linear regression may be performed on the temperature data collected in stage 1. For example, the following procedure may be performed in this regard: 1. Run a linear regression between a heated core and another core of the processor circuit system and obtain coefficients representing the temperature relationship between the two cores. 2. Repeat step 1 for each core on the system and obtain N-1 coefficients, where N is the number of processor cores in the processor circuit system (i.e., the system). 3. Repeat steps 1 and 2 for N data sets (each data set collected in stage 1 and corresponding to a different core that was heated). After deriving N-1 regression coefficients for each of the N processor cores, an ordered list (matrix) of coefficients for each stressed core may be created.

[0071] The third stage of the disclosed technology for inferring the physical layout of a processor circuit system including multiple processor cores may include performing a cluster analysis on the table output of stage 2. This may be done using a rule-based algorithm or a machine learning algorithm known to those skilled in the art (such as a K-means algorithm). For example, the top 4-5 clusters may be identified. The cluster analysis may be performed using a K-means algorithm (e.g., K=4 or 5) based on the regression coefficient of one core obtained in stage 2. This clustering may be performed for each of the N-1 regression coefficients of the N cores as obtained in stage 2. The identified clusters may have the following definitions: Cluster 1 may be the processing core running a power-intensive workload. Cluster 2 may be the core closest to the processing core running a power-intensive workload, i.e., a neighboring core that shares a surface (with the processing core running the power-intensive workload). Cluster 3 may be the second closest processing core, i.e., an edge core that shares an edge (with the processing core running the power-intensive workload). Cluster 4 may be [this may be for stacked / 3D layouts only] the third closest cores, i.e. the cores diagonally sharing a cube corner (with the processing cores running power intensive workloads). Cluster 5 may be all other cores that may be separated from the heated core by one or more cores.

[0072] The fourth stage of the disclosed technique for inferring the physical layout of a processor circuit system including multiple processor cores may include associating the nearby cores of each heated core to determine the physical layout. This may be based on the clustering results for each stressed core obtained in stage 3. Thus, possible physical layouts (die layouts) in 1D, 2D, or 3D may be programmatically created. For example, the process of mapping processing cores according to their clustering / coefficients may be as follows: 1. Select stressed core X (a core running a power-intensive workload), and in a 3D spatial layout, select all of the cores in the 2nd, 3rd, and 4th clusters (e.g., no more than 6 neighboring cores, 12 edge cores, etc.) in a manner that maximizes thermal affinity and does not violate spatial rules. Cores are picked from those cores surrounding core X, starting with the cores in the second cluster, then the third, and then the fourth, and step 1 is repeated for that core to fill in the nearby cores. This process stops when all cores in the 2nd, 3rd, and 4th clusters have been mapped. 3. If there are cores that were not mapped in steps 1 and 2, repeat steps 1 and 2 until all cores in the system have been mapped (i.e., there may be many separate islands of mapped cores due to multiple tiles, dies, or other thermally isolated cores). 4. If there are multiple islands of mapped cores, orient them based on the knowledge gained from the cores that fell into the 5th cluster in stage 3.

[0073] Example

[0074] Figure 3 The diagram illustrates temperature (measured) distribution 300 across processor circuitry including multiple processor cores by a core adjacency-unaware scheduler. Figure 3 As shown, the further away the core is from the heated cores 1-4, the lower the temperature of the core (the darker the core, the colder the core). That is, the temperature of cores 6-10 is higher than the temperature of cores 11-15, which is higher than the temperature of cores 16-20, which is higher than the temperature of cores 21-25. Figure 3 As depicted in , scheduling workloads on adjacent cores may result in higher individual core temperatures. For example, processor cores 1 and 4 each have a temperature of 55°C. For example, processor cores 2 and 3 each have a temperature of 60°C. This may result in the following disadvantages: Higher individual core temperatures may cause thermal throttling to be triggered, resulting in reduced performance of the triggered cores. Higher concentrations of heat in one area on the die may result in lower efficiency of passive cooling from the heat sink, which in turn may require more active cooling, which may result in greater energy consumption by the cooling system. Higher individual core temperatures may result in greater thermal degradation and may reduce the sustainable life of the affected cores (see also Figure 5 (left image in ).

[0075] Further details and aspects are mentioned in connection with the examples described above or below. Figure 3 The examples shown in may include one or more optional additional features corresponding to one or more aspects mentioned in conjunction with the proposed concept or one or more examples described above or below.

[0076] Figure 4 The figure shows a temperature (measured) distribution 400 across a processor circuit system including multiple processor cores by a core adjacency aware scheduler. The scheduler proposed in the present disclosure is aware of the core adjacency. Therefore, workloads 1 to 4 can be assigned to processor cores 1, 5, 21, and 25. These processor cores are located at the corners of the processor circuit system and can therefore have the greatest distance to each other. Therefore, the above disadvantages can be alleviated. For example, processor cores 1, 5, 21, and 25 each have a temperature of 50°C, which is 20°C lower than the cores 1, 5, 21, and 25. Figure 3 The core adjacency-aware scheduler proposed in this disclosure may have significant performance and power improvements (these improvements may apply to all modern processors, and so at scale, the potential impact across the industry may be even more significant).

[0077] Various scheduling algorithms known to those skilled in the art may be used. These algorithms may take into account resource availability and time constraints. As proposed in the present disclosure, any of these existing algorithms may be enhanced by taking into account the physical layout of all cores in the die and their thermal characteristics. A core adjacency-aware scheduler may schedule new workloads or move existing workloads that are being thermally throttled to cores that are physically farther away and therefore less likely to be affected by the temperature of neighboring cores.

[0078] Further details and aspects are mentioned in connection with the examples described above or below. Figure 4 The examples shown in may include one or more optional additional features corresponding to one or more aspects mentioned in conjunction with the proposed concept or one or more examples described above or below.

[0079] Figure 5 The diagram shows the Figure 3 The core temperature comparison of the system (ie, graph 510) and the Figure 4 Graph 510 shows the temperatures of the cores executing workloads 1 through 4, where the workloads are assigned to processor cores 1 through 4 without regard to temperature (see Figure 3 ). That is, the first core 512 ( Figure 3 1) executes workload 1, the second core 514 ( Figure 3 2) executes workload 2, the third core 516 ( Figure 3 3) executes workload 3, the fourth core 518 ( Figure 3 4 in ) executes workload 4. Processor cores 512 and 518 each have a temperature of 55° C., and processor cores 514 and 516 each have a temperature of 60° C. All cores have temperatures above a predefined thermal throttle threshold 530 .

[0080] Graph 520 shows the temperatures of the cores executing workloads 1 through 4, where the workloads are assigned to the processor cores taking the temperatures into account as described in this disclosure (see Figure 4 ). That is, the first core 522 ( Figure 3 1) executes workload 1, the second core 524 ( Figure 3 5) executes workload 2, the third core 526 ( Figure 3 21) executes workload 3, the fourth core 528 ( Figure 3 25 in FIG. 5 ) executes workload 4. The corresponding measured core temperatures are evenly distributed and thus lower than the temperatures in graph 510. All cores have temperatures above a predefined thermal throttle threshold 530.

[0081] The proposed technique can be identified by monitoring the distribution of workloads across the die. If workloads with elevated temperatures are running on physically distant cores, this may indicate the use of the proposed workload scheduler, which is aware of the physical layout of the die. Measuring the thermal distribution across the die can be used to detect whether the proposed technique is being used.

[0082] Further details and aspects are mentioned in connection with the examples described above or below. Figure 5 The examples shown in may include one or more optional additional features corresponding to one or more aspects mentioned in conjunction with the proposed concept or one or more examples described above or below.

[0083] Figure 6 The figure shows a flowchart of an example of a method 600. For example, the method 600 can be performed by an apparatus as described herein, such as the apparatus 100. The method 600 includes obtaining (610) a physical layout of a first processor circuit system including a plurality of processor cores and thermal information of the plurality of processor cores. The method 600 further includes determining (620) a first processor core of the plurality of processor cores for executing a first workload based on the physical layout of the first processor circuit system and the thermal information of the plurality of processor cores.

[0084] In combination with the proposed technology or above (for example, reference Figure 1) describes one or more examples explaining more details and aspects of method 600. Method 600 may include one or more additional optional features corresponding to one or more aspects of the proposed technology, or one or more examples described above or below.

[0085] Figure 7 The figure illustrates a flowchart of an example of a method 700. For example, the method 700 can be performed by an apparatus as described herein, such as the apparatus 200. The method 700 includes obtaining (710) a physical layout of a first processor circuit system including a plurality of processor cores and thermal information for the plurality of processor cores. The method 700 further includes identifying (720) a first processor core among the plurality of processor cores that is executing a first workload based on the thermal information of the first processor core. The method 700 further includes determining (730) a second processor core among the plurality of processor cores for executing the first workload based on the physical layout of the first processor circuit system and the thermal information of the plurality of processor cores. A temperature measurement of the first core is higher than a temperature measurement of the second core. The method 700 further includes assigning (740) the first workload to the second processor core.

[0086] In combination with the proposed technology or above (for example, reference Figure 2 ) describes more details and aspects of the method 700. The method 700 may include one or more additional optional features corresponding to one or more aspects of the proposed technology, or one or more examples described above.

[0087] In the following, some examples of the proposed technique are presented:

[0088] In the following, some examples of the proposed concept are presented:

[0089] An example (e.g., Example 1) relates to a device comprising an interface circuit system, machine-readable instructions, and a processor circuit system, wherein the processor circuit system is used to execute the machine-readable instructions to perform the following operations: obtain a physical layout of a first processor circuit system comprising multiple processor cores, and thermal information of the multiple processor cores; determine a first processor core among the multiple processor cores for executing a first workload based on the physical layout of the first processor circuit system and the thermal information of the multiple processor cores.

[0090] Another example (e.g., Example 2) relates to the previous example (e.g., Example 1) or to any other example, further including: thermal information of the multiple processor cores includes at least one of the following: a temperature measurement for each of the multiple cores, a thermal throttle threshold for each of the multiple cores, or a heat dissipation value for each of the multiple cores.

[0091] Another example (e.g., Example 3) relates to a previous example (e.g., one of Examples 1-2) or to any other example, further including, at least: the first processor core having the lowest temperature measurement among the plurality of processor cores, the first processor core having a temperature below a predetermined value, the first processor core having a temperature below the temperature measurement of at least half of the plurality of processor cores.

[0092] Another example (e.g., Example 4) relates to a previous example (e.g., one of Examples 1 to 3) or to any other example, further including: a processor circuit system for executing machine-readable instructions to determine a second processor core among multiple processor cores for executing a second workload based on a physical layout of the first processor circuit system, thermal information of the multiple processor cores, and / or the determined first processor core for executing the first workload.

[0093] Another example (e.g., Example 5) relates to the previous example (e.g., Example 4) or to any other example, further including: the first processor core and / or the second processor core are determined so that at least: the first processor core and the second processor core are not adjacent processor cores within the physical layout of the first processor circuit system, the first processor core and the second processor core have a predetermined spacing, there is a predetermined number of processor cores between the first processor core and the second processor core, or there is a maximum possible spacing within the physical layout between the first processor core and the second processor core.

[0094] Another example (e.g., Example 6) relates to a previous example (e.g., one of Examples 1 to 5) or to any other example, further including: the processor circuit system is used to execute machine-readable instructions to determine a division of the physical layout of the first processor circuit system into multiple regions, wherein each region of the multiple regions includes one or more processor cores of the multiple processor cores.

[0095] Another example (e.g., Example 7) relates to a previous example (e.g., Example 6) or to any other example, further including: a processor circuit system for executing machine-readable instructions to determine that a first processor core is part of a first region of multiple regions, the first region having a lowest average processor core temperature measurement.

[0096] Another example (e.g., Example 8) relates to the previous example (e.g., Example 7) or to any other example, further including, at least: the first processor core is randomly selected among the processor cores in the first region, or the first processor core is the processor core with the lowest processor core temperature measurement in the first region.

[0097] Another example (e.g., Example 9) relates to a previous example (e.g., one of Examples 6 to 8) or to any other example, further including: the processor circuit system is used to execute machine-readable instructions to determine that the second processor core is part of a second region of the multiple regions, and the second region has the second lowest average processor core temperature measurement.

[0098] Another example (e.g., Example 10) relates to the previous example (e.g., Example 9) or to any other example, further including, at least: the second processor core is randomly selected among the processor cores in the second region, or the second processor core is the processor core with the lowest processor core temperature measurement in the second region.

[0099] Another example (eg, Example 11) relates to a previous example (eg, one of Examples 6-10) or to any other example, further including: each region of the plurality of regions includes a same number of processor cores of the plurality of processor cores.

[0100] Another example (eg, Example 12) relates to a previous example (eg, Example 11) or to any other example, further including: each of the plurality of regions includes between 2 and 10 processor cores of the plurality of processor cores.

[0101] Another example (e.g., Example 13) relates to a previous example (e.g., one of Examples 1-12) or to any other example, further including: the processor circuit system is used to execute machine-readable instructions to assign the first workload to the first processor core.

[0102] Another example (eg, Example 14) relates to a previous example (eg, one of Examples 1-13) or to any other example, further comprising: the physical layout including spatial positioning of the processor core within the processor circuitry.

[0103] Another example (e.g., Example 15) relates to a previous example (e.g., one of Examples 1 to 14) or to any other example, further including: the physical layout includes spatial positioning of the processor cores relative to each other within a 2-dimensional plane within the processor circuit system.

[0104] Another example (eg, Example 15) relates to a previous example (eg, one of Examples 1 to 15) or to any other example, further including: the first workload can be a task, a process, an application, or a virtual machine.

[0105] An example (e.g., Example 16) relates to a device comprising an interface circuit system, machine-readable instructions, and a processor circuit system for executing the machine-readable instructions to perform the following operations: obtaining a physical layout of a first processor circuit system comprising multiple processor cores, and thermal information of the multiple processor cores; identifying a first processor core among the multiple processor cores that is executing a first workload based on the thermal information of the first processor core; determining a second processor core among the multiple processor cores for executing the first workload based on the physical layout of the first processor circuit system and the thermal information of the multiple processor cores, wherein a temperature measurement of the first core is higher than a temperature measurement of the second core; and assigning the first workload to the second processor core.

[0106] An example (e.g., Example 17) relates to a device comprising a processor circuit system configured to: obtain a physical layout of a first processor circuit system comprising multiple processor cores, and thermal information of the multiple processor cores; and determine a first processor core among the multiple processor cores for executing a first workload based on the physical layout of the first processor circuit system and the thermal information of the multiple processor cores.

[0107] An example (e.g., Example 18) relates to a device comprising a device for processing, which is configured to: obtain a physical layout of a first processor circuit system comprising multiple processor cores, and thermal information of the multiple processor cores; and determine a first processor core among the multiple processor cores for executing a first workload based on the physical layout of the first processor circuit system and the thermal information of the multiple processor cores.

[0108] An example (e.g., Example 19) relates to a method comprising: obtaining a physical layout of a first processor circuit system comprising multiple processor cores, and thermal information of the multiple processor cores; and determining a first processor core among the multiple processor cores for executing a first workload based on the physical layout of the first processor circuit system and the thermal information of the multiple processor cores.

[0109] Another example (e.g., Example 20) relates to a previous example (e.g., Example 19) or to any other example, further including that the thermal information of the multiple processor cores includes at least one of the following: a temperature measurement for each of the multiple cores, a thermal throttle threshold for each of the multiple cores, or a heat dissipation value for each of the multiple cores.

[0110] Another example (e.g., Example 21) relates to a previous example (e.g., one of Examples 19 to 20) or to any other example, further including, at least: the first processor core having the lowest temperature measurement among the plurality of processor cores, the first processor core having a temperature below a predetermined value, the first processor core having a temperature below the temperature measurement of at least half of the plurality of processor cores.

[0111] Another example (e.g., Example 22) relates to a previous example (e.g., one of Examples 19 to 21) or to any other example, further including: determining a second processor core among the multiple processor cores for executing a second workload based on the physical layout of the first processor circuit system, thermal information of the multiple processor cores, and / or the determined first processor core for executing the first workload.

[0112] Another example (e.g., Example 23) relates to the previous example (e.g., Example 18) or to any other example, further including: the first processor core and / or the second processor core are determined so that at least: the first processor core and the second processor core are not adjacent processor cores within the physical layout of the first processor circuit system, the first processor core and the second processor core have a predetermined spacing, there is a predetermined number of processor cores between the first processor core and the second processor core, or there is a maximum possible spacing within the physical layout between the first processor core and the second processor core.

[0113] Another example (e.g., Example 24) relates to a previous example (e.g., one of Examples 19 to 23) or to any other example, further including: determining a partitioning of the physical layout of the first processor circuit system into a plurality of regions, wherein each of the plurality of regions includes one or more processor cores from the plurality of processor cores.

[0114] Another example (e.g., Example 25) relates to a previous example (e.g., Example 24) or to any other example, further including: determining that the first processor core is part of a first region of a plurality of regions, the first region having a lowest average processor core temperature measurement.

[0115] Another example (e.g., Example 26) relates to a previous example (e.g., Example 25) or to any other example, further including, at least: the first processor core is randomly selected among the processor cores in the first region, or the first processor core is the processor core with the lowest processor core temperature measurement in the first region.

[0116] Another example (e.g., Example 27) relates to a previous example (e.g., one of Examples 24 to 26) or to any other example, further including: determining that the second processor core is part of a second region of the plurality of regions, the second region having the second lowest average processor core temperature measurement.

[0117] Another example (e.g., Example 28) relates to the previous example (e.g., Example 27) or to any other example, further including, at least: the second processor core is randomly selected among the processor cores in the second region, or the second processor core is the processor core with the lowest processor core temperature measurement in the second region.

[0118] Another example (eg, Example 29) relates to a previous example (eg, one of Examples 24-28) or to any other example, further including: each of the plurality of regions includes a same number of processor cores from the plurality of processor cores.

[0119] Another example (eg, Example 30) relates to a previous example (eg, Example 29) or to any other example, further comprising: each of the plurality of regions includes between 2 and 10 processor cores of the plurality of processor cores.

[0120] Another example (eg, Example 31) relates to a previous example (eg, one of Examples 19-30) or to any other example, further comprising assigning a first workload to a first processor core.

[0121] Another example (eg, Example 32) relates to a previous example (eg, one of Examples 19-31) or to any other example, further comprising: the physical layout comprising spatial positioning of the processor core within the processor circuitry.

[0122] Another example (e.g., Example 33) relates to a previous example (e.g., one of Examples 19 to 32) or to any other example, further including: the physical layout includes spatial positioning of the processor cores relative to each other within a 2-dimensional plane within the processor circuit system.

[0123] Another example (e.g., Example 34) relates to a previous example (e.g., one of Examples 19 to 33) or to any other example, further including: the first workload can be a task, a process, an application, or a virtual machine.

[0124] An example (e.g., Example 35) relates to a method comprising: obtaining a physical layout of a first processor circuit system comprising multiple processor cores, and thermal information of the multiple processor cores; identifying a first processor core among the multiple processor cores that is executing a first workload based on the thermal information of the first processor core; determining a second processor core among the multiple processor cores for executing the first workload based on the physical layout of the first processor circuit system and the thermal information of the multiple processor cores, wherein a temperature measurement of the first core is higher than a temperature measurement of the second core; and assigning the first workload to the second processor core.

[0125] Another example (eg, Example 36) relates to a non-transitory machine-readable storage medium comprising a program code that, when executed, causes a machine to perform a method according to Examples 19 to 34.

[0126] Another example (eg, Example 37) relates to a computer program having a program code for performing the method according to Examples 19 to 34 when the computer program is executed on a computer, a processor or a programmable hardware component.

[0127] Another example (eg, Example 38) relates to a machine-readable storage device comprising machine-readable instructions that, when executed, are used to implement a method as described in any pending example, or to realize an apparatus as described in any pending example.

[0128] The aspects and features described in relation to a particular example among the foregoing examples may also be combined with one or more of the other examples to replace the same or similar features of the other examples or to introduce these features additionally into the other examples.

[0129] Examples may further be or relate to (computer) programs, including program codes for executing one or more of the above methods when the program is executed on a computer, processor, or other programmable hardware component. Thus, the steps, operations, or processes of the different methods in the methods described above may also be performed by a programmed computer, processor, or other programmable hardware component. Examples may also encompass program storage devices, such as digital data storage media, which are machine-readable, processor-readable, or computer-readable and encode and / or contain machine-executable, processor-executable, or computer-executable programs and instructions. For example, program storage devices may include or may be digital storage devices, magnetic storage media (such as disks and tapes), hard drives, or optically readable digital data storage media. Other examples may also include a computer, a processor, a control unit, a (field) programmable logic array ((F)PLA), a (field) programmable gate array ((F)PGA), a graphics processor unit (GPU), an application-specific integrated circuit (ASIC), an integrated circuit (IC), or a system-on-a-chip (SoC) system programmed to perform the steps of the method described above.

[0130] It is further understood that the disclosure of several steps, processes, operations, or functions disclosed in the specification or claims should not be interpreted as implying that these operations must be performed in the order described, unless explicitly stated in a separate use case or necessary for technical reasons. Therefore, the previous description does not limit the performance of several steps or functions to a certain order. In addition, in other examples, a single step, function, process, or operation may include and / or be decomposed into several sub-steps, sub-functions, sub-processes, or sub-operations.

[0131] If some aspects have been described in conjunction with a device or system, these aspects should also be understood as descriptions of the corresponding methods. For example, a block, device, or functional aspects of a device or system can correspond to features (such as method steps) of a corresponding method. Accordingly, aspects described in conjunction with a method should also be understood as descriptions of properties or functional features of the corresponding block, corresponding element, corresponding device, or corresponding system.

[0132] As used herein, the term "module" refers to logic for performing one or more operations consistent with the present disclosure that can be implemented using hardware components or devices, software or firmware running on a processing unit, or a combination thereof. Software and firmware can be embodied as instructions and / or data stored on a non-transient computer-readable storage medium. As used herein, the term "circuitry" can include, alone or in any combination, non-programmable (hard-wired) circuitry, programmable circuitry (such as a processing unit), state machine circuitry, and / or firmware that stores instructions that can be executed by a programmable circuitry. The modules described herein can be embodied collectively or individually as circuitry that forms part of a computing system. Thus, any one of the modules can be implemented as a circuitry. A computing system referred to as being programmed to perform a method can be programmed to perform the method via software, hardware, firmware, or a combination thereof.

[0133] Any of the disclosed methods (or portions thereof) may be implemented as computer-executable instructions or computer program products. Such instructions may enable a computing system or one or more processing units capable of executing computer-executable instructions to perform any of the disclosed methods. As used herein, the term "computer" refers to any computing system or device described or mentioned herein. Thus, the term "computer-executable instructions" refers to instructions that can be executed by any computing system or device described or mentioned herein.

[0134] Computer-executable instructions can be, for example, part of an operating system of a computing system, an application stored locally on the computing system, or a remote application accessible to the computing system (e.g., via a web browser). Any of the methods described herein can be performed by computer-executable instructions that are executed by a single computing system or by one or more networked computing systems operating in a network environment. Computer-executable instructions and updates to the computer-executable instructions can be downloaded to a computing system from a remote server.

[0135] Furthermore, it should be understood that implementation of the disclosed techniques is not limited to any particular computer language or program. For example, the disclosed techniques can be implemented by software written in C++, C#, Java, Perl, Python, JavaScript, Adobe Flash, C#, assembly language, or any other programming language. Likewise, the disclosed techniques are not limited to any particular computer system or any particular type of hardware.

[0136] Furthermore, any of the software-based examples (including, for example, computer-executable instructions for causing a computer to perform any of the disclosed methods) can be uploaded, downloaded, or remotely accessed via suitable communication means, including, for example, the Internet, the World Wide Web, an intranet, cables (including fiber optic cables), magnetic communications, electromagnetic communications (including RF, microwave, ultrasonic, and infrared communications), electronic communications, or other such communications means.

[0137] The disclosed methods, apparatus, and systems should not be construed as limiting in any way. Instead, the present disclosure is directed to all novel and non-obvious features and aspects of each disclosed example, individually and in various combinations and subcombinations with each other. The disclosed methods, apparatus, and systems are not limited to any specific aspect or feature or combination thereof, nor do the disclosed examples require any one or more specific advantages to exist or to solve any one or more specific problems.

[0138] The theories of operation, scientific principles, or other theoretical descriptions presented herein with reference to the devices or methods of the present disclosure are provided for the purpose of better understanding and are not intended to limit the scope. The devices and methods in the appended claims are not limited to those devices and methods that function in the manner described by such theories of operation.

[0139] The following claims are hereby incorporated into the detailed description, wherein each claim may stand on its own as a separate example. It should also be noted that although a dependent claim in the claims refers to a specific combination with one or more other claims, other examples may include combinations of the dependent claim with the subject matter of any other dependent or independent claims. Such combinations are expressly set forth herein unless a specific combination is stated to be unintended in individual cases. Furthermore, even if a claim is not directly limited to referring to any other independent claim, features of that claim should also be included with respect to any other independent claim.

Claims

1. An apparatus comprising interface circuitry, machine-readable instructions, and processor circuitry, the processor circuitry configured to execute the machine-readable instructions to perform the following operations: obtaining a physical layout of a first processor circuit system including a plurality of processor cores and thermal information of the plurality of processor cores; A first processor core of the plurality of processor cores is determined for executing a first workload based on the physical layout of the first processor circuitry and the thermal information of the plurality of processor cores.

2. The device according to claim 1, wherein The thermal information for the plurality of processor cores includes at least one of a temperature measurement for each of the plurality of cores, a thermal throttle threshold for each of the plurality of cores, or a heat dissipation value for each of the plurality of cores.

3. The device according to claim 1, wherein At least The first processor core has a lowest temperature measurement among the plurality of processor cores, the first processor core has a temperature below a predetermined value, and the first processor core has a temperature below the temperature measurements of at least half of the plurality of processor cores.

4. The device according to claim 1, wherein The processor circuitry is configured to execute the machine-readable instructions to determine a second processor core among the plurality of processor cores for executing a second workload based on the physical layout of the first processor circuitry, the thermal information of the plurality of processor cores, and / or the determined first processor core executing the first workload.

5. The device according to claim 4, wherein The first processor core and / or the second processor core are determined such that at least The first processor core and the second processor core are not adjacent processor cores within the physical layout of the first processor circuitry, the first processor core and the second processor core have a predetermined spacing, there are a predetermined number of processor cores between the first processor core and the second processor core, or there is a maximum possible spacing within the physical layout between the first processor core and the second processor core.

6. The device according to claim 1, wherein The processor circuitry is to execute the machine-readable instructions to determine a partitioning of the physical layout of the first processor circuitry into a plurality of regions, wherein each of the plurality of regions includes one or more processor cores of the plurality of processor cores.

7. The device according to claim 6, wherein The processor circuitry is to execute the machine-readable instructions to determine that the first processor core is part of a first region of the plurality of regions, the first region having a lowest average processor core temperature measurement.

8. The device according to claim 7, wherein At least The first processor core is randomly selected among the processor cores in the first region, or the first processor core is the processor core in the first region having a lowest processor core temperature measurement.

9. The device according to claim 6, wherein The processor circuitry is to execute the machine-readable instructions to determine that the second processor core is part of a second region of the plurality of regions, the second region having a second lowest average processor core temperature measurement.

10. The device according to claim 9, wherein At least The second processor core is randomly selected among the processor cores in the second region, or the second processor core is the processor core in the second region having a lowest processor core temperature measurement.

11. The device according to claim 6, wherein Each of the plurality of regions includes a same number of processor cores from the plurality of processor cores.

12. The device according to claim 11, wherein Each of the plurality of regions includes between 2 and 10 processor cores of the plurality of processor cores.

13. The device according to claim 1, wherein The processor circuitry is to execute the machine-readable instructions to assign the first workload to the first processor core.

14. The device according to claim 1, wherein The physical layout includes the spatial positioning of processor cores within the processor circuitry.

15. The device according to claim 1, wherein The physical layout includes the spatial positioning of processor cores relative to each other within a 2-dimensional plane within the processor circuitry.

16. An apparatus comprising interface circuitry, machine-readable instructions, and processor circuitry, the processor circuitry configured to execute the machine-readable instructions to: obtaining a physical layout of a first processor circuit system including a plurality of processor cores and thermal information of the plurality of processor cores; identifying, based on thermal information of the first processor core, a first processor core among the plurality of processor cores that is executing a first workload; determining a second processor core of the plurality of processor cores for executing the first workload based on the physical layout of the first processor circuitry and the thermal information of the plurality of processor cores, wherein a temperature measurement of the first processor core is higher than a temperature measurement of the second processor core; and The first workload is assigned to the second processor core.

17. A method comprising: obtaining a physical layout of a first processor circuit system including a plurality of processor cores and thermal information of the plurality of processor cores; A first processor core of the plurality of processor cores is determined for executing a first workload based on the physical layout of the first processor circuitry and the thermal information of the plurality of processor cores.

18. The method according to claim 17, wherein The thermal information for the plurality of processor cores includes at least one of a temperature measurement for each of the plurality of cores, a thermal throttle threshold for each of the plurality of cores, or a heat dissipation value for each of the plurality of cores.

19. The method according to claim 17, wherein At least: the first processor core has a lowest temperature measurement among the plurality of processor cores, the first processor core has a temperature below a predetermined value, and the first processor core has a temperature below the temperature measurements of at least half of the plurality of processor cores.

20. The method of claim 17, further comprising: A second processor core of the plurality of processor cores is determined to execute a second workload based on the physical layout of the first processor circuitry, the thermal information of the plurality of processor cores, and / or the first processor core determined to execute the first workload.

21. The method according to claim 20, wherein The first processor core and / or the second processor core are determined so that at least: the first processor core and the second processor core are not adjacent processor cores within the physical layout of the first processor circuit system, the first processor core and the second processor core have a predetermined spacing, a predetermined number of processor cores exist between the first processor core and the second processor core, or a maximum possible spacing within the physical layout exists between the first processor core and the second processor core.

22. The method of claim 17, further comprising: A partitioning of the physical layout of the first processor circuitry into a plurality of regions is determined, wherein each of the plurality of regions includes one or more processor cores of the plurality of processor cores.

23. The method of claim 22, further comprising: It is determined that the first processor core is part of a first region of the plurality of regions, the first region having a lowest average processor core temperature measurement.

24. A non-transitory machine-readable storage medium comprising program code, which, when executed, causes a machine to perform the method according to claim 17.

25. A computer program product comprising a program code for performing the method according to claim 17 when the computer program is executed on a computer, a processor or a programmable hardware component.

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