Cache function logic verification method, storage medium and electronic device

Abstract

The invention discloses a cache function logic verification method, a storage medium and an electronic device.The cache function logic verification method comprises the steps that read return data and main storage transmission data are obtained, the read return data refer to data returned from a cache after the cache searches for data related to a read access request, and the main storage transmission data refer to the data returned from the cache after the cache searches for the data related to the read access request; the data transmitted by the main memory refers to data read from the main memory in a data searching process of the cache; according to an access address in the read access request, first prediction data related to the access address is obtained through a prediction mechanism, and the prediction mechanism is used for searching a corresponding relation between the address and the prediction data; and judging the correctness of the function logic of the cache at least according to the first prediction data, the read return data and the main memory transmission data to obtain a judgment result.

Description

Technical Field

[0001] The present application relates to the field of cache verification, and in particular to a cache functional logic verification method, storage medium, and electronic device. Background Art

[0002] Cache is a temporary storage device between the CPU and main memory, used to store frequently used data. To ensure cache functionality, cache designs are typically verified before production. Cache verification primarily ensures that the cache system correctly executes functions such as cache hit detection, data consistency, and replacement policies when processing data reads and writes. Existing technologies typically verify cache accuracy by comparing written and read data.

[0003] However, this approach has some drawbacks. Primarily, it cannot effectively distinguish whether data originates from cache or main memory, cannot accurately determine cache hits, and cannot capture potential errors in the cache's internal control logic, resulting in insufficient verification coverage and accuracy. These issues can lead to missed errors, impacting system reliability.

[0004] Accordingly, a new cache verification solution is needed in this field to solve the above problems. Summary of the Invention

[0005] In order to overcome the above-mentioned defects, the present invention is proposed to provide a solution or at least partially solve the technical problem in the prior art that during the cache verification process, it is impossible to distinguish whether the data comes from the cache or the main memory.

[0006] In a first aspect, the present invention provides a method for verifying the functional logic of a cache, in response to sending a read access request, the method comprising: obtaining read return data and main memory transmission data, wherein the read return data refers to data returned from the cache after the cache searches for data related to the read access request, and the main memory transmission data refers to data read from the main memory by the cache during the data search process; according to the access address in the read access request, obtaining first prediction data related to the access address through a prediction mechanism, wherein the prediction mechanism is used to determine the prediction data corresponding to the access address through simulation without relying on the cache or the main memory; judging the correctness of the functional logic of the cache based on at least the first prediction data, the read return data and the main memory transmission data to obtain a judgment result.

[0007] As an alternative or supplement to the above scheme, in a method according to an embodiment of the present invention, the correctness of the functional logic of the cache is judged at least based on the first prediction data, the read return data and the main memory transmission data to obtain a judgment result, including: determining the consistency between the read return data and the first prediction data; judging whether the functional logic of the cache is correct based on the consistency and whether the main memory transmission data includes data consistent with the first prediction data to obtain a judgment result, wherein the consistency is used to indicate whether the read return data is the same as the first prediction data.

[0008] As an alternative or supplement to the above scheme, in a method according to an embodiment of the present invention, the method also includes: simulating the behavior of the cache based on the access address to obtain an expected hit result, wherein the expected hit result is used to predict whether the first prediction data is located in the cache; judging the correctness of the functional logic of the cache based on at least the first prediction data, the read return data and the main memory transmission data to obtain a judgment result, including: judging the correctness of the functional logic of the cache based on the expected hit result, the first prediction data, the read return data and the main memory transmission data to obtain a judgment result.

[0009] As an alternative or supplement to the above scheme, in a method according to an embodiment of the present invention, the correctness of the functional logic of the cache is judged based on the expected hit result, the first prediction data, the read return data and the main memory transmission data to obtain a judgment result, including: determining the consistency between the read return data and the first prediction data; judging the correctness of the functional logic of the cache based on the expected hit result, the consistency and whether the main memory transmission data includes data consistent with the first prediction data to obtain a judgment result.

[0010] As an alternative or supplement to the above scheme, in a method according to an embodiment of the present invention, the correctness of the functional logic of the cache is judged based on the expected hit result, consistency, and whether the main memory transmission data includes data consistent with the first prediction data, and a judgment result is obtained, including: if the expected hit result is a hit, the main memory transmission data is empty, and the consistency is consistent, the functional logic of the cache is correct, wherein a hit means that there is data related to the access address in the cache table, and the main memory transmission data is empty to indicate that the main memory has not sent data to the cache; if the expected hit result is a miss, the consistency is consistent, the main memory transmission data includes data consistent with the first prediction data, and the functional logic of the cache is correct, wherein a miss means that there is no data related to the access address in the cache table.

[0011] As an alternative or supplement to the above scheme, in a method according to an embodiment of the present invention, the correctness of the functional logic of the cache is judged based on the expected hit result, consistency, and whether the main memory transmission data includes data consistent with the first prediction data, and a judgment result is obtained, including: when the expected hit result is a hit, the main memory transmission data is empty and the consistency is inconsistent, or the main memory transmission data is not empty, the functional logic of the cache is wrong; when the expected hit result is a miss, the consistency is inconsistent, or the main memory transmission data does not include the first prediction data, the functional logic of the cache is wrong.

[0012] As an alternative or supplement to the above scheme, in a method according to an embodiment of the present invention, the behavior of the cache is simulated according to the access address to obtain an expected hit result, including: according to the access address, searching the tag related to the access address from the cache table to obtain the expected hit result, wherein the cache table is used to simulate the association relationship between the tag and the predicted data in the cache.

[0013] As an alternative or supplement to the above scheme, according to the access address in the read access request, first prediction data related to the access address is obtained through a prediction mechanism, including: according to the access address, searching from a preset main memory table to obtain first prediction data corresponding to the access address, wherein the main memory table is used to simulate the correspondence between the address and the prediction data in the main memory; or, when the expected hit result is a hit, according to the access address, searching from the cache table, and combining the association between the tag and the prediction data to obtain the first prediction data; when the expected hit result is a miss, the data related to the access address is read from the main memory table to the cache table, and the first prediction data is obtained from the data related to the access address.

[0014] In a second aspect, a control device is provided, which includes a processor and a storage device, the storage device being suitable for storing multiple computer programs, and the computer programs being suitable for being loaded and run by the processor to execute the cache functional logic verification method of any one of the technical solutions of the above-mentioned cache functional logic verification method.

[0015] In a third aspect, a computer-readable storage medium is provided, which stores a plurality of computer programs, and the computer programs are suitable for being loaded and run by a processor to execute the cache functional logic verification method of any one of the technical solutions of the above-mentioned cache functional logic verification method.

[0016] The above one or more technical solutions of the present invention have at least one or more of the following beneficial effects:

[0017] In the technical solution of the present invention, by monitoring the data read from the main memory during a cache lookup, it is possible to determine, to a certain extent, whether the read return data comes from the cache or the main memory during the execution of a read access request. This makes the judgment of the cache function logic more accurate. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0019] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0020] Figure 1 This is a schematic diagram of the architecture of cache verification in the prior art;

[0021] Figure 2 yes Figure 1 Schematic diagram of the process of architecture execution;

[0022] Figure 3 This is a schematic diagram of a cache function logic verification system provided by an embodiment of the present application;

[0023] Figure 4 yes Figure 3 A schematic diagram of the system operation process;

[0024] Figure 5 This is a schematic diagram of a cache functional logic verification architecture provided by an embodiment of the present application;

[0025] Figure 6 This is a flow chart of a cache functional logic verification method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0026] In order to enable those skilled in the art to better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of this application.

[0027] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in a sequence other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0028] Here we first explain some terms involved in the present invention.

[0029] Main memory: The main memory in a computer system used to store data and instructions during program execution, usually referring to dynamic random access memory (DDR memory), which has the characteristics of large capacity and moderate access speed.

[0030] Figure 1 Provides a schematic diagram of the cache validation architecture. Figure 1 It includes multiple parts, such as: master module (master), reference model (refm), function comparison module (scoreboard) and device under test (DUT). The DUT here mainly includes cache and its downstream DDR / SRAM model (or "main memory"). Figure 1 It can be seen that the main control module includes multiple submodules, each of which has different functions. In this embodiment, the main control module is mainly used to simulate the access behavior of the CPU. Figure 1 The architecture in the cache simulates the CPU's read and write operations on the cache and compares the write and read results of data at the same address to determine whether the cache's functional logic is implemented correctly.

[0031] For details, please refer to Figure 2 You can first write to the cache, and then verify the correctness of the cache function logic through a read operation. Figure 2As shown in (A), in a write operation, the main control module can write data to the device under test and the reference module. Specifically, the driver initiates a write access request to the device under test through the bus interface. Usually, the write access request contains write data and write address, wherein the write data is used to indicate the actual data written to the device under test, and the write address is used to indicate the physical address to which the write data is to be written. On the one hand, the write access request is sensed by the monitor, which then samples the write access request and extracts at least the write data and write address, and sends the extracted data to the reference module. The reference module then saves the information (write data and write address) transmitted by the monitor. In other words, the reference module stores the association between data and address. On the other hand, the write access request is sent to the device under test and stored in a specific location according to the write address. As a result, data is written into the device under test.

[0032] like Figure 2 As shown in (B), in a read operation, the driver initiates a read access request to the cache through the bus interface. The read access request includes at least a read address, which is used to indicate the target address of the data to be read. Subsequently, the monitor also senses the read access request and then sends the read access request to the reference module. After receiving the read access request, the reference module obtains predicted data related to the read address based on the information of the read access request (such as the read address) and the association between the stored data and the address. On the other hand, the read access request is also sent to the device under test. After receiving the read access request, the device under test searches at least according to the read address and returns data after the search (or the data is called "read return data"). At the same time, the monitor collects the returned data and sends the read return data to the functional comparison module.

[0033] The functional comparison module then obtains the predicted data from the reference module and the read data returned by the device under test. It then compares the two data sets and, based on whether they match, determines whether the cache access behavior conforms to the expected logic, thereby verifying the correctness of the cache functionality. If the comparison results are inconsistent, the expected functional logic is considered to be inconsistent and is recorded as a fail. If the comparison results are consistent, the expected functional logic is considered to be consistent and is recorded as a pass.

[0034] Although, Figure 2 The solution verifies the consistency of write data and read return data, but it cannot determine whether the read return data is obtained from the cache or from the next level of main memory. In this way, it is unclear where the data comes from and whether the functional logic inside the cache is correct.

[0035] In view of this, an embodiment of the present application proposes a cache functional logic verification system, which simulates the logic of the device under test and compares the simulation results, write data, read return data and main memory transmission data to determine whether the read return data comes from the cache or the main memory, and combines the simulation results to realize the verification of the cache functional logic.

[0036] The cache function logic verification system operates in the same way as the aforementioned one when facing a write access request. Figure 2 The operation of (A) is similar, using the main memory table to store the address and prediction data in the write access request, which will not be repeated here.

[0037] like Figure 3 As shown, the cache function logic verification system includes: a bus monitoring module, a tag management module, a cacheline management module and a three-party comparison module. Among them, the cacheline management module is used to obtain relevant prediction data based on the read access request. For example, the cacheline management module can determine the first prediction data based on the prediction mechanism. In this embodiment, the first prediction data is regarded as the data that the cache will return when the cache function logic is normal. In other words, the first prediction data is a reference value obtained in theory. Among them, the prediction mechanism refers to determining the prediction data corresponding to the access address through simulation without relying on the cache or main memory. Generally speaking, the prediction mechanism can determine the first prediction data through similar methods such as the main memory table or the cache table. For example, the access address can be extracted from the read access request, and then the main memory table can be searched according to the access address to obtain the prediction data related to the access address (or "first prediction data"). The main memory table is used to simulate the information stored in the main memory, and the main memory table stores the address and the prediction data corresponding to the address.

[0038] To better understand the main memory table, an example is provided here to illustrate how the main memory table is constructed. Before automatic verification begins, the device under test typically does not store any data. At the start of automatic verification, data is first written to the device under test. At this point, the master control module issues a write access request, which includes at least the data to be written and a specified write address. Subsequently, the device under test receives the write access request and writes the data to the specified write address. Furthermore, the master control monitor, mst_monitor, receives the write access request and sends it to the cacheline management module. As previously mentioned, the write access request includes at least the data to be written and a specified write address. The cacheline management module then writes the data in the write access request to the main memory table, which then stores a copy of the data to be written and its associated address. For ease of description, the data in the main memory table is referred to as predicted data. Thus, when the master control module issues a read access request, the cacheline management module can find the predicted data corresponding to the access address in the read access request based on the access address in the read access request.

[0039] The management module of the tag is used to predict the expected hit result of this access based on the read access request. The expected hit result is used to predict whether the data related to the read access request (i.e., the first predicted data, referred to here as "target data" for ease of understanding) is located in the cache. The expected hit results include cache hits and cache misses. A cache hit means that the target data has been stored in the cache, and when the target data is read, the data can be read directly from the cache without accessing the main memory; while a cache miss means that the target data is not cached in the cache, and the target data needs to be read from the main memory when the data is read. In other words, the role of the tag management module is to predict whether the target data of this access exists in the cache based on the read access request, so as to determine whether the read access request will read data from the cache or external storage. In some embodiments, the tag management module is preset with a program for simulating the cache and a cache table used in conjunction with the program. The cache table is used to simulate a real cache. For example, the relationship between the tag and the predicted data in the cache can be simulated in the cache table. The tag management module can search the cache table for tags related to the access address based on the access address to obtain the expected hit result. In other words, the tag management module can obtain tags related to the target data based on the access address and search the cache table for tags.

[0040] In order to better understand the cache simulation program and cache table, an example is given here.

[0041] Assuming that there is no data written from the main memory in the cache at this time, there is also no data in the cache table. When the main control module sends a read access request (hereinafter referred to as read access request A), since there is no data in the cache, read access request A will read data from the main memory and return the required target data to the main control module. During this process, the main memory will send the data related to the access address (or "cache line") to the cache. The cache then finds the read return data (i.e., the target data) from the cache line and sends the read return data to the main control module. When the main control module requests the target data, the main memory does not only send the target data to the cache. To reduce the number of times the main memory sends data to the cache, the main memory generally sends data located near the target data to the cache. Here, the target data and other sent data are collectively referred to as a cache line. Therefore, after this read access request A is completed, the cache stores the data in the cache line. When the target data required by the next read access request is in the cache, the cache will send the data in the cache line to the main control module without having to read the data from the main memory again, thereby speeding up the data reading efficiency.

[0042] In this example, the main memory writes the cache line containing the target data into the cache. As mentioned above, the data in the main memory table is consistent with the data in the main memory. When a read access request A is issued, the program simulating the cache can determine the information of the cache line sent by the main memory to the cache based on the read access request A; in other words, the program simulating the cache can infer that some data in the main memory table will be written into the cache. At this time, the program simulating the cache can read the same data as the cache line from the main memory table to the cache table. As a result, the cache table stores the same data as the real cache. When the main control module sends another read access request, the Tag management module can determine whether the target data corresponding to the access request is stored in the cache table based on the cache table, and then predict whether this access will hit the cache.

[0043] The bus snooping module is configured to monitor data transmitted on the first and second main lines during the execution of a read access request. The first main line refers to the transmission line between the main control module and the cache, while the second main line is located within the device under test and connects the main memory and the cache. For example, during the execution of a read access request, the bus snooping module monitors the first main line to obtain a first monitoring result, and monitors the second main line to obtain a second monitoring result. The first monitoring result includes read return data returned from the device under test in response to the read access request. As can be appreciated, each read access request generates read return data regardless of whether a cache hit occurs during the execution of the read access request. The second monitoring result includes whether data is read from the main memory during the execution of the read access request, as well as the data read from the main memory. For example, the bus snooping module may include a first monitoring module and a second monitoring module, respectively configured to monitor the first and second buses. The second monitoring module in the bus snooping module may collect data transmitted on the first and second buses to determine whether data was transferred from the main memory to the cache during the execution of the read access request, thereby determining whether the read return data originated from the cache or the main memory. The bus monitoring module can serve as a slave interface, providing reference data for the device under test to access the main memory, and performing a three-way comparison with the prediction results of the tag management module and the cacheline management module to ensure the correctness of the cache logic.

[0044] The three-party comparison module is used to determine whether the cache logic is correct based on the prediction results of the cacheline management module, the prediction results of the tag management module, and the monitoring results of the bus monitoring module. Specifically, in the above, the cacheline management module obtained the prediction data; the tag management module obtained the predicted hit result about the cache; the bus monitoring module obtained the read return data returned by the device under test, as well as the data read from the main memory during the execution of the read access request. The three-party comparison module can predict whether the cache logic is correct based on these data. Among them, the tag management module simulates the operation process of the cache based on the read access request and the internal preset program. In other words, the tag management module predicts the result when the functional logic of the cache is predicted to be normal. Therefore, the prediction results of the tag management module are cache hits and cache misses, which are discussed separately.

[0045] 1) The prediction result of the Tag management module is a cache hit

[0046] If the prediction result of the tag management module is a cache hit, the function logic of the cache is judged to be correct based on the monitoring result of the bus monitoring module and the prediction result of the cacheline management module. Figure 4As shown, when the prediction result of the Tag management module is a cache hit, based on the monitoring result of the second monitoring module on the second bus, it is determined whether the main memory has an operation to send data to the cache. If there is such an operation, it is determined that the functional logic of the cache at this time is wrong. If there is no such operation, further, the actual return data obtained by the first monitoring module monitoring the first bus and the predicted data of the cacheline management module are compared, and whether the functional logic of the cache is correct is determined based on the comparison result. For example, when the actual return data is consistent with the predicted data, it means that the functional logic of the cache is correct; otherwise, it means that the functional logic of the cache is wrong.

[0047] For example, the prediction result of the Tag management module is a cache hit, which means that when the logical function of the cache is correct, the target data related to the read access request will be stored in the cache. Therefore, under the premise that the logical function of the cache is correct, data will not be read from the main memory. In other words, in this case, the main memory will not send data to the cache, so the monitoring result of the second monitoring module used to monitor the second bus is no monitored data. When the second monitoring module monitors that the main memory sends data to the cache, it means that for this read access request, the cache did not implement the function according to its preset logic. Therefore, when the second monitoring module monitors that the main memory sends data to the cache, it is considered that the functional logic of the cache is wrong.

[0048] When the second monitoring module does not monitor the main memory sending data to the cache, it at least indicates that the cache is reading data from its internal part. However, it is still necessary to determine whether the real return data returned by the cache is consistent with the target data indicated by the read access request instruction. Only when the cache does not read data from the main memory and the real return data is consistent with the target data indicated by the read access request instruction, the functional logic of the cache is correct. Therefore, in this embodiment, when the second monitoring module does not monitor the main memory sending data to the cache, the real return data is compared with the predicted data. If the real return data is consistent with the predicted data, it means that the data returned by the cache is the target data indicated by the read access request. If they are inconsistent, it means that the data returned by the cache is wrong. In other words, the functional logic of the cache is wrong.

[0049] 2) The prediction result of the tag management module is a cache miss

[0050] In the case that the prediction result of the tag management module is a cache miss, the function logic of the cache is judged to be correct based on the monitoring result of the bus monitoring module and the prediction result of the cacheline management module. Figure 4As shown, when the prediction result of the tag management module is a cache miss, the monitoring result of the second monitoring module is used to determine whether the main memory has an operation to send data to the cache. If no such operation is performed, it is determined that the cache function logic is incorrect.

[0051] If this operation is performed, the predicted data of the cacheline management module, the data read by the second monitoring module, and the actual return data of the first monitoring module are further compared. As a possible implementation method, when the main memory sends data to the cache, the data is sent in units of cache lines, and the target data is stored in the cache line. In other words, the data contained in the cache line includes the target data. When making a comparison, the data read by the second monitoring module can be extracted first to obtain the specified data, wherein the specified data is determined based on the access address in the read access request. Then compare the specified data, the predicted data, and the actual return data. If the three are consistent, it means that the functional logic of the cache is correct. Otherwise, it means that the functional logic of the cache is wrong.

[0052] For example, if the tag management module predicts a cache miss, this indicates that, when the cache logic is functioning correctly, the target data associated with the read access request is stored in main memory. Therefore, during the execution of the read access request, the target data is transferred from main memory to the cache, resulting in data transfer on the second bus. If the second monitoring module detects no data transfer on the second bus, it can be considered a cache logic error. However, if the second monitoring module detects data transfer on the second bus, it can proceed to the next step of the judgment. This judgment involves comparing three sets of data: the cacheline management module's predicted data, the data read by the second monitoring module, and the actual data returned by the first monitoring module. If the data read by the second monitoring module contains multiple data items, the specific data can be determined based on the access address in the read access request. If the cache logic is functioning correctly, the specific data retrieved will be consistent with the target data; otherwise, they will be inconsistent. Subsequently, the specific data, predicted data, and actual data returned are compared.

[0053] Specifically, when the predicted data is inconsistent with the actual return data, the cache function logic is considered to be wrong; when the specified data is inconsistent with the predicted data, the cache function logic is also considered to be wrong. It should be noted that when the specified data is inconsistent with the actual return data, the predicted data may also be consistent with the actual return data. Therefore, when the external storage sends data to the cache, the data consistency between the specified data and the actual return data will also be compared. This is because when the logical function of the cache is abnormal, some behaviors will appear erroneous when executing a read access request. For example, the target data has been stored in the cache, but the cache will also read data from the main memory and then return the correct target data to the main control module. Therefore, judging the logical function of the cache only by the predicted data and the actual return data will reduce the accuracy of the judgment.

[0054] In addition, when the data sent from the main memory to the cache includes the correct target data, if the cache logic function is wrong, the actual returned data may not be consistent with the predicted data. Therefore, the predicted data may also be compared with the actual returned data to see if they are consistent.

[0055] In this way, the three-way comparison module analyzes data from the cacheline management module, the tag management module, the first monitoring module, and the second monitoring module to determine whether the cache's functional logic is correct. This allows the cache's functional logic verification system to not only verify the consistency of read and write data, but also to further determine whether the data hits the cache and its source, effectively identifying internal cache logic errors. Compared to traditional verification solutions, this significantly improves verification accuracy and coverage, resolving issues such as the inability to distinguish between hits and errors and the inability to locate the source of errors, achieving efficient and accurate verification of cache functional logic.

[0056] In order to better understand the functional logic verification system of the cache, here we combine Figure 5 A detailed description of the cache functional logic verification system.

[0057] exist Figure 5 In the current test environment, the first monitoring module and the second monitoring module can be set separately. In this way, the first monitoring module and the second monitoring module can be closer to the monitored bus, thereby avoiding signal interference caused by too long lines. Figure 5In the test, the mst_monitor in the main control module serves as the first monitoring module, and a second monitoring module is provided on the test platform. The second monitoring module may include a bus sampling agent (slv_agent) and a main memory monitor (slv_monitor). The bus sampling agent is the control unit of the second monitoring module, which is used to drive the main memory monitor to correctly start the sampling process during the execution of a read access request. The main memory monitor is used to monitor the operation of reading data from the main memory of the device under test during the execution of a read access request. Figure 5 In the embodiment of the present invention, the main memory transmits information to the cache or the main control module via the second main line (bus2). The main memory monitor can monitor the second main line during the execution of the read access request, thereby recording whether there is an operation to read data from the main memory during the execution of the read access request and the data read if there is a read data operation.

[0058] exist Figure 5 In the process, the master driver in the master control module sends a read access request to the device under test through the bus1 bus (i.e., the first bus). The first monitoring module then samples the bus1 bus and sends the sampled data to the reference module. The reference module may include a cacheline management module and a tag management module. The cacheline management module can obtain predicted data based on the access address in the read access request and send the predicted data to the three-party comparison module. In addition, the tag management module can obtain a hit prediction result based on the access address in the read access request and send the hit prediction result to the three-party comparison module. The read access request will also drive the device under test to return the corresponding data. During this process, the second monitoring module will sample bus2 and determine whether the main memory sends data to the cache during this process. If the main memory sends data to the cache, the data will be sampled. Finally, the three-party comparison module will make a comprehensive judgment based on the predicted data of the tag management module, the hit prediction result of the tag management module, and the data read by the second monitoring module to determine whether the functional logic of the cache is correct.

[0059] The specific implementation process of the above system is described below.

[0060] For example, Figure 6 The flowchart of a method for verifying the functional logic of a cache provided by an embodiment of the present application is shown. It is understood that the method can be executed by any device, equipment, platform, or equipment cluster with computing and processing capabilities. Figure 6 As shown, the cache function logic verification method may include the following steps:

[0061] Step S601: Obtain read return data and main memory transmission data.

[0062] In an embodiment, read return data refers to data returned from the cache after the cache searches for data related to the read access request. Main memory transfer data refers to data read from the main memory during the data search process of the cache.

[0063] Step S602: According to the access address in the read access request, first prediction data related to the access address is obtained through a prediction mechanism.

[0064] In this embodiment, the prediction mechanism refers to determining the predicted data corresponding to the access address through simulation without relying on cache or main memory. The prediction mechanism typically uses a cache table or main memory table in conjunction with the access address to search for data, thereby determining the first predicted data. In one possible implementation, based on the access address, a search is performed in a preset main memory table to obtain the first predicted data corresponding to the access address. The main memory table has been described in detail above and will not be repeated here.

[0065] Step S603: judging the correctness of the functional logic of the cache at least based on the first prediction data, the read return data and the main memory transmission data to obtain a judgment result.

[0066] In this embodiment, the consistency between the read return data and the first prediction data can be obtained based on the read return data and the first prediction data. And by analyzing the main memory transmission data, it is determined whether the main memory transmission data contains target data. For example, when the functional logic of the cache is normal, the main memory transmission data will include target data, and the target data is consistent with the main memory transmission data. Therefore, it is possible to determine whether the main memory transmission data is correct based on whether the main memory transmission data includes data consistent with the first prediction data. In this embodiment, it is possible to determine whether the functional logic of the cache is correct based on the consistency between the read return data and the first prediction data and whether the main memory transmission data includes data consistent with the first prediction data, and obtain a judgment result. That is, only when the consistency is consistent and the main memory transmission data includes data consistent with the first prediction data, can the functional logic of the cache be considered normal.

[0067] By monitoring the data read from the main memory during a cache lookup, it is possible to determine, to a certain extent, whether the read return data comes from the cache or the main memory during the execution of a read access request. This makes the cache's functional logic more accurate.

[0068] Furthermore, when determining the correctness of the cache's functional logic, the expected hit result can also be combined with the judgment. For example, the cache's behavior can be simulated based on the access address to obtain the expected hit result. Subsequently, the correctness of the cache's functional logic can be determined based on the expected hit result, the first predicted data, the read-return data, and the main memory transfer data to obtain a judgment result. The expected hit result is used to predict whether the first predicted data is located in the cache.

[0069] As a possible implementation method, based on the access address, a search is performed from the cache table to see if there is a tag related to the access address, and an expected hit result is obtained. The cache table is used to simulate the association between the tag and the predicted data in the cache. The tag can be searched according to the access address to determine whether the target data is in the cache table, and then the expected hit result is obtained. Specifically, when it is determined that the target data is not in the cache table, the expected hit result is a miss; when it is determined that the target data is in the cache table, the expected hit result is a hit. If it is a hit, the tag data related to the access address can be searched from the cache table, and the first predicted data can be obtained through the association between the tag and the predicted data. When the expected hit result is a miss, the cache table simulates the action of the cache, thereby reading the cache line (or "data related to the access address") from the main memory table to the cache table, and then obtaining the first predicted data from the cache line.

[0070] Subsequently, if the expected hit result is a hit, a search can be performed in the cache table based on the access address, and the first prediction data can be obtained by combining the association between the tag and the prediction data. If the expected hit result is a miss, the data related to the access address is read from the main memory table into the cache table, and the first prediction data is obtained from the data related to the access address. Those skilled in the art can conceive of other methods for obtaining the first prediction data based on the previous description, which will not be repeated here.

[0071] Furthermore, the consistency between the read return data and the first predicted data can be determined, and the correctness of the cache function logic can be judged based on the expected hit result, consistency, and whether the main memory transmission data includes data consistent with the first predicted data to obtain a judgment result. For example, if the expected hit result is a hit, the main memory transmission data is empty, and the consistency is consistent, the cache function logic is correct, wherein a hit means that data related to the access address exists in the cache table, and the main memory transmission data is empty to indicate that the main memory has not sent data to the cache. If the expected hit result is a miss, the consistency is consistent, and the main memory transmission data includes data consistent with the first predicted data, the cache function logic is correct, wherein a miss means that data related to the access address does not exist in the cache table. When the expected hit result is a hit, the main memory transmission data is empty and the consistency is inconsistent, or the main memory transmission data is not empty, the cache function logic is incorrect. When the expected hit result is a miss, the consistency is inconsistent, or the main memory transmission data does not include the first predicted data, the cache function logic is incorrect.

[0072] In this embodiment, the expected hit result is derived based on the cache table, main memory table, and a preset cache simulation program. The cache table and main memory table are used to simulate the data mobilization process of the cache after receiving a read access request. The cache simulation program further ensures that this mobilization process is identical to that of a real cache. The resulting expected hit result indicates whether the read access request will hit the cache if the cache's functional logic is normal.

[0073] Therefore, by obtaining the expected hit result and combining the consistency with whether the main memory transmission data includes data consistent with the first prediction data, the functional logic of the cache is judged to obtain a judgment result.

[0074] It should be pointed out that although the various steps in the above embodiments are described in a specific order, those skilled in the art will understand that in order to achieve the effects of the present invention, different steps do not have to be performed in such an order. They can be performed simultaneously (in parallel) or in other orders. These changes are within the scope of protection of the present invention.

[0075] It will be understood by those skilled in the art that the present invention can implement all or part of the processes in the method of the above embodiment by instructing the relevant hardware through a computer program, and the computer program can be stored in a computer-readable storage medium. When the computer program is executed by the processor, it can implement the steps of each of the above method embodiments. Among them, the computer program includes a computer program, and the computer program can be in source code form, object code form, executable file or some intermediate form. The computer-readable storage medium may include: any entity or device, medium, USB flash drive, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory, random access memory, electric carrier signal, telecommunication signal and software distribution medium that can carry the computer program. It should be noted that the content contained in the computer-readable storage medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable storage media do not include electric carrier signals and telecommunication signals.

[0076] Furthermore, the present invention also provides a control device. In one embodiment of a control device according to the present invention, the control device includes a processor and a storage device. The storage device can be configured to store a program for executing the functional logic verification method of the cache of the above-mentioned method embodiment, and the processor can be configured to execute the program in the storage device, which includes but is not limited to the program for executing the functional logic verification method of the cache of the above-mentioned method embodiment. For ease of explanation, only the parts related to the embodiment of the present invention are shown. For specific technical details not disclosed, please refer to the method part of the embodiment of the present invention. The control device can be a control device device formed by various electronic devices.

[0077] Furthermore, the present invention also provides a computer-readable storage medium. In a computer-readable storage medium embodiment according to the present invention, the computer-readable storage medium can be configured to store a program for executing the functional logic verification method of the cache of the above-mentioned method embodiment, and the program can be loaded and run by the processor to implement the functional logic verification method of the cache. For ease of explanation, only the parts related to the embodiment of the present invention are shown. For specific technical details not disclosed, please refer to the method part of the embodiment of the present invention. The computer-readable storage medium can be a storage device formed by various electronic devices. Optionally, the computer-readable storage medium in the embodiment of the present invention is a non-temporary computer-readable storage medium.

[0078] Furthermore, it should be understood that since the configuration of each module is merely for the purpose of illustrating the functional units of the apparatus of the present invention, the physical devices corresponding to these modules may be the processor itself, or a portion of the software in the processor, a portion of the hardware, or a combination of software and hardware. Therefore, the number of modules in the figure is merely illustrative.

[0079] Those skilled in the art will appreciate that the various modules in the device can be adaptively split or merged. Such splitting or merging of specific modules does not cause the technical solution to deviate from the principles of the present invention. Therefore, the technical solutions after splitting or merging will fall within the scope of protection of the present invention.

[0080] It should be noted that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of this application, and these improvements and modifications should also be regarded as the scope of protection of this application.

Claims

1. A method for verifying cache function logic, characterized in that: The method comprises: In response to a read access request, obtaining read return data and main memory transfer data, wherein the read return data refers to data returned from the cache after the cache searches for data related to the read access request, and the main memory transfer data refers to data read from the main memory during the data search process; According to the access address in the read access request, first prediction data related to the access address is obtained through a prediction mechanism, wherein the prediction mechanism is used to, without relying on cache or main memory, Determining prediction data corresponding to the access address by simulation; The correctness of the functional logic of the cache is judged at least based on the first prediction data, the read return data and the main memory transmission data to obtain a judgment result.

2. The method according to claim 1, characterized in that The determining the correctness of the functional logic of the cache based on at least the first prediction data, the read return data, and the main memory transmission data to obtain a determination result includes: Determining consistency between the read-return data and the first predicted data, wherein the consistency is used to indicate whether the read-return data is identical to the first predicted data; Based on the consistency and whether the main memory transmission data includes data consistent with the first predicted data, it is judged whether the functional logic of the cache is correct to obtain a judgment result.

3. The method according to claim 1, characterized in that The method further comprises: Predicting whether a cache hit occurs based on the access address to obtain an expected hit result, wherein the expected hit result is used to predict whether the first predicted data is located in the cache; The determining the correctness of the functional logic of the cache based on at least the first prediction data, the read return data, and the main memory transmission data to obtain a determination result includes: The correctness of the functional logic of the cache is judged based on the expected hit result, the first prediction data, the read return data and the main memory transmission data to obtain a judgment result.

4. The method according to claim 3, characterized in that The correctness of the functional logic of the cache is judged according to the expected hit result, the first prediction data, the read return data, and the main memory transmission data to obtain a judgment result, including: Determining consistency between the read-return data and the first predicted data; The correctness of the functional logic of the cache is judged based on the expected hit result, the consistency, and whether the main memory transmission data includes data consistent with the first predicted data to obtain a judgment result.

5. The method according to claim 4, characterized in that The correctness of the functional logic of the cache is judged based on the expected hit result, the consistency, and whether the main memory transmission data includes data consistent with the first predicted data, to obtain a judgment result, including: If the expected hit result is a hit, the main memory transmission data is empty, and the consistency is consistent, the functional logic of the cache is correct, wherein the expected hit result is a hit means that data related to the access address exists in the cache table, and the main memory transmission data is empty to indicate that the main memory has not sent data to the cache; If the expected hit result is a miss, the consistency is consistent, the main memory transmission data includes data consistent with the first predicted data, and the functional logic of the cache is correct, wherein the expected hit result is a miss, which means that there is no data related to the access address in the cache table.

6. The method according to claim 4 or 5, characterized in that The correctness of the functional logic of the cache is judged based on the expected hit result, the consistency, and whether the main memory transmission data includes data consistent with the first predicted data, to obtain a judgment result, including: In the case where the expected hit result is a hit, when the main memory transfer data is empty and the consistency is inconsistent, or the main memory transfer data is not empty, the functional logic of the cache is wrong; in the case where the expected hit result is a miss, when the consistency is inconsistent, or the main memory transfer data does not include the first prediction data, the functional logic of the cache is wrong.

7. The method according to any one of claims 3 to 6, characterized in that: The step of predicting whether a cache hit occurs based on the access address to obtain an expected hit result includes: According to the access address, a tag related to the access address is searched from a cache table to obtain an expected hit result, wherein the cache table is used to simulate the association relationship between the tag and the predicted data in the cache.

8. The method according to any one of claims 1 to 6, characterized in that: The obtaining, according to the access address in the read access request, first prediction data related to the access address through a prediction mechanism includes: According to the access address, searching in a preset main memory table to obtain first prediction data corresponding to the access address, wherein the main memory table is used to simulate the corresponding relationship between the address in the main memory and the prediction data; or, When the expected hit result is a hit, searching the cache table according to the access address and obtaining first predicted data by combining the association between the tag and the predicted data; When the expected hit result is a miss, the data related to the access address is read from the main memory table to the cache table, and the first prediction data is obtained from the data related to the access address.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a stored program, wherein the program executes the method according to any one of claims 1 to 8 when executed.

10. An electronic device comprising a memory and a processor, characterized in that: A computer program is stored in the memory, and the processor is configured to execute the method according to any one of claims 1 to 8 through the computer program.

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