Memory register, access method and device of memory register and medium

Abstract

The invention discloses a memory register, a memory register access method, a memory register access device and a medium, the memory register comprises an M * N Bank array formed by a plurality of SRAM Banks, M and N are integers greater than zero, each row in the Bank array comprises a plurality of Banks for storing the same data, and addresses corresponding to the plurality of Banks for storing the same data are the same; each Bank corresponds to a plurality of addresses, and the Banks in different rows correspond to different addresses; the Bank array corresponds to a plurality of read data channels and a plurality of write data channels and is used for simultaneously performing read operation and write operation on a plurality of Banks in the Bank array. According to the technical scheme provided by the embodiment of the invention, the problem of Bank conflict when a plurality of data processing requests access the same Bank at the same time can be avoided, the output bandwidth of the register is fully utilized, and the processing efficiency of the data requests is improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a memory register, a method for accessing the memory register, a device, and a medium. Background Art

[0002] Currently, in a memory register (MREG), different static random-access memory (SRAM) banks correspond to different addresses and store different data.

[0003] If multiple data processing requests access the same bank at the same time, bank conflicts are likely to occur, resulting in the inability to fully utilize the register output bandwidth. Summary of the Invention

[0004] The present invention provides a memory register, a memory register access method, a device and a medium, which can avoid the problem of bank conflict when multiple data processing requests access the same bank at the same time, fully utilize the output bandwidth of the register, and improve the processing efficiency of data requests.

[0005] According to one aspect of the present invention, a memory register is provided, wherein the memory register includes an M*N bank array consisting of a plurality of static random access memory banks, where M and N are integers greater than zero;

[0006] Each row in the Bank array includes multiple banks storing the same data, and the multiple banks storing the same data have the same corresponding addresses;

[0007] Each bank corresponds to multiple addresses, and banks in different rows have different addresses.

[0008] The Bank array corresponds to multiple read data channels and multiple write data channels, which are used to simultaneously perform read operations and write operations on multiple banks in the Bank array.

[0009] Optionally, the number of rows of the Bank array is 8 and the number of columns is 4; the four banks in each row of the Bank array are used to store the same data;

[0010] The eight banks in each column of the bank array correspond to two read data channels, which are used to read the data stored in each bank in the corresponding column;

[0011] The four banks in each row of the bank array correspond to one write data channel, which is used to write data into the four banks simultaneously.

[0012] Optionally, the number of rows of the Bank array is 8 and the number of columns is 4; the two banks in each row of the Bank array are used to store the same data;

[0013] The eight banks in each column of the bank array correspond to two read data channels, which are used to read the data stored in each bank in the corresponding column;

[0014] Each bank block in the bank array corresponds to one write data channel, which is used to write data into the bank in the corresponding bank block;

[0015] The number of rows and columns of the Bank block is 2, and the two banks in each row of the Bank block are used to store the same data.

[0016] According to another aspect of the present invention, a method for accessing a memory register is provided, the method comprising:

[0017] After receiving a read data request, determine a target read data channel among all read data channels according to the target address matched by the read data request, and use the target read data channel to read the data stored in the target Bank;

[0018] After receiving a write data request, a target write data channel is determined among all write data channels according to a target address matched by the write data request, and data is simultaneously written to multiple target banks using the target write data channel.

[0019] Optionally, determining a target read data channel among all read data channels according to a target address matched by the read data request includes:

[0020] Screening candidate read data channels from all read data channels according to the target address matched by the read data request and a pre-built read data channel mapping table;

[0021] The read data channel mapping table includes a mapping relationship between each read data channel and an address;

[0022] The working status of each candidate read data channel is polled, and a candidate read data channel with an idle working status is selected as a target read data channel.

[0023] Optionally, if four banks in each row of the Bank array in the memory register store the same data,

[0024] Determining a target write data channel among all write data channels according to a target address matched by the write data request, and using the target write data channel to simultaneously write data to multiple target banks, including:

[0025] Filtering a target write data channel from all write data channels according to a target address matched by the write data request and a pre-built write data channel mapping table;

[0026] The write data channel mapping table includes a mapping relationship between each write data channel and an address;

[0027] Use the target write data channel to write data to the four banks in the corresponding row simultaneously.

[0028] Optionally, if two banks in each row of the Bank array in the memory register store the same data,

[0029] Determining a target write data channel among all write data channels according to a target address matched by the write data request, and using the target write data channel to simultaneously write data to multiple target banks, including:

[0030] Determine, according to the target address matched by the write data request, a target Bank block corresponding to the target address, and use the write data channel corresponding to the target Bank block as the target write data channel;

[0031] According to the target address matched by the write data request, two target banks are determined in the target bank block, and the target write data channel is used to write data into the two target banks simultaneously.

[0032] According to another aspect of the present invention, a device for accessing a memory register is provided, the device comprising:

[0033] A read request module is configured to, upon receiving a read data request, determine a target read data channel from all read data channels according to a target address matched by the read data request, and use the target read data channel to read data stored in a target bank;

[0034] The write request module is configured to, upon receiving a write data request, determine a target write data channel among all write data channels according to a target address matched by the write data request, and use the target write data channel to write data to multiple target banks simultaneously.

[0035] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the memory register access method described in any embodiment of the present invention when executed.

[0036] According to another aspect of the present invention, a computer program product is provided. The computer program product includes a computer program. When the computer program is executed by a processor, the method for accessing a memory register according to any embodiment of the present invention is implemented.

[0037] The technical solution provided by an embodiment of the present invention provides a register stack structure composed of a bank array. For an address segment within a certain bank, multiple other banks are used to store the same data in the same address segment. This can avoid the problem of bank conflict when multiple data processing requests access the same bank at the same time. In this way, the output bandwidth of the register can be fully utilized and the processing efficiency of data requests can be improved.

[0038] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0040] Figure 1 is a schematic structural diagram of a memory register provided according to an embodiment of the present invention;

[0041] Figure 2a 1 is a schematic diagram of a read data channel configuration of a memory register provided according to an embodiment of the present invention;

[0042] Figure 2b 1 is a schematic diagram of a configuration of a write data channel of a memory register provided according to an embodiment of the present invention;

[0043] Figure 3a 1 is a schematic diagram of another configuration of a read data channel of a memory register provided according to an embodiment of the present invention;

[0044] Figure 3b 1 is a schematic diagram of another configuration of a write data channel of a memory register provided according to an embodiment of the present invention;

[0045] Figure 4 is a flowchart of a method for accessing a memory register provided according to an embodiment of the present invention;

[0046] Figure 5 is a flowchart of another method for accessing a memory register provided according to an embodiment of the present invention;

[0047] Figure 6 is a flowchart of another method for accessing a memory register provided according to an embodiment of the present invention;

[0048] Figure 7 1 is a schematic structural diagram of a memory register access device provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0049] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0050] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0051] Figure 1 A schematic diagram of the structure of a memory register provided by an embodiment of the present invention is shown in FIG. Figure 1 As shown, the memory register includes an M*N Bank array consisting of multiple SRAM Banks, where M and N are integers greater than zero.

[0052] In this embodiment, each row in the Bank array includes multiple banks storing the same data, and the addresses corresponding to the multiple banks storing the same data are the same. Each Bank corresponds to multiple addresses, and the addresses corresponding to banks in different rows are different. The Bank array corresponds to multiple read data channels (for example Figure 1 R0-R7 in the bank array, and this embodiment does not limit the number) and multiple write data channels are used to simultaneously perform read operations and write operations on multiple banks in the bank array.

[0053] In a specific embodiment, assuming Figure 1In the array shown, Bank 0 and Bank 8 in the first row store the same data and correspond to the same address (e.g., 0-31). When multiple data processing requests access the same address space (e.g., 0-31), they can be mapped to Bank 0 and Bank 8, respectively. Each data processing request physically accesses a different bank, enabling multiple data processing requests to access the same address segment. Each bank supports simultaneous read and write operations, but different read or write data channels cannot access the same bank in a single cycle.

[0054] In one implementation of this embodiment, after receiving multiple write data requests, the memory register first queries the physical address corresponding to each write data request based on the logical addresses corresponding to the multiple write data requests and the address mapping relationship pre-configured by the memory management unit. It then determines the write data channel that matches each write data request based on the physical address. Finally, it uses the matching write data channel to simultaneously write the data corresponding to the multiple write data requests. The write operation can support simultaneous writing by multiple ports, and the mapping relationship between write data channels and banks is configurable through software.

[0055] In another implementation of this embodiment, after receiving multiple read data requests, the memory register can query the physical address corresponding to each read data request based on the logical address corresponding to the read data request and the address mapping relationship pre-configured by the memory management unit, and then determine the read data channel matching each read data request based on the physical address, and finally use the matching read data channel to read data from the corresponding bank. Figure 1 As shown, read data channels R0 and R4 can read data from Bank0-Bank7, read data channels R1 and R5 can read data from Bank8-Bank15, read data channels R2 and R6 can read data from Bank16-Bank23, and read data channels R3 and R7 can read data from Bank24-Bank31.

[0056] Specifically, when determining the read data channel to be used, it can be allocated according to the idle status of the read data channel. Assuming that a read data request can be processed by four read data channels R0, R1, R2, and R3, the working status of each read data channel can be polled. For example, when the R0 port is occupied, the R1 port can be used to avoid congestion caused by concentrated access to a certain read data channel; or the working order of each read data channel can be configured according to a pre-set access cycle, and this embodiment does not limit this.

[0057] The technical solution provided by an embodiment of the present invention provides a register stack structure composed of a bank array. For an address segment within a certain bank, multiple other banks are used to store the same data in the same address segment. This can avoid the problem of bank conflict when multiple data processing requests access the same bank at the same time. In this way, the output bandwidth of the register can be fully utilized and the processing efficiency of data requests can be improved.

[0058] Figure 2a A schematic diagram of a read data channel configuration of a memory register provided in an embodiment of the present invention is shown in FIG. Figure 2a As shown, the bank array has 8 rows and 4 columns. The 4 banks in each row of the bank array are used to store the same data. The 8 banks in each column of the bank array correspond to 2 read data channels for reading the data stored in each bank in the corresponding column. Figure 2b A schematic diagram of a memory register write data channel configuration provided by an embodiment of the present invention is shown in FIG. Figure 2b As shown, each row of four banks in the bank array corresponds to one write data channel, which is used to write data into the four banks simultaneously. Each bank corresponds to 32 addresses.

[0059] In this embodiment, the address depth corresponding to the memory register can be 256. The four banks in the same row will store exactly the same 512-bit data, thereby increasing the processing bandwidth of the read data. Different banks in different rows store different data, and the corresponding addresses are also different. Figure 2a As shown, the four banks in each column (such as Bank0-3, Bank4-7, Bank8-11, etc.) can be used as a parallel processing group rcluster, and each rcluster can be accessed by only one read data channel in the same cycle.

[0060] Every two read data channels are interconnected with every two rclusters. For example, ports R0 and R4 can access rcluster0 and rcluster1, ports R1 and R5 can access rcluster2 and rcluster3, ports R2 and R6 can access rcluster4 and rcluster5, and ports R3 and R7 can access rcluster6 and rcluster7. Each of the eight read data channels can access all 256 addresses. Since each rcluster can only read one address per cycle, addresses 0-127 and 128-255 can only output a maximum of four data points per cycle. Furthermore, two read data channels cannot access the same rcluster in the same cycle. For example, when port R0 is accessing rcluster1, port R4 can only access rcluster0.

[0061] In this embodiment, if Figure 2b As shown in the figure, each of the eight write data channels (W0-W7) can access four banks in the same row. Since banks in the same row store the same data, when writing to the same address, the memory register writes the same data to all four banks in the row simultaneously. For an address depth of 256, each write data channel can access an address depth of 32, which can be represented by a 5-bit address index.

[0062] The technical solution provided by an embodiment of the present invention provides a register stack structure composed of a bank array, and uses 4 banks in each row to store the same data in the same address space. This can avoid the problem of bank conflicts when multiple data processing requests access the same bank at the same time, thereby making full use of the output bandwidth of the register and improving the processing efficiency of data requests.

[0063] Figure 3a A schematic diagram of a read data channel configuration of a memory register provided in an embodiment of the present invention is shown in FIG. Figure 3a As shown, the bank array has 8 rows and 4 columns. The two banks in each row of the bank array are used to store the same data. The eight banks in each column of the bank array correspond to two read data channels for reading the data stored in each bank in the corresponding column.

[0064] Figure 3b A schematic diagram of a memory register write data channel configuration provided by an embodiment of the present invention is shown in FIG. Figure 3b As shown, each bank block in the bank array corresponds to one write data channel, which is used to write data to the bank within the corresponding bank block. The bank block has two rows and two columns, and the two banks in each row of the bank block are used to store the same data. Each bank corresponds to 32 addresses.

[0065] In this embodiment, the address depth corresponding to the memory register can be 512. For the four banks in the same row, the first two banks will store exactly the same 512-bit data, and the last two banks will store exactly the same 512-bit data, to increase the read bandwidth. The first two banks and the last two banks in the same row store different data, and the corresponding addresses are also different, with an address difference of 256. The corresponding addresses of banks in different rows increase in value and store different data.

[0066] like Figure 3aAs shown, the 8 banks in each column of the bank array correspond to 2 read data channels, wherein the address space accessible to ports R0, R4, R1, and R5 is 0-255, and the address space accessible to ports R2, R6, R3, and R7 is 256-511.

[0067] like Figure 3b As shown, for an address depth of 512, each write data channel can access a 2x2 bank block. Within each bank block, two banks in the same row store the same data. Banks in between rows correspond to different addresses and store different data. Each write data channel can access an address depth of 64, represented by a 6-bit address index. Ports W0, W2, W4, and W6 can access addresses 0-255, while ports W1, W3, W5, and W7 can access addresses 256-511.

[0068] The technical solution provided by an embodiment of the present invention provides a register stack structure composed of a bank array, using the first two banks in each row to store the same data in the same address space, and the last two banks to store another identical data in the same address space. This can avoid the problem of bank conflict when multiple data processing requests access the same bank at the same time, thereby making full use of the output bandwidth of the register and improving the processing efficiency of data requests.

[0069] The memory register provided in this embodiment is as follows: Figure 2a-2b 、 Figure 3a-Figure 3b As shown in the figure, depending on the configuration method, the address depth can be selected between 256 and 512. While the number of banks remains unchanged, different register depths can be configured by configuring the number of banks used to store each piece of identical data. This allows for flexible response to different application scenarios and fully utilizes the output bandwidth and storage capacity of the register file. For example, in scalar computing scenarios, fewer banks can be configured to store the same data to increase the storage depth; in AI neural network scenarios, more banks can be configured to store the same data to increase the output bandwidth.

[0070] Figure 4 This is a flowchart of a method for accessing a memory register provided by an embodiment of the present invention. This embodiment is applicable to the case of accessing data to the above-mentioned memory register. The method can be executed by a memory register access device, which can be configured in the memory register. Figure 4 As shown, the method includes:

[0071] Step 410: After receiving a read data request, a target read data channel is determined among all read data channels according to a target address matched by the read data request, and the target read data channel is used to read data stored in a target Bank.

[0072] Step 420: After receiving the write data request, determine a target write data channel among all write data channels according to the target address matched by the write data request, and use the target write data channel to write data to multiple target banks simultaneously.

[0073] The technical solution provided by the embodiment of the present invention can avoid the problem of bank conflict when multiple data processing requests access the same bank at the same time by determining the target write data channel among all write data channels according to the target address matched by the read data request after receiving a read data request, and using the target write data channel to read the data stored in the target bank after receiving a write data request.

[0074] Figure 5 A flowchart of another method for accessing a memory register provided by an embodiment of the present invention, wherein four banks in each row of a bank array in the memory register store the same data, such as Figure 5 As shown, the method includes:

[0075] Step 510 : After receiving a read data request, select candidate read data channels from all read data channels according to a target address matched by the read data request and a pre-built read data channel mapping table.

[0076] The read data channel mapping table includes a mapping relationship between each read data channel and an address.

[0077] Step 520: Poll the working status of each candidate read data channel, select the candidate read data channel with an idle working status as the target read data channel, and use the target read data channel to read the data stored in the target Bank.

[0078] Step 530: After receiving the write data request, a target write data channel is selected from all write data channels according to the target address matched by the write data request and a pre-built write data channel mapping table.

[0079] The write data channel mapping table includes a mapping relationship between each write data channel and an address.

[0080] Step 540: Use the target write data channel to write data to the four banks in the corresponding row simultaneously.

[0081] The technical solution provided by the embodiment of the present invention is as follows: after receiving a read data request, according to the target address matched by the read data request and the read data channel mapping table, an alternative read data channel is screened from all read data channels, the working status of each alternative read data channel is polled, and an alternative read data channel with an idle working status is screened as a target read data channel, and the target read data channel is used to read the data stored in the target Bank; after receiving a write data request, according to the target address matched by the write data request and the write data channel mapping table, the target write data channel is screened from all write data channels, and the target write data channel is used to write data to the four banks in the corresponding row at the same time. This technical solution can avoid the problem of bank conflict when multiple data processing requests access the same Bank at the same time, thereby making full use of the output bandwidth of the register and improving the processing efficiency of data requests.

[0082] Figure 6 A flowchart of another method for accessing a memory register provided by an embodiment of the present invention, wherein two banks in each row of a bank array in the memory register store the same data, such as Figure 6 As shown, the method includes:

[0083] Step 610 : After receiving a read data request, select candidate read data channels from all read data channels according to a target address matched by the read data request and a pre-built read data channel mapping table.

[0084] The read data channel mapping table includes a mapping relationship between each read data channel and an address.

[0085] Step 620: Poll the working status of each candidate read data channel, select a candidate read data channel with an idle working status as a target read data channel, and use the target read data channel to read the data stored in the target Bank.

[0086] Step 630: After receiving the write data request, determine the target Bank block corresponding to the target address according to the target address matched by the write data request, and use the write data channel corresponding to the target Bank block as the target write data channel.

[0087] The write data channel mapping table includes a mapping relationship between each write data channel and an address.

[0088] Step 640: Determine two target banks in the target bank block according to the target address matched by the write data request, and use the target write data channel to write data to the two target banks simultaneously.

[0089] The technical solution provided by the embodiment of the present invention is as follows: after receiving a read data request, according to the target address matched by the read data request and the read data channel mapping table, alternative read data channels are screened from all read data channels, the working status of each alternative read data channel is polled, and the alternative read data channel with an idle working status is screened as the target read data channel, and the target read data channel is used to read the data stored in the target Bank; after receiving a write data request, according to the target address matched by the write data request, the target Bank block corresponding to the target address is determined, and the write data channel corresponding to the target Bank block is used as the target write data channel; according to the target address matched by the write data request, two target Banks are determined in the target Bank block, and the target write data channel is used to write data to the two target Banks at the same time. This technical solution can avoid the problem of Bank conflict when multiple data processing requests access the same Bank at the same time, thereby making full use of the output bandwidth of the register and improving the processing efficiency of data requests.

[0090] Figure 7 A schematic diagram of a memory register access device according to an embodiment of the present invention is provided. The device is applied to a memory register, such as Figure 7 As shown, the device includes: a read request module 710 and a write request module 720.

[0091] A read request module 710 is configured to, upon receiving a read data request, determine a target read data channel from among all read data channels according to a target address matched by the read data request, and use the target read data channel to read data stored in a target bank;

[0092] The write request module 720 is configured to, upon receiving a write data request, determine a target write data channel among all write data channels according to a target address matched by the write data request, and use the target write data channel to simultaneously write data to multiple target banks.

[0093] The technical solution provided by the embodiment of the present invention can avoid the problem of bank conflict when multiple data processing requests access the same bank at the same time by determining the target write data channel among all write data channels according to the target address matched by the read data request after receiving a read data request, and using the target write data channel to read the data stored in the target bank after receiving a write data request.

[0094] The read request module 710 includes:

[0095] a read data channel mapping table query unit, configured to filter candidate read data channels from all read data channels based on a target address matched by the read data request and a pre-built read data channel mapping table, wherein the read data channel mapping table includes a mapping relationship between each read data channel and an address;

[0096] The data read channel state polling unit is used to poll the working state of each of the candidate data read channels, and select the candidate data read channels with an idle working state as target data read channels.

[0097] The write request module 720 includes:

[0098] a first processing unit configured to, when four banks in each row of the bank array in the memory register store identical data, select a target write data channel from all write data channels based on a target address matched by the write data request and a pre-built write data channel mapping table; and simultaneously write the data to the four banks in the corresponding row using the target write data channel; wherein the write data channel mapping table includes a mapping relationship between each write data channel and an address;

[0099] The second processing unit is used to determine the target Bank block corresponding to the target address according to the target address matched by the write data request when two Banks in each row of the Bank array in the memory register store the same data, and use the write data channel corresponding to the target Bank block as the target write data channel; determine two target Banks in the target Bank block according to the target address matched by the write data request, and use the target write data channel to write the data into the two target Banks at the same time.

[0100] The above device can execute the methods provided by all the above embodiments of the present invention, and has the corresponding functional modules and beneficial effects of executing the above methods. For technical details not fully described in the embodiments of the present invention, please refer to the methods provided by all the above embodiments of the present invention.

[0101] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0102] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A memory register, characterized in that: The memory register includes an M*N Bank array consisting of a plurality of static random access memory Banks, where M and N are integers greater than zero; Each row in the Bank array includes multiple banks storing the same data, and the multiple banks storing the same data have the same corresponding addresses; Each bank corresponds to multiple addresses, and banks in different rows have different addresses. The Bank array corresponds to multiple read data channels and multiple write data channels, which are used to simultaneously perform read operations and write operations on multiple banks in the Bank array.

2. The memory register according to claim 1, wherein: The number of rows in the Bank array is 8, and the number of columns is 4; The four banks in each row of the bank array are used to store the same data; The eight banks in each column of the bank array correspond to two read data channels, which are used to read the data stored in each bank in the corresponding column; The four banks in each row of the bank array correspond to one write data channel, which is used to write data into the four banks simultaneously.

3. The memory register according to claim 1, wherein: The number of rows in the Bank array is 8, and the number of columns is 4; The two banks in each row of the bank array are used to store the same data; The eight banks in each column of the bank array correspond to two read data channels, which are used to read the data stored in each bank in the corresponding column; Each bank block in the bank array corresponds to one write data channel, which is used to write data into the bank in the corresponding bank block; The number of rows and columns of the Bank block is 2, and the two banks in each row of the Bank block are used to store the same data.

4. A method for accessing a memory register, characterized in that: Applied to the memory register according to any one of claims 1 to 3, the method comprising: After receiving a read data request, determine a target read data channel among all read data channels according to the target address matched by the read data request, and use the target read data channel to read the data stored in the target Bank; After receiving a write data request, a target write data channel is determined among all write data channels according to a target address matched by the write data request, and data is simultaneously written to multiple target banks using the target write data channel.

5. The method according to claim 4, characterized in that Determining a target read data channel among all read data channels according to a target address matched by the read data request includes: Screening candidate read data channels from all read data channels according to the target address matched by the read data request and a pre-built read data channel mapping table; The read data channel mapping table includes a mapping relationship between each read data channel and an address; The working status of each candidate read data channel is polled, and a candidate read data channel with an idle working status is selected as a target read data channel.

6. The method according to claim 4, characterized in that If the four banks in each row of the Bank array in the memory register store the same data, Determining a target write data channel among all write data channels according to a target address matched by the write data request, and using the target write data channel to simultaneously write data to multiple target banks, including: Filtering a target write data channel from all write data channels according to a target address matched by the write data request and a pre-built write data channel mapping table; The write data channel mapping table includes a mapping relationship between each write data channel and an address; Use the target write data channel to write data to the four banks in the corresponding row simultaneously.

7. The method according to claim 4, characterized in that If two banks in each row of the Bank array in the memory register store the same data, Determining a target write data channel among all write data channels according to a target address matched by the write data request, and using the target write data channel to simultaneously write data to multiple target banks, including: Determine, according to the target address matched by the write data request, a target Bank block corresponding to the target address, and use the write data channel corresponding to the target Bank block as the target write data channel; According to the target address matched by the write data request, two target banks are determined in the target bank block, and the target write data channel is used to write data into the two target banks simultaneously.

8. A memory register access device, characterized in that: Applicable to the memory register according to any one of claims 1 to 3, the device comprising: A read request module is configured to, upon receiving a read data request, determine a target read data channel from all read data channels according to a target address matched by the read data request, and use the target read data channel to read data stored in a target bank; The write request module is configured to, upon receiving a write data request, determine a target write data channel among all write data channels according to a target address matched by the write data request, and use the target write data channel to write data to multiple target banks simultaneously.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the memory register access method according to any one of claims 4 to 7 when executed.

10. A computer program product, characterized in that The computer program product comprises a computer program, which, when executed by a processor, implements the method for accessing a memory register according to any one of claims 4 to 7.

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