Active Antenna Unit (AAU) control system

Abstract

The present application provides an active antenna unit (AAU) control system, which relates to the field of communication technology. The system includes: an AAU; a host computer for generating first information transmitted to the AAU; an acceleration processor including at least two chips, the first chip being an SOC chip and the second chip being an FPGA chip; the first chip being used to parse the first information, obtain a first control instruction and / or data to be calculated in the first information, and transmit the data to be calculated to the second chip; the second chip being used to perform a calculation task on the data to be calculated, obtain calculation result data, and send the calculation result data to the AAU and / or the first chip. The present application adopts a collaborative working mode of the SOC chip and the FPGA chip to distribute control tasks and calculation tasks to different hardware units, which has the effect of improving the processing power and real-time performance of the system, thereby solving the problems of low computing efficiency and single processing power of the AAU control system in the prior art.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to an active antenna unit (AAU) control system. Background Art

[0002] Current technologies for remotely controlling active antenna units (AAUs) primarily utilize designs based on traditional computing platforms, such as central processing units (CPUs) or single field programmable gate arrays (FPGAs). However, these AAU control systems present the following technical challenges: 1. Low computational efficiency: Traditional remote control systems rely on general-purpose processors (such as central processing units (CPUs)) for data processing and control operations. Because CPUs cannot efficiently handle large numbers of parallel computing tasks, the overall processing power of the system is limited. This is particularly true for real-time data processing and high-performance computing, resulting in low computational efficiency and performance bottlenecks when processing large amounts of data. 2. Limited processing power: Most systems utilize a single hardware acceleration solution (such as FPGAs or CPUs). FPGA-based systems are suitable for highly parallel tasks (such as matrix operations and data stream processing), while CPU-based systems are more adept at control and decision-making tasks. Existing solutions struggle to effectively combine the advantages of both, failing to provide more flexible and efficient computing resource scheduling. Summary of the Invention

[0003] The purpose of the technical solution of this application is to provide an active antenna unit AAU control system to solve the problems of low computational efficiency and single processing capability of the AAU control system using the existing technology.

[0004] The present invention provides an active antenna unit (AAU) control system, including:

[0005] AAU;

[0006] A host computer, configured to generate first information to be transmitted to the AAU;

[0007] An acceleration processor is connected to the host computer and the AAU respectively; wherein the acceleration processor includes at least two chips, the first chip of the at least two chips is a system-on-chip (SOC) chip, and the second chip is a field programmable gate array (FPGA) chip;

[0008] The first chip is used to parse the first information, obtain the first control instruction and / or data to be calculated in the first information, and transmit the data to be calculated to the second chip;

[0009] The second chip is used to perform the calculation task of the data to be calculated, obtain calculation result data, and send the calculation result data to the AAU and / or the first chip.

[0010] Optionally, in the AAU control system, the AAU is configured to parse the calculation result data, execute a transmission task corresponding to the calculation result data, obtain an execution result, and transmit the execution result to the first chip via the second chip;

[0011] The first chip is further configured to parse the execution result and transmit the parsed execution result to the host computer.

[0012] Optionally, in the AAU control system, the first chip includes:

[0013] a data processing module, configured to parse the first information and obtain the first control instruction and / or the data to be calculated;

[0014] a direct memory access (DMA) module, configured to obtain the data to be calculated from the data processing module;

[0015] The first interface module is used to obtain the data to be calculated transmitted by the DMA module, and to package the data to be calculated and transmit it to the second chip.

[0016] Optionally, in the AAU control system, the DMA module is also used to cache the data to be calculated.

[0017] Optionally, in the AAU control system, the DMA module obtains the data to be calculated transmitted by the data processing module through an AXIS interface; and / or,

[0018] The DMA module transmits the data to be calculated to the first interface module through the AXIS interface.

[0019] Optionally, in the AAU control system, the second chip includes:

[0020] a second interface module, configured to receive the data to be calculated transmitted by the first chip, and decapsulate the data to be calculated;

[0021] A calculation module is used to perform the calculation task of the data to be calculated and obtain the calculation result data;

[0022] The encapsulation module is used to obtain the calculation result data transmitted by the calculation module, encapsulate the calculation result data, and then transmit it to the AAU.

[0023] Optionally, in the AAU control system, the computing module includes a media access control (MAC) unit for performing media access control on the computing result data and converting the computing result data into a standard communication protocol.

[0024] Optionally, in the AAU control system, the computing module obtains the data to be calculated transmitted by the second interface module through the AXIS interface; and / or

[0025] The packaging module obtains the calculation result data transmitted by the MAC unit through the medium independent interface MII.

[0026] Optionally, in the AAU control system, the first information includes one or more of the following:

[0027] Upgrade data;

[0028] Control instructions;

[0029] Business data.

[0030] At least one of the above technical solutions of this application has the following beneficial effects:

[0031] In the AAU control system described in the embodiment of the present application, the host computer is connected to the AAU through an acceleration processor. The acceleration processor includes a first chip which is a SOC chip, and a second chip which is a FPGA chip. The first chip and the second chip form a collaborative computing platform. The SOC chip is good at executing control and decision-making tasks, and is responsible for system management and scheduling of control tasks. The FPGA chip is capable of executing high-parallel task calculations and performs high-parallel data calculations. In this way, the control task processing and data processing are separated and executed through different chips to improve the data computing efficiency and processing capability of the information sent to the AAU, thereby solving the problems of low computing efficiency and single processing capability of the AAU control system in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiment below. The accompanying drawings are for illustration purposes only and are not to be considered as limiting the present application. The same reference symbols are used throughout the drawings to represent the same components. In the drawings:

[0033] Figure 1This is a schematic diagram of the structure of the AAU control system described in an embodiment of the present application;

[0034] Figure 2 This is a schematic diagram of the working principle of the acceleration processor in an embodiment of the present application. DETAILED DESCRIPTION

[0035] To make the technical problems, technical solutions, and advantages to be solved by this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0036] In order to solve the problems of low computing efficiency and single processing capability of the AAU control system using the existing technology, an embodiment of the present application provides an AAU control system, in which the host computer is connected to the AAU through an acceleration processor, and the acceleration processor includes a first chip which is a system-level integrated circuit (System on Chip, SOC) chip, and a second chip which is an FPGA chip. The first chip and the second chip form a collaborative computing platform, which utilizes the characteristics of the SOC chip that is good at executing control and decision-making tasks and is responsible for system management and scheduling of control tasks, and utilizes the function of the FPGA chip that can execute high-parallel task calculations to execute high-parallel data calculations. In this way, the control task processing and data processing are separated and executed by different chips to improve the data computing efficiency and processing capability of the information sent to the AAU, thereby solving the problems of low computing efficiency and single processing capability of the AAU control system in the existing technology.

[0037] like Figure 1 This is a schematic diagram of the structure of the active antenna unit AAU control system according to an embodiment of the present application, including:

[0038] AAU 10;

[0039] The host computer 20 is used to generate first information transmitted to the AAU 10;

[0040] The acceleration processor 30 is connected to the host computer 20 and the AAU 10 respectively; wherein the acceleration processor 30 includes at least two chips, wherein the first chip 31 of the at least two chips is a SOC chip, and the second chip 32 is a field programmable gate array FPGA chip;

[0041] The first chip 31 is used to parse the first information, obtain the first control instruction and / or data to be calculated in the first information, and transmit the data to be calculated to the second chip 32;

[0042] The second chip 32 is used to perform calculation tasks of the data to be calculated, obtain calculation result data, and send the calculation result data to the AAU 10 and / or the first chip 31.

[0043] In an embodiment of the present application, optionally, the acceleration processor 30 is connected to the host computer 20 via the Internet and to the AAU 10 via optical fiber, and remote control, remote monitoring or data upgrade of the AAU 10 is achieved through the host computer 20 and the acceleration processor 30.

[0044] Using the AAU control system described in this embodiment, the acceleration processor 30 includes at least two chips, which can be chips of different types. By including at least two chips of different types, the hardware unit for performing control task processing and the hardware unit for performing data processing on the acceleration processor 30 are separated, and the acceleration processor 30 forms a heterogeneous acceleration card system.

[0045] In the embodiment of the present application, the host computer 20 is responsible for the operation and control of the entire AAU control system. Specifically, it is mainly responsible for the generation of remote control instructions, the sending and receiving of data, data upgrade control, resource management, and system status monitoring.

[0046] The host computer 20 generates first information to be transmitted to the AAU during the execution of corresponding operations and controls.

[0047] The first information includes one or more of the following:

[0048] Upgrade data;

[0049] Control instructions;

[0050] Business data.

[0051] In the embodiment of the present application, the host computer 20 and the acceleration processor 30 are connected via the Internet, and the host computer 20 remotely controls the acceleration processor via the Internet.

[0052] Specifically, the host computer 20 formats the first message to be sent requesting the task based on the requested task, ensuring that the first message complies with the transmission protocol requirements. After formatting, the host computer 20 transmits the first message to the acceleration processor 30 via a network interface (e.g., Ethernet) with the acceleration processor 30. If the task requested by the first message requires a remote upgrade, the first message includes upgrade data, including the complete firmware or configuration file for the upgrade. If the task requested by the first message is to execute a control operation, the first message includes control instructions.

[0053] The acceleration processor 30 includes at least two chips, wherein the first chip 31 is a SOC chip, such as a Zynq-7000 chip, which is formed as a main control chip for providing a flexible control mechanism and is responsible for managing the processing and transmission process of the first information sent by the host computer 20. After parsing the first information, the first chip 31 obtains the first control instruction and / or the data to be calculated, and distributes the obtained data to be calculated to the second chip 32. The second chip 32 is an FPGA chip, such as a Virtex UltraScale+ chip, which is responsible for executing parallel data calculation tasks, such as performing matrix multiplication and / or convolution operations, etc., to obtain calculation result data. Taking advantage of the significant performance advantage of the high parallel computing capability of the FPGA chip in processing large-scale data, in this embodiment, the FPGA chip is combined with the SOC chip to execute data calculation tasks, significantly improving the data processing speed and reducing latency.

[0054] Specifically, combined Figure 1 and Figure 2 As shown, the first chip 31 exchanges data with the host computer 20 and receives first information sent by the host computer 20 through a network interface. The first information includes one or more of upgrade data, control instructions, and service data. The control instructions can be one or more of control instructions for resource management, control instructions for task scheduling, and control instructions for hardware status monitoring. The service data can be service data for implementing the control instructions. The upgrade data is data for upgrading the AAU.

[0055] The first chip 31 works in conjunction with various hardware modules via peripheral interfaces supported by the operating system, rationally allocating tasks to the processor within the first chip 31 itself or to the second chip 32. The second chip 32 is used to handle highly parallel data computations, without involving system management and control tasks. For operations requiring large-scale parallel computing, this significantly improves computational efficiency, reduces the processing burden on the first chip 31, and thus accelerates overall data processing speed.

[0056] In the embodiment of the present application, the first chip 31 and the second chip 32 are optionally connected via a serial deserializer (SerDes) electrical interface for data exchange to ensure real-time data processing. For example, the SerDes electrical interface may include four 10G-SerDes electrical interfaces.

[0057] Using the AAU control system described in the embodiment of the present application, after receiving the first information sent by the host computer 20, the first chip 31 parses and processes the first information and obtains a first control instruction and / or data to be calculated based on the parsing results. If a first control instruction is obtained, that is, a control task of a task type that needs to be executed by the first chip 31 is obtained, the first chip 31 itself processes the first control instruction. If data to be calculated is obtained, that is, a computing task of a task type that needs to be executed by the second chip 32, the data and instructions corresponding to the data to be calculated are transmitted to the internal storage area of ​​the second chip 32 via the SerDes electrical interface, and the computing task is executed by the second chip 32.

[0058] Optionally, after the second chip 32 executes the calculation task and obtains the calculation result data, in one embodiment, the calculation result data can be returned to the first chip 31 through the SerDes electrical interface, and the first chip 31 returns the calculation result data to the host computer 20 to perform further data processing and decision-making; in another embodiment, the second chip 32 can also transmit the calculation result data to the AAU 10, so that the AAU 10 executes the transmission task corresponding to the calculation result data.

[0059] Combine Figure 1 As shown, in the embodiment of the present application, optionally, the first chip 31 includes:

[0060] a data processing module 311, configured to parse the first information and obtain the first control instruction and / or the data to be calculated;

[0061] a direct memory access (DMA) module 312 , configured to obtain the data to be calculated from the data processing module;

[0062] The first interface module 313 is configured to obtain the data to be calculated transmitted by the DMA module, and to encapsulate the data to be calculated and transmit it to the second chip.

[0063] Optionally, the data processing module 311 can be a ZYNQ module, which receives the first information transmitted by the host computer 20 through a network interface (such as Ethernet). After obtaining the first information, the data processing module 311 performs protocol parsing and data processing on the received first information so that the first information after data processing can be compatible with the data that can be processed by the first chip 31.

[0064] Optionally, in a remote upgrade scenario, the first information obtained by the data processing module 311 includes upgrade data, and the data processing module 311 detects the integrity of the upgrade data and performs sub-packaging processing on the upgrade data to obtain data to be calculated; in a remote control scenario, the data processing module 311 parses the first information to obtain the corresponding first control instruction.

[0065] The data to be calculated processed by the data processing module 311 is transmitted to the DMA module 312 , and the DMA module 312 is used to transmit the first information after the analysis process to the first interface module 313 .

[0066] Optionally, the DMA module 312 is further configured to cache the data to be calculated in the first information.

[0067] Optionally, the DMA module 312 obtains the data to be calculated transmitted by the data processing module 311 through the AXIS interface, and / or the DMA module 312 transmits the data to be calculated to the first interface module 313 through the AXIS interface.

[0068] Optionally, the first interface module 313 may be an Advanced eXtensible Interface (AXI) Ethernet module, which is responsible for Ethernet transmission of data and ensures that the data can be transmitted to the second chip 32 .

[0069] The second chip 32 includes a second interface module 321 for receiving the data to be calculated transmitted by the first interface module 313 of the first chip 31 and performing decapsulation processing on the data to be calculated.

[0070] Optionally, the second interface module 321 is an AXI_Ethernet module, and the first chip 31 and the second chip 32 are connected via Ethernet.

[0071] Alternatively, as Figure 1 As shown, the second chip 32 further includes:

[0072] The calculation module 322 is used to perform the calculation task of the data to be calculated and obtain the calculation result data;

[0073] The encapsulation module 323 is used to obtain the calculation result data transmitted by the calculation module 322, and encapsulate the calculation result data and then transmit it to the AAU 10.

[0074] In this embodiment, computing module 322 is an FPGA logic module capable of accelerating processing tasks on the data being computed, such as executing high-load computing tasks such as digital pre-distortion (DPD) and carrier aggregation (CA). The specific processing required is dynamically adjusted based on the computing task corresponding to the data being computed to ensure processing efficiency and accuracy.

[0075] Optionally, the computing module 322 includes a media access control (MAC) unit for performing media access control on the calculation result data obtained by the computing module 322 when performing the computing task, and converting the calculation result data into a standard communication protocol to ensure that the data can be transmitted in accordance with the standard communication protocol.

[0076] In the embodiment of the present application, optionally, the calculation module 322 obtains the data to be calculated transmitted by the second interface module 321 through the AXIS interface; and / or,

[0077] The encapsulation module 323 obtains the calculation result data transmitted by the MAC unit through a Media Independent Interface (MII).

[0078] Optionally, the encapsulation module 323 is a Common Public Radio Interface Module (CPRI). Through the MII interface, the MAC unit sends the calculation result data to the encapsulation module 323. The encapsulation module 323 is responsible for encapsulating the data according to the standard CPRI protocol and converting the calculation result data from the network interface (electrical port) signal to the optical port signal.

[0079] The calculation result data encapsulated by the encapsulation module 323 is transmitted as an optical signal via an optical fiber to the optical port of the AAU 10. After receiving the optical signal, the AAU 10 unpacks the calculation result data and sends it to its internal processing module for further operations, such as signal transmission, reception, processing, or forwarding.

[0080] In the embodiment of this application, Figure 1 As shown, the AAU 10 is used to parse the calculation result data, execute the transmission task corresponding to the calculation result data, obtain the execution result, and transmit the execution result to the first chip 31 through the second chip 32;

[0081] The first chip 31 is further configured to analyze the execution result and transmit the analyzed execution result to the host computer 20 .

[0082] Specifically, in the embodiment of the present application, the AAU 10 performs a corresponding transmission task based on the data type and transmission task of the received calculation result data. The transmission task may include remotely updating data or performing a specific operation, such as adjusting the transmission power or frequency.

[0083] In the case that the transmission task includes remote upgrade data, the AAU 10 decodes the received firmware or configuration file through the internal processing system and performs corresponding system updates.

[0084] In an embodiment of the present application, optionally, the AAU 10 executes a transmission task corresponding to the calculation result data, and after obtaining the execution result, returns the execution result to the acceleration processor 30 through the optical port (CPRI protocol). In the acceleration processor 30, the execution result is transmitted to the first chip 31 through the second chip 32, and is unpacked in the data processing module 311 of the first chip 31. The unpacked execution result is then transmitted to the host computer 20 to ensure that the host computer can receive real-time status updates or information confirmations.

[0085] After receiving the execution result returned by the first chip 31, the host computer 20 analyzes and confirms the operation status. If it is a remote upgrade operation, the execution result usually includes the upgrade success or failure status, or any abnormalities during the upgrade process; if it is a control operation, the execution result includes the execution result of the corresponding control operation instruction.

[0086] Optionally, after the host computer 20 receives the execution result returned by the AAU 10 and confirms that the task is completed, the entire data flow process ends. Afterwards, the host computer 20 can choose to continue executing other tasks or end the current operation.

[0087] In the embodiment of the present application, an acceleration processor including two chips is used as an example for explanation. It can be understood that the acceleration processor can also include more than two chips, and computing tasks can be performed by at least two chips respectively, or control tasks can be performed by at least two chips respectively. The specific principles are the same as the above method and will not be described in detail here.

[0088] Compared to existing single-hardware acceleration solutions (such as a single CPU or FPGA), the AAU control system described in this embodiment utilizes a collaborative approach between a SOC chip and an FPGA chip, distributing control and computation tasks to different hardware units. This improves the system's processing power and real-time performance. The advantages of FPGAs are particularly evident in large-scale parallel data processing, enabling the system to not only optimize data processing speed but also effectively reduce power consumption and latency. Furthermore, the system's flexibility and scalability enable it to adapt to diverse application scenarios, addressing the existing challenges of flexible scheduling and efficient task allocation.

[0089] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may be physically included separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0090] The above-mentioned integrated unit implemented in the form of a software functional unit can be stored in a computer-readable storage medium. The above-mentioned software functional unit is stored in a storage medium and includes a number of instructions for causing a computer device (which can be a personal computer, server, or network device, etc.) to perform some of the steps of the sending and receiving methods described in various embodiments of this application. The aforementioned storage medium includes: USB flash drives, mobile hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, optical disks, and other media capable of storing program code.

[0091] The above is a preferred embodiment of the present application. It should be pointed out that for ordinary personnel in this technical field, several improvements and modifications can be made without departing from the principles described in the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. An active antenna unit (AAU) control system, characterized in that: include: AAU; A host computer, configured to generate first information to be transmitted to the AAU; An acceleration processor is connected to the host computer and the AAU respectively; wherein the acceleration processor includes at least two chips, the first chip of the at least two chips is a system-on-chip (SOC) chip, and the second chip is a field programmable gate array (FPGA) chip; The first chip is used to parse the first information, obtain the first control instruction and / or data to be calculated in the first information, and transmit the data to be calculated to the second chip; The second chip is used to perform the calculation task of the data to be calculated, obtain calculation result data, and send the calculation result data to the AAU and / or the first chip.

2. The AAU control system according to claim 1, characterized in that: The AAU is used to parse the calculation result data, execute the transmission task corresponding to the calculation result data, obtain the execution result, and transmit the execution result to the first chip through the second chip; The first chip is further configured to parse the execution result and transmit the parsed execution result to the host computer.

3. The AAU control system according to claim 1, characterized in that: The first chip includes: a data processing module, configured to parse the first information and obtain the first control instruction and / or the data to be calculated; a direct memory access (DMA) module, configured to obtain the data to be calculated from the data processing module; The first interface module is used to obtain the data to be calculated transmitted by the DMA module, and to package the data to be calculated and transmit it to the second chip.

4. The AAU control system according to claim 3, characterized in that: The DMA module is also used to cache the data to be calculated.

5. The AAU control system according to claim 3, characterized in that: The DMA module obtains the data to be calculated transmitted by the data processing module through the AXIS interface; and / or, The DMA module transmits the data to be calculated to the first interface module through the AXIS interface.

6. The AAU control system according to claim 1 or 3, characterized in that: The second chip includes: a second interface module, configured to receive the data to be calculated transmitted by the first chip, and decapsulate the data to be calculated; A calculation module is used to perform the calculation task of the data to be calculated and obtain the calculation result data; The encapsulation module is used to obtain the calculation result data transmitted by the calculation module, encapsulate the calculation result data, and then transmit it to the AAU.

7. The AAU control system according to claim 6, characterized in that: The computing module includes a media access control (MAC) unit configured to perform media access control on the computing result data and convert the computing result data into a standard communication protocol.

8. The AAU control system according to claim 7, characterized in that: The computing module obtains the data to be calculated transmitted by the second interface module through the AXIS interface; and / or, The packaging module obtains the calculation result data transmitted by the MAC unit through the medium independent interface MII.

9. The AAU control system according to claim 1, characterized in that: The first information includes one or more of the following: Upgrade data; Control instructions; Business data.

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