High-speed multiplexing IO time sequence convergence method, system and terminal

Abstract

The invention provides a high-speed multiplexing IO time sequence convergence method and system and a terminal.The high-speed multiplexing IO time sequence analysis and repairing operation is independently completed from function time sequence checking of an integrated circuit, IO time sequence constraints for high-speed multiplexing IO are established, the worst circuit working condition is operated, and the worst circuit working condition is operated; dividing each high-speed multiplexing IO into one or more high-speed multiplexing IO groups so as to respectively execute time sequence analysis and repair operation on each high-speed multiplexing IO group, and when all the high-speed multiplexing IO groups are subjected to time sequence convergence, sequentially running a plurality of preset specified circuit working conditions and executing regression test operation; therefore, time sequence analysis and time sequence repair of each high-speed multiplexing IO are automatically completed, and the technical problems of complex time sequence constraint, large static time sequence analysis calculation amount, large time sequence correction workload and high time sequence convergence time cost in the existing high-speed multiplexing IO time sequence check are solved.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit design, and in particular to a timing closure method, system, and terminal for high-speed multiplexed IO. Background Art

[0002] For general-purpose chips such as MCU (Microcontroller Unit), due to their wide range of applications, IO (Input / Output) function multiplexing is commonly used, that is, each IO can be used for multiple different functions. Among them, according to the rate at which the IO transmits data, each IO that uses function multiplexing can be divided into low-speed multiplexing IO and high-speed multiplexing IO. For low-speed multiplexing IO, such as UART (Universal Asynchronous Receiver / Transmitter), I2C (Inter-Integrated Circuit), etc., the running speed is slow and timing convergence is usually not required. However, for high-speed multiplexing IO, such as SDRAM (Synchronous Dynamic Random Access Memory), Ethernet, etc., there are high requirements for interface timing, so timing checks and timing convergence are required.

[0003] When designing a chip, static timing analysis tools (STA) are usually used in conjunction with timing constraints to perform automated timing analysis. Timing corrections are performed based on the timing analysis results, and layout and routing tools are used to optimize the chip design layout. The layout positions of various components on the chip and the connection lines between them are updated, and iterations are repeated until the timing convergence target is achieved and timing signoff is completed.

[0004] However, performing timing checks on high-speed multiplexed IO to achieve timing closure has the following drawbacks:

[0005] ① Due to the use of functional multiplexing, this high-speed multiplexed IO can be used to transmit clock signals or data signals. For different functions, the IO has different operating modes and corresponds to different interface timing requirements. In this case, if the IO timing check is performed at the same time as the functional timing check, not only will the timing constraints of the functional static timing analysis become very complex, but the calculation amount will also increase exponentially. At the same time, some unreasonable timing paths are likely to interfere with the normal analysis, affecting the accuracy of the timing analysis results.

[0006] Unlike functional timing checks, which only require setup and hold times, I / O timing checks are more complex. High-speed multiplexed I / O timing checks have different requirements based on different protocols, such as timing skew between multi-bit data signals or the delay of the entire timing path. These special requirements prevent static timing analysis tools from automatically correcting timing, requiring manual adjustment of delay times on each timing path, which is very labor-intensive.

[0007] ③ The various protocols of high-speed multiplexed IO are usually more complex. At the same time, the timing convergence link is usually limited under the pressure of the tape-out node. As a result, achieving the timing convergence goal of high-speed multiplexed IO requires multiple engineers to work in parallel. Parallel timing repair will cause conflicts with the adjustment of some common paths, which in turn causes multiple iterations of layout and routing and static timing analysis, increasing the time for timing convergence. Summary of the Invention

[0008] In view of the shortcomings of the prior art described above, the purpose of the present application is to provide a timing closure method, system and terminal for high-speed multiplexed IO, which are used to solve the technical problems existing in the existing high-speed multiplexed IO timing check, such as complex timing constraints, large static timing analysis calculation volume, large timing correction workload and high timing convergence time cost.

[0009] To achieve the above-mentioned objectives and other related objectives, the first aspect of the present application provides a timing closure method for high-speed multiplexed IO, which is applied to integrated circuit design work, including: constructing an IO multiplexing information table to obtain multiple high-speed multiplexed IOs for transmitting high-speed signals, and dividing each high-speed multiplexed IO into one or more high-speed multiplexed IO groups according to the different IO functions of each high-speed multiplexed IO; obtaining an initial design layout of the integrated circuit, and constructing an IO layout and routing netlist and IO timing constraints; running the worst circuit operating conditions, and according to the constructed IO layout and routing netlist and IO timing constraints, performing timing analysis and repair operations on each high-speed multiplexed IO group respectively until the timing of all high-speed multiplexed IOs of all high-speed multiplexed IO groups converges; running multiple preset specified circuit operating conditions in sequence, performing regression testing operations on all high-speed multiplexed IOs until the timing of all high-speed multiplexed IOs converges; using a layout and routing tool to update the initial design layout of the integrated circuit to obtain an optimized design layout.

[0010] In some embodiments of the first aspect of the present application, the method of constructing an IO layout and routing netlist and IO timing constraints includes: obtaining an overall layout and routing netlist and overall timing constraints of the initial design layout based on the obtained initial design layout of the integrated circuit; screening multiple functional elements associated with each high-speed multiplexed IO based on the overall layout and routing netlist, obtaining circuit connection paths between each high-speed multiplexed IO and each associated functional element, and constructing the IO layout and routing netlist; defining multiple clocks according to different operating modes of each high-speed multiplexed IO, and specifying the timing relationship between the input signal, output signal of each high-speed multiplexed IO and the clock signal generated by each clock, and constructing the IO timing constraints.

[0011] In some embodiments of the first aspect of the present application, the IO timing constraints include: clock frequency constraints and clock period constraints of the clock signal, input delay constraints between the input signal and the clock signal, output delay constraints between the output signal and the clock signal, path delay constraints between the input signal and the output signal, and timing skew constraints between different data bits of the signal.

[0012] In some embodiments of the first aspect of the present application, the method of performing timing analysis and repair operations on the high-speed multiplexed IO group based on the constructed IO layout and routing netlist and IO timing constraints includes: using a static timing analysis tool to perform a timing analysis operation on the high-speed multiplexed IO group to generate a timing analysis result of the high-speed multiplexed IO group; judging whether the high-speed multiplexed IO group has converged in timing based on the timing analysis result and the IO timing constraints, and if the high-speed multiplexed IO group has not converged in timing, performing a timing repair operation on the high-speed multiplexed IO group to generate a corresponding target IO timing engineering change instruction script; using a layout and routing tool to run the target IO timing engineering change instruction script and update the IO layout and routing netlist; based on the updated IO layout and routing netlist, using a static timing analysis tool to re-perform a timing analysis operation on the high-speed multiplexed IO group and judge whether the high-speed multiplexed IO group has converged in timing, and if the high-speed multiplexed IO group has not converged in timing, performing a timing repair operation on the high-speed multiplexed IO group, and iterating repeatedly until the high-speed multiplexed IO group has converged in timing.

[0013] In some embodiments of the first aspect of the present application, a static timing analysis tool is used to perform a timing analysis operation on a high-speed multiplexed IO group, and a method for generating a timing analysis result of the high-speed multiplexed IO group includes: generating a timing path list of the high-speed multiplexed IO group based on the IO layout and routing netlist; wherein the timing path list includes: multiple timing paths associated with each high-speed multiplexed IO in the high-speed multiplexed IO group; generating an IO static timing analysis instruction script for the high-speed multiplexed IO group based on the timing path list and the IO timing constraints to calculate the timing margin of each timing path; generating a timing analysis result of the high-speed multiplexed IO group based on the timing margin of each timing path to filter one or more illegal timing paths; if a illegal timing path exists in the high-speed multiplexed IO group, it is determined that the high-speed multiplexed IO group has not converged in timing; wherein the timing analysis result includes: the IO function and operating mode of each high-speed multiplexed IO in the high-speed multiplexed IO group, and the timing margin of each timing path.

[0014] In some embodiments of the first aspect of the present application, a method for performing a timing repair operation on a high-speed multiplexed IO group that has not achieved timing closure to generate a corresponding target IO timing engineering change instruction script includes: obtaining one or more timing violation paths of the high-speed multiplexed IO group that has not achieved timing closure, performing timing repair on each of the timing violation paths, and generating a timing engineering change instruction script for each of the timing violation paths; generating an initial IO timing engineering change instruction script for the high-speed multiplexed IO group based on each of the timing engineering change instruction scripts, for execution using a static timing analysis tool, and re-performing a timing analysis operation on the high-speed multiplexed IO group; determining whether the high-speed multiplexed IO group has simulated timing closure, and if the high-speed multiplexed IO group has not simulated timing closure, screening one or more new timing violation paths of the high-speed multiplexed IO group, performing timing repair on each of the new timing violation paths, and updating the initial IO timing engineering change instruction script; and repeatedly iterating until the high-speed multiplexed IO group has simulated timing closure, thereby generating a target IO timing engineering change instruction script for the high-speed multiplexed IO group.

[0015] In some embodiments of the first aspect of the present application, the method of performing timing repair on the violating timing path includes: determining the timing target of the violating timing path based on the IO timing constraint, and judging whether the violating timing path needs to increase the delay or shorten the delay; if the delay needs to be increased, calculating the target delay increase value of the violating timing path, and inserting one or more buffers with preset specified transmission delay parameters between the buffer chains corresponding to the violating timing path, and generating a first type of timing engineering change instruction script; if the delay needs to be shortened, calculating the target delay reduction value of the violating timing path, and replacing one or more buffers with larger transmission delay parameters between the buffer chains corresponding to the violating timing path with one or more buffers with smaller transmission delay parameters, and generating a second type of timing engineering change instruction script.

[0016] In some embodiments of the first aspect of the present application, the IO multiplexing information table includes: high-speed function identifiers and IO multiplexing information of each function selection mode; the IO multiplexing information includes: functional element ports of the integrated circuit associated with each IO in the current function selection mode and options for the corresponding ports; the options are the number of IOs to which the same port of the same functional element can be connected.

[0017] To achieve the above-mentioned purpose and other related purposes, the second aspect of the present application provides a high-speed multiplexed IO timing convergence system, the high-speed multiplexed IO timing convergence system comprising: a high-speed multiplexed IO screening module, used to construct an IO multiplexing information table, obtain a plurality of high-speed multiplexed IOs for transmitting high-speed signals, and divide each high-speed multiplexed IO into one or more high-speed multiplexed IO groups according to the different IO functions of each high-speed multiplexed IO; a timing constraint construction module, connected to the high-speed multiplexed IO screening module, used to obtain the initial design layout of the integrated circuit, and construct an IO layout and routing netlist and IO timing constraints; a first timing convergence module, connected to the timing constraint A bundle construction module is used to run the worst-case circuit operating conditions and, based on the constructed IO layout and routing netlist and IO timing constraints, perform timing analysis and repair operations on each high-speed multiplexed IO group until the timing of all high-speed multiplexed IOs in all high-speed multiplexed IO groups converges; a second timing closure module is connected to the first timing closure module and is used to sequentially run multiple preset specified circuit operating conditions and perform regression testing operations on all high-speed multiplexed IOs until the timing of all high-speed multiplexed IOs converges; a design layout update module is connected to the second timing closure module and is used to use layout and routing tools to update the initial design layout of the integrated circuit to obtain an optimized design layout.

[0018] To achieve the above-mentioned purpose and other related purposes, the third aspect of the present application provides a timing convergence terminal for high-speed multiplexed IO, wherein the timing convergence terminal for high-speed multiplexed IO includes: a processor and a memory; the memory is used to store a computer program; the processor is used to execute the computer program stored in the memory, so that the terminal executes the timing convergence method for high-speed multiplexed IO described in any of the above-mentioned embodiments.

[0019] As described above, the present application provides a timing closure method, system, and terminal for high-speed multiplexed IO. The method separates the timing analysis and repair operations for high-speed multiplexed IO from the functional timing check of the integrated circuit and establishes IO timing constraints for the high-speed multiplexed IO. The method first runs the worst-case circuit operating conditions and divides each high-speed multiplexed IO into one or more high-speed multiplexed IO groups to perform timing analysis and repair operations on each high-speed multiplexed IO group separately. When all high-speed multiplexed IO groups have fully converged in timing, the method then runs multiple preset specified circuit operating conditions in sequence and performs regression testing operations, thereby automatically completing the timing analysis and timing repair of each high-speed multiplexed IO. Therefore, the present application has the following beneficial effects: it can effectively shorten the timing closure time of each high-speed multiplexed IO, reduce the number of iterations, and effectively solve the technical problems existing in existing high-speed multiplexed IO timing checks, such as complex timing constraints, large static timing analysis calculations, large timing correction workload, and high timing closure time cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 FIG. 1 is a flow chart of a method for timing closure of high-speed multiplexed IO according to an embodiment of the present application.

[0021] Figure 2 A schematic diagram showing an IO reuse information table in one embodiment of the present application is shown.

[0022] Figure 3 Shown is a flowchart of performing timing analysis and repair operations in one embodiment of the present application.

[0023] Figure 4 Shown is a flowchart of performing a timing repair operation in one embodiment of the present application.

[0024] Figure 5 Shown is a structural diagram of a timing closure system for high-speed multiplexed IO in one embodiment of the present application.

[0025] Figure 6 Shown is a structural diagram of a timing closure terminal for high-speed multiplexed IO in one embodiment of the present application. DETAILED DESCRIPTION

[0026] The following describes the embodiments of the present application through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present application from the content disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments. The details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other unless they conflict.

[0027] In the embodiments of this application, terms such as "first" and "second" are used to distinguish between identical or similar items with substantially the same functions and effects. For example, the terms "first timing closure module" and "second timing closure module" are used solely to distinguish between different timing closure modules and do not define their order. Those skilled in the art will understand that terms such as "first" and "second" do not define the number or execution order of the modules, and do not necessarily imply differences between the modules.

[0028] To address the problems in the above-mentioned background technology, the present invention provides a timing closure method, system, and terminal for high-speed multiplexed IO. The method aims to separate the timing analysis and timing repair operations of high-speed multiplexed IO from the functional timing check of integrated circuit design work and complete them separately. Timing constraints for high-speed multiplexed IO are established to automatically complete the timing analysis and timing repair of each high-speed multiplexed IO. This can effectively shorten the timing closure time of each high-speed multiplexed IO and reduce the number of iterations, thereby solving the technical problems existing in existing high-speed multiplexed IO timing checks, such as complex timing constraints, large static timing analysis calculations, large timing correction workload, and high timing closure time cost.

[0029] In order to make the invention objectives, technical solutions and advantages of this application more clearly understood, the following embodiments and the accompanying drawings are used to further explain the technical solutions in the embodiments of this application. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0030] like Figure 1 FIG2 is a flow chart showing a method for timing closure of a high-speed multiplexed IO in an embodiment of the present application. The method for timing closure of a high-speed multiplexed IO in this embodiment is applied to integrated circuit design work and includes steps S1 to S5.

[0031] Step S1: constructing an IO multiplexing information table to obtain a plurality of high-speed multiplexing IOs for transmitting high-speed signals, and dividing each high-speed multiplexing IO into one or more high-speed multiplexing IO groups according to different IO functions of each high-speed multiplexing IO.

[0032] In one embodiment, the IO multiplexing information table includes: a high-speed function identifier for each function selection mode and IO multiplexing information. The IO multiplexing information includes: the functional component port of the integrated circuit associated with each IO in the current function selection mode and the corresponding port options; the function selection mode selects the corresponding IO for different IO functions, and the options are the number of IOs that can be connected to the same port of the same functional component. Thus, one or more IOs with different function selection modes are screened, and those with high-speed function identifiers are screened to determine them as high-speed multiplexed IOs.

[0033] For example, Figure 2 As shown, the function selection modes of the IO multiplexing information table include ALT1, ALT2, and ALT3. IO1 can be connected to option 2 of port 1 of function element 1 in ALT1 function selection mode; IO2 can be connected to option 2 of port 2 of function element 1 in ALT1 function selection mode; IO3 can be connected to option 1 of port 1 of function element 1 in ALT1 function selection mode, to option 1 of port 1 of function element 2 in ALT2 function selection mode, and to option 1 of port 1 of function element 3 in ALT3 function selection mode; IO4 can be connected to option 1 of port 2 of function element 1 in ALT1 function selection mode, and to option 1 of port 2 of function element 2 in ALT2 function selection mode. Therefore, according to the IO multiplexing information table, IO3 and IO4 are determined to be high-speed multiplexed IOs.

[0034] According to the different functions of each high-speed multiplexed IO, each high-speed multiplexed IO is divided into one or more high-speed multiplexed IO groups, such as a high-speed multiplexed IO group for Ethernet function, a high-speed multiplexed IO group for SRAM (static random access memory) function, or a high-speed multiplexed IO group for DRAM (dynamic random access memory) function. Each high-speed multiplexed IO group may include one or more high-speed multiplexed IOs.

[0035] Step S2: Obtain the initial design layout of the integrated circuit and construct an IO layout and routing netlist and IO timing constraints.

[0036] In one embodiment, the specific working method of step S2 includes the following steps.

[0037] ① Based on the obtained initial design layout of the integrated circuit, obtain the total layout and routing netlist and total timing constraints of the initial design layout.

[0038] It should be understood that the design layout of an integrated circuit is a two-dimensional planar design that describes the layout and interconnection relationships of components on the integrated circuit through geometric figures (such as polysilicon layers, metal layers, etc.), and is used to convert the logical functions of the circuit into physical implementations. The layout and routing netlist, referred to as the PR (Physical Design Netlist) netlist, is structured data that describes the physical connection relationships of all functional components in the design layout. It contains the precise coordinates of component instances (such as transistors and logic gates), metal layer wiring paths and connection relationships, constraint information, etc. Therefore, after obtaining the initial design layout of the integrated circuit, the layout and interconnection relationships of each component instance on the integrated circuit can be obtained based on the initial design layout, and the total layout and routing netlist and total timing constraints of the initial design layout can be read. In a specific embodiment, the initial design layout can be parsed to extract the geometric information and physical layout of each component instance such as transistors, metal layers, and through-holes in the initial design layout; the circuit connection relationship of each component instance is reconstructed according to the physical layout, and a netlist containing the component instance type, coordinates, and interconnection information is generated for conversion into a total layout and routing netlist with a target netlist format using a specific tool (such as edif2verilog); the parasitic parameters of the initial design layout are extracted, the signal path delay is calculated, and the total timing constraints of the initial design layout are obtained.

[0039] ② Based on the overall layout and routing netlist, multiple functional elements associated with each high-speed multiplexing IO are screened, a circuit connection path between each high-speed multiplexing IO and each associated functional element is obtained, and the IO layout and routing netlist is constructed.

[0040] ③ According to the different working modes of each high-speed multiplexed IO, multiple clocks are defined respectively, and the timing relationship between the input signal and output signal of each high-speed multiplexed IO and the clock signal generated by each clock is specified to construct the IO timing constraints.

[0041] For example, the high-speed multiplexed IO in the high-speed multiplexed IO group of Ethernet function, the working modes mainly include: RGMII (Reduced Gigabit Media Independent Interface) mode, RMII (Reduced Media Independent Interface) mode and MII (Media Independent Interface) mode. The timing requirements of different working modes are different. Therefore, this application defines multiple clocks for different working modes of high-speed multiplexed IO, and constructs the IO timing constraints based on the clock signals generated by each clock to constrain each working mode separately. The purpose of this design in this embodiment of the present application is to accurately construct the timing constraints of high-speed multiplexed IO applicable to different functions and different working modes, so that the timing check of high-speed multiplexed IO is more accurate and the high performance of the integrated circuit is guaranteed.

[0042] In one embodiment, the IO timing constraints include: clock frequency constraints and clock period constraints of the clock signal, input delay constraints between the input signal and the clock signal, output delay constraints between the output signal and the clock signal, path delay constraints between the input signal and the output signal, and timing skew constraints between different data bits of the signal.

[0043] Step S3: Run the worst circuit operating conditions, and perform timing analysis and repair operations on each high-speed multiplexing IO group according to the constructed IO layout and routing netlist and IO timing constraints, until the timing of all high-speed multiplexing IOs of all high-speed multiplexing IO groups converges.

[0044] In one embodiment, if Figure 3 As shown, the method of performing timing analysis and repair operations on each high-speed multiplexing IO group in step S3 includes steps S31 to S34.

[0045] Step S31: using a static timing analysis tool to perform a timing analysis operation on the high-speed multiplexing IO group to generate a timing analysis result of the high-speed multiplexing IO group.

[0046] Static timing analysis tools, referred to as STA (Static Timing Analysis) tools, are mainly used to check whether the integrated circuit design meets the timing constraints, thereby ensuring the correctness of the integrated circuit timing and improving the reliability and stability of the integrated circuit.

[0047] In a specific embodiment, the specific working method of step S31 includes the following steps.

[0048] ① Based on the IO layout and routing netlist, generate a timing path list for the high-speed multiplexed IO group.

[0049] The timing path list includes: multiple timing paths associated with each high-speed multiplexing IO in the high-speed multiplexing IO group.

[0050] It should be understood that a timing path is used in integrated circuit design to describe the propagation time of a signal from its starting point to its end point. It consists of a starting point, data path delay, unit delay, and end point. The starting point refers to the location where a clock edge triggers data, such as the clock pin or input port of a sequential element; the location where data is captured, such as the data input or output port of a register. Based on the IO layout and routing netlist, the circuit connection paths between each high-speed multiplexed IO and its associated functional components are obtained, and multiple timing paths for each high-speed multiplexed IO are determined, thereby generating the timing path list.

[0051] ② Based on the timing path list and the IO timing constraints, generate an IO static timing analysis instruction script for the high-speed multiplexing IO group to calculate the timing margin of each timing path.

[0052] In a specific embodiment, the generated IO static timing analysis instruction script includes the command method:

[0053] Report_timing-through<functional element port>-through <io>-from / to <clock>

[0054] This command method can specify a unique timing path and calculate the timing margin of each timing path.

[0055] It should be understood that timing margin refers to the difference between the actual signal transmission time and the theoretically required shortest or longest time in a digital circuit. That is, it is the buffer time reserved in the timing to ensure that the circuit can correctly transmit and process data under various circumstances. It reflects the stability and reliability of the circuit in terms of timing. The larger the timing margin, the higher the circuit's tolerance to various changing factors and the lower the possibility of timing errors.

[0056] ③ Based on the timing margin of each timing path, generate the timing analysis results of the high-speed multiplexed IO group to screen one or more timing violation paths. If a timing violation path exists in the high-speed multiplexed IO group, it is determined that the high-speed multiplexed IO group has not achieved timing convergence.

[0057] The timing analysis results include but are not limited to: the IO function and working mode of each high-speed multiplexing IO in the high-speed multiplexing IO group and the timing margin of each timing path.

[0058] One or more timing violation paths are screened based on the timing slack of each timing path. Specifically, when the timing slack is less than 0, the corresponding timing path is a timing violation path and requires timing repair.

[0059] In this embodiment, based on the timing analysis results, the optimal timing path and the worst timing path of the high-speed multiplexed IO group can be marked, and the timing delay of the multi-bit data signals in the high-speed multiplexed IO group can be calculated to obtain the timing skew value of each data signal.

[0060] Step S32: Based on the timing analysis results and the IO timing constraints, determine whether the high-speed multiplexed IO group has achieved timing convergence. If the high-speed multiplexed IO group has not achieved timing convergence, perform a timing repair operation on the high-speed multiplexed IO group and generate a corresponding target IO timing engineering change instruction script.

[0061] In a specific embodiment, if Figure 4 As shown, the method of performing a timing repair operation on the high-speed multiplexing IO group that has not converged in timing in step S32 and generating a corresponding target IO timing engineering change instruction script includes steps S321 to S325.

[0062] Step S321: obtaining one or more timing violation paths of the high-speed multiplexed IO group that has not reached timing closure, performing timing repair on each timing violation path, and generating a timing engineering change instruction script for each timing violation path.

[0063] In a specific embodiment, the method of performing timing repair on each timing violation path includes the following steps.

[0064] ① Based on the IO timing constraints, determine the timing target of the violating timing path, and determine whether the violating timing path needs to increase or decrease the delay.

[0065] It should be noted that, based on the IO timing constraints, more detailed and stricter timing targets can be set for each violating timing path. For example, based on the input delay constraint, output delay constraint, and clock frequency constraint of the IO timing constraints, it is ultimately converted into the timing delay of a certain timing path to ensure that the timing margin is greater than 0, so that each timing path meets its own timing target, thereby ensuring that each high-speed multiplexed IO meets the IO timing constraints, that is, timing convergence.

[0066] It should be understood that each timing path is provided with a pair of flag buffers, serving as a first flag buffer and a second flag buffer, respectively. One or more buffers are provided between the first flag buffer and the second flag buffer, forming a buffer chain for the corresponding timing path. Each buffer is preset with a specified transmission delay parameter. The timing delay of the timing path is closely related to the transmission delay parameter of each buffer.

[0067] In one embodiment, a delay data table can be constructed, which includes transmission delay parameters of buffers of various sizes and delay data of other load elements (such as inverters) on the timing path. The specific user can determine it based on the required load and timing requirements, and this application is not limited.

[0068] ② If the delay needs to be increased, the target delay increase value of the violating timing path is calculated, and one or more buffers with preset specified transmission delay parameters are inserted between the buffer chains corresponding to the violating timing path accordingly to generate the first type of timing engineering change instruction script.

[0069] Preferably, when inserting the buffer, it is preferred to insert it closer to the subsequent components to avoid problems such as insufficient driving capability of the timing path.

[0070] ③ If the delay needs to be shortened, the target delay reduction value of the violating timing path is calculated, and based on this, one or more buffers with larger transmission delay parameters between the buffer chains corresponding to the violating timing path are replaced with one or more buffers with smaller transmission delay parameters to generate a second type of timing engineering change instruction script.

[0071] It should be noted that when the present application performs timing repair on the illegal timing path, it only processes the buffer chain between the two flag buffers, and does not affect any common timing paths between the high-speed multiplexed IOs and between the functional elements. This can avoid mutual interference between different timing repairs, thereby reducing the number of iterations of the timing repair operation on the high-speed multiplexed IO group, so that the high-speed multiplexed IO group can reach timing convergence as soon as possible.

[0072] Step S322: Generate an initial IO timing engineering change instruction script of the high-speed multiplexing IO group according to each timing engineering change instruction script.

[0073] Specifically, the initial IO timing engineering change instruction script of the high-speed multiplexing IO group is generated together according to different types of timing engineering change instruction scripts of each illegal timing path.

[0074] Step S323: using a static timing analysis tool to run the initial IO timing engineering change instruction script, re-perform a timing analysis operation on the high-speed multiplexing IO group, and determine whether the high-speed multiplexing IO group has achieved simulated timing closure.

[0075] The initial IO timing engineering change order script is run in a static timing analysis tool to simulate the insertion and replacement of buffers. The timing slack of all timing paths is recalculated to determine whether there are still violating timing paths with a timing slack less than 0. If there are still violating timing paths, the high-speed multiplexed IO group has not achieved simulated timing closure. If there are no violating timing paths, the high-speed multiplexed IO group has achieved simulated timing closure.

[0076] Step S324: If the high-speed multiplexed IO group has not converged in simulation, steps S321 to S323 are repeated to screen one or more new timing violation paths of the high-speed multiplexed IO group, perform timing repair on each new timing violation path, and update the initial IO timing engineering change instruction script.

[0077] Step S325: If the high-speed multiplexed IO group has achieved simulated timing closure, a target IO timing engineering change instruction script for the high-speed multiplexed IO group is generated according to the updated initial IO timing engineering change instruction script.

[0078] In one embodiment, steps S321 to S323 are iteratively executed until all timing paths meet the set timing targets, i.e., the high-speed multiplexed IO group has achieved simulated timing closure. If the target is still not met after repeated iterations, the iterations are terminated when the number of iterations reaches a pre-set upper limit, and the final target IO timing engineering change instruction script is output.

[0079] Step S33: using a placement and routing tool to run the target IO timing engineering change instruction script and update the IO placement and routing netlist.

[0080] Layout involves the proper placement of the various functional components within a circuit within a designated area of an integrated circuit. Routing, after layout is complete, involves connecting the pins of the various functional components using metal wires based on the circuit's connections, creating a complete circuit path. Placement and routing tools enable the proper placement of logic gates and other functional components on the integrated circuit and connect them to achieve the designed functionality. By employing placement and routing tools for proper layout and routing, high-performance, low-power, and compact integrated circuit designs can be achieved to meet the needs of diverse application scenarios.

[0081] Step S34: Based on the updated IO layout and routing netlist, use a static timing analysis tool to re-perform timing analysis on the high-speed multiplexed IO group, and determine whether the timing of the high-speed multiplexed IO group has converged. If the timing of the high-speed multiplexed IO group has not converged, perform a timing repair operation on the high-speed multiplexed IO group, and iterate repeatedly until the timing of the high-speed multiplexed IO group has converged.

[0082] In this embodiment, each high-speed multiplexed IO group can perform timing analysis and repair operations in parallel without interfering with each other, which can effectively reduce the time required to complete the timing closure of all high-speed multiplexed IOs. When all high-speed multiplexed IO groups have achieved timing closure, steps S4 and S5 are continued.

[0083] Step S4: sequentially running a plurality of preset specified circuit operating conditions, performing regression test operations on all high-speed multiplexed IOs until the timing of all high-speed multiplexed IOs converges.

[0084] Under the worst-case circuit operating conditions, all high-speed multiplexed IO groups achieve timing closure. Therefore, under other circuit operating conditions, each high-speed multiplexed IO group is likely to achieve timing closure. Even if timing closure is not achieved, there are relatively few timing violation paths. Buffers can be directly inserted or replaced in these timing violation paths for timing repair, enabling each high-speed multiplexed IO group to quickly complete regression testing operations.

[0085] Step S5: using a layout and routing tool to update the initial design layout of the integrated circuit to obtain an optimized design layout.

[0086] In a specific embodiment, the specific working method of step S500 includes: importing the initial design layout of the integrated circuit and the obtained total timing constraints into a layout and routing tool, and using the layout algorithm of the layout and routing tool to adjust the position of each functional element to reduce critical path delay, reduce power consumption and improve wiring routability; after completing the layout optimization, using the routing algorithm of the layout and routing tool to connect each functional element, while optimizing the wiring length, reducing the number of vias and avoiding wiring congestion to obtain an updated design layout; performing physical verification on the updated design layout, such as design rule checking, electrical rule checking and design layout and principle Figure 1 When problems are found during physical verification, the layout and routing of the design will be readjusted until the physical verification passes and meets the design requirements, thereby obtaining the optimized design layout of the integrated circuit.

[0087] like Figure 5 FIG. 5 shows a schematic diagram of a high-speed multiplexed IO timing closure system 500 according to an embodiment of the present application. The high-speed multiplexed IO timing closure system 500 includes: a high-speed multiplexed IO screening module 501, a timing constraint building module 502, a first timing closure module 503, a second timing closure module 504, and a design layout update module 505, which are connected in sequence.

[0088] Specifically, the high-speed multiplexing IO screening module 501 is used to construct an IO multiplexing information table, obtain multiple high-speed multiplexing IOs for transmitting high-speed signals, and divide each high-speed multiplexing IO into one or more high-speed multiplexing IO groups according to different IO functions of each high-speed multiplexing IO.

[0089] The timing constraint building module 502 is used to obtain the initial design layout of the integrated circuit and build an IO layout and routing netlist and IO timing constraints.

[0090] The first timing closure module 503 is used to run the worst circuit working conditions and perform timing analysis and repair operations on each high-speed multiplexing IO group according to the constructed IO layout and routing netlist and IO timing constraints until all high-speed multiplexing IO timings of all high-speed multiplexing IO groups converge.

[0091] The second timing closure module 504 is configured to sequentially run a plurality of preset specified circuit operating conditions and perform regression testing operations on all high-speed multiplexed IOs until the timing of all high-speed multiplexed IOs is converged.

[0092] The design layout update module 505 is used to update the initial design layout of the integrated circuit using a placement and routing tool to obtain an optimized design layout.

[0093] It should be understood that the execution process of each module to implement a specific function has been described in detail in the above method embodiment, and for the sake of brevity, it will not be repeated here.

[0094] It should also be understood that the division of modules in the embodiments of the present application is illustrative and is merely a logical functional division. In actual implementation, other division methods may be used. Furthermore, the functional modules in the various embodiments of the present application may be integrated into a single processor, or may exist physically separately, or two or more modules may be integrated into a single module. The aforementioned integrated modules may be implemented in the form of hardware or software functional modules.

[0095] The timing closure method for high-speed multiplexing IO provided in the embodiment of the present application can be implemented on the terminal side or the server side. As for the hardware structure of the timing closure terminal 600 for high-speed multiplexing IO, please refer to Figure 6 , which is an optional hardware structure diagram of the high-speed multiplexed IO timing convergence terminal 600 provided in an embodiment of the present application, the high-speed multiplexed IO timing convergence terminal 600 can be a mobile phone, a computer device, a tablet device, a personal digital processing device, a factory background processing device, etc. The high-speed multiplexed IO timing convergence terminal 600 includes: at least one processor 601, a memory 602, at least one network interface 604 and a user interface 606. In addition, the various components in the high-speed multiplexed IO timing convergence terminal 600 are coupled together through a bus system 605. It can be understood that the bus system 605 is used to realize the connection and communication between these components. In addition to the data bus, the bus system 605 also includes a power bus, a control bus and a status signal bus. However, for the sake of clarity, in Figure 6 The various buses are all labeled as bus systems in FIG. The user interface 606 may include a display, keyboard, mouse, trackball, click gun, keys, buttons, touch pad or touch screen, etc.

[0096] It can be understood that the memory 602 can be a volatile memory or a non-volatile memory, and can also include both volatile and non-volatile memories. This application is not specifically limited. The memory 602 in the embodiment of the present application is used to store various categories of data to support the operation of the timing convergence terminal 600 of the high-speed multiplexed IO. Examples of these data include: any executable program for operating on the timing convergence terminal 600 of the high-speed multiplexed IO, such as an operating system 6021 and an application 6022; the operating system 6021 includes various system programs, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and processing hardware-based tasks. The application 6022 can include various applications, such as a media player (MediaPlayer), a browser (Browser), etc. The timing convergence method for implementing the high-speed multiplexed IO provided in the method embodiment of the present application can be included in the application 6022.

[0097] The timing closure method for high-speed multiplexed IO disclosed in the above-mentioned embodiment of the method of the present application can be applied to the processor 601, or implemented by the processor 601. The processor 601 may be an integrated circuit chip with signal processing capabilities. During implementation, the steps of the above-mentioned method can be completed by the hardware integrated logic circuit in the processor 601 or by instructions in the form of software. The above-mentioned processor 601 can be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The processor 601 can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiments of the present application. The general-purpose processor 601 can be a microprocessor or any conventional processor, etc.

[0098] In an exemplary embodiment, the high-speed multiplexed IO timing closure terminal 600 can be used by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), and complex programmable logic devices (CPLDs) to execute the aforementioned high-speed multiplexed IO timing closure method.

[0099] Those skilled in the art will appreciate that all or part of the steps in the above-described method embodiments can be implemented using hardware associated with a computer program. The aforementioned computer program can be stored in a computer-readable storage medium. When executed, the program performs the steps in the above-described method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0100] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

[0101] In summary, the present application provides a timing closure method, system, and terminal for high-speed multiplexed IO. By separating the timing analysis and repair operations for high-speed multiplexed IO from the functional timing check of the integrated circuit, and establishing IO timing constraints for the high-speed multiplexed IO, the worst-case circuit operating conditions are first run, and each high-speed multiplexed IO is divided into one or more high-speed multiplexed IO groups. Timing analysis and repair operations are performed on each high-speed multiplexed IO group separately. When all high-speed multiplexed IO groups have fully converged in timing, multiple preset specified circuit operating conditions are run in sequence, and regression testing operations are performed, thereby automatically completing the timing analysis and timing repair of each high-speed multiplexed IO. Therefore, the present application has the following beneficial effects: it can effectively shorten the timing closure time of each high-speed multiplexed IO, reduce the number of iterations, and effectively solve the technical problems existing in the existing high-speed multiplexed IO timing check, such as complex timing constraints, large static timing analysis calculations, large timing correction workload, and high timing closure time cost. Therefore, the present application effectively overcomes the various shortcomings of the prior art and has high industrial utilization value.

[0102] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical concepts disclosed in this application shall be covered by the claims of this application.< / clock> < / io>

Claims

1. A high-speed multiplexed IO timing closure method, applied to integrated circuit design, characterized in that: include: Constructing an IO multiplexing information table to obtain a plurality of high-speed multiplexing IOs for transmitting high-speed signals, and dividing each high-speed multiplexing IO into one or more high-speed multiplexing IO groups according to different IO functions of each high-speed multiplexing IO; Obtain the initial design layout of the integrated circuit and build the IO layout and routing netlist as well as IO timing constraints; Run the worst-case circuit operating conditions and perform timing analysis and repair operations on each high-speed multiplexing IO group based on the constructed IO layout and routing netlist and IO timing constraints until the timing of all high-speed multiplexing IOs in all high-speed multiplexing IO groups converges; Run multiple preset specified circuit operating conditions in sequence and perform regression testing on all high-speed multiplexed IOs until all high-speed multiplexed IO timings converge; Use place and route tools to update the initial design layout of the integrated circuit to obtain an optimized design layout.

2. The timing closure method for high-speed multiplexing IO according to claim 1, characterized in that: Ways to build IO placement and routing netlists and IO timing constraints include: According to the obtained initial design layout of the integrated circuit, obtaining a total layout and routing netlist and total timing constraints of the initial design layout; According to the overall layout and routing netlist, multiple functional elements associated with each high-speed multiplexed IO are screened, a circuit connection path between each high-speed multiplexed IO and each associated functional element is obtained, and the IO layout and routing netlist is constructed; According to different working modes of each high-speed multiplexed IO, multiple clocks are defined respectively, and the timing relationship between the input signal and output signal of each high-speed multiplexed IO and the clock signal generated by each clock is specified to construct the IO timing constraint.

3. The timing closure method for high-speed multiplexing IO according to claim 2, characterized in that: The IO timing constraints include: clock frequency constraints and clock period constraints of the clock signal, input delay constraints between the input signal and the clock signal, output delay constraints between the output signal and the clock signal, path delay constraints between the input signal and the output signal, and timing skew constraints between different data bits of the signal.

4. The timing closure method for high-speed multiplexing IO according to claim 1, characterized in that: Based on the constructed IO placement and routing netlist and IO timing constraints, the following methods are used to perform timing analysis and repair operations on the high-speed multiplexed IO group: Using a static timing analysis tool to perform a timing analysis operation on the high-speed multiplexed IO group to generate a timing analysis result of the high-speed multiplexed IO group; Determine whether the high-speed multiplexed IO group has achieved timing closure based on the timing analysis results and the IO timing constraints. If the high-speed multiplexed IO group has not achieved timing closure, perform a timing repair operation on the high-speed multiplexed IO group and generate a corresponding target IO timing engineering change instruction script. Using a placement and routing tool to run the target IO timing engineering change instruction script and update the IO placement and routing netlist; Based on the updated IO layout and routing netlist, a static timing analysis tool is used to re-perform timing analysis on the high-speed multiplexed IO group and determine whether the timing of the high-speed multiplexed IO group has converged. If the timing of the high-speed multiplexed IO group has not converged, a timing repair operation is performed on the high-speed multiplexed IO group. The iteration is repeated until the timing of the high-speed multiplexed IO group has converged.

5. The timing closure method for high-speed multiplexing IO according to claim 4, characterized in that: Use a static timing analysis tool to perform timing analysis on a high-speed multiplexed IO group. Methods for generating timing analysis results for the high-speed multiplexed IO group include: Generate a timing path list for the high-speed multiplexing IO group based on the IO placement and routing netlist; wherein the timing path list includes: multiple timing paths associated with each high-speed multiplexing IO in the high-speed multiplexing IO group; Generate an IO static timing analysis instruction script for the high-speed multiplexing IO group according to the timing path list and the IO timing constraints to calculate the timing margin of each timing path; Based on the timing margin of each timing path, a timing analysis result of the high-speed multiplexed IO group is generated to screen one or more timing violation paths. If a timing violation path exists within the high-speed multiplexed IO group, it is determined that the high-speed multiplexed IO group has not achieved timing closure. The timing analysis result includes: the IO function and operating mode of each high-speed multiplexed IO within the high-speed multiplexed IO group, as well as the timing margin of each timing path.

6. The timing closure method for high-speed multiplexing IO according to claim 4, characterized in that: Perform timing repair operations on high-speed multiplexed I / O groups that have not yet closed their timing and generate the corresponding target I / O timing engineering change instruction script in the following ways: Obtain one or more timing violation paths of a high-speed multiplexed IO group that has not reached timing convergence, perform timing repairs on each timing violation path, and generate a timing engineering change instruction script for each timing violation path; Generate an initial IO timing engineering change instruction script for the high-speed multiplexed IO group based on each timing engineering change instruction script, so as to be run by a static timing analysis tool and re-perform a timing analysis operation on the high-speed multiplexed IO group; Determine whether the high-speed multiplexed IO group simulates timing closure, and if the high-speed multiplexed IO group does not simulate timing closure, screen one or more new timing violation paths of the high-speed multiplexed IO group, perform timing repair on each new timing violation path, and update the initial IO timing engineering change instruction script; Repeat the iteration until the high-speed multiplexed IO group has simulated timing convergence, and generate the target IO timing engineering change instruction script of the high-speed multiplexed IO group.

7. The timing closure method for high-speed multiplexing IO according to claim 6, characterized in that: Ways to perform timing repair on timing violation paths include: Determine the timing target of the violating timing path according to the IO timing constraint, and determine whether the violating timing path needs to increase delay or shorten delay; If the delay needs to be increased, a target delay increase value of the violating timing path is calculated, and one or more buffers with preset specified transmission delay parameters are inserted between the buffer chains corresponding to the violating timing path accordingly, thereby generating a first type of timing engineering change instruction script; If the delay needs to be shortened, the target delay reduction value of the violating timing path is calculated, and based on this, one or more buffers with larger transmission delay parameters between the buffer chains corresponding to the violating timing path are replaced with one or more buffers with smaller transmission delay parameters to generate a second type of timing engineering change instruction script.

8. The timing closure method for high-speed multiplexing IO according to claim 1, characterized in that: The IO multiplexing information table includes: the high-speed function identifier and IO multiplexing information of each function selection mode; the IO multiplexing information includes: the functional element port of the integrated circuit associated with each IO in the current function selection mode and the corresponding port options; the options are the number of IOs that can be connected to the same port of the same functional element.

9. A high-speed multiplexed IO timing closure system, characterized in that: include: A high-speed multiplexed IO screening module is used to construct an IO multiplexing information table, obtain multiple high-speed multiplexed IOs for transmitting high-speed signals, and divide each high-speed multiplexed IO into one or more high-speed multiplexed IO groups according to the different IO functions of each high-speed multiplexed IO; A timing constraint construction module, connected to the high-speed multiplexing IO screening module, is used to obtain the initial design layout of the integrated circuit and construct an IO layout and routing netlist and IO timing constraints; A first timing closure module, connected to the timing constraint construction module, is used to run the worst circuit operating conditions and perform timing analysis and repair operations on each high-speed multiplexing IO group according to the constructed IO layout and routing netlist and IO timing constraints until all high-speed multiplexing IOs of all high-speed multiplexing IO groups have converged in timing; a second timing closure module, connected to the first timing closure module, configured to sequentially run a plurality of preset specified circuit operating conditions and perform regression testing operations on all high-speed multiplexed IOs until the timing of all high-speed multiplexed IOs is converged; The design layout update module is connected to the second timing closure module and is used to update the initial design layout of the integrated circuit using a placement and routing tool to obtain an optimized design layout.

10. A high-speed multiplexed IO timing closure terminal, characterized in that: include: processor and memory; The memory is used to store computer programs; The processor is configured to execute the computer program stored in the memory, so as to enable the high-speed multiplexing IO timing closure terminal to execute the high-speed multiplexing IO timing closure method according to any one of claims 1 to 8.

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