A true value table-based sensitive path judgment method, device, equipment and medium

Abstract

The present application relates to the technical field of integrated circuits, and discloses a sensitive path judgment method, device and equipment based on a truth table and a medium, the method comprising: obtaining a target lookup table in a circuit netlist and truth table data corresponding to the target lookup table; performing a binary bit operation on an input combination of the target lookup table to obtain at least one set of verification data; the verification data comprising a verification input combination and a verification output; obtaining a sensitive analysis result based on the at least one set of verification data and the truth table data; and judging a timing arc type of a timing path based on the sensitive analysis result. The above scheme uses a binary bit operation to process the input combination of the lookup table, which can quickly generate verification data; based on the verification data and the truth table data, the sensitive analysis result of the lookup table is obtained, so that the timing arc type of the timing path can be efficiently and accurately judged.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and specifically to a sensitive path determination method, apparatus, device, and medium based on a truth table. Background Technology

[0002] In digital circuit design, static timing analysis is often required to verify whether the logic unit delays between timing units (such as flip-flops, DSPs, RAMs, etc.) meet the setup and hold time requirements.

[0003] Logic units primarily refer to look-up tables (LUTs). Not all paths formed by logic units have a real impact on circuit performance. Some paths are insensitive, meaning the input signal will not propagate to the output; in other words, these paths do not exist. STAs should not analyze these paths, as the results would be overly pessimistic and deviate from reality, and it would also be a waste of time and space. Summary of the Invention

[0004] In view of this, the present invention provides a sensitive path determination method, apparatus, device and medium based on truth table to solve the problem that current static time series analysis cannot efficiently identify sensitive paths.

[0005] Firstly, the present invention provides a sensitive path determination method based on a truth table.

[0006] The method includes:

[0007] Obtain the target lookup table in the circuit netlist, and the truth table data corresponding to the target lookup table; the target timing path is composed of various lookup tables; the truth table data is used to characterize the mapping relationship between all input combinations and output values ​​of the corresponding target lookup table;

[0008] Perform binary bit operations on the input combinations of the target lookup table to obtain at least one set of verification data; the verification data includes verification input combinations and verification outputs;

[0009] Based on the at least one set of verification data and the truth table data, the sensitivity analysis results are obtained; the sensitivity analysis results include positive monotonically increasing, negative monotonically increasing, and non-monotonic.

[0010] Based on the sensitivity analysis results, the time arc type of the time path corresponding to the target lookup table is determined.

[0011] In one optional implementation, performing binary bit operations on the input combinations of the target lookup table to obtain at least one set of verification data includes:

[0012] Obtain the target input combination and the corresponding target output value from the target lookup table;

[0013] The target input value of the target input port in the target input combination is flipped, while the input values ​​of the other input ports remain unchanged, to obtain the verification input combination;

[0014] Based on the truth table data, obtain the verification output corresponding to the verification input combination.

[0015] The process of obtaining the sensitivity analysis results based on the at least one set of validation data and the truth table data includes:

[0016] Iterate through all input combinations of the target lookup table, and obtain each comparison result based on each input combination, the reversed input combination, the output value, and the verification output;

[0017] The sensitivity analysis results are obtained based on the comparison results.

[0018] In one optional implementation, the step of traversing all input combinations of the target lookup table according to the above steps, and obtaining each comparison result based on each input combination, the reversed input combination, the output value, and the verification output, includes:

[0019] The input combination and the flipped input combination are compared to determine the input flip type; the input flip type includes rising edge and falling edge.

[0020] Compare the output value with the verification output to determine the output toggle type; the output toggle type includes rising edge and falling edge.

[0021] The comparison result is determined based on the input flip type and the output flip type.

[0022] In one optional implementation, determining the comparison result based on the input flip type and the output flip type includes:

[0023] If the input flip type is the same as the output flip type, then the comparison result is positively monotonically increasing;

[0024] If the input flip type is different from the output flip type, then the comparison result is negative monotonically increasing.

[0025] In one optional implementation, obtaining the sensitivity analysis results based on the comparison results includes:

[0026] If all the comparison results are positively monotonically increasing, then the sensitivity analysis result is positively monotonically increasing.

[0027] If all the comparison results are negatively monotonically increasing, then the sensitivity analysis result is negatively monotonically increasing.

[0028] If each comparison result shows both positive and negative monotonically increasing, then the sensitivity analysis result is non-monotonic.

[0029] In one optional implementation, determining the time arc type of the time path corresponding to the target lookup table based on the sensitivity analysis results includes:

[0030] When the monotonicity of the input and output ports corresponding to the target timing path is consistent in each lookup table, the timing arc type of the target timing path is a positive function timing arc or a negative function timing arc.

[0031] When the monotonicity of the input and output ports corresponding to the target timing path in the target lookup table is inconsistent, the timing arc type of the target timing path is a non-functional timing arc.

[0032] In an optional implementation, the method further includes:

[0033] If there are non-functional time arcs in the time path corresponding to the target lookup table, then the non-functional time arcs will be removed during the time series analysis.

[0034] Secondly, the present invention provides a sensitive path determination device based on a truth table, the device comprising:

[0035] The path acquisition module acquires the target lookup table in the circuit netlist and the truth table data corresponding to the target lookup table; the target timing path is composed of various lookup tables; the truth table data is used to characterize the mapping relationship between all input combinations and output values ​​of the corresponding target lookup table;

[0036] An operation module is used to perform binary bit operations on the input combinations of the target lookup table to obtain at least one set of verification data; the verification data includes verification input combinations and verification outputs;

[0037] An analysis module is used to obtain the sensitivity analysis results based on the at least one set of verification data and the truth table data; the sensitivity analysis results include positive monotonically increasing, negative monotonically increasing, and non-monotonic;

[0038] The judgment module is used to determine the time arc type of the time path corresponding to the target lookup table based on the sensitivity analysis results.

[0039] In one optional implementation, the operation module is configured to:

[0040] Obtain the target input combination and the corresponding target output value from the target lookup table;

[0041] The target input value of the target input port in the target input combination is flipped, while the input values ​​of the other input ports remain unchanged, to obtain the verification input combination;

[0042] Based on the truth table data, obtain the verification output corresponding to the verification input combination;

[0043] The analysis module is used for:

[0044] Iterate through all input combinations of the target lookup table, and obtain each comparison result based on each input combination, the reversed input combination, the output value, and the verification output;

[0045] The sensitivity analysis results are obtained based on the comparison results.

[0046] In one optional implementation, the analysis module is further configured to:

[0047] The input combination and the flipped input combination are compared to determine the input flip type; the input flip type includes rising edge and falling edge.

[0048] Compare the output value with the verification output to determine the output toggle type; the output toggle type includes rising edge and falling edge.

[0049] The comparison result is determined based on the input flip type and the output flip type.

[0050] In one optional implementation, the analysis module is further configured to:

[0051] If the input flip type is the same as the output flip type, then the comparison result is positively monotonically increasing;

[0052] If the input flip type is different from the output flip type, then the comparison result is negative monotonically increasing.

[0053] In one optional implementation, the analysis module is further configured to:

[0054] If all the comparison results are positively monotonically increasing, then the sensitivity analysis result is positively monotonically increasing.

[0055] If all the comparison results are negatively monotonically increasing, then the sensitivity analysis result is negatively monotonically increasing.

[0056] If each comparison result shows both positive and negative monotonically increasing, then the sensitivity analysis result is non-monotonic.

[0057] In one optional implementation, the analysis module is further configured to:

[0058] When the monotonicity of the input and output ports corresponding to the target timing path is consistent in each lookup table, the timing arc type of the target timing path is a positive function timing arc or a negative function timing arc.

[0059] When the monotonicity of the input and output ports corresponding to the target timing path in the target lookup table is inconsistent, the timing arc type of the target timing path is a non-functional timing arc.

[0060] In one optional implementation, the analysis module is further configured to:

[0061] If there are non-functional time arcs in the time path corresponding to the target lookup table, then the non-functional time arcs will be removed during the time series analysis.

[0062] Thirdly, the present invention provides a computer device, including: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the computer instructions to perform the sensitive path determination method based on the truth table described in the first aspect or any corresponding embodiment.

[0063] Fourthly, the present invention provides a computer-readable storage medium storing computer instructions for causing a computer to execute the sensitive path determination method based on a truth table as described in the first aspect or any corresponding embodiment thereof.

[0064] Fifthly, the present invention provides a computer program product, including computer instructions, which are used to cause a computer to execute the sensitive path determination method based on a truth table as described in the first aspect or any corresponding embodiment.

[0065] The technical solution provided in this application may include the following beneficial effects:

[0066] The process involves obtaining the target lookup table from the circuit netlist and the corresponding truth table data. The target timing path is composed of various lookup tables. The truth table data represents the mapping relationship between all input combinations and output values ​​of the corresponding target lookup table. Binary bit operations are then performed on the input combinations of the target lookup table to obtain at least one set of verification data. The verification data includes verification input combinations and verification outputs. Based on the at least one set of verification data and the truth table data, the sensitivity analysis result of the target timing path is determined to be positively monotonically increasing, negatively monotonically increasing, or non-monotonic. Based on the sensitivity analysis result, the timing arc type of the target timing path can be determined. This scheme utilizes binary bit operations to process the input combinations of the lookup table, which can quickly generate verification data. Based on the verification data and the truth table data, the sensitivity analysis result of the lookup table is obtained, thus enabling efficient and accurate determination of the timing arc type of the timing path. Attached Figure Description

[0067] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0068] Figure 1 This is a flowchart illustrating a sensitive path determination method based on a truth table according to an embodiment of the present invention.

[0069] Figure 2 This is a flowchart illustrating another sensitive path determination method based on a truth table according to an embodiment of the present invention.

[0070] Figure 3 This is a structural block diagram of a sensitive path determination device based on a truth table according to an embodiment of the present invention;

[0071] Figure 4 This is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. Detailed Implementation

[0072] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0073] In digital circuit design, static timing analysis is often required to verify whether the logic unit delays between timing units (such as flip-flops, DSPs, RAMs, etc.) meet the setup and hold time requirements.

[0074] Logic units primarily refer to look-up tables (LUTs). Not all paths formed by logic units have a real impact on circuit performance. Some paths are insensitive, meaning the input signal will not propagate to the output; in other words, these paths do not exist. STAs should not analyze these paths, as the results would be overly pessimistic and deviate from reality, and it would also be a waste of time and space.

[0075] LUTs can be configured (programmed) to implement different logical operations, such as AND, OR, NOT, XOR, etc., as well as more complex combinational logic functions. Their working principle is similar to a pre-filled mapping table, i.e., a truth table, which directly looks up the output result based on the combination of input signals. In other words, the functionality of the LUT and the characteristics of timing analysis are uniquely determined by its internal truth table. This invention provides a sensitive path identification method based on a truth table to solve the problem that current static timing analysis fails to efficiently identify sensitive paths.

[0076] According to an embodiment of the present invention, a sensitive path determination method based on a truth table is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0077] This embodiment provides a sensitive path determination method based on a truth table, which can be used in computer devices. Figure 1 This is a flowchart of a sensitive path determination method based on a truth table according to an embodiment of the present invention, as shown below. Figure 1 As shown, the process includes the following steps:

[0078] Step 101: Obtain the target lookup table in the circuit netlist and the truth table data corresponding to the target lookup table.

[0079] In this embodiment, the timing path is composed of various lookup tables. Therefore, to determine whether each timing path needs to be pruned, it is first necessary to analyze the lookup tables that constitute the timing path. For the target lookup table in each lookup table, the truth table data in the target lookup table is used to characterize the mapping relationship between all input combinations and output values ​​of the corresponding target lookup table.

[0080] In this embodiment, the netlist file of the circuit can be read to identify and locate the target timing path. The netlist details the circuit components and their connections. Further, on the target path, all LUT components are identified, and their identifiers and connections are obtained. For each LUT, its truth table is extracted or generated, clarifying all input combinations and their corresponding output values.

[0081] Step 102: Perform binary bit operations on the input combination of the target lookup table to obtain at least one set of verification data; the verification data includes the verification input combination and the verification output.

[0082] In this embodiment, all possible input combinations are determined based on the number of bits in the LUT input. Then, for each input combination, a specific binary bit operation (such as flipping a bit) is performed to generate a new input combination. Finally, the original input combination, the bit-operated input combination, and their corresponding output values ​​(obtained by consulting the truth table) are combined to form a verification dataset.

[0083] Step 103: Based on the at least one set of validation data and the truth table data, obtain the sensitivity analysis results; the sensitivity analysis results include positive monotonically increasing, negative monotonically increasing, and non-monotonic.

[0084] In the embodiments of this application, by using verification data to observe the effect of input changes (such as a bit changing from 0 to 1 or from 1 to 0) on the output, it can be determined whether the target lookup table is positively monotonically increasing, negatively monotonically increasing, or non-monotonic.

[0085] Step 104: Based on the sensitivity analysis results, determine the timing arc type of the timing path.

[0086] The sensitivity analysis results of all LUTs on the target path are summarized. If all LUTs on the path are positively monotonically increasing or negatively monotonically increasing, the path is considered a sensitive path. In this case, the time arc type of the time series path can be a positive function time arc or a negative function time arc. If there are non-monotonic LUTs in a time series path, such as one path being positively monotonically increasing and another being positively monotonically decreasing, or the sensitivity combination between LUTs makes the path insensitive to input changes, then the time arc type corresponding to the target time series path is a non-function time arc. Subsequent time series analysis can ignore the path of the non-function time arc, thereby improving the analysis efficiency of path time series analysis.

[0087] In summary, the target lookup table in the circuit netlist and the corresponding truth table data are obtained, and the target timing path is composed of various lookup tables. The truth table data represents the mapping relationship between all input combinations and output values ​​of the corresponding target lookup table. Binary bit operations are then performed on the input combinations of the target lookup table to obtain at least one set of verification data. The verification data includes verification input combinations and verification outputs. Based on at least one set of verification data and the truth table data, the sensitivity analysis result of the target timing path is determined to be positively monotonically increasing, negatively monotonically increasing, or non-monotonic. Based on the sensitivity analysis result, the timing arc type of the target timing path can then be determined. This scheme utilizes binary bit operations to process the input combinations of the lookup table, which can quickly generate verification data. Based on the verification data and the truth table data, the sensitivity analysis result of the lookup table is obtained, thus enabling efficient and accurate determination of the timing arc type of the timing path.

[0088] This embodiment provides a sensitive path determination method based on a truth table, which can be used in the aforementioned computer equipment. Figure 2 This is a flowchart of a sensitive path determination method based on a truth table according to an embodiment of the present invention, as shown below. Figure 2 As shown, the process includes the following steps:

[0089] Step 201: Obtain the target lookup table in the circuit netlist and the truth table data corresponding to the target lookup table.

[0090] The circuit netlist file is read to parse out the types, connections, and timing path information of each component in the circuit. The target timing path is determined, which is a path composed of several interconnected lookup tables. All LUT components are sequentially identified along the target timing path, and the identification information of each LUT and its position within the entire path are obtained. For each target lookup table, its truth table data is extracted or calculated. The truth table data provides all input combinations of the LUT and their corresponding output values, providing a basis for subsequent sensitivity analysis.

[0091] Step 202: Obtain the target input combination and the corresponding target output value of the target lookup table.

[0092] For each lookup table extracted in step 201, determine one or more target input combinations from its truth table, and simultaneously obtain the output values ​​corresponding to these combinations.

[0093] Step 203: Invert the target input value of the target input port in the target input combination, and keep the input values ​​of the other input ports unchanged to obtain the verification input combination.

[0094] Specifically, one or more input ports to be flipped are selected from the target input combination; then the input values ​​of the selected ports are inverted while the other inputs remain unchanged, thus obtaining a new verification input combination, so as to observe the output response through single-point or multi-point input changes.

[0095] Step 204: Based on the truth table data, obtain the verification output corresponding to the verification input combination.

[0096] Based on the verification input combinations generated in step 203, the verification outputs corresponding to these verification input combinations are determined by consulting the truth table data.

[0097] Step 205: Traverse all input combinations of the target lookup table, and obtain each comparison result based on each input combination, the reversed input combination, the output value, and the verification output.

[0098] Specifically, each target input combination of the LUT is processed individually. The original input combination is compared with the flipped verification input combination to identify which input port has changed.

[0099] In one possible implementation, the input combination and the flipped input combination are compared to determine the input flip type; the input flip type includes rising edge and falling edge; the output value is compared with the verification output to determine the output flip type; the output flip type includes rising edge and falling edge; the comparison result is determined based on the input flip type and the output flip type.

[0100] Compare the original input combination with the input combination after the inversion operation, and observe which input port value changed. If the value of that port changes from 0 to 1, the input change is considered a "rising edge"; if it changes from 1 to 0, it is considered a "falling edge". Similarly, compare the original output value with the verification output (i.e., the output value after the inversion input), and observe the change in the output value. If the output value changes from low to high, it is considered a "rising edge"; if it changes from high to low, it is considered a "falling edge".

[0101] In one possible implementation, if the input flip type and the output flip type are the same, the comparison result is positive and monotonically increasing; if the input flip type and the output flip type are different, the comparison result is negative and monotonically increasing.

[0102] In this embodiment, the logical relationship can be determined based on the matching of the input flip type and the output flip type: if the input flip and the output flip are of the same type (both rising edge or both falling edge), it indicates that the input change and the output change are in the same direction, corresponding to a positive monotonically increasing case. If the input flip and the output flip are of different types (e.g., the input is a rising edge, while the output is a falling edge), it indicates that there is a reverse change, corresponding to a negative monotonically increasing case.

[0103] Step 206: Based on the comparison results, obtain the sensitivity analysis results.

[0104] By using the results of each sensitivity analysis, the sensitivity of the entire time series path is comprehensively judged, thereby determining whether the path is sensitive to the input data, and performing path pruning optimization on insensitive paths.

[0105] Specifically, if all comparison results are positively monotonically increasing, then the sensitivity analysis result is positively monotonically increasing; if all comparison results are negatively monotonically increasing, then the sensitivity analysis result is negatively monotonically increasing; if all comparison results exhibit both positive and negative monotonically increasing trends, then the sensitivity analysis result is non-monotonic.

[0106] Step 207: Based on the sensitivity analysis results, determine the timing arc type of the timing path.

[0107] In a possible implementation, when the monotonicity of the input and output ports corresponding to the target timing path in each lookup table is consistent, the timing arc type of the target timing path is a positive function timing arc or a negative function timing arc;

[0108] When the monotonicity of the input and output ports corresponding to the target timing path in the target lookup table is inconsistent, the timing arc type of the target timing path is a non-function timing arc.

[0109] In a possible implementation, if there is a non-function timing arc in the timing path corresponding to the target lookup table, the non-function timing arc is removed during the timing analysis process, so as to achieve pruning of the non-function timing arc during the timing analysis process.

[0110] Specifically, according to the connection order of the logic units (LUTs), the subsequent logic units starting from the first non-monotonic lookup table in the target timing path can be removed, so as to obtain a "pruned sensitive path", the purpose of which is to only retain those critical paths that can stably respond to input changes for subsequent optimization and verification.

[0111] The following specifically describes the processing process of a single LUT in combination with a specific scenario.

[0112] For a timing arc with sensitivity of positve-unate, there are only two sensitive paths: rise-rise and fall-fall. For a timing arc with sensitivity of negative-unate, there are only two sensitive paths: rise-fall and fall-rise. For a timing arc with sensitivity of non-unate, there are the above 4 paths.

[0113] By processing multiple LUTs in parallel, using a multi-threaded or distributed computing framework, the sensitivities of multiple LUTs are judged simultaneously. The following will detail the processing process of a single LUT.

[0114] Function (input parameter: id):

[0115] Initialize variables:

[0116] state = unknown / / The initial state is unknown

[0117] bitOffset = 1 << id / / The offset of the current input

[0118] Traverse all possible input combinations:

[0119] Execute for i from 0 to the number of LUT input ports:

[0120] / / Extract the current bit value and the next bit value

[0121] currBitVal = (currInit >> i) & 1

[0122] nextBitVal=(currInit>>(i+bitOffset))&1

[0123] / / Determine the state

[0124] If currBitVal is 1 and nextBitVal is 0, then 1.fall

[0125] If state is unknown:

[0126] state = negative-unate

[0127] Otherwise, if the state is positive-unate:

[0128] return non-unate / / Exit check

[0129] If currBitVal is 0 and nextBitVal is 1: / / 2.rise

[0130] If state is unknown:

[0131] state = positive-unate

[0132] Otherwise, if the state is negative-unate:

[0133] return non-unate / / Exit check

[0134] return state

[0135] The judgment logic is as follows: Iterate through all possible combinations of changes corresponding to the current input port, and find the changes of the output port from the truth table:

[0136] 1. If the change in the input port is consistent with the change in the output port, it is temporarily considered a positive unate, and the investigation continues.

[0137] 2. If the change in the input port is opposite to that of the output port, it is temporarily considered a negative-unate, and the investigation continues.

[0138] 3. If an expression appears that is both positive-unate and negative-unate, it is considered non-unate, and the check is terminated.

[0139] Furthermore, in this embodiment, different LUTs can be processed in parallel, that is, multiple LUTs are assigned to different threads, and each thread independently processes the sensitivity judgment task of one or more LUTs.

[0140] Therefore, the technical solution shown in this application supports parallel path classification for multiple input combinations, combining path judgment logic with parallel computing. It can simultaneously process the input signal flips of multiple LUTs, thereby quickly determining the type of each path. This method effectively reduces the overhead of repetitive computation through batch operations, significantly improving the path analysis efficiency of large-scale designs; it also quickly parses the truth table of the input signal using binary bit operations (such as bit shifting and bitwise AND) to extract the current state (currBitVal) and the flip state (nextBitVal) from the input signal.

[0141] During path classification, a state machine mechanism and consistency check logic are employed to ensure the accuracy and reliability of the classification results. Initial state protection: the initial state is unknown to avoid misclassification of path type.

[0142] The scheme illustrated in this application embodiment can also be specifically optimized for path analysis in large-scale designs: it has wide adaptability and is suitable for static timing analysis of complex logic designs such as FPGAs and ASICs. It significantly improves efficiency by reducing analysis time through parallelization and automation processes; it is well-suited for large-scale designs, especially in reducing invalid path checks in complex logic netlists.

[0143] In summary, the target lookup table in the circuit netlist and the corresponding truth table data are obtained, and the target timing path is composed of various lookup tables. The truth table data represents the mapping relationship between all input combinations and output values ​​of the corresponding target lookup table. Binary bit operations are then performed on the input combinations of the target lookup table to obtain at least one set of verification data. The verification data includes verification input combinations and verification outputs. Based on at least one set of verification data and the truth table data, the sensitivity analysis result of the target timing path is determined to be positively monotonically increasing, negatively monotonically increasing, or non-monotonic. Based on the sensitivity analysis result, the sensitive and non-sensitive paths of the target timing path can be determined. This scheme utilizes binary bit operations to process the input combinations of the lookup table, which can quickly generate verification data. Based on the verification data and the truth table data, the sensitivity analysis result of the lookup table is obtained, thus enabling efficient and accurate determination of the timing arc type of the timing path.

[0144] This embodiment also provides a sensitive path determination device based on a truth table, which is used to implement the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0145] This embodiment provides a sensitive path determination device based on a truth table, such as... Figure 3 As shown, it includes:

[0146] The path acquisition module 301 acquires the target lookup table in the circuit netlist and the truth table data corresponding to the target lookup table; the target timing path is composed of various lookup tables; the truth table data is used to characterize the mapping relationship between all input combinations and output values ​​of the corresponding target lookup table;

[0147] Operation module 302 is used to perform binary bit operations on the input combinations of the target lookup table to obtain at least one set of verification data; the verification data includes verification input combinations and verification outputs;

[0148] Analysis module 303 is used to obtain the sensitivity analysis results based on the at least one set of verification data and the truth table data; the sensitivity analysis results include positive monotonically increasing, negative monotonically increasing, and non-monotonic;

[0149] The judgment module 304 is used to determine the timing arc type of the timing path based on the sensitivity analysis results.

[0150] In one optional implementation, the operation module is configured to:

[0151] Obtain the target input combination and the corresponding target output value from the target lookup table;

[0152] The target input value of the target input port in the target input combination is flipped, while the input values ​​of the other input ports remain unchanged, to obtain the verification input combination;

[0153] Based on the truth table data, obtain the verification output corresponding to the verification input combination;

[0154] The analysis module is used for:

[0155] Iterate through all input combinations of the target lookup table, and obtain each comparison result based on each input combination, the reversed input combination, the output value, and the verification output;

[0156] The sensitivity analysis results are obtained based on the comparison results.

[0157] In one optional implementation, the analysis module is further configured to:

[0158] The input combination and the flipped input combination are compared to determine the input flip type; the input flip type includes rising edge and falling edge.

[0159] Compare the output value with the verification output to determine the output toggle type; the output toggle type includes rising edge and falling edge.

[0160] The comparison result is determined based on the input flip type and the output flip type.

[0161] In one optional implementation, the analysis module is further configured to:

[0162] If the input flip type is the same as the output flip type, then the comparison result is positively monotonically increasing;

[0163] If the input flip type is different from the output flip type, then the comparison result is negative monotonically increasing.

[0164] In one optional implementation, the analysis module is further configured to:

[0165] If all the comparison results are positively monotonically increasing, then the sensitivity analysis result is positively monotonically increasing.

[0166] If all the comparison results are negatively monotonically increasing, then the sensitivity analysis result is negatively monotonically increasing.

[0167] If each comparison result shows both positive and negative monotonically increasing, then the sensitivity analysis result is non-monotonic.

[0168] In one optional implementation, the analysis module is further configured to:

[0169] When the monotonicity of the input and output ports corresponding to the target timing path is consistent in each lookup table, the timing arc type of the target timing path is a positive function timing arc or a negative function timing arc.

[0170] When the monotonicity of the input and output ports corresponding to the target timing path in the target lookup table is inconsistent, the timing arc type of the target timing path is a non-functional timing arc.

[0171] In one optional implementation, the analysis module is further configured to:

[0172] If there are non-functional time arcs in the time path corresponding to the target lookup table, then the non-functional time arcs will be removed during the time series analysis.

[0173] In summary, the target lookup table in the circuit netlist and the corresponding truth table data are obtained, and the target timing path is composed of various lookup tables. The truth table data represents the mapping relationship between all input combinations and output values ​​of the corresponding target lookup table. Binary bit operations are then performed on the input combinations of the target lookup table to obtain at least one set of verification data. The verification data includes verification input combinations and verification outputs. Based on at least one set of verification data and the truth table data, the sensitivity analysis result of the target timing path is determined to be positively monotonically increasing, negatively monotonically increasing, or non-monotonic. Based on the sensitivity analysis result, the timing arc type of the target timing path can then be determined. This scheme utilizes binary bit operations to process the input combinations of the lookup table, which can quickly generate verification data. Based on the verification data and the truth table data, the sensitivity analysis result of the lookup table is obtained, thus enabling efficient and accurate determination of the timing arc type of the timing path.

[0174] Further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0175] In this embodiment, the sensitive path determination device based on the truth table is presented in the form of a functional unit. Here, a unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0176] This invention also provides a computer device having the above-described features. Figure 3 The sensitive path detection device based on the truth table is shown.

[0177] Please see Figure 4 , Figure 4 This is a schematic diagram of the structure of a computer device provided in an optional embodiment of the present invention, such as... Figure 4 As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 4Take a processor 10 as an example.

[0178] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GPA), or any combination thereof.

[0179] The memory 20 stores instructions executable by at least one processor 10 to cause the at least one processor 10 to perform the method shown in the above embodiments.

[0180] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0181] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0182] The computer device also includes a communication interface 30 for communicating with other devices or communication networks.

[0183] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.

[0184] A portion of this invention can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to the invention through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions, or the computer compiling the instructions and then executing the corresponding compiled program, or the computer reading and executing the instructions, or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0185] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A sensitive path determination method based on a truth table, characterized in that, The method includes: Obtain the target lookup table in the circuit netlist, and the truth table data corresponding to the target lookup table; the truth table data is used to characterize the mapping relationship between all input combinations and output values ​​of the corresponding target lookup table; Perform binary bit operations on the input combinations of the target lookup table to obtain at least one set of verification data; the verification data includes verification input combinations and verification outputs; Based on the at least one set of verification data and the truth table data, sensitivity analysis results are obtained; the sensitivity analysis results include positive monotonically increasing, negative monotonically increasing, and non-monotonic. Based on the sensitivity analysis results, the time arc type of the time path corresponding to the target lookup table is determined.

2. The method according to claim 1, characterized in that, The step of performing binary bit operations on the input combinations of the target lookup table to obtain at least one set of verification data includes: Obtain the target input combination and the corresponding target output value from the target lookup table; The target input value of the target input port in the target input combination is flipped, while the input values ​​of the other input ports remain unchanged, to obtain the verification input combination; Based on the truth table data, obtain the verification output corresponding to the verification input combination; The process of obtaining the sensitivity analysis results based on the at least one set of validation data and the truth table data includes: Iterate through all input combinations of the target lookup table, and obtain each comparison result based on each input combination, the reversed input combination, the output value, and the verification output; The sensitivity analysis results are obtained based on the comparison results.

3. The method according to claim 2, characterized in that, The sensitivity analysis results obtained based on the comparison results include: If all the comparison results are positively monotonically increasing, then the sensitivity analysis result is positively monotonically increasing. If all the comparison results are negatively monotonically increasing, then the sensitivity analysis result is negatively monotonically increasing. If each comparison result shows both positive and negative monotonically increasing, then the sensitivity analysis result is non-monotonic.

4. The method according to claim 3, characterized in that, The comparison results are obtained based on each input combination, the inverted input combination, the output value, and the verification output, including: Iterate through all input combinations of the target lookup table, and for each input combination, perform the following operations: The input combination and the flipped input combination are compared to determine the input flip type; the input flip type includes rising edge and falling edge. Compare the output value with the verification output to determine the output toggle type; the output toggle type includes rising edge and falling edge. The comparison result is determined based on the input flip type and the output flip type.

5. The method according to claim 4, characterized in that, Determining the comparison result based on the input flip type and the output flip type includes: If the input flip type is the same as the output flip type, then the comparison result is positively monotonically increasing; If the input flip type is different from the output flip type, then the comparison result is negative monotonically increasing.

6. The method according to any one of claims 2 to 5, characterized in that, The step of determining the time series arc type of the time series path corresponding to the target lookup table based on the sensitivity analysis results includes: When the monotonicity of the input and output ports corresponding to the target timing path is consistent in each lookup table, the timing arc type of the target timing path is a positive function timing arc or a negative function timing arc. When the monotonicity of the input and output ports corresponding to the target timing path in the target lookup table is inconsistent, the timing arc type of the target timing path is a non-functional timing arc.

7. The method according to claim 6, characterized in that, The method further includes: If there are non-functional time arcs in the time path corresponding to the target lookup table, then the non-functional time arcs will be removed during the time series analysis.

8. A sensitive path determination device based on a truth table, characterized in that, The device includes: The path acquisition module acquires the target lookup table in the circuit netlist and the truth table data corresponding to the target lookup table; the truth table data is used to characterize the mapping relationship between all input combinations and output values ​​of the corresponding target lookup table. The operation module performs binary bit operations on the input combinations of the target lookup table to obtain at least one set of verification data; the verification data includes verification input combinations and verification output. An analysis module is used to obtain sensitivity analysis results based on the at least one set of verification data and the truth table data; the sensitivity analysis results include positive monotonically increasing, negative monotonically increasing, and non-monotonic; The judgment module is used to determine the time arc type of the time path corresponding to the target lookup table based on the sensitivity analysis results.

9. A computer device, characterized in that, include: The system includes a memory and a processor, which are interconnected. The memory stores computer instructions, and the processor executes the computer instructions to perform a sensitive path determination method based on a truth table, as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing the computer to execute a sensitive path determination method based on a truth table as described in any one of claims 1 to 7.

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