Design examination method and device of printed circuit board, electronic equipment and storage medium

Abstract

The invention discloses a printed circuit board design review method and device, electronic equipment and a storage medium, and relates to the technical field of printed circuit board design review, and the method comprises the steps: disassembling complex review into a plurality of calculation tasks, respectively mapping the calculation tasks to corresponding hardware acceleration modules, and carrying out the parallel processing capability, the continuous value and the probability value output by the pre-trained review model are quickly obtained, the review time is greatly shortened, and the review efficiency is improved. By means of the review model based on mass data training, design data is comprehensively and accurately analyzed, the defect that errors are prone to occurring in manual review is avoided, and review accuracy is remarkably improved. Quantized data output by the model provides a basis for judging design data quality and positioning problem types, and assists in discovering potential problems. Meanwhile, a clear examination result is output according to the model, and a problem attribute and an optimization strategy are given, so that a direction is indicated for design improvement, the manual investigation and thinking cost is reduced, and the manual and trial and error cost is effectively reduced.

Description

Technical Field

[0001] The present application relates to the technical field of printed circuit board design review, and in particular to a printed circuit board design review method, device, electronic device and storage medium. Background Art

[0002] Printed Circuit Board (PCB) design is the process of implementing circuit functionality by rationally planning the layout of electronic components and laying out their connections according to circuit schematics. This encompasses a series of operations, from circuit schematic planning to the final production file output. PCB layout and routing focuses on the specific operations involved. Layout refers to the proper placement of components on the PCB, while routing involves designing the electrical connections between the laid-out components.

[0003] However, the current PCB layout and wiring review method has many drawbacks. Traditional review mainly relies on manual experience. Even if the PCB design software has its own wiring tools for preliminary layout, manual adjustment and review are still required based on complex factors such as board size, layout requirements, and signal interference. As the complexity of boards increases day by day, manual review faces huge challenges. On the one hand, labor costs have risen sharply, and wiring personnel need long-term professional training and rich experience accumulation to cope with complex designs; on the other hand, review efficiency is extremely low, defect detection is inconsistent, it is difficult to detect problems in real time and comprehensively, and data collection is also difficult. In addition, although existing electronic design automation (EDA) tools have certain automation functions, they cannot meet the stringent requirements of high precision and high efficiency when dealing with complex server PCB designs, resulting in extended product development cycles and increased costs, which seriously restricts the development of the electronic equipment manufacturing industry. Summary of the Invention

[0004] The present application provides a design review method, device, electronic device and storage medium for a printed circuit board, in order to at least solve the problems in the related art of EDA tools that rely on manual experience and have limited automation functions, resulting in high labor and trial-and-error costs, low review efficiency and poor accuracy, and difficulty in meeting the high-precision and high-efficiency requirements of complex server PCB designs.

[0005] The present application provides a design review method for a printed circuit board, comprising: obtaining design data of a printed circuit board to be reviewed; generating computing tasks corresponding to the design data based on the design data and a pre-trained review model; mapping at least one of the computing tasks to a corresponding hardware acceleration module to obtain a computing result of the at least one computing task through the hardware acceleration module; obtaining a continuous value and / or a probability value output by the review model based on the computing result of the at least one computing task, wherein the continuous value is used to indicate whether the design data is qualified, and the probability value is used to indicate the possibility that the design data belongs to a pre-marked problem type; determining a review result based on the continuous value and / or the probability value, wherein the review result includes problem attributes and optimization strategies corresponding to the design data.

[0006] The present application also provides a design review device for a printed circuit board, comprising:

[0007] A data acquisition module, used to acquire design data of the printed circuit board to be reviewed;

[0008] A computing task generation module is used to generate computing tasks corresponding to the design data based on the design data and the pre-trained review model;

[0009] a mapping module, configured to map at least one of the computing tasks to a corresponding hardware acceleration module, so as to obtain a computing result of the at least one computing task through the hardware acceleration module;

[0010] a review module, configured to obtain a continuous value and / or a probability value output by the review model based on the calculation results of at least one calculation task, wherein the continuous value is used to indicate whether the design data is qualified, and the probability value is used to indicate the possibility that the design data belongs to a pre-marked problem type;

[0011] The review result output module is used to determine the review result based on the continuous value and / or probability value. The review result includes the problem attributes and optimization strategy corresponding to the design data.

[0012] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned printed circuit board design review methods when executing the computer program.

[0013] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned printed circuit board design review methods are implemented.

[0014] The present application also provides a computer program product, comprising a computer program, which implements the steps of any of the above-mentioned printed circuit board design review methods when executed by a processor.

[0015] Through this application, the complex PCB design review is broken down into multiple computing tasks, each task is mapped to the corresponding hardware acceleration module, and different hardware modules can handle multiple computing tasks at the same time. Compared with relying entirely on manual review, it can quickly determine the continuous value and probability value output by the pre-trained review model, greatly shortening the review time and solving the problem of low efficiency of manual review. The review is conducted using a pre-trained review model, which is trained based on a large amount of data. It can analyze the design data more comprehensively and accurately, reduce the error-prone situations in manual review, and improve the accuracy of the review. The continuous value and probability value output by the review model provide a quantitative basis for judging whether the design data is qualified and what type of problem it belongs to, which helps to discover potential problems more accurately. The review results are determined according to the output of the review model, and the problem attributes and optimization strategies are given. This provides a direction for subsequent design improvements, reduces the time and energy of manual problem investigation and thinking about improvement methods, and reduces labor costs and trial and error costs to a certain extent. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0017] Figure 1A A schematic diagram of a specific application environment architecture on which the execution of a printed circuit board design review method provided in an embodiment of the present application relies;

[0018] Figure 1B A schematic diagram of the structure of the FPGA hardware acceleration module provided in an embodiment of the present application;

[0019] Figure 2 A schematic diagram of a flow chart of a design review method for a printed circuit board provided in an embodiment of the present application;

[0020] Figure 3 A schematic structural diagram of a printed circuit board design review device provided in an embodiment of the present application;

[0021] Figure 4 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0022] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0023] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0024] In order to more clearly illustrate the embodiments of the present application, the following briefly introduces the technical terms used in the embodiments:

[0025] A printed circuit board (PCB), also known as a printed circuit board or printed circuit board, is an important electronic component. It consists of an insulating base, connecting wires, and pads for assembling and soldering electronic components, serving the dual functions of a conductive circuit and an insulating base. By printing a conductive pattern on an insulating base, various electronic components such as resistors, capacitors, and chips are connected together according to design requirements, achieving electrical connections and signal transmission in electronic devices, enabling them to function properly. PCBs are an indispensable component in electronic devices and are widely used in numerous fields, including computers, communications, consumer electronics, automotive electronics, and aerospace.

[0026] Electronic Design Automation (EDA) tools are software tools used to assist engineers in a range of electronic design tasks, including circuit design, simulation, verification, layout drawing, and chip manufacturing. They automate and intelligently process complex electronic system design processes, significantly improving design efficiency, reducing design costs, and minimizing design errors. Using EDA tools, engineers can complete the entire process from system-level design to physical layout design on a computer. They are widely used in fields such as integrated circuit design and printed circuit board design.

[0027] A Field Programmable Gate Array (FPGA) is an integrated circuit based on configurable logic cells. Users can customize its internal logic functions and connections through programming to implement different digital circuit functions. It is often used in scenarios that require flexible implementation of various logic functions and a short development cycle.

[0028] A graphics processing unit (GPU) is a processor specifically designed for rapidly processing graphics data and performing complex graphics rendering tasks. It can process large amounts of image data in parallel, freeing the CPU from the heavy lifting of graphics processing, significantly improving the computer's graphics processing capabilities and display performance. GPUs are widely used in fields that require processing large amounts of graphics data.

[0029] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0030] In conjunction with the specific application environment architecture or specific hardware architecture on which the execution of the printed circuit board design review method depends, the specific application environment architecture or specific hardware architecture is described herein.

[0031] like Figure 1A As shown in the figure, the application environment architecture includes a PCB design data interface, an FPGA hardware acceleration module, and a review result output module. The FPGA hardware acceleration module includes an artificial intelligence algorithm module. The artificial intelligence algorithm module uses artificial intelligence algorithms to analyze and process input PCB design data, such as identifying errors and defects in the design.

[0032] The PCB design data interface is responsible for importing, parsing, and processing PCB design data from various EDA tools, converting it into a format that the system can handle. Core functions of the PCB design data interface include supporting multiple file formats, extracting design elements, format conversion, and error detection and resolution. The PCB design data interface supports large-scale, rapid import of PCB design data, offering high efficiency and scalability.

[0033] The FPGA hardware acceleration module is mapped with artificial intelligence algorithms, which are responsible for analyzing, optimizing and identifying problems in PCB design data. Figure 1BAs shown, the FPGA hardware acceleration module includes a data interface, a computation unit, and memory. The data interface is responsible for communicating with the host computer to receive input data and return computation results. This data interface can be based on the high-speed Peripheral Component Interconnect Express (PCIe) bus standard, ensuring that data throughput meets computational requirements. The computation unit of the FPGA hardware acceleration module is built based on the FPGA's logic units, such as logic look-up tables (LUTs) and digital signal processing (DSPs). This computation unit is responsible for the core computation of the pre-trained review model, including but not limited to convolution operations, matrix multiplication, and activation functions. Different computational tasks correspond to different computation units, such as the first computation unit for layout optimization and the second computation unit for routing optimization. The memory is used to store the input data, intermediate results, and model parameters of the pre-trained review model, thereby avoiding latency caused by accessing external memory and optimizing access efficiency. FPGAs have parallel computing capabilities, and this module provides hardware acceleration support for the execution of artificial intelligence algorithms, improving computational efficiency and shortening processing time. The combination of these two elements fully utilizes the FPGA's parallel computing power and reconfigurability to efficiently process PCB design data.

[0034] The review result output module is responsible for presenting the analysis results of the FPGA hardware acceleration module to the user in a clear and intuitive manner, making it convenient for designers or related personnel to obtain review information so that they can improve or confirm the PCB design.

[0035] An embodiment of the present application provides a design review method for a printed circuit board. The method is described in detail in conjunction with the execution flow of the design review method for a printed circuit board.

[0036] like Figure 2 As shown, Figure 2 A schematic flow chart of a design review method for a printed circuit board provided in an embodiment of the present application, the method comprising the following steps S201 to S205:

[0037] S201. Obtain design data of a printed circuit board to be reviewed.

[0038] Specifically, the PCB design data interface communicates with the processor to obtain the design data of the printed circuit board (PCB) to be reviewed from different electronic design automation (EDA) tools. The processor can be a central processing unit (CPU) or a GPU.

[0039] The PCB design data interface may be PCIe. The EDA tool may be Altium Designer, Cadence Allegro, Eagle, OrCAD, KiCad, etc., which is not specifically limited in this application.

[0040] Design data includes image data and graph structure data. The image data can be a circuit schematic diagram, which contains the circuit board's layer settings, component layout, wiring information, via parameters, network definitions, etc.

[0041] After obtaining the design data of the printed circuit board to be reviewed, the following steps S2011 to S2013 may be performed:

[0042] S2011. Check whether the design data is wrong or missing.

[0043] When errors or missing design data are detected in the PCB to be reviewed, an error prompt is generated and displayed to the user.

[0044] If not, execute step S2012.

[0045] By automatically detecting logical errors (such as network connection conflicts) or missing data (such as missing layer definitions) before design data enters the review process, downstream calculation tasks are prevented from running based on erroneous data. This reduces invalid calculations, minimizes hardware resource waste, and reduces the chain reaction problems caused by error propagation.

[0046] S2012. Convert the design data into design data in a universal format.

[0047] PCB design data from different EDA tools come in different formats, such as the Gerber format, the database format (ODB++), and the electronic assembly and interconnect design data exchange format (IPC-2581).

[0048] For example, Altium Designer primarily uses the .PcbDoc format to store PCB design data. Autodesk EAGLE (Eagle) uses data storage formats such as .brd (for PCB design files) and .sch (for schematic design files). OrCAD uses a variety of file formats to manage PCB design data. Common ones include .brd (for PCB design files) and .dsn (for schematic design files). .kicad_pcb is the PCB design file format used by KiCad.

[0049] Converting PCB design data generated by various EDA tools into a unified universal format enables multi-tool collaborative design review and facilitates subsequent processing.

[0050] S2013. Extract the design elements of the printed circuit board to be reviewed from the design data in a common format, including but not limited to: component layout, routing path, stacking structure, and network table.

[0051] The extracted design elements can be used as input data for the pre-trained review model, thereby reducing the model input dimension and improving the model inference speed.

[0052] S202: Generate a computing task corresponding to the design data based on the design data and the pre-trained review model.

[0053] The pre-trained review model is used to predict whether the design data is qualified and / or the likelihood that the design data falls within a pre-labeled issue type. Pre-labeled issue types include, but are not limited to, signal integrity, power integrity, and electromagnetic compatibility. Signal integrity concerns the quality of the signal during transmission, including whether distortion or other issues may occur; power integrity concerns the stability of the power supply system, including voltage fluctuations; and electromagnetic compatibility concerns the ability of the device to function properly in an electromagnetic environment and whether it may interfere with other devices. The pre-trained review model is built on a convolutional neural network and can incorporate an attention mechanism. This convolutional neural network, incorporating an attention mechanism, performs feature extraction and optimized learning on the design data.

[0054] The calculation tasks corresponding to the design data include but are not limited to layout optimization tasks and wiring optimization tasks. For example, the electrical rule checking task is used to check whether the electrical rules in the design data are correct, such as whether the current and voltage in the circuit are within a reasonable range, whether the connection between components complies with electrical specifications, etc. The thermal analysis task is used to analyze the heat dissipation of some equipment design data that generates heat, to ensure that the equipment does not malfunction due to overheating during operation. The crosstalk calculation task is used to calculate the mutual interference between different signals in designs involving signal transmission to ensure the accuracy of signal transmission. Electromagnetic field simulation is used to simulate the working conditions of the equipment in an electromagnetic field environment and evaluate its performance and possible problems. Power integrity analysis is used to evaluate the stability and reliability of the power supply system, such as checking whether the output voltage of the power supply is stable.

[0055] The design data is evaluated using a pre-trained review model and corresponding computational tasks are generated based on the design data. The hardware acceleration module then builds the corresponding computational units to perform subsequent mapping and computational steps. For example, if the design data involves a complex circuit layout, the model may generate tasks such as electrical rule checking and crosstalk calculation to assess the rationality of the layout.

[0056] The training process of the pre-trained review model includes the following steps S1 to S7:

[0057] S1. Obtain sample design data and determine the pre-labeled question type corresponding to the sample design data.

[0058] Based on the design records, simulation results and historical problems of the printed circuit board, the types of problems existing in the design data are marked in advance;

[0059] Obtain sample design data from Gerber files, ODB++ files, or EDA tools, and extract layer information from these sample design data, such as routing layers, component layers, and pad layers. Annotate the sample design data to identify potential issues, such as signal crosstalk, power supply noise, and rule violations.

[0060] S2. Preprocess the sample design data.

[0061] Preprocessing includes but is not limited to format conversion, layering, graph transformation, data enhancement, and normalization.

[0062] In some embodiments, the sample design data is first converted into sample design images, which include images corresponding to different stacked structures. A graphic transformation is then performed on the sample design images to obtain a first image set. Image enhancement is then performed on the first image set to obtain a second image set, and pixel values of the second image set are then normalized.

[0063] For example, the sample design data is formatted and converted to obtain sample design images, such as those in PNG or JPEG formats. The sample design data is then layered to obtain images of the wiring layer, component layer, and pad layer. Graphic transformations include rotation, scaling, and flipping to enhance the diversity of the sample design data. Data augmentation includes random cropping and color dithering to improve the model's generalization capabilities. Normalization normalizes the pixel values of the sample design images to the [0, 1] range for easier model processing.

[0064] S3. Divide the preprocessed sample design data into training set, validation set and test set.

[0065] The sample design data after preprocessing is a 224*224 pixel, 3-channel RGB image.

[0066] Optionally, 75% of the preprocessed sample data is used as the training set, 15% of the sample data is used as the validation set, and 5% of the sample data is used as the test set. This ensures that the data is evenly distributed during model training and avoids bias.

[0067] In some embodiments, an adversarial network is introduced to generate simulated data based on the training set to expand the training set, thereby enhancing the robustness of the convolutional neural network. Among them, the adversarial network (GANs) consists of a generator and a discriminator, and its core idea is the minimum and maximum game between the two. During the training process, the generator and the discriminator are trained alternately. The generator is continuously optimized to generate more realistic simulated data, and the discriminator is continuously optimized to improve the ability to distinguish true from false, and eventually reaches a Nash equilibrium state, at which time the data generated by the generator is difficult to distinguish by the discriminator, and the generator can generate high-quality simulated data.

[0068] The objective function is as follows:

[0069]

[0070] G min D max V(D,G) indicates that the generator G tries to minimize the value function V(D,G), while the discriminator D tries to maximize the value function V(D,G). V(D,G) is used to measure the performance of the generator G and the discriminator D in the current state. represents the discriminant ability of the discriminator D to the real data x, [·] represents the distribution of real data p data The expectation of the real data x is obtained by sampling; logD(x) represents the logarithm of the probability that the discriminator D judges the real data x to be true. The more accurate the discriminator is in judging the real data x, the closer D(x) is to 1, the larger the value of logD(x), and the larger the expectation. [log(1-D(G(z)))] represents the ability of the discriminator D to judge the simulated data G(z) generated by the generator G; G(z) is the simulated data generated by the generator G based on the noise z, and 1-D(G(z)) is the probability that the discriminator D judges the simulated data G(z) as false. The more accurate the discriminator's judgment of the simulated data, the closer 1-D(G(z)) is to 1, the larger the value of log(1-D(G(z))), and the greater the expectation of this part.

[0071] S4. Build the original model based on convolutional neural network.

[0072] Optionally, build the original model based on a convolutional neural network with an attention mechanism. This mechanism automatically focuses on key areas and important features when processing PCB data. When analyzing PCB image data, the attention mechanism allows the model to focus on densely wired areas and critical signal lines, improving the accuracy of critical inspections and preventing important issues from being overlooked due to minor information.

[0073] Convolutional neural networks that incorporate the attention mechanism include a non-local module. This module is used to capture long-range dependencies in feature maps. By calculating the relationships between features at different locations, it effectively extracts long-range dependency features and improves the model's ability to perceive global information.

[0074] The core technical formula of the Non-Local module is as follows:

[0075]

[0076] Where yi represents the response value at position i in the output feature map. x is the input feature map, and C(x) is the normalization factor used to ensure the numerical stability of the output. is the sum operation of all positions j in the feature map; f(x i ,x j ) is the similarity between position i and all other positions j, reflecting the degree of association between position features; g(x j ) is a value transformation function used to transform the feature at position j.

[0077] The original model consists of a convolutional layer, a maximum pooling layer, a fully connected layer, and an output layer. Convolutional layers are used to extract image features and can be up to four in number. The maximum pooling layer (MaxPooling2D) reduces the size of the feature map to achieve feature dimensionality reduction. The fully connected layer's input is the flattened feature map. The output layer is designed based on classification and / or regression tasks and includes a first output layer for classification tasks and a second output layer for regression tasks. The first output layer uses the Softmax activation function to output class probabilities, while the second output layer uses a linear activation function to output continuous values.

[0078] S5. Adjust the model parameters of the original model according to the training set.

[0079] Model parameters include but are not limited to convolution kernel values.

[0080] The training set is input into the original model to obtain the predicted probability value and predicted continuous value output by the original model. The classification task is trained based on the cross entropy loss function (Categorical Crossentropy), and the regression task is trained based on the mean squared error loss function (MeanSquared Error).

[0081] Optionally, based on the above embodiment, the model parameters of the original model are adjusted according to the training set and simulation data.

[0082] S6. Adjust the hyperparameters of the original model based on the validation set.

[0083] Hyperparameters include but are not limited to learning rate and batch size.

[0084] S7. Evaluate the adjusted original model based on the test set to obtain the pre-trained review model.

[0085] The Adam optimizer is used, and the learning rate is set. The convolutional neural network that has been trained and converged is used to infer whether the design data is qualified and / or the type of problem to which the design data belongs.

[0086] The above embodiment uses a large amount of training data to learn the relationship between the characteristics of various design data and potential problems, and constructs a data-driven, highly automated, and adaptable PCB review model. This model can comprehensively consider multiple factors to make judgments, significantly improving the efficiency and accuracy of complex PCB design reviews and promoting the transformation of electronic design automation from rule-driven to intelligent-driven.

[0087] S203: Map at least one of the computing tasks to a corresponding hardware acceleration module, so as to obtain a computing result of the at least one computing task through the hardware acceleration module.

[0088] Map the computational tasks corresponding to the design data to the corresponding hardware acceleration module. Different computational tasks are assigned to the corresponding modules based on the functions and characteristics of the hardware acceleration modules. For example, electromagnetic field simulation tasks are mapped to hardware acceleration modules with powerful graphics processing capabilities, as electromagnetic field simulations typically require processing large amounts of graphics data. Hardware acceleration modules typically have specialized hardware architectures and instruction sets that can efficiently handle specific types of computational tasks. This mapping method fully utilizes the advantages of hardware acceleration modules and improves computational efficiency. At the same time, direct access to the design data cache through the hardware acceleration module reduces data transmission delays, thereby improving computational efficiency.

[0089] S204. Based on the calculation results of at least one calculation task, obtain the continuous value and / or probability value output by the review model.

[0090] After the hardware acceleration module completes the calculation task, it returns the calculation results. The review model will further process and analyze these calculation results. The algorithm within the model will generate continuous values and / or probability values based on the calculation results. For example, if the results of the electrical rule check show that certain parameters in the circuit are outside the normal range, the model will generate a continuous value indicating that the design data is unqualified based on the degree of these deviations; for the results of the power integrity analysis, the model will calculate the probability value of the design data having problems with power integrity based on relevant indicators. For example, suppose the review model outputs a continuous value of 0.92, indicating that the design data has a 92% pass rate; suppose the review model outputs a probability value of 78% for crosstalk risk, indicating that the design data may have a crosstalk risk.

[0091] S205: Determine the review result based on the continuous value and / or probability value. The review result includes the problem attributes and optimization strategy corresponding to the design data.

[0092] Problem attributes include, but are not limited to, problem type, location, and severity. Optimization strategies are designed to minimize and optimize design errors by learning electrical rules by maximizing cumulative rewards. These include, but are not limited to, adjusting routing paths, adding decoupling capacitors, and optimizing power layer splits. Cumulative rewards are a metric used to evaluate the quality of routing solutions. Maximizing this reward means adhering to electrical rules (such as avoiding short circuits and meeting signal integrity requirements) while minimizing routing to achieve overall optimization.

[0093] In some embodiments, problem attributes corresponding to the design data, including the problem location, are determined based on continuous values and / or probability values. Then, at the problem location, an optimization strategy is determined by learning electrical rules by maximizing cumulative rewards. Using a reinforcement learning algorithm, within a PCB routing environment, with the goal of maximizing cumulative rewards, a routing method that complies with electrical rules is learned, minimizing routing paths and optimizing the overall routing solution. Specifically, the design data for the PCB to be reviewed is first gridded to identify routed paths, unrouted paths, and obstacles. Routed paths record completed routing, unrouted paths represent areas that still require routing, and obstacles (such as vias and component pins) are areas that cannot be traversed during the routing process. At the problem location, the next routing direction is then determined from multiple possible routing directions based on the gridded design data and maximizing cumulative rewards. The mechanism for maximizing cumulative rewards includes reward points for successful connections, penalty points for design rule violations, penalty points for routing path length, and reward points for crosstalk reduction.

[0094] If two points that need to be connected (such as pins) can be successfully connected, a reward of the first score (such as +10) will be obtained; if the wiring violates the design rules, a penalty of the second score (such as -5) will be imposed; the wiring path length l is proportional to the penalty score, and the proportional coefficient is α, which is the penalty score corresponding to the wiring path length - αl. α is an adjustable parameter used to control the degree of emphasis on the path length; the degree of crosstalk reduction (measured by SI_score), the reward score corresponding to the degree of crosstalk reduction is +β*SI_score. β is an adjustable parameter used to measure the degree of emphasis on signal integrity.

[0095] In some embodiments, after executing step S205 (determining the review result based on the continuous value and / or the probability value), it also includes displaying the design board diagram of the printed circuit board to be reviewed in a graphical interface, marking the problem location in the design board diagram, and then generating a review report based on the problem type, severity and optimization strategy.

[0096] For example, Matplotlib can be used to plot PCB design images in a graphical interface, highlighting signal crosstalk areas, and ReportLab can be used to generate review reports that include a list of issues, problem descriptions, optimization strategies, and visualization results.

[0097] In some embodiments, after the user modifies the design data of the printed circuit board according to the optimization strategy, the modified design is input into the pre-trained review model for re-review.

[0098] In some embodiments, the review results are saved to support users to view historical records.

[0099] In summary, the printed circuit board design review method provided in the embodiment of the present application transforms the PCB design review from an experience-based manual trial-and-error mode to a data-driven intelligent optimization process through the deep integration of "AI+hardware acceleration", significantly improving the efficiency and accuracy of complex server PCB design.

[0100] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0101] The embodiment of the present application also provides a design review device for a printed circuit board, such as Figure 3 As shown, the design review device includes:

[0102] The data acquisition module 301 is used to acquire the design data of the printed circuit board to be reviewed;

[0103] A computing task generating module 302 is configured to generate computing tasks corresponding to the design data based on the design data and the pre-trained review model;

[0104] A mapping module 303 is configured to map at least one of the computing tasks to a corresponding hardware acceleration module, so as to obtain a computing result of the at least one computing task through the hardware acceleration module;

[0105] Review module 304, configured to obtain a continuous value and / or a probability value output by the review model based on the calculation results of at least one calculation task, wherein the continuous value indicates whether the design data is qualified, and the probability value indicates the likelihood that the design data belongs to a pre-annotated problem type;

[0106] The review result output module 305 is used to determine the review result according to the continuous value and / or the probability value. The review result includes the problem attribute and optimization strategy corresponding to the design data.

[0107] As an optional implementation provided in an embodiment of the present application, the design review device for a printed circuit board also includes a model training module, which is used to: obtain sample design data and determine the pre-labeled problem type corresponding to the sample design data; preprocess the sample design data, and the preprocessing includes format conversion, graphic transformation, image enhancement and normalization; divide the preprocessed sample design data into a training set, a validation set and a test set; construct an original model based on a convolutional neural network, and the original model includes an input layer, a convolution layer, a pooling layer, a fully connected layer and an output layer, and the output layer is designed based on a classification task and / or a regression task; adjust the model parameters of the original model according to the training set; adjust the hyperparameters of the original model according to the validation set; and evaluate the adjusted original model according to the test set to obtain a review model.

[0108] As an optional implementation provided in an embodiment of the present application, the model training module is specifically used to: convert sample design data into sample design images, the sample design images including images corresponding to different stacking structures; perform graphic transformation on the sample design images to obtain a first image set; perform image enhancement on the first image set to obtain a second image set; and perform pixel value normalization on the second image set.

[0109] As an optional implementation provided in an embodiment of the present application, the model training module is specifically used to generate simulated data based on a training set through an adversarial network; and adjust the model parameters of the original model based on the training set and the simulated data.

[0110] As an optional implementation provided in an embodiment of the present application, the design review device for a printed circuit board also includes a design data processing module, which is used to: detect whether the design data is incorrect or missing; if not, convert the design data into design data in a universal format; extract design elements of the printed circuit board to be reviewed from the design data in the universal format, so as to input the design elements into a pre-trained review model.

[0111] As an optional implementation provided in an embodiment of the present application, the review result output module is specifically used to: determine the problem attributes corresponding to the design data based on continuous values and / or probability values, the problem attributes including the problem location; at the problem location, determine the optimization strategy by maximizing the cumulative reward to learn the electrical rules.

[0112] As an optional implementation method provided in an embodiment of the present application, the problem attributes corresponding to the design data include problem type, problem location and severity; the design review device for the printed circuit board also includes a visualization module, which is used to: display the design board drawing of the printed circuit board to be reviewed in a graphical visualization interface; mark the problem location in the design board drawing; and generate a review report based on the design board drawing after the problem location is marked, the problem type, severity and optimization strategy.

[0113] The description of the features in the embodiment corresponding to the printed circuit board design review device can refer to the relevant description of the embodiment corresponding to the printed circuit board design review method, and will not be repeated here.

[0114] The embodiment of the present application also provides an electronic device, such as Figure 4 As shown, it includes a memory 401 and a processor 402. The memory 401 stores a computer program, and the processor 402 is configured to run the computer program to execute the steps in any of the above-mentioned printed circuit board design review method embodiments.

[0115] An embodiment of the present application further provides a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps of any of the above-mentioned printed circuit board design review method embodiments when run.

[0116] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0117] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps of any of the above-mentioned printed circuit board design review method embodiments are implemented.

[0118] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of any of the above-mentioned printed circuit board design review method embodiments are implemented.

[0119] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0120] The above describes in detail the design review method, apparatus, electronic device, and storage medium for a printed circuit board provided by this application. This document uses specific examples to illustrate the principles and implementation methods of this application. The description of the above examples is intended only to facilitate understanding of the method and core concepts of this application. It should be noted that those skilled in the art may make various improvements and modifications to this application without departing from the principles of this application, and such improvements and modifications fall within the scope of protection of the claims of this application.

Claims

1. A design review method for a printed circuit board, characterized in that: include: Obtain design data of the printed circuit board to be reviewed; Generate a computing task corresponding to the design data based on the design data and a pre-trained review model; Mapping at least one of the computing tasks to a corresponding hardware acceleration module, so as to obtain a computing result of the at least one computing task through the hardware acceleration module; Based on the calculation result of the at least one calculation task, obtaining a continuous value and / or a probability value output by the review model, wherein the continuous value is used to indicate whether the design data is qualified, and the probability value is used to indicate the possibility that the design data belongs to a pre-marked problem type; A review result is determined according to the continuous value and / or the probability value, where the review result includes problem attributes and optimization strategies corresponding to the design data.

2. The method according to claim 1, characterized in that The training steps of the review model include: Obtaining sample design data, and determining a pre-labeled question type corresponding to the sample design data; Preprocessing the sample design data, wherein the preprocessing includes format conversion, graphic transformation, image enhancement and normalization; Dividing the preprocessed sample design data into a training set, a validation set, and a test set; Constructing an original model based on a convolutional neural network, wherein the original model includes an input layer, a convolution layer, a pooling layer, a fully connected layer, and an output layer, wherein the output layer is designed based on a classification task and / or a regression task; Adjusting the model parameters of the original model according to the training set; Adjusting the hyperparameters of the original model based on the validation set; The adjusted original model is evaluated according to the test set to obtain the review model.

3. The method according to claim 2, characterized in that Preprocessing the sample design data includes: converting the sample design data into a sample design image, wherein the sample design image includes images corresponding to different stacking structures; Performing graphic transformation on the sample design image to obtain a first image set; performing image enhancement on the first image set to obtain a second image set; Normalizing pixel values of the second image set.

4. The method according to claim 2, characterized in that The adjusting the model parameters of the original model according to the training set includes: generating simulated data based on the training set through an adversarial network; The model parameters of the original model are adjusted according to the training set and the simulation data.

5. The method according to claim 1, wherein Before generating a computing task corresponding to the design data based on the design data and the pre-trained review model, the method further includes: Detecting whether the design data is wrong or missing; If not, converting the design data into design data in a universal format; Design elements of the printed circuit board to be reviewed are extracted from the design data in the universal format, so as to input the design elements into the pre-trained review model.

6. The method according to claim 1, characterized in that Determining the review result according to the continuous value and / or the probability value includes: determining, according to the continuous value and / or the probability value, a problem attribute corresponding to the design data, the problem attribute including a problem location; At the problem location, the optimization strategy is determined by learning electrical rules by maximizing cumulative rewards.

7. The method according to claim 1, characterized in that The problem attributes corresponding to the design data include problem type, problem location and severity; After determining the review result according to the continuous value and / or the probability value, the method further includes: Displaying the design board diagram of the printed circuit board to be reviewed in a graphical visualization interface; Mark the problem location on the design board; A review report is generated based on the design board drawing after marking the problem location, the problem type, the severity and the optimization strategy.

8. A design review device for a printed circuit board, characterized in that: include: A data acquisition module, used to acquire design data of the printed circuit board to be reviewed; A computing task generating module, configured to generate computing tasks corresponding to the design data based on the design data and a pre-trained review model; a mapping module, configured to map at least one of the computing tasks to a corresponding hardware acceleration module, so as to obtain a computing result of the at least one computing task through the hardware acceleration module; a review module, configured to obtain a continuous value and / or a probability value output by the review model based on a calculation result of the at least one calculation task, wherein the continuous value is used to indicate whether the design data is qualified, and the probability value is used to indicate the likelihood that the design data belongs to a pre-annotated problem type; The review result output module is used to determine the review result according to the continuous value and / or the probability value, and the review result includes the problem attribute and optimization strategy corresponding to the design data.

9. An electronic device, characterized in that: include: memory for storing computer programs; A processor is configured to implement the steps of the printed circuit board design review method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the steps of the printed circuit board design review method according to any one of claims 1 to 7 are implemented.

Images