A multi-level addressing based pulse event encoding method and system

Abstract

The present application relates to pulse neural network coding and its application field, specifically to a kind of pulse event coding method and system based on multi-level addressing.The present application utilizes pulse sparsity, simultaneously introduces synapse partition concept, all synapses corresponding to neuron are divided into equal-sized partitions, then synapse partition is address coded, and then the synapses in each synapse partition are two-level address coded, synapse partition address and synapse address are mapped by using two-level memory, the bit width of synapse index in pulse event coding is reduced, and finally the total storage is reduced, compared with the original scheme, the total storage overhead is reduced by more than 95%.The present application uses multi-level addressing technology to carry out pulse event coding, and has high coding efficiency and strong scalability;When applied to pulse neural network circuit or chip, the area and power consumption of the circuit can be greatly reduced.

Description

Technical Field

[0001] The present invention relates to pulse neural network coding and its application field, and in particular to a pulse event coding method and system based on multi-level addressing. Background Art

[0002] Spiking neural network (SNN) has the characteristics of bionics and low power consumption. Neurons transmit information through binary spikes, and synapses perform calculations through binary spikes. Neuron models such as Figure 1 However, the effective pulses ("1" pulses) in SNNs are extremely sparse. For example, in the VGG model (Visual Geometry Group Network), the proportion of "1" pulses is less than 20%. This means that a large number of invalid "0" pulses are transmitted between neurons and participate in synaptic calculations, significantly reducing computational efficiency in the circuit and increasing power consumption.

[0003] In response to the above situation, an existing advanced solution is to use pulse event coding technology to encode, transmit and calculate only valid "1" pulses. The core idea is that if a neuron outputs a valid pulse, it is represented as a neuron index and the index is transmitted to the next level neuron; if the neuron outputs an invalid pulse, it is not encoded or transmitted. After the next level neuron receives the event package, it finds the corresponding synapse based on the previous level neuron index and performs calculations. The main problem faced by this technical solution is that valid pulses require multiple bits to represent, which may result in large communication bandwidth and storage capacity overhead. When designing neuron memory, in order to ensure compatibility under various sparsities, the design capacity usually needs to be greater than or equal to the maximum case in actual application. Compared with the binary coding scheme, the storage overhead required by the pulse event coding technology is extremely large. Summary of the Invention

[0004] To address the aforementioned problems and shortcomings, and to address the inability of existing spiking neural network coding techniques to effectively balance computational efficiency and storage overhead, the present invention proposes a method and system for pulse event coding based on multi-level addressing. The present invention employs multi-level addressing technology for pulse event coding, thereby reducing storage overhead and improving coding efficiency.

[0005] A pulse event encoding method based on multi-level addressing, specifically:

[0006] All synapses corresponding to a neuron are divided into continuous partitions of equal size, and each synaptic partition is address-coded in sequence; the synapses within each synaptic partition are also address-coded in sequence.

[0007] The first-level memory is an address memory, whose address space corresponds to the number of synaptic partitions, and the number of bits storing address data meets the address index requirements of the second-level memory; the data stored at each address is used to index the event memory address corresponding to the first event in the synaptic partition.

[0008] The secondary memory is an event memory, and the address space is designed according to the effective pulse ratio. If the total number of synapses is N and the effective pulse ratio is M, the event memory address space is N*M; the number of bits of the storage address meets the synaptic event index requirement in each synaptic partition; each address stores an event packet, which contains the synaptic partition switching signal + synaptic index, which is used to index the first synaptic event in the corresponding synaptic partition.

[0009] If the neuron outputs a valid pulse 1, it is represented as a neuron index in the form of the first-level memory address + the second-level memory address; if the neuron outputs an invalid pulse 0, it is not encoded or transmitted; after the next-level neuron receives the event packet, it finds the corresponding synapse based on the previous-level neuron index and performs calculations.

[0010] Furthermore, the primary memory is implemented using static random access memory SRAM, or a functional circuit.

[0011] A pulse event coding system based on multi-level addressing, its structure is as follows Figure 2 As shown, it includes a neuron synapse partition encoding module, a primary memory, a secondary memory, and an address and event index module.

[0012] The neuron synapse partition coding module is used to divide all synapses corresponding to a neuron into continuous partitions of equal size, and perform address coding on the synapse partitions in sequence, and perform address coding on the synapses in the partitions in sequence.

[0013] The primary memory is used to store the event memory address corresponding to the first event in the synaptic partition, and its address space corresponds to the number of synaptic partitions. The number of bits of the stored address data meets the secondary memory address index requirement.

[0014] The secondary memory is used to store the synaptic event index in each synaptic partition. The address space of the secondary memory is designed according to the effective pulse ratio. If the total number of synapses is N and the effective pulse ratio is M, the event memory address space is N*M; the number of bits of the storage address meets the synaptic event index requirement in each synaptic partition; each address stores an event packet, the data of which is the synaptic partition switching signal + synaptic index, which is used to index the first synaptic event in the corresponding synaptic partition.

[0015] The address and event index module is used to perform multi-level addressing of the neuron's pulse events and determine the pulse event coding; if the neuron outputs a valid pulse 1, it is represented as a neuron index in the form of the first-level memory address + the second-level memory address; if the neuron outputs an invalid pulse 0, it is not encoded or transmitted.

[0016] Furthermore, the above-mentioned pulse event coding system based on multi-level addressing corresponding to a neuron is extended to the entire pulse neural network circuit or chip to perform synaptic calculations, so as to give a good balance between computing efficiency and storage overhead.

[0017] In summary, compared to the prior art, the present invention utilizes pulse sparsity and introduces the concept of synaptic partitioning, dividing all synapses corresponding to neurons into partitions of equal size. The synaptic partitions are then address-encoded, and the synapses within each synaptic partition are then secondarily address-encoded. By using a two-level memory to map the synaptic partition address and synaptic address, the bit width of the synaptic index in the pulse event encoding is reduced, ultimately reducing the total storage overhead by over 95% compared to the prior art. The present invention employs multi-level addressing technology for pulse event encoding, resulting in high encoding efficiency and strong scalability. Furthermore, when applied to pulse neural network circuits or chips, the circuit area and power consumption can be significantly reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 Schematic diagram of the spiking neural network neuron model;

[0019] Figure 2 is a system block diagram of the present invention;

[0020] Figure 3 Memory overhead for example event;

[0021] Figure 4 The embodiment is based on a pulse event encoding scheme of multi-level addressing. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the method and process of the present invention are further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0023] A pulse event coding system based on multi-level addressing, such as Figure 2 As shown, it includes a neuron synapse partition encoding module, a primary memory, a secondary memory, and an address and event index module;

[0024] The synaptic partition coding module is used for dividing all synapses corresponding to one neuron into equal-size continuous partitions, and sequentially coding addresses of the synaptic partitions, as shown in 01. Figure 2-1 The synaptic partition coding module is used for dividing all synapses corresponding to one neuron into equal-size continuous partitions, and sequentially coding addresses of the synaptic partitions, as shown in 01. Figure 2-1 02.

[0025] The first-level memory is used for storing event memory addresses corresponding to the first event in the synaptic partition, the address space of which corresponds to the number of synaptic partitions, and the number of bits of the stored address data meets the index requirement of the second-level memory, as shown in 03. Figure 2-1 03.

[0026] The second-level memory is used for storing synaptic event indexes in each synaptic partition, and the address space of the second-level memory is designed according to the effective pulse proportion. If the total number of synapses is N and the effective pulse proportion is M, the event memory address space is N*M. The number of bits of the stored address meets the synaptic event index requirement in each synaptic partition. Each address stores one event package, which contains synaptic partition switching signals and synaptic indexes, and is used for indexing the first synaptic event in the corresponding synaptic partition, as shown in 04. Figure 2-1 04.

[0027] The address and event index module is used for multi-level addressing of the pulse events of the neuron, and determining pulse event coding. The pulse event coding is completed through address indexing from the first-level memory to the second-level memory, and then through event indexing from the second-level memory to the synapses. If the neuron outputs a valid pulse 1, it is represented as a neuron index, and the index is transmitted to the next neuron. If the neuron outputs an invalid pulse 0, it is not coded and transmitted.

[0028] For the embodiment, it is assumed that one neuron has 64K synapses, and a maximum specification memory is designed, that is, all pulses in the case of a sparsity of 0 can be stored, and the storage overhead of the binary coding scheme is 64Kb. According to the existing pulse event coding scheme, 17 bits are needed to represent a single pulse (1 bit of time synchronization + 16 bits of synaptic index), and the storage overhead of the neuron is 1088Kb, which is 16 times higher than that of the binary coding scheme, and the total storage overhead is serious, as shown in 02. Figure 3 02.

[0029] According to the technical scheme of the present application, the 64K synapses of one neuron in the above example are divided into 256 equal-size continuous synaptic partitions, as shown in 05. Figure 4 05: The partition address coding is 0x000-0x100, each synaptic partition contains 256 continuous synapses, and the synaptic address coding is 0x000-0x100.

[0030] The corresponding first-level memory address space is designed as 256, corresponding to the number of synaptic partition. Each address stores 12-bit data (assuming that the proportion of valid pulses is less than 1 / 16, the event memory scale is designed as 4K), which is used to index the event memory (i.e. second-level memory) address corresponding to the first event in the synaptic partition. The embodiment takes the pulse neural network circuit design as the background, and uses static random access memory (SRAM) to realize.

[0031] The corresponding second-level memory address space is designed as 4K, corresponding to the event memory scale in the above calculation, each address stores an event package, including 9-bit data (1-bit synaptic partition switching signal + 8-bit synaptic index), which is used to index the first synaptic event in the corresponding synaptic partition.

[0032] The pulse event of one neuron is indexed by the first-level memory to the second-level memory address, and then indexed by the second-level memory to the synaptic event, so as to complete the pulse-neuron mapping, as shown in Figure 2-1 05 and Figure 4 If the neuron outputs a valid pulse 1, it is represented as a neuron index, and the index is transmitted to the next stage of neurons; if the neuron outputs an invalid pulse 0, it is not encoded and transmitted; after the next stage of neurons receives the event package, the corresponding synapse is found according to the index of the previous stage of neurons, and calculation is carried out.

[0033] After using the technical solution of the present application, the first-level memory is 3Kb, the second-level memory is 36Kb, and the final total memory overhead is reduced to 39Kb, which is reduced by more than 96% compared with the total storage overhead of 1088Kb in the prior art. For a pulse neural network circuit system containing multiple neurons, by using the pulse event encoding method of the above one neuron to the entire pulse neural network circuit system, significant area and power consumption benefits will be obtained.

[0034] As can be seen from the above embodiment, the present application utilizes the sparsity of pulses, introduces the concept of synaptic partition, divides all synapses corresponding to a neuron into partitions of equal size, then encodes the synaptic partition addresses, and then encodes the synaptic addresses in each synaptic partition, and uses two-level memories to map the synaptic partition addresses and synaptic addresses, which greatly reduces the bit width of the synaptic index in pulse event encoding, and finally reduces the total storage. Compared with the prior art, the total storage of the present application is reduced by more than 95%, and the encoding efficiency of the present application is high, and the scalability is strong, which can greatly reduce the area and power consumption of the circuit when applied to a pulse neural network circuit or chip.

Claims

1. A pulse event encoding method based on multi-level addressing, characterized in that: Specifically: All synapses corresponding to a neuron are divided into continuous partitions of equal size, and each synaptic partition is address-coded in sequence; the synapses within each synaptic partition are also address-coded in sequence; The primary memory is an address memory, whose address space corresponds to the number of synaptic partitions, and the number of bits storing address data meets the address index requirements of the secondary memory; the data stored at each address is used to index the event memory address corresponding to the first event in the synaptic partition; The secondary memory is an event memory, and the address space is designed according to the effective pulse ratio. If the total number of synapses is N and the effective pulse ratio is M, then the event memory address space is N*M; the number of bits of the storage address meets the synaptic event index requirements in each synaptic partition; Each address stores an event packet, which contains the synaptic partition switching signal + synaptic index, which is used to index the first synaptic event in the corresponding synaptic partition; If the neuron outputs a valid pulse of 1, it is represented as the neuron index in the form of the first-level memory address + the second-level memory address; If a neuron outputs an invalid pulse 0, it will not be encoded or transmitted; after the next-level neuron receives the event packet, it will find the corresponding synapse based on the index of the previous-level neuron and perform calculations.

2. The pulse event encoding method based on multi-level addressing as claimed in claim 1, characterized in that: The primary memory is implemented using static random access memory SRAM.

3. The pulse event encoding method based on multi-level addressing as claimed in claim 1, characterized in that: The primary memory is implemented using a functional circuit.

4. A pulse event coding system based on multi-level addressing, characterized in that: It includes a neuron synapse partition encoding module, a primary memory, a secondary memory, and an address and event index module; The neuron synapse partition coding module is used to divide all synapses corresponding to a neuron into continuous partitions of equal size, and perform address coding on the synapse partitions in sequence, and perform address coding on the synapses within the partitions in sequence; The primary memory is used to store the event memory address corresponding to the first event in the synaptic partition, the address space of which corresponds to the number of synaptic partitions, and the number of bits of the stored address data meets the secondary memory address index requirement; The secondary memory is used to store the synaptic event index in each synaptic partition. The address space of the secondary memory is designed according to the effective pulse ratio. If the total number of synapses is N and the effective pulse ratio is M, the event memory address space is N*M; the number of bits of the storage address meets the synaptic event index requirement in each synaptic partition; Each address stores an event packet, which contains the synaptic partition switching signal + synaptic index, which is used to index the first synaptic event in the corresponding synaptic partition; The address and event index module is used to perform multi-level addressing on the pulse events of neurons and determine the pulse event codes; If the neuron outputs a valid pulse of 1, it is represented as the neuron index in the form of the first-level memory address + the second-level memory address; If a neuron outputs an invalid pulse 0, it is not encoded or transmitted.

5. The pulse event coding system based on multi-level addressing as claimed in claim 4, characterized in that: The pulse event coding system based on multi-level addressing corresponding to a neuron is extended to the entire pulse neural network circuit or chip to perform synaptic calculations, so as to strike a good balance between computing efficiency and storage overhead.

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