Light emitting driver and display device including same

Abstract

The invention relates to a light emitting driver and a display device including the same. A light emitting driver is disclosed. The light emitting driver includes: a Q node controller configured to control a voltage at a Q node by applying a start signal, a carry signal, or a high potential driving voltage to the Q node in response to a first clock signal; a QB node controller configured to control a voltage at the QB node by applying a high-potential driving voltage or a low-potential driving voltage to the QB node in response to a first clock signal; an output buffer configured to output a high-potential driving voltage or a low-potential driving voltage to the corresponding light emitting lines in response to voltages at the Q node and the QB node; and a pump controller configured to change the voltage at the Q node according to the second clock signal while the light emitting signal is output at the on level in response to the start signal or the carry signal.

Description

Technical Field

[0001] The present disclosure relates to a light emitting driver and a display device including the same. Background Art

[0002] With the development of the information society, various demands for display devices for displaying images are increasing, and various types of display devices such as liquid crystal display (LCD) devices and organic light emitting diode (OLED) display devices are utilized.

[0003] A display device may include pixels arranged on a display panel and a driver for driving the pixels. The driver may include, for example, a gate driver for controlling the driving timing of the pixels, a data driver for supplying data voltages to the pixels, and a light emitting driver for controlling the light emitting timing of the pixels.

[0004] When a light emission signal of a light emission driver for controlling light emission timing of a pixel is not normally supplied to the pixel, the pixel cannot properly emit light to cause abnormal driving, and the quality of an image displayed on the display panel may be deteriorated. Summary of the Invention

[0005] Embodiments are directed to providing a light emitting driver connected to a Q-node to reduce stress of a transistor to which a high gate-source voltage is applied and to improve reliability, and a display including the same.

[0006] Furthermore, embodiments are directed to providing a light emitting driver having a reduced number of transistors compared to conventional light emitting drivers and a display device including the same.

[0007] In one embodiment, a display device includes: a display panel including a plurality of pixels; and a light-emitting driver including a plurality of stage circuits, the plurality of stage circuits being configured to apply light-emitting signals to the plurality of pixels through a plurality of light-emitting lines, wherein each of the plurality of stage circuits includes: a Q-node controller, the Q-node controller being configured to control the voltage at the Q-node by applying one of a start signal, a carry signal, or a high-potential drive voltage to the Q-node in response to a first clock signal received by the Q-node controller; and a QB-node controller, the QB-node controller being configured to control the voltage at the Q-node by applying the high-potential drive voltage or a low-potential drive voltage lower than the high-potential drive voltage to the QB node in response to the first clock signal. a driving voltage to control the voltage at the QB node; an output buffer, the output buffer being connected to the Q node and the QB node, the output buffer being configured to output the high-potential driving voltage or the low-potential driving voltage to the corresponding light-emitting line among the multiple light-emitting lines as a light-emitting signal of the stage circuit in response to the voltage at the Q node and the voltage at the QB node; and a pump controller, the pump controller being connected to the Q node and receiving a second clock signal and the start signal or the carry signal, the pump controller being configured to change the voltage at the Q node multiple times according to the second clock signal in response to the start signal or the carry signal when the light-emitting signal causes a conduction level of one pixel connected to the corresponding light-emitting line among the multiple pixels to turn on.

[0008] In one embodiment, a light-emitting driver includes: a plurality of stage circuits configured to apply light-emitting signals to a plurality of pixels through a plurality of light-emitting lines, wherein each stage circuit of the plurality of stage circuits includes: a Q-node controller configured to control the voltage at the Q-node by applying one of a start signal, a carry signal, or a high-potential drive voltage to the Q-node in response to a first clock signal; and a QB-node controller configured to control the voltage at the Q-node by applying the high-potential drive voltage or a low-potential drive voltage lower than the high-potential drive voltage to the QB-node in response to the first clock signal. The voltage at the QB node is controlled, and the QB node controller includes a transistor directly connected to the input terminal of the high-potential driving voltage, and the transistor receives the voltage at the Q node at the gate electrode of the transistor through a buffer transistor connected to the gate electrode of the transistor and the Q node; and an output buffer, the output buffer is connected to the Q node and the QB node, and the output buffer is configured to output the high-potential driving voltage or the low-potential driving voltage to the corresponding light-emitting line among the multiple light-emitting lines in response to the voltage at the Q node and the voltage at the QB node as a light-emitting signal of the stage circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram illustrating a display device according to one embodiment.

[0010] Figure 2 is a diagram schematically showing a configuration of a light emitting driver according to one embodiment.

[0011] Figure 3 is a schematic diagram showing a method according to an embodiment of the present invention. Figure 2 Diagram of the stage circuit.

[0012] Figure 4 Specifically illustrating an embodiment Figure 3 Circuit diagram of the stage circuit.

[0013] Figure 5 is a diagram showing a drive according to one embodiment Figure 4 The timing diagram of the stage circuit method.

[0014] Figure 6 It specifically shows that according to another embodiment Figure 3 Circuit diagram of the stage circuit.

[0015] Figure 7 is a diagram showing a drive according to one embodiment Figure 6 The timing diagram of the stage circuit method.

[0016] Figure 8 The driving method according to one embodiment is shown Figure 6 The timing diagram of the stage circuit method.

[0017] Figure 9 is a circuit diagram showing a pixel according to one embodiment. DETAILED DESCRIPTION

[0018] Hereinafter, embodiments will be described with reference to the accompanying drawings. In this specification, when a first component (or region, layer, portion, etc.) is described as being "on," "connected," or "coupled to" a second component, this means that the first component may be directly connected / coupled to the second component or a third component may be provided therebetween.

[0019] The same reference numerals denote the same components. In addition, in the drawings, the thickness, proportion and size of the components are exaggerated in order to effectively describe the technical content. The term "and / or" includes all one or more combinations that can be defined by the associated configurations.

[0020] Terms such as first and second may be used to describe various components, but these components are not limited by these terms. These terms are used only to distinguish one component from another. For example, a first component can be referred to as a second component, and similarly, a second component can be referred to as a first component without departing from the scope of the embodiments. Unless the context clearly indicates otherwise, a singular expression includes a plural expression.

[0021] Terms such as "below," "at the lower side," "above," and "at the upper side" are used to describe the relationship between components shown in the drawings. These terms are relative concepts and are described with respect to directions marked in the drawings.

[0022] It should be understood that terms such as “include” or “have” are intended to specify the presence of the features, quantities, steps, operations, components, parts, or a combination thereof described in the specification, and do not preclude the presence or possibility of adding one or more other features, quantities, steps, operations, components, parts, or a combination thereof.

[0023] Figure 1 is a block diagram illustrating a display device according to one embodiment.

[0024] Please refer to Figure 1 The display device 1 includes a timing controller 10 , a gate driver 20 , a data driver 30 , a light emitting driver 40 , a power supply unit 50 , and a display panel 60 .

[0025] The timing controller 10 may receive an image signal RGB and a control signal CS from an external host system, etc. The image signal RGB may include a plurality of grayscale data. The control signal CS may include, for example, a horizontal synchronization signal, a vertical synchronization signal, and a main clock signal.

[0026] The timing controller 10 may process the image signals RGB and the control signal CS according to the operating conditions of the display panel 60 , and generate and output image data DATA, a gate driving control signal CONT1 , a data driving control signal CONT2 , a light emitting driving control signal CONT3 , and a power control signal CON4 .

[0027] The gate driver 20 may generate a gate signal based on the gate driving control signal CONT1 output from the timing controller 10. The gate driver 20 may provide the generated gate signal to the pixels PX through the plurality of gate lines GL.

[0028] The data driver 30 may generate data signals based on the data driving control signal CONT2 and the image data DATA output from the timing controller 10. The data driver 30 may provide the generated data signals to the pixels PX through the plurality of data lines DL.

[0029] The light emitting driver 40 may generate a light emitting control signal based on the light emitting drive control signal CONT3 output from the timing controller 10. The light emitting driver 40 may provide the generated light emitting control signal to the pixels PX through the plurality of light emitting lines EL.

[0030] The power supply unit 50 may generate a high potential driving voltage ELVDD and a low potential driving voltage ELVSS based on the power control signal CON4 and may provide the generated driving voltages ELVDD and ELVSS to the pixels PX through corresponding power lines PL1 and PL2, respectively.

[0031] A plurality of pixels PX (or sub-pixels) are provided on the display panel 60. For example, the pixels PX may be arranged in a matrix on the display panel 60. The pixels PX arranged in a pixel row are connected to the same gate line GL and emission line EL, and the pixels PX arranged in a pixel column are connected to the same data line DL. The pixels PX may emit light having a brightness corresponding to the gate signal and the data signal supplied through the gate line GL and the data line DL in response to a light emission control signal applied through the emission line EL.

[0032] In one embodiment, each pixel PX can display one of red, green, and blue. In another embodiment, each pixel PX can display one of cyan, magenta, and yellow. In various embodiments, each pixel PX can display one of red, green, blue, and white.

[0033] The timing controller 10, the gate driver 20, the data driver 30, the light emitting driver 40, and the power supply unit 50 may each be configured as a separate integrated circuit (IC) or at least a partially integrated IC. Furthermore, at least one of the gate driver 20 and the light emitting driver 40 may be configured in the form of an in-panel gate integrally formed with the display panel 60.

[0034] Figure 2 is a diagram schematically showing a configuration of a light emitting driver according to one embodiment.

[0035] Reference Figure 2 , the light emitting driver 40 may include a plurality of stage circuits ST1 to ST4. For ease of description, Figure 2 Four stage circuits ST1 to ST4 included in the light emitting driver 40 are illustrated, but any number of stage circuits may be included in the light emitting driver 40 .

[0036] The second stage circuit ST2 may be associated with the first stage circuit ST1, the third stage circuit ST3 may be associated with the second stage circuit ST2, and the fourth stage circuit ST4 may be associated with the third stage circuit ST3. The first to fourth stage circuits ST1 to ST4 may have substantially the same configuration.

[0037] The stage circuits ST1 to ST4 can be respectively connected to the corresponding light-emitting lines EL1 to EL4 to output the high potential driving voltage EVEH or the low potential driving voltage EVEL lower than the high potential driving voltage EVEH as light-emitting signals to the light-emitting lines EL1 to EL4 in response to the clock signals ECLK1 and ECLK2.

[0038] The first stage circuit ST1 can receive the start signal EVST. In addition, the second to fourth stage circuits ST2 to ST4 can respectively receive the carry signals CR1 to CR3 output from the previous stage circuits ST1 to ST3. For example, the second stage circuit ST2 can receive the first carry signal CR1 output from the first stage circuit ST1, the third stage circuit ST3 can receive the second carry signal CR2 output from the second stage circuit ST2, and the fourth stage circuit ST4 can receive the third carry signal CR3 output from the third stage circuit ST3. Each of the stage circuits ST1 to ST4 is pulled up to a state capable of outputting a light-emitting signal by the start signal EVST or the carry signals CR1 to CR3 at the gate-on level.

[0039] According to one embodiment, the light emitting driver 40 can be configured to operate in a forward mode and a reverse mode. In the forward mode, the light emitting driver 40 can sequentially drive the associated stage circuits ST1 to ST4 from the first stage circuit ST1 to the last stage circuit. In the reverse mode, the light emitting driver 40 can sequentially drive the associated stage circuits ST1 to ST4 from the last stage circuit to the first stage circuit ST1. In the reverse mode, the start signal EVST can be applied to the last stage circuit, and the stage circuits ST1 to ST3 can be configured to receive the carry signals CR2 to CR4 from the subsequent stage circuits ST2 to ST4.

[0040] The clock signals ECLK1 and ECLK2 may be square wave signals in which a gate-on voltage and a gate-off voltage alternate every one horizontal period (1H). The first clock signal ECLK1 and the second clock signal ECLK2 may have the same waveform and may be pulse signals whose phases are offset by a predetermined interval. For example, the second clock signal ECLK2 may have the same waveform as the first clock signal ECLK1 and may be a pulse signal whose phase is offset by half a cycle relative to the first clock signal ECLK1 (i.e., the phase is opposite to the first clock signal ECLK1). In the illustrated embodiment, each of the stage circuits ST1 to ST4 is configured to receive two clock signals ECLK1 and ECLK2, but is not limited thereto and may provide a greater or lesser number of clock signals.

[0041] The driving voltages EVEH and EVEL required to drive the stage circuits ST1 to ST4 can be applied to the stage circuits ST1 to ST4. For example, a high-potential driving voltage EVEH as a first-level voltage and a low-potential driving voltage EVEL as a second-level voltage lower than the first-level voltage can be applied to the stage circuits ST1 to ST4. In various embodiments, the stage circuits ST1 to ST4 can be configured to receive one or more high-potential driving voltages EVEH having different levels and / or one or more low-potential driving voltages EVEL having different levels.

[0042] The high potential driving voltage EVEH and the low potential driving voltage EVEL may have a DC voltage level. The high potential driving voltage EVEH is used to turn on the pixel PX (see Figure 1 ), and the low potential driving voltage EVEL is a voltage for turning off the transistor provided in the pixel PX, and in one embodiment, the voltage level of the high potential driving voltage EVEH can be set to a voltage level higher than the low potential driving voltage EVEL. In other words, the first level voltage can be greater than the second level voltage. In addition, the second level voltage can have a level equal to or similar to the ground voltage, for example.

[0043] When the transistors in pixel PX and the transistors in stage circuits ST1 to ST4 are of the same type, the transistors in stage circuits ST1 to ST4 can be turned on in response to a high-potential drive voltage EVEH, and the transistors in stage circuits ST1 to ST4 can be turned off in response to a low-potential drive voltage EVEL. Conversely, when the transistors in pixel PX and the transistors in stage circuits ST1 to ST4 are different types, the transistors in stage circuits ST1 to ST4 can be turned off in response to a high-potential drive voltage EVEH, and the transistors in stage circuits ST1 to ST4 can be turned on in response to a low-potential drive voltage EVEL. Therefore, a predetermined transistor does not necessarily need to be turned on by the high-potential drive voltage EVEH, and a predetermined transistor does not necessarily need to be turned off by the low-potential drive voltage EVEL. In other words, a predetermined transistor can be turned off in response to the high-potential drive voltage EVEH, and a predetermined transistor can be turned on in response to the low-potential drive voltage EVEL. Hereinafter, for ease of description, it is assumed that the high-potential drive voltage EVEH (i.e., a high-level voltage) is the on-level voltage, and the low-potential drive voltage EVEL (i.e., a low-level voltage) is the off-level voltage.

[0044] The stage circuits ST1 to ST4 are configured to also receive the reset signal RST. The stage circuits ST1 to ST4 may be initialized by being pulled down in response to the reset signal RST.

[0045] The stage circuits ST1 to ST4 may output light emission signals. The light emission signals output from the stage circuits ST1 to ST4 may be provided to corresponding light emission lines EL1 to EL4, respectively.

[0046] The stage circuits ST1 to ST4 can also output carry signals CR1 to CR4. The carry signals CR1 to CR4 output from the stage circuits ST1 to ST4 can be provided to subsequent stage circuits, respectively. For example, the first carry signal CR1 output from the first stage circuit ST1 can be provided to the second stage circuit ST2, the second carry signal CR2 output from the second stage circuit ST2 can be provided to the third stage circuit ST3, the third carry signal CR3 output from the third stage circuit ST3 can be provided to the fourth stage circuit ST4, and the fourth carry signal CR4 output from the fourth stage circuit ST4 can be provided to the fifth stage circuit (not shown).

[0047] Except for the type of received signals, the stage circuits ST1 to ST4 included in the light emitting driver 40 may have substantially the same configuration. For example, except for receiving an input signal (i.e., the start signal EVST or the carry signals CR1 to CR4 of the previous stage circuit), the first stage circuit ST1 as the first stage circuit for receiving the start signal EVST and the remaining stage circuits (e.g., the second stage circuit ST2 to the fourth stage circuit ST4) for receiving the carry signals CR1 to CR4 of the previous stage circuit may have substantially the same circuit configuration and may operate in substantially the same manner.

[0048] Figure 3 is a schematic diagram showing a method according to an embodiment of the present invention. Figure 2 Diagram of the stage circuit.

[0049] Reference Figure 3 The stage circuit ST may include a Q-node controller 41 , a QB-node controller 42 , a pump controller 43 , and an output buffer 44 .

[0050] The output buffer 44 may include at least one pull-up transistor Tup and at least one pull-down transistor Tdn. The pull-up transistor Tup may be electrically connected between the low-potential driving voltage EVEL and the output terminal of the light-emitting signal. The pull-up transistor Tup may be turned on according to the voltage at the Q node EQ to output the low-potential driving voltage EVEL as the light-emitting signal to the light-emitting line EL.

[0051] The pull-down transistor Tdn is electrically connected between the high potential driving voltage EVEH and the output terminal of the emission signal and is turned on according to the voltage of the QB node EQB to output the high potential driving voltage EVEH signal as the emission signal to the emission line EL.

[0052] The Q-node controller 41 may control the voltage at the Q-node EQ, and the QB-node controller 42 may control the voltage at the QB-node EQB.

[0053] The pump controller 43 (e.g., a circuit) may be electrically connected to the Q-node EQ. The pump controller 43 may be configured to receive a start signal EVST, a clock signal ECLK, a high potential drive voltage EVEH, and a low potential drive voltage EVEL. Furthermore, the pump controller 43 may be configured to receive a light emission signal output from the output buffer 44 via the light emission line EL.

[0054] The pump controller 43 can be controlled to adjust the voltage level of the Q-node EQ based on the voltage levels of the input signal and the light-emission signal. For example, during a period in which a light-emission signal at an on-level is output, the pump controller 43 can control the voltage at the Q-node EQ to maintain a level sufficient to turn on the pull-up transistor Tup. Since the voltage level of the Q-node EQ is stably maintained by the pump controller 43, a light-emission signal at an on-level can be stably supplied even during a long light-emission period.

[0055] Figure 4 is a diagram showing a method according to an embodiment Figure 3 Circuit diagram of the stage circuit.

[0056] Reference Figure 4 The stage circuit ST may include a Q-node controller 41 , a QB-node controller 42 , a pump controller 43 , and an output buffer 44 . Furthermore, the stage circuit ST may further include a signal input unit 45 and a reset unit 46 .

[0057] The Q-node controller 41 is configured to control the voltage at the Q-node EQ by applying the start signal EVST, the carry signal CR, or the first high potential driving voltage EVEH1 to the Q-node EQ in response to the first clock signal ECLK1. To this end, the Q-node controller 41 may include a first transistor T1 and a second transistor T2.

[0058] The first transistor T1 can be electrically connected between the input node EI of the start signal EVST or the carry signal CR output from the previous stage and the Q node EQ. For example, the source electrode of the first transistor T1 is connected to the Q node EQ, and the drain electrode is connected to the start signal EVST or the carry signal CR output from the previous stage. The gate electrode of the first transistor T1 is configured to receive the first clock signal ECLK1. The first transistor T1 can be turned on according to the first clock signal ECLK1 to apply the start signal EVST or the carry signal CR input through the signal input unit 45 to the Q node EQ.

[0059] The second transistor T2 can be electrically connected between the input terminal of the first high potential driving voltage EVEH1, the Q node EQ, and the source electrode of the first transistor T1. The gate electrode of the second transistor T2 is connected to the QB node EQB. When the voltage at the QB node EQB is set to the on-level, the second transistor T2 can be turned on, and the first high potential driving voltage EVEH1 can be applied to the Q node EQ. When the QB node EQB is set to the on-level voltage, the Q node EQ can be set to the off-level voltage through the second transistor T2.

[0060] The QB node controller 42 is configured to control the voltage at the QB node EQB by applying a first high potential driving voltage EVEH1 or a first low potential driving voltage EVEL1 to the QB node EQB in response to a first clock signal ECLK1. To this end, the QB node controller 42 may include a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6. Furthermore, the QB node controller 42 may further include a first buffer transistor TB1 and a second buffer transistor TB2.

[0061] The third transistor T3 can be electrically connected between the input terminal of the first low potential drive voltage EVEL1 and the QB node EQB. For example, the source electrode of the third transistor T3 is connected to the QB node EQB, and the drain electrode of the third transistor T3 is connected to the input terminal of the first low potential drive voltage EVEL1. The gate electrode of the third transistor T3 is connected to the QB' node EQB'. When the voltage at the QB' node EQB' is set to the conduction level, the third transistor T3 can be turned on to apply the first low potential drive voltage EVEL1 to the QB node EQB.

[0062] The fourth transistor T4 can be electrically connected between the input terminal of the first low potential drive voltage EVEL1 and the QB' node EQB'. For example, the source electrode of the fourth transistor T4 is connected to the QB' node EQB' and the gate electrode of the third transistor T3, and the drain electrode of the fourth transistor T4 is connected to the input terminal of the first low potential drive voltage EVEL1. The gate electrode of the fourth transistor T4 is configured to receive the first clock signal ECLK1. The fourth transistor T4 can be turned on according to the first clock signal ECLK1 to apply the first low potential drive voltage EVEL1 to the QB' node EQB'. When the fourth transistor T4 is turned on and the voltage at the QB' node EQB' is set to the first low potential drive voltage EVEL1, the third transistor T3 is turned on and the voltage at the QB node EQB is set to the first low potential drive voltage EVEL1.

[0063] The fifth transistor T5 can be electrically connected between the QB' node EQB' and the input terminal of the first high potential drive voltage EVEH1. For example, the source electrode of the fifth transistor T5 is connected to the input terminal of the first high potential drive voltage EVEH1, and the drain electrode of the fifth transistor T5 is connected to the QB' node EQB' and the gate electrode of the third transistor T3. The gate electrode of the fifth transistor T5 can be configured to receive the voltage at the Q node EQ. When the voltage at the Q node EQ is set to the on-level, the fifth transistor T5 can be turned on to apply the first high potential drive voltage EVEH1 to the QB' node EQB'. When the fifth transistor T5 is turned on and the voltage at the QB' node EQB' is set to the first high potential drive voltage EVEH1, the third transistor T3 is turned off, thereby not applying the first low potential drive voltage EVEL1 to the QB node EQB.

[0064] In one embodiment, the gate electrode of the fifth transistor T5 can be electrically connected to the Q-node EQ via the first buffer transistor TB1. The first buffer transistor TB1 can be electrically connected between the gate electrode of the fifth transistor T5 and the Q-node EQ. For example, the source electrode of the first buffer transistor TB1 is connected to the Q-node EQ, and the drain electrode of the first buffer transistor TB1 is connected to the gate electrode of the fifth transistor T5. The gate electrode of the first buffer transistor TB1 is configured to receive the start signal EVST or the carry signal CR. The first buffer transistor TB1 is turned on in response to the start signal EVST or the carry signal CR to transmit the voltage at the Q-node EQ to the gate electrode of the fifth transistor T5.

[0065] The high-potential drive voltages EVEH1 and EVEH2 applied to the stage circuit ST have a high voltage level of approximately 25V or greater. When the first high-potential drive voltage EVEH1 is applied to the Q-node EQ, causing the stage circuit ST to enter a pull-up state, the high gate-source voltage of the fifth transistor T5, whose gate electrode is connected to the Q-node EQ, rapidly increases. This increases the component stress of the fifth transistor T5, thereby shortening its service life. In the illustrated embodiment, the gate electrode of the fifth transistor T5 is indirectly connected to the Q-node EQ via the first buffer transistor TB1, rather than directly connected to the Q-node EQ. The first buffer transistor TB1 acts as a resistor between the Q-node EQ and the gate electrode of the fifth transistor T5, thereby preventing the high-potential voltage from being suddenly transmitted to the gate electrode of the fifth transistor T5. Therefore, the first buffer transistor TB1 can reduce the stress applied to the fifth transistor T5 and increase the component's service life, thereby improving the stability and reliability of the stage circuit ST.

[0066] At the same time, the first buffer transistor TB1 is turned on and off by the start signal EVST or the carry signal CR. The start signal EVST and the carry signal CR are alternating ...

[0067] The sixth transistor T6 can be electrically connected between the input terminal of the first high potential drive voltage EVEH1 and the QB node EQB. For example, the source electrode of the sixth transistor T6 is connected to the input terminal of the first high potential drive voltage EVEH1, and the drain electrode of the sixth transistor T6 is connected to the QB node EQB. The gate electrode of the sixth transistor T6 can be configured to receive the voltage at the Q node EQ. When the voltage at the Q node EQ is set to the on-level, the sixth transistor T6 can be turned on to apply the first high potential drive voltage EVEH1 to the QB node EQB. When the Q node EQ is set to the on-level voltage, the QB node EQB can be set to the off-level voltage through the sixth transistor T6.

[0068] As described with reference to the fifth transistor T5, the gate electrode of the sixth transistor T6 can be electrically connected to the Q-node EQ via the second buffer transistor TB2. The second buffer transistor TB2 can be electrically connected between the gate electrode of the sixth transistor T6 and the Q-node EQ. For example, the source electrode of the second buffer transistor TB2 is connected to the gate electrode of the sixth transistor T6, and the drain electrode of the second buffer transistor TB2 is connected to the Q-node EQ. The gate electrode of the second buffer transistor TB2 is configured to receive the start signal EVST or the carry signal CR. The second buffer transistor TB2 is turned on in response to the start signal EVST or the carry signal CR to transmit the voltage at the Q-node EQ to the gate electrode of the sixth transistor T6. Since the function and effect of the second buffer transistor TB2 are the same as those described with respect to the first buffer transistor TB1, a detailed description thereof will be omitted.

[0069] While the emission signal EM is output at the on-level, the pump controller 43 is configured to change the voltage at the Q node EQ according to the second clock signal ECLK2 in response to the start signal EVST or the carry signal CR. To this end, the pump controller 43 may include a clock transistor Tclk, a pump capacitor Cpump, a feedback transistor Tfeed, a pump transistor Tpump, and a reset transistor Treset.

[0070] The clock transistor Tclk may be electrically connected between the pumping capacitor Cpump and the input terminal of the second clock signal ECLK2. For example, the source electrode of the clock transistor Tclk is connected to the pumping capacitor Cpump, and the drain electrode of the clock transistor Tclk is connected to the input terminal of the second clock signal ECLK2. The gate electrode of the clock transistor Tclk is configured to receive the start signal EVST or the carry signal CR. The clock transistor Tclk may be turned on in response to the start signal EVST or the carry signal CR to apply a voltage corresponding to the second clock signal ECLK2 to the pumping capacitor Cpump.

[0071] The pumping capacitor Cpump may be electrically connected between the clock transistor Tclk and the pumping transistor Tpump. For example, a first capacitor electrode of the pumping capacitor Cpump is connected to the source electrode of the clock transistor Tclk, and a second capacitor electrode of the pumping capacitor Cpump is connected to the source electrode of the pumping transistor Tpump. The pumping capacitor Cpump may store a voltage applied by the clock transistor Tclk.

[0072] The feedback transistor Tfeed can be electrically connected between the first low-potential driving voltage EVEL1 and the gate electrode of the pumping transistor Tpump. For example, the source electrode of the feedback transistor Tfeed is connected to the gate electrode of the pumping transistor Tpump, and the drain electrode of the feedback transistor Tfeed is connected to the first low-potential driving voltage EVEL1. The gate electrode of the feedback transistor Tfeed is connected to the light-emitting line EL. While the light-emitting signal EM at the on-level is output to the light-emitting line EL, the feedback transistor Tfeed is turned on to apply the first low-potential driving voltage EVEL1 to the gate electrode of the pumping transistor Tpump. Therefore, when the feedback transistor Tfeed is turned on, the pumping transistor Tpump can be turned on in response to the first low-potential driving voltage EVEL1.

[0073] The pumping transistor Tpump is diode-connected between the pumping capacitor Cpump and the Q-node EQ. The gate electrode of the pumping transistor Tpump is connected to the feedback transistor Tfeed. When the first low-potential driving voltage EVEL1 is applied to the gate electrode through the feedback transistor Tfeed, the pumping transistor Tpump is turned on to electrically connect the pumping capacitor Cpump to the Q-node EQ.

[0074] The reset transistor Treset can be electrically connected between the input terminal of the first high-potential drive voltage EVEH1 and the pumping capacitor Cpump. For example, the source electrode of the reset transistor Treset is connected to the input terminal of the first high-potential drive voltage EVEH1, and the drain electrode of the reset transistor Treset is connected to the pumping capacitor Cpump. In addition, the drain electrode of the reset transistor Treset can be electrically connected to the gate electrode of the pumping transistor Tpump. The gate electrode of the reset transistor Treset is connected to the QB node EQB. The reset transistor Treset can be turned on according to the voltage at the QB node EQB to apply the first high-potential drive voltage EVEH1 to the gate electrode of the pumping transistor Tpump, thereby turning off the pumping transistor Tpump.

[0075] The output buffer 44 is configured to output high-potential driving voltages EVEH1 and EVEH2 or low-potential driving voltages EVEL1 and EVEL2 to the corresponding emission line EL in response to the voltages at the Q node EQ and the QB node EQB. To this end, the output buffer 44 may include one or more pull-up transistors Tup1 and Tup2 and one or more pull-down transistors Tdn1 and Tdn2. For example, the output buffer 44 may include a pair of pull-up transistors Tup1 and Tdn1 for outputting the emission signal EM and a pair of pull-up transistors Tup2 and Tdn2 for outputting the carry signal CR.

[0076] The first pull-up transistor Tup1 may be electrically connected between the second low-potential driving voltage EVEL2 and the emission line EL. The gate electrode of the first pull-up transistor Tup1 is connected to the Q node EQ. When the voltage at the Q node EQ is set to a conduction level, the first pull-up transistor Tup1 may output the second low-potential driving voltage EVEL2 as the emission signal EM to the emission line EL.

[0077] In one embodiment, a boost capacitor Cboot may be connected between the emission line EL and the gate electrode of the first pull-up transistor Tup1. When the emission signal EM at the on-level is output to the emission line EL, the boost capacitor Cboot may boost the voltage of the gate electrode of the first pull-up transistor Tup1 to a low level, thereby stably maintaining the on-state of the first pull-up transistor Tup1.

[0078] The first pull-down transistor Tdn1 may be electrically connected between the second high potential driving voltage EVEH2 and the emission line EL. The gate electrode of the first pull-down transistor Tdn1 is connected to the QB node EQB. When the voltage at the QB node EQB is set to a conduction level, the first pull-down transistor Tdn1 may output the second high potential driving voltage EVEH2 as the emission signal EM to the emission line EL.

[0079] The second pull-up transistor Tup2 may be electrically connected between an output terminal of the first low potential drive voltage EVEL1 and the carry signal CR. A gate electrode of the second pull-up transistor Tup2 is connected to the Q node EQ. When the voltage at the Q node EQ is set to a conduction level, the second pull-up transistor Tup2 may output the first low potential drive voltage EVEL1 as the carry signal CR.

[0080] The second pull-down transistor Tdn2 may be electrically connected between an output terminal of the first high potential drive voltage EVEH1 and a carry signal CR. A gate electrode of the second pull-down transistor Tdn2 is connected to the QB node EQB. When the voltage at the QB node EQB is set to an on-level, the second pull-down transistor Tdn2 may output the first high potential drive voltage EVEH1 as the carry signal CR.

[0081] As described above, the light emitting driver 40 according to one embodiment (see Figure 2 ) can be configured to operate in a forward mode and a reverse mode. In this embodiment, the stage circuit ST is configured to receive the carry signal CR_F or the forward start signal EVST_F output from the previous stage circuit ST, or receive the carry signal CR_B or the reverse start signal EVST_B output from the subsequent stage circuit ST through the signal input unit 45. The signal input unit 45 may include a seventh transistor T7 and an eighth transistor T8.

[0082] One electrode of the seventh transistor T7 is connected to an input terminal of a forward start signal EVST_F or an input terminal of a carry signal CR of a preceding circuit ST. The other electrode of the seventh transistor T7 is connected to an input node EI. A gate electrode of the seventh transistor T7 can be connected to a forward low potential drive voltage EVEL_F. The seventh transistor T7 can be turned on by the forward low potential drive voltage EVEL_F applied when the light emitting driver 40 is in the forward mode, so as to apply the forward start signal EVST_F to the input node EI.

[0083] One electrode of the eighth transistor T8 is connected to an input terminal of the reverse start signal EVST_B or an input terminal of the carry signal CR of the subsequent circuit ST, and the other electrode is connected to the input node EI. The gate electrode of the eighth transistor T8 can be connected to the reverse low potential drive voltage EVEL_B. The eighth transistor T8 can be turned on by the reverse low potential drive voltage EVEL_B applied when the light emitting driver 40 is in the reverse mode to apply the reverse start signal EVST_B to the input node EI.

[0084] The stage circuit ST may further include a reset unit 46. The reset unit 46 may include a ninth transistor T9 and a tenth transistor T10.

[0085] The ninth transistor T9 can be electrically connected between the input terminal of the first high potential driving voltage EVEH1 and the Q node EQ. For example, the source electrode of the ninth transistor T9 is connected to the input terminal of the first high potential driving voltage EVEH1, and the drain electrode of the ninth transistor T9 is connected to the Q node EQ. The gate electrode of the ninth transistor T9 is configured to receive a reset signal RST. The ninth transistor T9 can be turned on in response to the reset signal RST to reset the Q node EQ to the first high potential driving voltage EVEH1.

[0086] The tenth transistor T10 can be electrically connected between an input terminal for the first high-potential driving voltage EVEH1 and the light-emitting line EL. For example, a source electrode of the tenth transistor T10 is connected to the input terminal for the first high-potential driving voltage EVEH1, and a drain electrode of the tenth transistor T10 is connected to the light-emitting line EL. A gate electrode of the tenth transistor T10 is configured to receive a reset signal RST. The tenth transistor T10 can be turned on in response to the reset signal RST to output the first high-potential driving voltage EVEH1 at an off-level to the light-emitting line EL.

[0087] When the ninth and tenth transistors T9 and T10 are turned on in response to the reset signal RST, the Q node EQ may be reset to a high potential voltage, the QB node EQB may be reset to a low potential voltage, and the emission signal EM at a turn-off level may be output to the emission line EL.

[0088] In one embodiment, in the stage circuit ST, at least one of the transistors directly connected to the first high potential driving voltage EVEH1 may be formed by two sub-transistors connected in series. For example, the second transistor T2 may be formed by two sub-second transistors T21 and T22 connected in series (e.g., connected in series), and the fifth transistor T5 may be formed by two sub-fifth transistors T51 and T52 connected in series. Figure 4 As shown, the gate electrodes of the two sub-second transistors T21 and T22 are connected to each other, and the gate electrodes of the sub-fifth transistors T51 and T52 are connected to each other. Furthermore, the sixth transistor T6 can be formed by two sub-sixth transistors T61 and T62 connected in series, the ninth transistor T9 can be formed by two sub-ninth transistors T91 and T92 connected in series, and the reset transistor Treset can be formed by two sub-reset transistors Treset1 and Treset2 connected in series. Similar to the second and fifth transistors, the gate electrodes of the two sub-sixth transistors T61 and T62 are connected to each other, the gate electrodes of the two sub-ninth transistors T91 and T92 are connected to each other, and the gate electrodes of the two sub-reset transistors Treset1 and Treset2 are connected to each other.

[0089] Therefore, by distributing stress applied during operation to a plurality of sub-transistors, it is possible to reduce stress applied to each transistor and improve stability and reliability of operation.

[0090] In the illustrated embodiment, the stage circuit ST is configured to receive two high potential drive voltages EVEH1 and EVEH2 and two low potential drive voltages EVEL1 and EVEL2. However, the present embodiment is not limited thereto, and a smaller or larger number of high potential drive voltages and / or low potential drive voltages may be applied to the stage circuit ST. For example, the first high potential drive voltage EVEH1 and the second high potential drive voltage EVEH2 may be voltages at the same level or different levels, and the first low potential drive voltage EVEL1 and the second low potential drive voltage EVEL2 may be voltages at the same level or different levels. In addition, according to the configuration of the stage circuit ST and / or the pixel PX (see Figure 1 ) of the transistor type (for example, N-type or P-type), the high potential driving voltages EVEH1 and EVEH2 and the low potential driving voltages EVEL1 and EVEL2 can be applied in reverse.

[0091] Figure 5 is a diagram showing a drive according to one embodiment Figure 4 The timing diagram of the stage circuit method. Figure 5 In the example, it is assumed that the light emitting driver 40 (see Figure 2 ) is driven in forward mode.

[0092] Reference together Figure 4 and Figure 5 , the positive start signal EVST_F may be applied at an off level (ie, a high level) for a first period t1 in one frame. In addition, while the positive start signal EVST_F at the off level is applied, the first clock signal ECLK1 may be applied at an on level (ie, a low level).

[0093] When the first transistor T1 is turned on in response to the first clock signal ECLK1 , the forward start signal EVST_F may be transmitted to the Q node EQ, and the voltage at the Q node EQ may be set to a high level.

[0094] Furthermore, when the fourth transistor T4 is turned on in response to the first clock signal ECLK1, the first low-potential driving voltage EVEL1 may be applied to the gate electrode of the third transistor T3, turning on the third transistor T3. The first low-potential driving voltage EVEL1 may then be transmitted to the QB node EQB via the third transistor T3, setting the voltage at the QB node EQB to a low level. The first pull-down transistor Tdn1 and the second pull-down transistor Tdn2 may be turned on in response to the voltage at the QB node EQB being at a low level, and the second high-potential driving voltage EVEH2 and the first high-potential driving voltage EVEH1 may be output to the emission signal EM and the carry signal CR, respectively.

[0095] While the voltage at the QB node EQB is set to a low level, the first high potential driving voltage EVEH1 may be applied to the Q node EQ through the second transistor T2 turned on in response thereto, thereby stably maintaining the voltage at the Q node EQ at a high level.

[0096] Furthermore, while the voltage at the QB node EQB is set to a low level, the first high-potential driving voltage EVEH1 is applied to the gate electrode of the pumping transistor Tpump via the reset transistor Treset, which is turned on in response thereto, thereby turning off the pumping transistor Tpump. In other words, the pump controller 43 can be separated from the Q node EQ. In other words, while the emission signal EM at the off level is output, the pump controller 43 does not operate.

[0097] Thereafter, the forward start signal EVST_F may be applied at a turn-on level (i.e., a low level). When the forward low potential driving voltage EVEL_F is applied to the gate electrode of the seventh transistor T7 within the second period t2, the seventh transistor T7 may be turned on to apply the forward start signal EVST_F to the Q node controller 41, the QB node controller 42, and the pump controller 43.

[0098] Therefore, the first buffer transistor TB1 and the second buffer transistor TB2 can be turned on in response to the positive start signal EVST_F, and the Q node EQ and the gate electrode of the fifth transistor T5 and the gate electrode of the sixth transistor T6 can be electrically connected. In addition, the clock transistor Tclk can be turned on to electrically connect the gate electrode of the pump transistor Tpump to the input terminal of the second clock signal ECLK2.

[0099] While the forward start signal EVST_F at the on level is applied, the first and second clock signals ECLK1 and ECLK2 may be alternately applied at the on level (ie, low level).

[0100] First, when the first clock signal ECLK1 is applied at a turn-on level, the first transistor T1 can be turned on to transmit the forward start signal EVST_F to the Q node EQ, and the voltage at the Q node EQ can be set to a low level. The first pull-up transistor Tup1 and the second pull-up transistor Tup2 can be turned on in response to the voltage at the Q node EQ at a low level, and the second low potential driving voltage EVEL2 and the first low potential driving voltage EVEL1 can be output to the emission signal EM and the carry signal CR, respectively.

[0101] When the low-level emission signal EM is output, the voltage level of the Q node EQ can be further reduced by the boosting capacitor Cboot. In other words, the voltage at the Q node EQ can be reduced by the boosting capacitor Cboot to a level sufficient to turn on the pull-up transistors Tup1 and Tup2.

[0102] While the voltage at the Q node EQ is set to a low level, the sixth transistor T6 can be turned on to transmit the first high potential driving voltage EVEH1 to the QB node EQB, and the voltage at the QB node EQB can be set to a high level. In addition, the fifth transistor T5 can be turned on to transmit the first high potential driving voltage EVEH1 to the gate electrode of the third transistor T3, and the third transistor T3 can be turned off, thereby stably maintaining the voltage at the QB node EQB at a high level.

[0103] At the same time, while the emission signal EM at the on-level is output, the feedback transistor Tfeed can be turned on to transmit the first low-potential driving voltage EVEL1 to the gate electrode of the pumping transistor Tpump. Therefore, while the emission signal EM at the on-level is output, the pumping transistor Tpump can remain in the on state, and the pumping capacitor Cpump can be electrically connected to the Q-node EQ for coupling.

[0104] When the positive start signal EVST_F at the on-level is applied, the clock transistor Tclk is turned on, and thus the second clock signal ECLK2 can be applied to the pumping capacitor Cpump. While the second clock signal ECLK2 repeats high and low levels, the voltage at the Q node EQ can be changed through the coupled pumping capacitor Cpump.

[0105] Specifically, when the second clock signal ECLK2 changes from a high level to a low level, current may flow from the Q node EQ to the pumping capacitor Cpump through the pumping transistor Tpump to reduce the voltage level of the Q node EQ. On the other hand, when the second clock signal ECLK2 changes from a low level to a high level, the voltage at the Q node EQ remains unchanged through the diode-connected pumping transistor Tpump.

[0106] As described above, through the pump controller 43, while the emission signal EM is output at the on-level, the Q node EQ can gradually decrease in response to the second clock signal ECLK2, which repeats a high level and a low level. For example, the voltage at the Q node EQ can decrease by the first level Δ1 for each cycle of the second clock signal ECLK2. Therefore, the difference between the voltage at the Q node EQ and the voltage for turning on the pull-up transistors Tup1 and Tup2 can gradually increase. Therefore, while the emission signal EM is output at the on-level, the pull-up transistors Tup1 and Tup2 can stably maintain the on-state, and the emission signal EM at the on-level can be continuously output.

[0107] Figure 6 It specifically shows that according to another embodiment Figure 3 Circuit diagram of the stage circuit.

[0108] refer to Figure 6 The stage circuit ST' may include a Q-node controller 41', a QB-node controller 42', a pump controller 43', and an output buffer 44'. In addition, the stage circuit ST' may further include a signal input unit 45'.

[0109] The Q-node controller 41 ′ may include a first transistor T1 .

[0110] The first transistor T1 can be electrically connected between the input node EI of the start signal EVST or the carry signal CR output from the previous stage and the Q node EQ. The gate electrode of the first transistor T1 is configured to receive the clock signal ECLK. The first transistor T1 can be turned on according to the clock signal ECLK to apply the start signal EVST or the carry signal CR input through the signal input unit 45' to the Q node EQ.

[0111] The QB node controller 42 ′ may include a second transistor T2 , a third transistor T3 , and a fourth transistor T4 .

[0112] The second transistor T2 may be electrically connected between an input terminal of a first low potential driving voltage EVEL and the QB node EQB. A gate electrode of the second transistor T2 may be connected to the QB' node EQB'. When the voltage at the QB' node EQB' is set to a conduction level, the second transistor T2 may be turned on to apply the low potential driving voltage EVEL to the QB node EQB.

[0113] The third transistor T3 can be electrically connected between the QB' node EQB' and the input terminal of the high potential drive voltage EVEH. The gate electrode of the third transistor T3 is connected to the Q node EQ. When the voltage at the Q node EQ is set to the on-level, the third transistor T3 can be turned on to apply the high potential drive voltage EVEH to the QB' node EQB'. When the third transistor T3 is turned on and the voltage at the QB' node EQB' is set to the high potential drive voltage EVEH, the second transistor T2 is turned off to not apply the low potential drive voltage EVEL to the QB node EQB.

[0114] The fourth transistor T4 may be electrically connected between an input terminal of a high potential driving voltage EVEH and the QB node EQB. A gate electrode of the fourth transistor T4 may be electrically connected to the Q node EQ. When the voltage at the Q node EQ is set to an on-level, the fourth transistor T4 may be turned on to apply the high potential driving voltage EVEH to the QB node EQB. When the Q node EQ is set to an on-level voltage, the QB node EQB may be set to an off-level voltage through the fourth transistor T4.

[0115] The pump controller 43 ′ may include a clock transistor Tclk, a pump capacitor Cpump, a feedback transistor Tfeed, and a pump transistor Tpump.

[0116] A clock transistor Tclk may be electrically connected between a pumping capacitor Cpump and an input terminal of a pumping clock signal ECLK_pump. A gate electrode of the clock transistor Tclk may be configured to receive a start signal EVST or a carry signal CR. The clock transistor Tclk may be turned on in response to the start signal EVST or the carry signal CR to apply a voltage corresponding to the pumping clock signal ECLK_pump to the pumping capacitor Cpump.

[0117] The pump clock signal ECLK_pump may be a pulse signal having the same waveform as the clock signal ECLK and an opposite phase. In one embodiment, the pump clock signal ECLK_pump may control a pulse voltage level or a pulse delay to control the voltage at the Q node EQ.

[0118] The pumping capacitor Cpump may be electrically connected between the clock transistor Tclk and the pumping transistor Tpump. The pumping capacitor Cpump may store a voltage applied by the clock transistor Tclk.

[0119] The feedback transistor Tfeed can be electrically connected between the low-potential driving voltage EVEL and the gate electrode of the pumping transistor Tpump. The gate electrode of the feedback transistor Tfeed is connected to the emission line EL. When the emission signal EM at the on-level is output to the emission line EL, the feedback transistor Tfeed is turned on to apply the low-potential driving voltage EVEL to the gate electrode of the pumping transistor Tpump. Therefore, when the feedback transistor Tfeed is turned on, the pumping transistor Tpump can be turned on in response to the low-potential driving voltage EVEL.

[0120] The pump transistor Tpump is diode-connected between the pump capacitor Cpump and the Q-node EQ. The gate electrode of the pump transistor Tpump is connected to the feedback transistor Tfeed. When a low-potential drive voltage EVEL is applied to the gate electrode through the feedback transistor Tfeed, the pump transistor Tpump is turned on to electrically connect the pump capacitor Cpump to the Q-node EQ.

[0121] The output buffer 44' may include one or more pull-up transistors Tup1 and Tup2 and one or more pull-down transistors Tdn1 and Tdn2. For example, the output buffer 44' may include a pair of pull-up transistors Tup1 and Tdn1 for outputting the emission signal EM and a pair of pull-up transistors Tup2 and Tdn2 for outputting the carry signal CR.

[0122] The first pull-up transistor Tup1 may be electrically connected between the low-potential driving voltage EVEL and the emission line EL. A gate electrode of the first pull-up transistor Tup1 is connected to the Q node EQ. When the voltage at the Q node EQ is set to a conduction level, the first pull-up transistor Tup1 may output the low-potential driving voltage EVEL as the emission signal EM to the emission line EL.

[0123] A first pull-down transistor Tdn1 may be electrically connected between the high-potential driving voltage EVEH and the emission line EL. A gate electrode of the first pull-down transistor Tdn1 is connected to the QB node EQB. When the voltage at the QB node EQB is set to an on-level, the first pull-down transistor Tdn1 may output the high-potential driving voltage EVEH as the emission signal EM to the emission line EL.

[0124] The second pull-up transistor Tup2 can be electrically connected between the low potential drive voltage EVEL and the output terminal of the carry signal CR. The gate electrode of the second pull-up transistor Tup2 is connected to the Q node EQ. When the voltage at the Q node EQ is set to the on-level, the second pull-up transistor Tup2 can output the low potential drive voltage EVEL as the carry signal CR.

[0125] The second pull-down transistor Tdn2 may be electrically connected between an output terminal of the high potential drive voltage EVEH and the carry signal CR. A gate electrode of the second pull-down transistor Tdn2 is connected to the QB node EQB. When the voltage at the QB node EQB is set to a conduction level, the second pull-down transistor Tdn2 may output the high potential drive voltage EVEH as the carry signal CR.

[0126] The signal input unit 45 ′ may include a fifth transistor T5 .

[0127] One electrode of the fifth transistor T5 is connected to an input terminal of a forward start signal EVST_F or an input terminal of a carry signal CR of a preceding circuit ST. The other electrode of the fifth transistor T5 is connected to an input node EI. A gate electrode of the fifth transistor T5 can be connected to a forward low potential drive voltage EVEL_F. The fifth transistor T5 can be turned on by the forward low potential drive voltage EVEL_F applied when the light emitting driver 40 is in the forward mode, so as to apply the forward start signal EVST_F to the input node EI.

[0128] Figure 7 is a diagram showing a drive according to one embodiment Figure 6 The timing diagram of the stage circuit method.

[0129] Reference together Figure 6 and Figure 7 , the positive start signal EVST_F may be applied at an off level (ie, a high level) in a first period t1 in one frame. In addition, while the positive start signal EVST_F at the off level is applied, the clock signal ECLK may be applied at an on level (ie, a low level).

[0130] When the first transistor T1 is turned on in response to the clock signal ECLK, the forward start signal EVST_F may be transmitted to the Q node EQ, and the voltage at the Q node EQ may be set to a high level.

[0131] In response to the voltage at the Q node EQ, the third transistor T3 is turned off, and the second transistor T2 is turned on by the low potential driving voltage EVEL applied to the gate electrode of the second transistor T2 to apply the low potential driving voltage EVEL to the QB node EQB. Therefore, the voltage at the QB node EQB can be set to a low level. The first pull-down transistor Tdn1 and the second pull-down transistor Tdn2 can be turned on in response to the voltage at the QB node EQB being at a low level, and the high potential driving voltage EVEH can be output to the emission signal EM and the carry signal CR.

[0132] Thereafter, the forward start signal EVST_F may be applied at a turn-on level (i.e., a low level) during the second period t2. When the forward low potential driving voltage EVEL_F is applied to the gate electrode of the fifth transistor T5 within the second period t2, the fifth transistor T5 may be turned on to apply the forward start signal EVST_F to the Q-node controller 41', the QB-node controller 42', and the pump controller 43'.

[0133] While the forward start signal EVST_F at the on level is applied, the clock signal ECLK and the pumping clock signal ECLK_pump may be alternately applied at the on level (ie, low level).

[0134] First, when the clock signal ECLK is applied at a turn-on level, the first transistor T1 can be turned on to transmit the forward start signal EVST_F to the Q node EQ, and the voltage at the Q node EQ can be set to a low level. The first pull-up transistor Tup1 and the second pull-up transistor Tup2 can be turned on in response to the voltage at the Q node EQ at a low level, and the low potential driving voltage EVEL can be output to the emission signal EM and the carry signal CR.

[0135] While the voltage at the Q node EQ is set to a low level, the fourth transistor T4 can be turned on to transmit the high potential driving voltage EVEH to the QB node EQB, and the voltage at the QB node EQB can be set to a high level. In addition, the third transistor T3 can be turned on to transmit the high potential driving voltage EVEH to the gate electrode of the second transistor T2, and the second transistor T2 can be turned off, thereby stably maintaining the voltage at the QB node EQB at a high level.

[0136] At the same time, while the emission signal EM at the on-level is output, the feedback transistor Tfeed can be turned on to transmit the low-potential driving voltage EVEL to the gate electrode of the pump transistor Tpump. Therefore, while the emission signal EM at the on-level is output, the pump transistor Tpump can maintain a turned-on state, and the pumping capacitor Cpump can be electrically connected to the Q-node EQ for coupling.

[0137] When the positive start signal EVST_F at the on level is applied, the clock transistor Tclk is turned on, and thus the pumping clock signal ECLK_pump can be applied to the pumping capacitor Cpump. While the pumping clock signal ECLK_pump repeats high and low levels, the voltage at the Q node EQ can be changed through the coupled pumping capacitor Cpump.

[0138] Specifically, when the pump clock signal ECLK_pump changes from a high level to a low level, current may flow from the Q node EQ to the pump capacitor Cpump through the pump transistor Tpump to reduce the voltage level of the Q node EQ. On the other hand, when the pump clock signal ECLK_pump changes from a low level to a high level, the voltage at the Q node EQ does not change due to the diode-connected pump transistor Tpump.

[0139] As described above, the pump controller 43' can gradually decrease the voltage at the Q node EQ in response to the pump clock signal ECLK_pump, which repeats the high and low levels, when the emission signal EM is output at the on-level. Therefore, the difference between the voltage at the Q node EQ and the voltage for turning on the pull-up transistors Tup1 and Tup2 can gradually increase. Therefore, while the emission signal EM is output at the on-level, the pull-up transistors Tup1 and Tup2 can stably maintain the on-state, and the emission signal EM at the on-level can be continuously output.

[0140] The pump controller 43' can control the change in voltage at the Q node EQ according to the voltage applied to the pump capacitor Cpump. The voltage applied to the pump capacitor Cpump can be controlled according to the amount of current that can flow through the clock transistor Tclk, and the amount of current can be controlled according to the gate-source voltage of the clock transistor Tclk.

[0141] When the gate electrode voltage of the clock transistor Tclk is fixed, the gate-source voltage is determined according to the voltage level of the pumping clock signal ECLK_pump. Therefore, as the voltage level of the pulse of the pumping clock signal ECLK_pump is adjusted, the degree of voltage drop of the Q node EQ can be adjusted.

[0142] In the illustrated embodiment, the pulse voltage level of the pump clock signal ECLK_pump is set to be relatively low. For example, the pulse voltage level of the pump clock signal ECLK_pump can be set to be lower than the pulse voltage level of the clock signal ECLK. Consequently, since the gate-source voltage of the clock transistor Tclk is relatively reduced, the amount of current flowing through the pump capacitor Cpump is reduced. In other words, since the amount of current flowing from the Q node EQ to the pump capacitor Cpump is reduced, the voltage at the Q node EQ decreases relatively less.

[0143] exist Figure 7 In the embodiment shown, for each cycle of the pump clock signal ECLK_pump, the voltage at the Q node EQ decreases by a second level Δ2. Here, the second level Δ2 may be less than the reference level. Figure 5 The first level Δ1 is described.

[0144] When the voltage at the Q node EQ gradually decreases, a high gate-source voltage may be applied to the third transistor T3 and the fourth transistor T4 whose gate electrodes are connected to the Q node EQ, thereby increasing element stress. Figure 7 In the embodiment of the present invention, when the drop width of the voltage at the Q node EQ is adjusted by controlling the pump clock signal ECLK_pump, a high gate-source voltage can be prevented from being applied to the third transistor T3 and the fourth transistor T4. As a result, according to this embodiment, component stress can be reduced, thereby increasing the service life of the components and improving the stability and reliability of the stage circuit ST'.

[0145] Figure 8 The driving method according to another embodiment is shown Figure 6 The timing diagram of the stage circuit method.

[0146] and Figure 7 Compared with the implementation method, Figure 8 In an embodiment, the pulse delay of the pump clock signal ECLK_pump is adjusted. Specifically, the pulse generation time of the pump clock signal ECLK_pump can be delayed by increasing the length of the predetermined rise time. For example, the pump clock signal ECLK_pump can be controlled to have a longer rise time than the clock signal ECLK. The pulse delay can be adjusted by adding a resistor to the input line or input pin to which the pump clock signal ECLK_pump is applied.

[0147] When the pulse of the pump clock signal ECLK_pump is delayed, the time during which the conduction level is maintained is relatively short, and thus the voltage at the Q node EQ decreases relatively less. Figure 8 In the embodiment shown, for each cycle of the pump clock signal ECLK_pump, the voltage at the Q node EQ decreases by a third level Δ3. Here, the third level Δ3 may be less than the reference level. Figure 5 The first level Δ1 is described.

[0148] When the voltage at the Q node EQ gradually decreases, a high gate-source voltage may be applied to the third transistor T3 and the fourth transistor T4 whose gate electrodes are connected to the Q node EQ, thereby increasing element stress. Figure 8 In the embodiment of the present invention, when the drop width of the voltage at the Q node EQ is adjusted by controlling the pump clock signal ECLK_pump, a high gate-source voltage can be prevented from being applied to the third transistor T3 and the fourth transistor T4. As a result, according to this embodiment, component stress can be reduced, thereby increasing the service life of the components and improving the stability and reliability of the stage circuit ST'.

[0149] Figure 9 is a circuit diagram showing a pixel according to one embodiment.

[0150] Reference Figure 9 The pixel PX may include a driving transistor DT, a light emitting element LD connected to the driving transistor DT, and a control circuit CC for controlling the amount of driving current to be applied to the light emitting element LD through the driving transistor DT. For example, the control circuit CC may include a switching transistor SWT, a light emission control transistor ET, and a storage capacitor Cst.

[0151] A first electrode of the driving transistor DT is connected to the high potential driving voltage ELVDD, and a second electrode thereof is connected to the anode of the light-emitting element LD. A gate electrode of the driving transistor DT is connected to a first node N1. The driving transistor DT can be turned on according to the voltage applied to the first node N1 to control the amount of driving current flowing from the high potential driving voltage ELVDD to the light-emitting element LD.

[0152] The switching transistor SWT is connected between the first node N1 and the data line DL. A gate electrode of the switching transistor SWT is connected to the gate line GL. The switching transistor SWT can be turned on in response to a gate signal SCAN applied to the gate line GL. When the switching transistor SWT is turned on, a data voltage Vdata applied to the data line DL can be applied to the first node N1.

[0153] The storage capacitor Cst is connected between the first node N1 and the anode of the light emitting element LD. The storage capacitor Cst may store a voltage corresponding to a voltage difference between the first node N1 and the anode of the light emitting element LD.

[0154] The emission control transistor ET is connected between the drive transistor DT and the light-emitting element LD. A gate electrode of the emission control transistor ET is connected to the emission line EL. The emission control transistor ET can be turned on in response to an emission signal EM applied to the emission line EL. When the emission control transistor ET is turned on, the drive transistor DT and the light-emitting element LD can be connected to form a current path from the high-potential drive voltage ELVDD to the light-emitting element LD.

[0155] The light-emitting element LD may have an anode connected to the driving transistor DT via the emission control transistor ET and a cathode connected to the low-potential driving voltage ELVSS. When the driving transistor DT and the emission control transistor ET are turned on, a current path may be formed between the high-potential driving voltage ELVDD and the low-potential driving voltage ELVSS, allowing a driving current to flow to the light-emitting element LD. The light-emitting element LD may emit light having a brightness corresponding to the amount of the applied driving current.

[0156] According to one embodiment, a display device 1 (see Figure 1) may be a display including a backlight unit such as an LCD device, and may be a self-luminous display device such as an OLED display device, a quantum dot display device, and a micro LED display device.

[0157] When the display device 1 is an OLED display device, each pixel PX may include a self-luminous OLED as a light-emitting element. When the display device 1 is a quantum dot display, each pixel PX may include a light-emitting element formed from quantum dots, which are semiconductor crystals and self-luminous. When the display device 1 is a micro-LED display device, each pixel PX may include a self-luminous micro-LED made of an inorganic material as a light-emitting element. When the display device 1 is a nano-LED display device, each pixel PX may include a self-luminous nano-LED made of an inorganic material as a light-emitting element.

[0158] According to the light emitting driver and the display including the same according to the embodiment, by improving the reliability of the light emitting driver, it is possible to stably maintain the level of a light emitting signal output during a light emitting period and improve the quality of an image.

[0159] Furthermore, according to the light emitting driver and the display including the same according to the embodiment, a thin and ultra-small display device can be realized by reducing the number of transistors.

[0160] Although the embodiments of the present disclosure have been described above with reference to the accompanying drawings, those skilled in the art to which the present disclosure pertains will appreciate that the above-described technical configurations of the present disclosure may be implemented in other specific forms without changing the technical spirit or basic features of the present disclosure. Therefore, it should be understood that the above-described embodiments are illustrative rather than restrictive in all aspects. In addition, the scope of the present disclosure is described by the claims to be described rather than by specific embodiments. In addition, the meaning and scope of the claims and all changes or modifications derived from equivalent concepts should be interpreted as being included within the scope of the present disclosure.

[0161] CROSS-REFERENCE TO RELATED APPLICATIONS

[0162] This application claims priority to Korean Patent Application No. 10-2024-0018643, filed on February 7, 2024, which is hereby incorporated by reference in its entirety for all purposes.

Claims

1. A display device, comprising: A display panel, the display panel comprising a plurality of pixels; a light emitting driver including a plurality of stage circuits configured to apply light emitting signals to the plurality of pixels through a plurality of light emitting lines, Wherein, each stage circuit of the plurality of stage circuits comprises: a Q-node controller configured to control a voltage at the Q-node by applying one of a start signal, a carry signal, or a high-potential driving voltage to the Q-node in response to a first clock signal received by the Q-node controller; a QB node controller configured to control a voltage at the QB node by applying the high potential driving voltage or a low potential driving voltage lower than the high potential driving voltage to the QB node in response to the first clock signal; an output buffer connected to the Q node and the QB node, the output buffer being configured to output the high potential driving voltage or the low potential driving voltage as a light emitting signal of the stage circuit to a corresponding light emitting line among the plurality of light emitting lines in response to a voltage at the Q node and a voltage at the QB node; and a pump controller connected to the Q node and receiving a second clock signal and the start signal or the carry signal, the pump controller being configured to change the voltage at the Q node a plurality of times according to the second clock signal in response to the start signal or the carry signal while the light-emitting signal outputs a conduction level at which one of the plurality of pixels connected to the corresponding light-emitting line is turned on.

2. The display device according to claim 1, wherein Each of the plurality of stage circuits further comprises: at least one transistor having a gate electrode receiving the voltage at the Q node; and at least one buffer transistor connected to the Q node and the gate electrode of the at least one transistor, the at least one buffer transistor being configured to transmit a voltage at the Q node to the gate electrode of the at least one transistor in response to the start signal or the carry signal.

3. The display device according to claim 2, wherein: The start signal or the carry signal is a pulse signal having an on-level and an off-level alternately, and the on-level is different from the off-level.

4. The display device according to claim 1, wherein Each of the plurality of stage circuits further comprises: at least one transistor having an electrode directly connected to an input terminal of the high-potential drive voltage, The at least one transistor includes a plurality of sub-transistors connected in series.

5. The display device according to claim 1, wherein The Q node controller includes: a first transistor connected to the Q node and an input node, the start signal or the carry signal being input to the first transistor at the input node, a gate electrode of the first transistor being connected to an input terminal of the first clock signal; and A second transistor is connected to the input terminal of the high potential driving voltage and is connected to the first transistor at the Q node, and a gate electrode of the second transistor is connected to the QB node. The display device according to claim 1 , wherein: The QB node controller includes: a third transistor connected to the input terminal of the low potential driving voltage and the QB node, and having a gate electrode connected to the QB′ node; a fourth transistor connected to the input terminal of the low potential driving voltage, the QB′ node, and the gate electrode of the third transistor, wherein the gate electrode of the fourth transistor is connected to the input terminal of the first clock signal; a fifth transistor connected to the input terminal of the high potential driving voltage, the QB′ node, the gate electrode of the third transistor, and the fourth transistor, the gate electrode of the fifth transistor receiving the voltage at the Q node; and a first buffer transistor connected to the Q node and the gate electrode of the fifth transistor, the gate electrode of the first buffer transistor being connected to an input node to which the start signal or the carry signal is applied, The first buffer transistor is configured to transmit the voltage at the Q node to the gate electrode of the fifth transistor in response to the start signal or the carry signal.

7. The display device according to claim 6, wherein: The QB node controller further includes: a sixth transistor connected to the input terminal of the high potential driving voltage and the QB node, wherein a gate electrode of the sixth transistor receives the voltage at the Q node; and a second buffer transistor connected to the Q node and the gate electrode of the sixth transistor, the gate electrode of the second buffer transistor connected to the input node, The second buffer transistor is configured to transmit the voltage at the Q node to the gate electrode of the sixth transistor in response to the start signal or the carry signal.

8. The display device according to claim 1, wherein The pump controller includes: Pump capacitors; a pumping transistor connected to the QB node and a first capacitor electrode of the pumping capacitor, a gate electrode of the pumping transistor connected to the first capacitor electrode of the pumping capacitor; a clock transistor connected to the second capacitor electrode of the pumping capacitor and an input terminal of the second clock signal, a gate electrode of the clock transistor being connected to an input node at which the start signal or the carry signal is input; and A feedback transistor is connected to the gate electrode of the pumping transistor and the input terminal of the low-potential driving voltage, and the gate electrode of the feedback transistor is connected to the corresponding light-emitting line.

9. The display device according to claim 8, wherein The pump controller further includes: A reset transistor is connected to an input terminal of the high potential driving voltage, a gate electrode of the pumping transistor, and the first capacitor electrode of the pumping capacitor, and the gate electrode of the reset transistor is connected to the QB node.

10. The display device according to claim 1, wherein The output buffer comprises: a first pull-up transistor connected to the input terminal of the low-potential driving voltage and the corresponding light-emitting line, a gate electrode of the first pull-up transistor being connected to the Q node; and A first pull-down transistor is connected to the input terminal of the high-potential driving voltage and the corresponding light-emitting line, and a gate electrode of the first pull-down transistor is connected to the QB node.

11. The display device according to claim 10, wherein: The output buffer further comprises: a second pull-up transistor connected to the input terminal of the low potential drive voltage and the output terminal of a carry signal, the gate electrode of the second pull-up transistor being connected to the Q node; and A second pull-down transistor is connected to the input terminal of the high-potential driving voltage and the output terminal of the carry signal, and a gate electrode of the second pull-down transistor is connected to the QB node.

12. The display device according to claim 1, wherein Each of the plurality of stage circuits further comprises: A signal input circuit is configured to apply the start signal or the carry signal to the Q-node controller, the QB-node controller, and the pump controller.

13. The display device according to claim 1, wherein Each of the plurality of stage circuits further comprises: A reset circuit is connected to the Q node and configured to initialize a voltage at the Q node to the high-potential driving voltage in response to a reset signal.

14. The display device according to claim 1, wherein The pump controller includes: Pump capacitors; a pumping transistor connected to the QB node and a first capacitor electrode of the pumping capacitor, a gate electrode of the pumping transistor connected to the first capacitor electrode of the pumping capacitor; a clock transistor connected between the second capacitor electrode of the pumping capacitor and an input terminal of a pumping clock signal, a gate electrode of the clock transistor being connected to an input node at which the start signal or the carry signal is input; and A feedback transistor is connected to the gate electrode of the pumping transistor and the input terminal of the low-potential driving voltage, and the gate electrode of the feedback transistor is connected to the corresponding light-emitting line.

15. The display device according to claim 14, wherein The pulse voltage level of the pumping clock signal is set to be lower than the pulse voltage level of the first clock signal.

16. The display device according to claim 14, wherein: The pump clock signal is a pulse signal with a predetermined rise time.

17. A light-emitting driver, comprising: a plurality of stage circuits configured to apply light emission signals to a plurality of pixels through a plurality of light emission lines, Wherein, each stage circuit of the plurality of stage circuits comprises: a Q-node controller configured to control a voltage at the Q-node by applying one of a start signal, a carry signal, or a high-potential driving voltage to the Q-node in response to a first clock signal; a QB node controller configured to control a voltage at the QB node by applying the high potential driving voltage or a low potential driving voltage lower than the high potential driving voltage to the QB node in response to the first clock signal, the QB node controller comprising a transistor directly connected to an input terminal of the high potential driving voltage, the transistor receiving the voltage at the Q node at the gate electrode of the transistor via a buffer transistor connected to the gate electrode of the transistor and the Q node; An output buffer is connected to the Q node and the QB node, and is configured to output the high-potential driving voltage or the low-potential driving voltage as a light-emitting signal of the stage circuit to a corresponding light-emitting line among the multiple light-emitting lines in response to the voltage at the Q node and the voltage at the QB node.

18. The light emitting driver according to claim 17, wherein: A gate electrode of the buffer transistor receives the start signal or the carry signal, where the start signal or the carry signal is a pulse signal including an on-level and an off-level alternately, the on-level being different from the off-level.

19. The light emitting driver according to claim 17, wherein: The transistor directly connected to the input terminal of the high potential driving voltage includes a plurality of transistors connected in series, The gate electrodes of the plurality of transistors are connected to each other.

20. The light emitting driver according to claim 17, further comprising: A pump controller is configured to change a voltage at the Q node according to a second clock signal in response to the start signal or the carry signal while the light emitting signal is output at an on-level.

21. The light emitting driver according to claim 20, wherein: The pump controller includes: Pump capacitors; a pumping transistor connected to the QB node and a first capacitor electrode of the pumping capacitor, a gate electrode of the pumping transistor connected to the first capacitor electrode of the pumping capacitor; a clock transistor connected to the second capacitor electrode of the pumping capacitor and an input terminal of the second clock signal, a gate electrode of the clock transistor being connected to an input node at which the start signal or the carry signal is input; and A feedback transistor is connected to the gate electrode of the pumping transistor and the input terminal of the low-potential driving voltage, and the gate electrode of the feedback transistor is connected to the corresponding light-emitting line.

22. The light emitting driver according to claim 21, wherein: A pulse voltage level of the second clock signal is lower than a pulse voltage level of the first clock signal.

23. The light emitting driver according to claim 21, wherein: The second clock signal is a pulse signal with a predetermined rise time.

24. The light emitting driver according to claim 21, wherein: The first clock signal and the second clock signal have the same pulse voltage level but different phases.

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