Display panel and display device

Abstract

The invention relates to a display panel and a display device, and relates to the technical field of display. The display panel comprises a display area and a non-display area at least partially surrounding the display area, and the non-display area at least comprises a first non-display area, a fillet area, a fillet transition area and a second non-display area which are arranged in sequence; the display panel comprises a scanning driving circuit, the scanning driving circuit comprises a plurality of first shifting register units and a plurality of second shifting register units, the first shifting register units are located in a first non-display area and a fillet area, and the second shifting register units are located in a fillet transition area; the gate drive circuit comprises a plurality of third shift register units, and third shift registers are located in the first non-display area and the fillet area; wherein the plurality of first shift register units and the plurality of second shift register units are arranged along the edge of the outer side of the display area, and each third shift register unit is correspondingly positioned on one side, deviating from the display area, of one first shift register unit. The narrow frame can be realized.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display technology, display devices are gradually moving towards thin structures with high screen-to-body ratio and narrow bezels. To improve the visual effect, display panels are often designed with special shapes such as C-angle, R-angle or U-shape.

[0003] Display panels are equipped with a driver circuit including a shift register to drive the pixel circuits. This driver circuit increases the width of the bezel, hindering the development of narrow-bezel displays. For display panels with irregular designs, such as rounded corners, the shift registers in the area corresponding to the rounded corners are difficult to arrange in a regular pattern, resulting in a larger area in the bezel corresponding to the rounded corners, hindering the realization of a narrow bezel. Summary of the Invention

[0004] In view of this, embodiments of the present application provide a display panel and a display device that can achieve a narrow frame.

[0005] In a first aspect, embodiments of the present application provide a display panel comprising: a display area and a non-display area at least partially surrounding the display area, wherein the non-display area comprises at least a first non-display area, a rounded corner area, a rounded corner transition area, and a second non-display area arranged in sequence; the display panel comprises:

[0006] A scan driving circuit comprising a plurality of first shift register units and a plurality of second shift register units, wherein the first shift register units are located in the first non-display area and the rounded corner area, and the second shift register units are located in the rounded corner transition area;

[0007] The gate driving circuit includes a plurality of third shift register units, wherein the third shift registers are located in the first non-display area and the rounded corner area; wherein,

[0008] A plurality of first shift register units and a plurality of second shift register units are arranged along the outer edge of the display area, each of the third shift register units is located corresponding to a side of the first shift register unit away from the display area, and at least some of the second shift register units are used to provide electrical signals to the pixel circuits of the display area.

[0009] In a second aspect, an embodiment of the present application further provides a display device, which includes the display panel provided in the first aspect.

[0010] The display panel and display device provided by the embodiments of the present application include a display area and a non-display area that at least partially surrounds the display area, wherein the non-display area includes at least a first non-display area, a rounded corner area, a rounded corner transition area, and a second non-display area arranged in sequence; the display panel also includes a scan drive circuit and a gate drive circuit, wherein the scan drive circuit includes a plurality of first shift register units and a plurality of second shift register units, wherein the first shift register units are located in the first non-display area and the rounded corner area, and the second shift register units are located in the rounded corner transition area; the gate drive circuit includes a plurality of third shift register units, wherein the third shift register units are located in the first non-display area and the rounded corner area, wherein the plurality of first shift register units and the plurality of second shift register units are arranged along the outer edge of the display area, Each third shift register unit is located on a side of a first shift register unit away from the display area, and at least part of the second shift register unit is used to provide an electrical signal to the pixel circuit of the display area. In this way, the second shift register unit and the third shift register unit are decoupled and arranged, that is, the second shift register unit is set separately in the rounded transition area, and the third shift register unit is not set. The rounded transition area is effectively utilized, and the utilization rate of the rounded transition area is improved. The distance between each shift register unit and the pixel circuit can be shortened, and more first shift register units and second shift register units can be arranged in an arc shape, shortening the routing between each shift register unit and the pixel circuit, which is conducive to achieving a narrow frame and improving the screen-to-body ratio and aesthetics. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 This is one of the structural schematic diagrams of a display panel provided in an embodiment of the present application;

[0012] Figure 2 This is a second structural diagram of a display panel provided in an embodiment of the present application;

[0013] Figure 3 The third cross-sectional schematic diagram of a display panel provided in an embodiment of the present application;

[0014] Figure 4 This is a fourth cross-sectional schematic diagram of a display panel provided in an embodiment of the present application;

[0015] Figure 5 A fifth cross-sectional schematic diagram of a display panel provided in an embodiment of the present application;

[0016] Figure 6 A sixth cross-sectional schematic diagram of a display panel provided in an embodiment of the present application;

[0017] Figure 7 The seventh cross-sectional schematic diagram of a display panel provided in an embodiment of the present application;

[0018] Figure 8 The eighth cross-sectional schematic diagram of a display panel provided in an embodiment of the present application;

[0019] Figure 9 A ninth cross-sectional schematic diagram of a display panel provided in an embodiment of the present application;

[0020] Figure 10 This is a tenth cross-sectional schematic diagram of a display panel provided in an embodiment of the present application;

[0021] Figure 11 This is an eleventh cross-sectional schematic diagram of a display panel provided in an embodiment of the present application;

[0022] Figure 12 A schematic structural diagram of the connection relationship between a gate drive circuit and a scan drive circuit and a pixel circuit, respectively, provided in an embodiment of the present application;

[0023] Figure 13 A schematic structural diagram of a pixel circuit provided in an embodiment of the present application;

[0024] Figure 14 A schematic structural diagram of another pixel circuit provided in an embodiment of the present application;

[0025] Figure 15 A schematic structural diagram of another pixel circuit provided in an embodiment of the present application;

[0026] Figure 16 A schematic structural diagram of another pixel circuit provided in an embodiment of the present application;

[0027] Figure 17 A schematic structural diagram of a display device provided in an embodiment of the present application.

[0028] Description of reference numerals:

[0029] 10. Display area; 110. Pixel circuit; 20. Non-display area; 21. First non-display area; 22. Rounded corner area; 23. Rounded corner transition area; 24. Second non-display area; 25. Third non-display area; 201. First side non-display area; 202. Second side non-display area; 30. Scan drive circuit; 31. First shift register unit; 311. Valid first shift register; 312. Virtual first shift register; 32. Second shift register unit; 321. Valid second shift register; 322. Virtual second shift register; 40. Gate drive circuit; 41. Third shift register unit; 411. Valid third shift register; 412. Virtual third shift register; 421. Light-emitting control shift register; 422. Bias control shift register; 423. Gate control shift register. DETAILED DESCRIPTION

[0030] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the disclosure of the present application.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The term "and / or" as used herein includes any and all combinations of one or more of the relevant listed items.

[0032] In the case of using “including,” “having,” and “comprising” described herein, another component may be added unless a clear limiting term such as “only,” “consisting of,” etc. is used. Unless mentioned otherwise, a term in the singular form may include a plural form and should not be understood as having one number.

[0033] It should be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of this application.

[0034] It should also be understood that when interpreting an element, even if not explicitly described, the element is interpreted as including a range of error, which should be within the acceptable deviation range of the specific value determined by those skilled in the art. For example, "approximately," "approximately," or "substantially" can mean within one or more standard deviations, and is not limited here.

[0035] Furthermore, in the specification, the phrase “planar distribution diagram” refers to a drawing when the target portion is viewed from above, and the phrase “cross-sectional diagram” refers to a drawing when a section taken by vertically cutting the target portion is viewed from the side.

[0036] In addition, the drawings are not drawn to a 1:1 scale, and the relative sizes of the elements in the drawings are drawn only as examples and not necessarily according to the true scale.

[0037] Figure 1 A schematic diagram of the structure of a display panel provided in an embodiment of the present application. Figure 1As shown, in some exemplary embodiments, a display panel is provided, which includes a display area 10 and a non-display area 20 at least partially surrounding the display area 10. The display panel further includes a scan driving circuit 30 and a gate driving circuit 40.

[0038] The display area 10 may include a plurality of pixel circuits 110, and the plurality of pixel circuits 110 may be arranged in an array within the display area 10. The pixel circuits 110 may drive the light-emitting elements in the display area 10 to emit light, thereby realizing display.

[0039] The non-display area 20 includes at least a first non-display area 21, a rounded corner area 22, a rounded corner transition area 23, and a second non-display area 24, which are arranged in sequence. The first non-display area 21, the rounded corner area 22, the rounded corner transition area 23, and the second non-display area 24 can be arranged in sequence along the outer edge of the display area 10, wherein the outer edge can be understood as the boundary between the display area 10 and the non-display area 20, and is close to one side of the display area 10. Exemplarily, the outer edges of the display area 10 and the non-display area 20 may include a first linear edge, a curved edge, and a second linear edge connected in sequence, wherein the first non-display area 21 may be located near the first linear edge, the rounded corner area 22 may be located near the curved edge, the rounded corner transition area 23 may be located near the transition edge between the curved edge and the second linear edge (which may include a portion of the curved edge and / or the second linear edge), and the second non-display area 24 may be located near the second linear edge.

[0040] The scan drive circuit 30 includes a plurality of first shift register units 31 and a plurality of second shift register units 32. The first shift register units 31 are located in the first non-display area 21 and the rounded corner area 22. At least some of the first shift register units 31 can be used to provide electrical signals to the pixel circuits 110 in the display area 10 to drive the pixel circuits 110. The second shift register units 32 are located in the rounded corner transition area 23. At least some of the second shift register units 32 are used to provide electrical signals to the pixel circuits 110 in the display area 10 to drive the pixel circuits 110. The first shift register units 31 and the second shift register units 32 can provide the same electrical signal. The first shift register units 31 and the second shift register units 32 can provide the same electrical signal to different pixel circuits 110.

[0041] In the scan drive circuit 30, multiple first shift register units 31 and multiple second shift register units 32 are arranged along the outer edge of the display area 10. For example, the multiple first shift register units 31 are arranged in sequence along the first straight edge and part of the curved edge of the display area 10 within the first non-display area 21 and the rounded corner area 22; and the multiple second shift register units 32 are arranged in sequence along the remaining curved edge within the rounded corner transition area 23. The first shift register units 31 and the multiple second shift register units 32 in the rounded corner area 22 can be arranged in an arc shape. Furthermore, the first shift register units 31 and the multiple second shift register units 32 in the rounded corner area 22 can be arranged in an arc shape on the side close to the display area 10.

[0042] The gate driver circuit 40 includes a plurality of third shift register units 41. The third shift registers are located in the first non-display area 21 and the rounded corner area 22. At least some of the third shift register units 41 can be used to provide electrical signals to the pixel circuits 110 in the display area 10 to drive the pixel circuits 110. The electrical signals provided by the third shift register units 41 can be different from the electrical signals provided by the first shift register unit 31 and the second shift register unit 32.

[0043] In the gate driver circuit 40, each third shift register unit 41 is located on a side of a corresponding first shift register unit 31 facing away from the display area 10. That is, the third shift register and the first shift register are co-located in the first non-display area 21 and the rounded corner area 22. The corresponding third shift register and the first shift register can be connected to the same pixel circuit 110. The third shift register units 41 in the rounded corner area 22 can be arranged in an arc shape. The number of third shift register units 41 can be the same as the number of first shift registers.

[0044] It should be noted that the third shift register unit 41 is not disposed on the side of the second shift register unit 32 facing away from the display area 10. That is, the second shift register unit 32 is independently disposed in the rounded transition area 23. In the embodiment of the present application, the rounded transition area 23 can be understood as an area where the second shift register can be independently disposed, and is not sufficient to correspond to the area on the side of the second shift register unit 32 facing away from the display area 10 for disposing the third shift register.

[0045] The display panel provided by the above embodiment includes a display area 10 and a non-display area 20 that at least partially surrounds the display area 10, wherein the non-display area 20 includes at least a first non-display area 21, a rounded corner area 22, a rounded corner transition area 23, and a second non-display area 24 that are arranged in sequence; the display panel also includes a scan drive circuit 30 and a gate drive circuit 40, wherein the scan drive circuit 30 includes a plurality of first shift register units 31 and a plurality of second shift register units 32, the first shift register unit 31 is located in the first non-display area 21 and the rounded corner area 22, the second shift register unit 32 is located in the rounded corner transition area 23, the gate drive circuit 40 includes a plurality of third shift register units 41, the third shift register is located in the first non-display area 21 and the rounded corner area 22, and the second shift register unit 32 is located in the rounded corner transition area 23. The display area 21 and the rounded corner area 22 are provided, wherein a plurality of first shift register units 31 and a plurality of second shift register units 32 are arranged along the outer edge of the display area 10, and each third shift register unit 41 is correspondingly located on the side of a first shift register unit 31 away from the display area 10, and at least part of the second shift register units 32 is used to provide electrical signals to the pixel circuit 110 of the display area 10. In this way, the second shift register unit 32 is independently set in the rounded corner transition area 23, which effectively utilizes the rounded corner transition area 23, improves the utilization rate of the rounded corner transition area 23, and can shorten the distance between each shift register unit and the pixel circuit 110, thereby reducing wiring, which is conducive to achieving a narrow frame, improving the screen ratio and aesthetics.

[0046] It can be understood that, in the display panel of the related art, the shift register unit in the scan drive circuit 30 is correspondingly provided with a shift register unit in the gate drive circuit 40 on the side away from the display area 10, that is, if the arrangement method in the related art is followed, the first shift register unit 31 and the second shift register unit 32 are correspondingly provided with a third shift register unit 41 close to the side away from the display area 10, that is, the first shift register unit 31 and the third shift register unit 41 are arranged together, and the second shift register unit 32 and the third shift register unit 41 are arranged together. Based on this, since the rounded transition area 23 is not sufficient to correspond to the side of the second shift register unit 32 away from the display area 10 A third shift register unit 41 is set, therefore, it is necessary to enlarge the rounded area 22 to realize the common arrangement of two shift register units of different driving circuits, which will result in a larger distance between the shift register unit in the rounded area 22 and the pixel circuit 110 electrically connected to it; in addition, since the pixel circuit 110 is arranged in an array, and the shift register units in the rounded area 22 are arranged in an arc shape, there is a large misalignment between the shift register units away from the center of the display area 10 and the pixel circuit 110 electrically connected to it, resulting in a longer line between the misaligned shift register unit and the pixel circuit 110, and the more the misalignment, the longer the line, further increasing the rounded area 22, which is not conducive to achieving a narrow frame and affects the aesthetics and screen-to-body ratio.

[0047] The display panel provided in the embodiment of the present application decouples the second shift register unit 32 and the third shift register unit 41, that is, the second shift register unit 32 is separately provided in the rounded transition area 23, and the third shift register unit 41 is not provided. In this way, the rounded transition area 23 is fully utilized. Compared with the display panel in the related art, the display panel in the present application shortens the distance A' between the shift register unit and the pixel circuit 110. The A' value is small, and more first shift register units 31 and second shift register units 32 can be arranged in an arc shape, thereby shortening the wiring between each shift register unit and the pixel circuit 110, reducing the rounded area 22, and reducing the R-angle frame, thereby achieving a narrow frame.

[0048] Figures 2 to 5 A schematic diagram of the structure of a display panel provided in an embodiment of the present application. Figures 2 to 5 In some exemplary embodiments, the plurality of second shift register units 32 are all valid second shift register units 32. The output end of the valid second shift register unit 32 is electrically connected to the pixel circuit 110. The valid second shift register unit 32 is used to provide an electrical signal to the pixel circuit 110 in the display area 10 to drive the pixel circuit 110. In this way, the rounded corner transition area 23 can be effectively utilized, the utilization rate of the rounded corner transition area 23 can be improved, and it helps to achieve a narrow frame. Exemplarily, the second shift register unit 32 may include one second shift register, and the plurality of second shift registers in the rounded corner transition area 23 may all be valid second shift registers 321.

[0049] Figure 6 and Figure 7 A schematic diagram of the structure of a display panel provided in an embodiment of the present application. Figures 6 and 7 In some exemplary embodiments, among the plurality of second shift register units 32, some of the second shift register units 32 are valid second shift register units 32, and the remaining second shift register units 32 are dummy second shift register units 32. The output end of the dummy second shift register unit 32 (dummy) is suspended. Exemplarily, the second shift register unit 32 may include one second shift register. Among the plurality of second shift registers in the rounded transition region 23, some of the second shift registers may be valid second shift registers 321, and the remaining second shift registers may be dummy second shift registers 322; the dummy second shift register 322 may be located between the valid second shift registers 321.

[0050] It can be understood that the second shift register unit 32 is arranged in an arc shape, and there may be misalignment between the second shift register unit 32 and the pixel circuit 110 electrically connected to it. In this regard, the embodiment of the present application can compensate for the misalignment by setting a virtual second shift register unit 32, thereby shortening the wiring length between the shift register unit and the pixel circuit 110, thereby reducing the wiring area, and helping to achieve a narrow frame.

[0051] Please continue reading Figures 2 to 7 In some exemplary embodiments, the second shift register unit 32 near the second non-display area 24 is an effective second shift register unit 32. The second shift register unit 32 near the second non-display area 24 can be understood as the second shift register unit 32 that is closest to the second non-display area 24. The second shift register unit 32 near the second non-display area 24 can provide an electrical signal to the pixel circuit 110 in the display area 10, thereby driving the pixel circuit 110. In this way, the second shift register unit 32 near the second non-display area 24 is set as an effective second shift register unit 32 according to the driving requirements of the pixel circuit 110, which not only ensures display performance, but also fully and effectively utilizes the space of the rounded transition area 23, can shorten the wiring, and help achieve a narrow frame.

[0052] Please continue reading Figures 2 to 7 In some exemplary embodiments, the second shift register unit 32 near the rounded corner area 22 is an effective second shift register unit 32. The second shift register unit 32 near the rounded corner area 22 can be understood as the second shift register unit 32 closest to the rounded corner area 22. The second shift register unit 32 near the rounded corner area 22 is adjacent to the first shift register unit 31 near the rounded corner transition area 23, wherein the first shift register unit 31 near the rounded corner transition area 23 can be understood as the first shift register unit 31 closest to the rounded corner transition area 23.

[0053] Please continue reading Figures 2 to 7 In some exemplary embodiments, the plurality of first shift register units 31 include valid first shift register units 31 and dummy first shift register units 31. The output terminal of the valid first shift register unit 31 is electrically connected to the pixel circuit 110 in the display area 10, and the valid first shift register unit 31 can provide an electrical signal to the pixel circuit 110. The output terminal of the dummy first shift register unit 31 is suspended. The dummy first shift register unit 31 is located in the rounded corner area 22. The dummy first shift register unit 31 can be used to compensate for the misalignment between the shift register unit and the pixel circuit 110, thereby shortening the wiring between the shift register unit and the pixel circuit 110, thereby reducing the area occupied by the wiring, and helping to achieve a narrow frame.

[0054] Please continue reading Figures 2 to 7 In some exemplary embodiments, the first shift register unit 31 includes at least one first shift register, and the second shift register unit 32 includes one second shift register, wherein the number of valid second shift registers 321 is less than or equal to the number of virtual first shift registers 312. Exemplarily, the number of valid second shift registers 321 is the same as the number of virtual first shift registers 312. In another exemplary embodiment, the number of valid second shift registers 321 is less than the number of virtual first shift registers 312. For example, the third shift register unit 41 includes one third shift register, and in the presence of a virtual third shift register 412, the number of valid second shift registers 321 is less than the number of virtual first shift registers 312.

[0055] It can be understood that the first shift register unit 31 and the third shift register unit 41 are arranged one-to-one, that is, each third shift register is located on the side of at least one first shift register in the same first shift register unit 31 that is away from the display area 10. Therefore, a virtual first shift register 312 can be set, and the number of valid second shift registers 321 can be set to be the same as the number of virtual first shift registers 312, thereby filling the separately set valid second shift registers 321. Based on this, when there is a virtual third shift register unit 41 in the gate drive circuit 40, a corresponding virtual first shift register 312 can also be set, thereby achieving a one-to-one arrangement of the first shift register unit 31 and the third shift register unit 41, and a separate arrangement of the second shift register unit 32. In this way, while achieving a narrow frame, it helps to improve the uniformity of the display panel.

[0056] Please continue reading Figures 2 to 7 In some exemplary embodiments, the plurality of third shift register units 41 include at least an effective third shift register unit 41. Exemplarily, each third shift register unit 41 is an effective third shift register unit 41. The output end of the effective third shift register unit 41 can be electrically connected to the pixel circuit 110 via a signal line. The effective third shift register 411 can be used to provide an electrical signal to the pixel circuit 110. The number of effective third shift register units 41 can be set accordingly according to the driving requirements of the display panel. In this way, the driving requirements of the display panel can be met and the display performance can be guaranteed.

[0057] Please continue reading Figures 2 to 7In some exemplary embodiments, the plurality of third shift register units 41 further include a virtual third shift register unit 41. That is, the gate drive circuit 40 includes a portion of effective third shift register units 41 and a portion of virtual third shift register units 41. The virtual third shift register 412 is located in the rounded corner area 22. The output end of the virtual third shift register unit 41 may be suspended. It is understandable that the third shift register in the rounded corner area 22 is arranged in an arc shape, which may be misaligned with the pixel circuit 110 in the display area 10. To this end, the virtual third shift register unit 41 can be provided to compensate for the misalignment and shorten the length of the signal line between the shift register unit and the pixel circuit 110, thereby reducing the R corner frame.

[0058] Please continue reading Figures 2 to 7 In some exemplary embodiments, the third shift register unit 41 near the rounded corner transition region 23 is an effective third shift register unit 41. The third shift register unit 41 near the rounded corner transition region 23 can be understood as the third shift register unit 41 closest to the rounded corner transition region 23. The output end of the third shift register unit 41 near the rounded corner transition region 23 can be connected to the pixel circuit 110 via a signal line. The third shift register unit 41 near the rounded corner transition region 23 can be used to provide an electrical signal to the pixel circuit 110 to drive the pixel circuit 110.

[0059] It can be understood that at least part of the second shift register unit 32 is used to provide electrical signals to the pixel circuit 110 of the display area 10, that is, at least part of the second shift register unit 32 is a valid second shift register unit 32. Correspondingly, by setting the third shift register unit 41 close to the side of the rounded transition area 23 as a valid third shift register unit 41, the third shift register unit 41 can be used to provide electrical signals to the pixel circuit 110 electrically connected to the partially valid second shift register unit 32, thereby meeting the driving requirements of the pixel circuit 110, which is beneficial to shortening the wiring length between the driving circuit and the pixel circuit 110, and thereby reducing the R-corner frame.

[0060] Please continue reading Figures 2 to 7In some exemplary embodiments, the first shift register unit 31 includes N first shift registers, and the third shift register unit 41 includes a third shift register. N is a positive integer, and N can be 1, 2, or other suitable values. Each third shift register is located on a side of the N first shift registers facing away from the display area 10. The second shift register unit 32 may include a second shift register. The first shift register and the second shift register may adopt the same circuit structure. The first shift register and the second shift register may provide the same electrical signal to the pixel circuits 110 in different rows. The third shift register may adopt a circuit structure different from that of the first shift register and the second shift register, and provide an electrical signal different from that of the first shift register and the second shift register.

[0061] The fact that the third shift register unit 41 includes one third shift register can be understood as follows: the number of shift registers of the same type in the third shift register unit 41 is one. The third shift register unit 41 can include at least one shift register. When the third shift register unit 41 includes multiple shift registers, the various shift registers can be arranged sequentially along the direction of the first shift register unit 31 away from the display area 10, and the shift registers of the same type can be arranged in an arc shape toward one side of the display area 10.

[0062] Figures 8 to 11 This is a schematic diagram of the structure of the display panel provided in the embodiment of the present application. Figure 8 and Figure 9 As shown, in some exemplary embodiments, the third shift register unit 41 includes a light emitting control shift register 421 or a bias control shift register 422. Figure 10 and Figure 11 As shown, in another exemplary embodiment, the third shift register unit 41 includes a light emitting control shift register 421 and a gate control shift register 423, wherein the gate control shift register 423 may be located between the light emitting control shift register 421 and the first shift register unit 31. Figure 11 As shown, in another exemplary embodiment, the third shift register unit 41 includes a bias control shift register 422 and a gate control shift register 423 , wherein the gate control shift register 423 may be located between the bias control shift register 422 and the first shift register unit 31 .

[0063] Figure 12 This is a schematic diagram of the connection relationship between the gate drive circuit 40 and the scan drive circuit 30 and the pixel circuit 110 provided in an embodiment of the present application. Figure 12In some exemplary embodiments, the output of each valid first shift register 311 can be electrically connected to a row of pixel circuits 110 via a signal line, and each valid second shift register 321 can be electrically connected to a row of pixel circuits 110 via a signal line, that is, a one-drive-one method is used to drive the pixel circuits 110; the output of each valid third shift register 411 can be electrically connected to N rows of pixel circuits 110 via a signal line, that is, a one-drive-N method is used to drive the pixel circuits 110. The outputs of the virtual first shift register 312 and the virtual third shift register 412 can both be left floating.

[0064] Take N=2 as an example, Figure 12 As shown, the first shift register unit 31 includes two first shift registers, the second shift register unit 32 includes a second shift register, and the third shift register unit 41 includes a third shift register. Each third shift register is located on the side of the two first shift registers away from the display area 10. In addition, the output end of each first shift register can be electrically connected to a row of pixel circuits 110 through a signal line, and the output end of each second shift register can be electrically connected to a row of pixel circuits 110 through a signal line, that is, the pixel circuit 110 is driven in a one-drive-one manner. The output end of each third shift register can be electrically connected to two rows of pixel circuits 110 through a signal line, that is, the pixel circuit 110 is driven in a one-drive-two manner. It should be noted that in the application, the position correspondence between the first shift register and the third shift register can be set according to the actual driving method. The above N=2 is only an exemplary description.

[0065] It is understood that the first shift register and the third shift register having a positional correspondence, and the N rows of pixel circuits 110 electrically connected to the third shift register, are the same as the N rows of pixel circuits 110 electrically connected to the N first shift registers. The positional correspondence means that the third shift register is located on the side of the N first shift registers facing away from the display area 10. In this way, the first shift register and the third shift register can be arranged accordingly based on the driving mode of each shift register, which is beneficial for improving the uniformity of the display panel and enhancing the display effect. It also helps to regularly arrange the signal lines between each shift register and the pixel circuit 110, further improving the uniformity of the display panel.

[0066] Please continue reading Figures 2 to 7In some exemplary embodiments, the display panel includes a plurality of shift register modules located in the rounded corner area 22. Each shift register module includes a corresponding first shift register unit 31 and a third shift register unit 41. The corresponding first shift register unit 31 and the corresponding third shift register unit 41 refer to a third shift register and the N first shift registers having a positional correspondence, that is, each third shift register is located on a side of the N first shift registers facing away from the display area 10.

[0067] like Figures 2 to 7 As shown, in the same shift register module, the first shift register and the third shift register are both valid shift registers, and the shift register module is recorded as the first shift register module; or, as Figures 2 to 5 As shown, in the same shift register module, the first shift register and the third shift register are both virtual shift registers, and the shift register module is recorded as the second shift register module; or, in the same shift register module, the first shift register is a valid shift register, the third shift register is a virtual shift register, and the shift register module is recorded as the third shift register module; or, as Figures 2 to 5 As shown, in the same shift register module, the first shift register is a virtual shift register, the third shift register is a valid shift register, and the shift register module is recorded as the fourth shift register module; or, as Figures 5 to 7 As shown, in the same shift register module, part of the first shift registers are valid shift registers, the remaining part of the first shift registers are virtual shift registers, and the third shift register is a valid shift register, and the shift register module is recorded as the fifth shift register module; or, as Figure 6 and Figure 7 As shown, in the same shift register module, part of the first shift registers are valid shift registers, the remaining part of the first shift registers are virtual shift registers, and the third shift register is a virtual shift register, and the shift register module is recorded as the sixth shift register module.

[0068] Combine Figure 2 In the case of N=1, the multiple shift register modules of the rounded corner area 22 may include a first shift register module, a second shift register module, a third shift register module and a fourth shift register module. Figures 3 to 7In the case where N>1, the multiple shift register modules in the rounded corner area 22 may include multiple combinations of the first shift register module, the second shift register module, the third shift register module, the fourth shift register module, the fifth shift register module, and the sixth shift register module. In addition, the multiple shift register modules in the rounded corner area 22 can be freely combined and arranged in an arc along the outer edge of the display area 10. The number of various shift register modules can be set according to factors such as the driving requirements of the pixel circuit 110 and the area of the rounded corner area 22, and no excessive restrictions are made here. In this way, each shift register in the same shift register module can be designed according to the effective and virtual ones, which improves the flexibility of the arrangement of the shift registers in the display panel, adapts to the arc arrangement of the shift register modules in the rounded corner area 22, and helps to reduce the R corner frame.

[0069] Please continue reading Figures 8 to 11 In some exemplary embodiments, the third shift register unit 41 includes a light emission control shift register 421 or a bias control shift register 422. The effective light emission control shift register 421 is used to provide a light emission control signal Emit to the pixel circuit 110 of the display area 10. The effective bias control shift register 422 is used to provide a bias control signal SPX to the pixel circuit 110 of the display area 10. In this way, the light emission control signal Emit can be provided to the pixel circuit 110 through the effective light emission control shift register 421, or the bias control signal SPX can be provided to the pixel circuit 110 through the effective bias control shift register 422, thereby driving the pixel circuit 110.

[0070] Please continue reading Figures 8 to 11 In some exemplary embodiments, the non-display area 20 includes a first side non-display area 201 and a second side non-display area 202 that are oppositely disposed.

[0071] Please continue reading Figure 8 and Figure 10 In some exemplary embodiments, the third shift register unit 41 in the first-side non-display area 201 includes a light-emitting control shift register 421, and the third shift register unit 41 in the second-side non-display area 202 includes a light-emitting control shift register 421. The light-emitting control shift registers 421 in the non-display areas 20 on both sides can drive the same row of pixel circuits 110. In this way, the pixel circuits 110 are driven in a two-drive-one manner, which helps improve display performance.

[0072] Please continue reading Figure 9 and Figure 11In some exemplary embodiments, the third shift register unit 41 in the first-side non-display area 201 includes a light-emission control shift register 421, and the third shift register unit 41 in the second-side non-display area 202 includes a bias control shift register 422. The effective light-emission control shift register 421 and the effective bias control shift register 422 can drive the same row of pixel circuits 110. In this way, the pixel circuits 110 are driven in a one-to-one manner, ensuring display performance.

[0073] Please continue reading Figure 10 and Figure 11 In some exemplary embodiments, the third shift register unit 41 further includes a gate control shift register 423. The effective gate control shift register 423 is configured to provide a gate control signal SN to the pixel circuit 110 of the display area 10. Thus, the effective gate control shift register 423 can provide a gate control signal to the pixel circuit 110, thereby driving the pixel circuit 110. The gate control signal may include one or more of S1N, S2N, SN(n), and SN(n-5), as described below.

[0074] Please continue reading Figure 10 In some exemplary embodiments, the third shift register unit 41 in the first-side non-display area 201 includes a light-emitting control shift register 421 and a gate control shift register 423, and the third shift register unit 41 in the second-side non-display area 202 includes a light-emitting control shift register 421 and a gate control shift register 423. The light-emitting control shift register 421 and the gate control shift register 423 in the same third shift register unit 41 can drive the same row of pixel circuits 110, and the same type of shift registers in the non-display areas 20 on both sides can drive the same row of pixel circuits 110. In this way, using a two-drive-one approach to drive the pixel circuits 110 helps improve display performance.

[0075] Please continue reading Figure 11In some exemplary embodiments, the third shift register unit 41 in the first-side non-display area 201 includes a light-emission control shift register 421 and a gate control shift register 423, and the third shift register unit 41 in the second-side non-display area 202 includes a bias control shift register 422 and a gate control shift register 423. The light-emission control shift register 421 and the gate control shift register 423 in the same third shift register unit 41 can drive the same row of pixel circuits 110, and the bias control shift register 422 and the gate control shift register 423 in the same third shift register unit 41 can drive the same row of pixel circuits 110. Furthermore, the light-emission control shift register 421 and the bias control shift register 422 can drive the same row of pixel circuits 110, and the bias control shift registers 422 in the non-display areas 20 on both sides can drive the same row of pixel circuits 110. In this way, display performance is guaranteed.

[0076] Please continue reading Figures 8 to 11 In some exemplary embodiments, the effective first shift register unit 31 and the effective second shift register unit 32 are respectively used to output a scan control signal S(n) to the pixel circuits 110 of the display area 10, wherein the scan control signal includes at least one of a scan signal, an initialization signal, and a bias signal DVH. In the effective first shift register unit 31, the effective first shift register 311 can be electrically connected to a row of pixel circuits 110 via a signal line, thereby providing a scan control signal to the pixel circuits 110 in the row. In the effective second shift register unit 32, the effective second shift register 321 can be electrically connected to a row of pixel circuits 110 via a signal line, thereby providing a scan control signal to the pixel circuits 110 in the row. In this way, the effective first shift register unit 31 and the effective second shift register unit 32 can provide gate control signals to the pixel circuits 110, thereby driving the pixel circuits 110. The scan signal can include one or more of S1, S2, Scan(n-1), and Scan(n), and the initialization signal can include one or more of Vref1 and Vref2, as described below.

[0077] Figures 13 to 16 This is a schematic diagram of the structure of the pixel circuit 110 provided in an embodiment of the present application. Figures 12 to 16In some exemplary embodiments, the pixel circuit 110 may include a driving transistor M3, a data writing transistor M2, a first emission control transistor M1, a second emission control transistor M6, a threshold compensation transistor M4, a first initialization transistor M5, a second initialization transistor M7, and a first capacitor Cst. The gate of the driving transistor M3 is electrically connected to the first end of the first capacitor Cst, the second electrode of the first initialization transistor M5, and the first electrode of the threshold compensation transistor M4, respectively. The first electrode of the driving transistor M3 is electrically connected to the second electrode of the first emission control transistor M1 and the first electrode of the data writing transistor M2, respectively. The second electrode of the driving transistor M3 is electrically connected to the second electrode of the threshold compensation transistor M4 and the first electrode of the second emission control transistor M6, respectively. The first electrode of the first emission control transistor M1 is electrically connected to the second end of the first capacitor Cst and is configured to receive a first power supply signal PVDD. The gates of the first emission control transistor M1 and the second emission control transistor M6 are configured to receive an emission control signal Emit, respectively. The second electrode of the second emission control transistor M6 is electrically connected to the anode of the light-emitting element. The first electrode of the first initialization transistor M5 is used to receive the first initialization signal Vref1, and the first electrode of the second initialization transistor M7 is used to receive the second initialization signal Vref2. The second electrode of the data write transistor M2 is used to receive the data write signal. The cathode of the light-emitting element is used to receive the second power supply signal PVEE. In other words, the pixel circuit 110 can adopt a 7T1C structure, where T represents a transistor and C represents a capacitor. The light-emitting control signal Emit can be provided by the active third shift register unit 41.

[0078] Please continue reading Figure 14 and Figure 16 In some exemplary embodiments, the pixel circuit 110 further includes a bias transistor M8. A first electrode of the bias transistor M8 is configured to receive a bias signal DVH, and a second electrode of the bias transistor M8 is electrically connected to a first electrode of the drive transistor M3, a second electrode of the first emission control transistor M1, and a first electrode of the data write transistor M2. In other words, the pixel circuit 110 may also employ an 8T1C or 8T2C structure.

[0079] Please continue reading Figure 15 and Figure 16 In some exemplary embodiments, the pixel circuit 110 may further include a second capacitor C2 electrically connected to the gate of the data writing transistor M2 and the gate of the driving transistor M3. That is, the pixel circuit 110 may adopt a 7T2C or 8T2C structure.

[0080] It should be noted that the above is only an exemplary description. In actual applications, the pixel circuit 110 can be selected to adopt a 7T1C, 7T2C, 8T1C, 8T2C structure according to needs, or other suitable structures such as 9T1C, 9T2C, etc., which are not limited here.

[0081] Please continue reading Figure 13 In some exemplary embodiments, the pixel circuit 110 may have a 7T1C structure, wherein the first electrode of the first initialization transistor M5 may be configured to receive the first scan signal S1, and the gates of the second initialization transistor M7, the threshold compensation transistor M4, and the data write transistor M2 may each be configured to receive the second scan signal S2. The first scan signal S1 may be provided by an active first shift register unit 31 or an active second shift register unit 32, and the second scan signal S2 may be provided by an active first shift register unit 31 or an active second shift register unit 32. Exemplarily, the pixel circuit 110 may employ the aforementioned 7T1C structure, wherein each transistor may be a low-temperature polysilicon (LTPS) transistor.

[0082] Please continue reading Figure 14 In some exemplary embodiments, in the pixel circuit 110, such as an 8T1C structure, the first electrode of the first initialization transistor M5 can be used to receive the first scan signal S1, the gate of the threshold compensation transistor M4 and the gate of the data write transistor M2 can each be used to receive the second scan signal S2, and the gate of the second initialization transistor M7 and the gate of the bias transistor M8 can be used to receive the bias control signal SPX. The first scan signal S1 can be provided by an active first shift register unit 31 or an active second shift register unit 32, the second scan signal S2 can be provided by an active first shift register unit 31 or an active second shift register unit 32, and the bias control signal SPX can be provided by an active third shift register unit 41. Each transistor can be a low-temperature polysilicon transistor.

[0083] Please continue reading Figure 15In some exemplary embodiments, in the pixel circuit 110, such as a 7T2C structure, the gate of the data write transistor M2 can be used to receive the third scan signal Scan(n), the gate of the second initialization transistor M7 can be used to receive the fourth scan signal Scan(n-1), the gate of the first initialization transistor M5 can be used to receive the first gate control signal SN(n-5), and the gate of the threshold compensation transistor M4 can be used to receive the second gate control signal SN(n). The third scan signal Scan(n) can be provided by an active first shift register unit 31 or an active second shift register unit 32, and the fourth scan signal Scan(n-1) can be provided by an active first shift register unit 31 or an active second shift register unit 32. The first gate control signal SN(n-5) can be provided by an active third shift register unit 41, and the second gate control signal SN(n) can be provided by an active third shift register unit 41. Among them, the first initialization transistor M5 and the threshold compensation transistor M4 can be low temperature polycrystalline oxide (LTPO) transistors, and the second initialization transistor M7, the data writing transistor M2, the first emission control transistor M1, the second emission control transistor M6 and the driving transistor M3 can be low temperature polysilicon transistors.

[0084] Please continue reading Figure 16 In some exemplary embodiments, in the pixel circuit 110, such as in an 8T2C structure, the gate of the data write transistor M2 may be configured to receive the fifth scan signal Scan, the gate of the second initialization transistor M7 may be configured to receive the bias control signal SPX, the gate of the first initialization transistor M5 may be configured to receive the third gate control signal S1N, and the gate of the threshold compensation transistor M4 may be configured to receive the fourth gate control signal S2N. The fifth scan signal Scan may be provided by an active first shift register unit 31 or an active second shift register unit 32. The third gate control signal S1N may be provided by an active third shift register unit 41, and the fourth gate control signal S2N may be provided by an active third shift register unit 41. The bias control signal SPX may be provided by an active third shift register unit 41. The first initialization transistor M5 and the threshold compensation transistor M4 may be low-temperature polycrystalline oxide transistors, and the second initialization transistor M7, the data write transistor M2, the first emission control transistor M1, the second emission control transistor M6, the bias control transistor, and the drive transistor M3 may be low-temperature polycrystalline silicon transistors.

[0085] Please continue reading Figures 1 to 7In some exemplary embodiments, the non-display area 20 further includes a third non-display area 25. The third non-display area 25 is located at least on the side of the first non-display area 21, the rounded corner area 22, the rounded corner transition area 23, and the second non-display area 24 facing away from the display area 10. The display panel may also include multiple signal lines, some of which, such as power signal lines, may be located in the third non-display area 25. The power signal lines can be used to transmit power signals. In this way, wiring can be performed within the third non-display area 25 to meet the power supply requirements of the display area 10.

[0086] Based on the same application concept, an embodiment of the present application also provides a display device. Figure 17 This is a schematic diagram of the structure of the display device 1002 provided in an embodiment of the present application, as shown in FIG. Figure 17 As shown, the display device 1002 includes the display panel 1001 in any of the above embodiments. Figure 17 As shown, the display device 1002 includes a display panel 1001. Therefore, the display device 1002 also has the beneficial effects of the display panel 1001 in the above embodiment. The similarities can be understood by referring to the above explanation of the display panel 1001, which will not be repeated below.

[0087] The display device 1002 provided in the embodiment of the present application can be Figure 17 The mobile phone shown can also be any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, industrial control equipment, medical display screens, touch interactive terminals, etc. The embodiments of this application do not specifically limit this.

[0088] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0089] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A display panel, characterized in that: include: a display area and a non-display area at least partially surrounding the display area, wherein the non-display area at least includes a first non-display area, a rounded corner area, a rounded corner transition area, and a second non-display area arranged in sequence; The display panel includes: A scan driving circuit comprising a plurality of first shift register units and a plurality of second shift register units, wherein the first shift register units are located in the first non-display area and the rounded corner area, and the second shift register units are located in the rounded corner transition area; The gate driving circuit includes a plurality of third shift register units, wherein the third shift registers are located in the first non-display area and the rounded corner area; wherein, A plurality of first shift register units and a plurality of second shift register units are arranged along the outer edge of the display area, each of the third shift register units is located corresponding to a side of the first shift register unit away from the display area, and at least some of the second shift register units are used to provide electrical signals to the pixel circuits of the display area.

2. The display panel according to claim 1, wherein: The second shift register units are all valid second shift register units; or, Among the plurality of second shift register units, some of the second shift register units are valid second shift register units, and the remaining part of the second shift register units are virtual second shift register units.

3. The display panel according to claim 2, wherein: The second shift register unit close to the second non-display area is a valid second shift register unit.

4. The display panel according to claim 3, wherein: The second shift register unit close to the rounded corner area is a valid second shift register unit.

5. The display panel according to claim 2, wherein: The plurality of first shift register units include valid first shift register units and virtual first shift register units; wherein the virtual first shift register units are located in the rounded corner area.

6. The display panel according to claim 5, wherein: The first shift register unit includes at least one first shift register, and the second shift register unit includes a second shift register, wherein the number of effective second shift registers is less than or equal to the number of virtual first shift registers.

7. The display panel according to any one of claims 1 to 6, characterized in that: The plurality of third shift register units include at least an effective third shift register unit.

8. The display panel according to claim 7, wherein: The third shift register unit close to the rounded corner transition area is a valid third shift register unit.

9. The display panel according to claim 7, wherein: The plurality of third shift register units further include a virtual third shift register unit; wherein the virtual third shift register is located in the rounded corner area.

10. The display panel according to any one of claims 1 to 6, wherein: The first shift register unit includes N first shift registers, and the third shift register unit includes one third shift register; wherein N is a positive integer.

11. The display panel according to claim 10, wherein: The display panel includes a plurality of shift register modules located in the rounded corner area, wherein each of the shift register modules includes the first shift register unit and the third shift register unit correspondingly arranged; In the same shift register module, the first shift register and the third shift register are both virtual shift registers; or, In the same shift register module, the first shift register and the third shift register are both valid shift registers; or, In the same shift register module, the first shift register is a valid shift register, and the third shift register is a virtual shift register; or, In the same shift register module, the first shift register is a virtual shift register, and the third shift register is a valid shift register; or, In the same shift register module, part of the first shift registers are valid shift registers, the remaining part of the first shift registers are virtual shift registers, and the third shift register is a valid shift register; or, In the same shift register module, part of the first shift registers are valid shift registers, the remaining part of the first shift registers are virtual shift registers, and the third shift register is a virtual shift register.

12. The display panel according to any one of claims 1 to 6, characterized in that: The third shift register unit includes a light emitting control shift register or a bias control shift register; wherein, An effective light emitting control shift register is used to provide a light emitting control signal to the pixel circuit of the display area; The effective bias control shift register is used to provide a bias control signal to the pixel circuit of the display area.

13. The display panel according to claim 12, wherein: The third shift register unit further includes a gate control shift register, wherein an effective gate control shift register is used to provide a gate control signal to the pixel circuit of the display area.

14. The display panel according to claim 12, wherein: The effective first shift register unit and the effective second shift register unit are respectively used to output a scan control signal to the pixel circuit of the display area, wherein the scan control signal includes at least one of a scan signal, an initialization signal and a bias signal.

15. A display device, characterized in that: The device comprises the display panel according to any one of claims 1 to 14.

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