Pixel circuit, array substrate and display panel

Abstract

The invention discloses a pixel circuit, an array substrate and a display panel. The pixel circuit comprises a data write-in module, a driving module, a compensation module, a node reset module and a storage coupling module. The node reset module, the data write-in module and the storage coupling module are connected to a first node, and the node reset module is used for charging the first node according to a first power supply voltage on a first power supply line in a compensation stage under the control of a first scanning signal on a first scanning line; the compensation module is used for writing voltage information related to the threshold voltage of the driving module into the control end of the driving module according to the first power supply voltage; the data write-in module is used for transmitting data voltage to the first node in a data write-in stage under the control of a second scanning signal on a second scanning line; and the storage coupling module is used for coupling the voltage variation of the control end of the driving module to the control end of the driving module in a data writing stage. The display effect of the display panel can be improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a pixel circuit, an array substrate and a display panel. Background Art

[0002] With the development of display technology, users' requirements for display effects are getting higher and higher.

[0003] In the prior art, there is a problem of poor picture display effect. Summary of the Invention

[0004] The present invention provides a pixel circuit, an array substrate and a display panel to improve the display effect of a display image and enhance the user experience.

[0005] In a first aspect, an embodiment of the present invention provides a pixel circuit, comprising: a data writing module, a driving module, a compensation module, a node reset module, and a storage coupling module; the node reset module is connected to the data writing module and the storage coupling module at a first node, and the node reset module is also connected to the first end of the driving module and the first power line, and is used to charge the first node according to the first power supply voltage on the first power line during a compensation phase under the control of a first scan signal on the first scan line; the compensation module is connected between the control end of the driving module and the second end of the driving module, and is used to write voltage information related to the threshold voltage of the driving module to the control end of the driving module according to the first power supply voltage; the data writing module is used to transmit a data voltage to the first node during a data writing phase under the control of a second scan signal on the second scan line; the storage coupling module is connected to the control end of the driving module, and is used to couple a voltage change of the first node to the control end of the driving module during the data writing phase; the driving module is used to output a driving current according to the voltage of the control end of the driving module during a light-emitting phase.

[0006] Optionally, the storage coupling module includes a storage unit and a coupling unit, the first end of the storage unit is connected to the first power line, the second end of the storage unit and the first end of the coupling unit are connected to the first node, and the second end of the coupling unit is electrically connected to the control end of the driving module.

[0007] Optionally, the storage unit includes a first capacitor; the coupling unit includes a second capacitor; the first end of the first capacitor serves as the first end of the storage unit, and the second end of the first capacitor serves as the second end of the storage unit; the first end of the second capacitor serves as the first end of the coupling unit, and the second end of the second capacitor serves as the second end of the coupling unit.

[0008] Optionally, the pulse width of the effective level of the first scan signal on the first scan line is greater than or equal to 1 divided by a set value, and the set value is equal to the product of the number of rows of pixel circuits included in the display panel where the pixel circuits are located and the refresh frequency.

[0009] Optionally, the node module includes a first switch unit, a first end of the first switch unit is connected to the first node, a second end of the first switch unit is connected to the first end of the driving module and the first power line; the control end of the first switch unit is connected to the first scan line, and the first switch unit is used to, in a compensation phase, be turned on in response to the valid level of a first scan signal on the first scan line, and transmit the first power supply voltage to the first node; and, in a data writing phase, be turned off in response to the invalid level of the first scan signal on the first scan line; the compensation module includes a second switch unit, a first end of the second switch unit is connected to the second end of the driving module, a second end of the second switch unit is connected to the control end of the driving module, and the control end of the second switch unit is connected to the first scan line, and the second switch unit is used to, in a compensation phase, be turned on in response to the valid level of the first scan signal, and write voltage information related to the threshold voltage of the driving module to the control end of the driving module according to the first power supply voltage; and, in a data writing phase, be turned off in response to the invalid level of the first scan signal;

[0010] Optionally, the first switching unit includes a first transistor, the gate of the first transistor serves as the control end of the first switching unit, the first electrode of the first transistor serves as the first end of the first switching unit, and the second electrode of the first transistor serves as the second end of the first switching unit.

[0011] Optionally, the second switch unit includes a second transistor, the gate of the second transistor serves as the control end of the second switch unit, the first electrode of the second transistor serves as the first end of the second switch unit, and the second electrode of the second transistor serves as the second end of the second switch unit.

[0012] Optionally, the control end of the data writing module is connected to the second scan line, the first end of the data writing module is connected to the data line, and the second end of the data writing module is connected to the first node. The data writing module is used to turn on in response to the effective level of the second scan signal on the second scan line during the data writing stage.

[0013] Optionally, the data writing module is further configured to be turned off in response to an invalid level of the second scanning signal on the second scanning line during the compensation phase and the light emitting phase.

[0014] Optionally, the effective level of the second scan signal does not overlap with the effective level of the first scan signal on the first scan line.

[0015] Optionally, the effective level of the second scanning signal is the same as the effective level of the first scanning signal, and the pulse width duration of the effective level of the second scanning signal is equal to the pulse width duration of the effective level of the first scanning signal.

[0016] Optionally, the compensation phase is performed before the data writing phase.

[0017] Optionally, the data writing module includes a third transistor, the gate of the third transistor serves as the control end of the data writing module, the first electrode of the third transistor serves as the first end of the data writing module, and the second electrode of the third transistor serves as the second end of the data writing module.

[0018] Optionally, the pixel circuit also includes a light-emitting control module, the control end of the light-emitting control module is connected to the light-emitting control signal line, the first end of the light-emitting control module is connected to the second end of the driving module, the second end of the light-emitting control module is used to connect to the first end of the light-emitting module, and the second end of the light-emitting control module is connected to the second power line; the light-emitting control module is used to turn on in response to the effective level of the light-emitting control signal during the light-emitting stage under the control of the light-emitting control signal on the light-emitting control signal line.

[0019] Optionally, the light emitting control module is further configured to be turned off in response to an invalid level of the light emitting control signal during the compensation phase and the data writing phase.

[0020] Optionally, the light emitting control module includes a fourth transistor, the gate of the fourth transistor serves as the control end of the light emitting control module, the first electrode of the fourth transistor serves as the first end of the light emitting control module, and the second electrode of the fourth transistor serves as the second end of the light emitting control module.

[0021] Optionally, the pixel circuit further includes a first initialization module, the first initialization module is connected to the first initialization signal line, and the first initialization module is used to initialize the first end of the light-emitting module during the initialization phase.

[0022] Optionally, the first initialization module includes a fifth transistor, the gate of the fifth transistor serves as the control terminal of the first initialization module, the first electrode of the fifth transistor serves as the first terminal of the first initialization module, and the second electrode of the fifth transistor serves as the second terminal of the first initialization module.

[0023] Optionally, the pixel circuit further includes a second initialization module, and the second initialization module is used to initialize the control end of the driving module during the initialization phase.

[0024] Optionally, the control end of the second initialization module is connected to the third scan line, the first end of the second initialization module is connected to the second initialization signal line, and the second initialization module is used to turn on in response to the effective level of the third scan signal on the third scan line during the initialization phase.

[0025] Optionally, the effective level of the third scanning signal is the same as the effective level of the second scanning signal, and the pulse width duration of the effective level of the third scanning signal is equal to the pulse width duration of the effective level of the second scanning signal.

[0026] Optionally, an initialization phase is performed before the compensation phase.

[0027] Optionally, the control end of the first initialization module is connected to the third scan line, the first end of the first initialization module is connected to the first initialization signal line, and the second end of the first initialization module is connected to the first end of the light emitting module.

[0028] Optionally, the second initialization module includes a sixth transistor, the gate of the sixth transistor serves as the control terminal of the second initialization module, the first electrode of the sixth transistor serves as the first terminal of the second initialization module, and the second electrode of the sixth transistor serves as the second terminal of the second initialization module.

[0029] Optionally, the start time of the effective level of the first scanning signal is before the end time of the effective level of the third scanning signal, and the end time of the effective level of the first scanning signal is after the end time of the effective level of the third scanning signal; or, the effective level of the first scanning signal does not overlap with the effective level of the third scanning signal.

[0030] Optionally, the effective level of the second scanning signal does not overlap with the effective level of the first scanning signal and the effective level of the third scanning signal.

[0031] Optionally, the effective level of the first scanning signal does not overlap with the effective level of the third scanning signal.

[0032] Optionally, within one frame, the working process of the pixel circuit includes at least two groups of non-luminous stages performed successively, each group of non-luminous stages includes an initialization stage, a compensation stage and a data writing stage; wherein, within one frame, the time interval between the first valid level of the third scanning signal and the second valid level of the third scanning signal is greater than the time interval between the first valid level of the first scanning signal and the second valid level of the first scanning signal, and is greater than the time interval between the first valid level of the second scanning signal and the second valid level of the second scanning signal.

[0033] Optionally, within one frame, a time interval between a first valid level of the first scanning signal and a first valid level of the third scanning signal is greater than a time interval between a first valid level of the second scanning signal and a first valid level of the first scanning signal.

[0034] Optionally, within a frame, in the kth non-luminous stage, the time interval between the effective level of the first scanning signal and the effective level of the third scanning signal is equal to the time interval between the effective level of the second scanning signal and the effective level of the first scanning signal, where k is a positive integer greater than or equal to 2.

[0035] Optionally, the control end of the first initialization module is connected to the first scan line, the first end of the first initialization module is connected to the first initialization signal line, and the second end of the first initialization module is connected to the first end of the light-emitting module; the first initialization module is used to turn on in response to the effective level of the first scan signal on the first scan line during the initialization stage.

[0036] Optionally, the compensation module is also used to turn on in response to the effective level of the first scanning signal during the initialization stage; the light-emitting control module is also used to turn on in response to the effective level of the light-emitting control signal during the initialization stage, so that the first initialization voltage on the first initialization signal line is transmitted to the control end of the driving module through the first initialization module, the light-emitting control module and the compensation module.

[0037] Optionally, the pulse width of the effective level of the first scan signal on the first scan line is greater than or equal to 1 divided by a set value, and the set value is equal to the product of the number of rows of pixel circuits included in the display panel where the pixel circuits are located and the refresh frequency.

[0038] In a second aspect, an embodiment of the present invention provides an array substrate comprising a plurality of pixel circuits provided by any embodiment of the present invention.

[0039] Optionally, multiple pixel circuits are arranged in an array; the display panel also includes a first scanning circuit, the first scanning circuit includes a multi-stage cascaded first shift register; the data writing module and the compensation module in the same pixel circuit are connected to the output ends of the first shift registers of different stages of the first scanning circuit.

[0040] Optionally, the pixel circuit further includes a first initialization module. In the same pixel circuit, the control end of the first initialization module, the data writing module, and the compensation module are connected to the output ends of the first shift registers at different stages.

[0041] Optionally, in the same pixel circuit, the shift register connected to the compensation module is a subsequent stage of the shift register connected to the first initialization module.

[0042] Optionally, the effective levels of the scanning signals output by two adjacent first shift registers partially overlap, and the first shift register connected to the data writing module is the next T stages of the first shift register connected to the compensation module, where T is greater than or equal to 2.

[0043] Optionally, the effective levels of the scanning signals output by two adjacent first shift registers do not overlap, and the first shift register connected to the data writing module is the next n stages of the first shift register connected to the compensation module, where n is greater than or equal to 1.

[0044] Optionally, the pixel circuit further includes a first initialization module;

[0045] Optionally, the effective levels of the scanning signals output by two adjacent stages of the first shift registers partially overlap or do not overlap, and in the same pixel circuit, the first shift register connected to the compensation module is a subsequent stage of the first shift register connected to the first initialization module;

[0046] Alternatively, the effective levels of the scanning signals output by two adjacent stages of the first shift register do not overlap, and within one frame, the scanning signals output by the first shift register include at least two effective levels; the array substrate further includes a second scanning circuit, the second scanning circuit includes a multi-stage cascaded second shift register, the first initialization module is connected to the output end of the second shift register; within one frame, the output end of the second shift register outputs at least two effective levels;

[0047] In one frame, a time interval between a first valid level and a second valid level output by the second shift register is greater than a time interval between a first valid level and a second valid level output by the first shift register.

[0048] In a third aspect, an embodiment of the present invention further provides a display panel, comprising the array substrate provided by any embodiment of the present invention.

[0049] The pixel circuit provided in an embodiment of the present invention separates the compensation phase from the data writing phase. This ensures that the threshold voltage compensation of the driver module and the data voltage writing process do not restrict each other, allowing the driver module's threshold voltage to be fully compensated, thereby improving the compensation effect. Because the threshold voltage compensation and data writing do not affect each other, the driver module's threshold voltage can be fully compensated even at high refresh rates, thereby improving display brightness variations, enhancing the uniformity of the displayed image, and enhancing the display quality. Furthermore, in this embodiment, the storage coupling module can directly couple the voltage change of the first node to the control terminal of the driver module, ensuring that the data voltage is free of voltage loss.

[0050] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0052] Figure 1 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0053] Figure 2 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0054] Figure 3 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0055] Figure 4 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0056] Figure 5 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0057] Figure 6 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0058] Figure 7 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0059] Figure 8 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0060] Figure 9 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0061] Figure 10 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0062] Figure 11a This is a driving timing waveform diagram of a pixel circuit provided by an embodiment of the present invention;

[0063] Figure 11b is a driving timing waveform diagram of another pixel circuit provided by an embodiment of the present invention;

[0064] Figure 12 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0065] Figure 13 is a driving timing waveform diagram of another pixel circuit provided by an embodiment of the present invention;

[0066] Figure 14 It is a structural schematic diagram of a display panel provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0067] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0068] It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and the accompanying drawings are used to distinguish similar items and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, such that the embodiments of the present invention described herein can be implemented in sequences other than those illustrated or described herein. Furthermore, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions.

[0069] As described in the background technology, in the prior art, there is a problem of poor screen display effect. Specifically, the display effect will be affected by the brightness uniformity. The higher the brightness uniformity, the better the display effect. In the prior art, in order to improve the brightness uniformity, it is usually adopted to compensate the threshold voltage of the driving transistor in the pixel circuit to improve the brightness uniformity of the entire display screen. However, in the existing pixel circuit structure, the threshold voltage compensation time of the driving transistor and the time of writing the data voltage to the gate of the driving transistor are mutually restricted, and the time of writing the data voltage is short, which is not conducive to the compensation of the threshold voltage, affecting the brightness uniformity, resulting in poor display effect.

[0070] In view of the above problems, an embodiment of the present invention provides a pixel circuit and a display panel. The pixel circuit provided by the embodiment of the present invention is first introduced below.

[0071] Figure 1 This is a schematic diagram of a pixel circuit according to an embodiment of the present invention. Figure 1 The pixel circuit includes: a data writing module 11, a driving module 12, a compensation module 13, a node resetting module 19 and a storage coupling module 14.

[0072] The node reset module 19 is connected to the first node N1, the data writing module 11, and the storage coupling module 14. The node reset module 19 is also connected to the first end of the driving module 13 and the first power line L1, and is used to charge the first node N1 according to the first power supply voltage VDD on the first power line L1 during the compensation phase under the control of the first scan signal on the first scan line S1.

[0073] The compensation module 13 is connected between the control terminal G1 of the driver module 12 and the second terminal of the driver module 12 and is configured to write voltage information related to the threshold voltage of the driver module 12 to the control terminal G1 of the driver module 12 based on the first power supply voltage VDD. The data writing module 11 is configured to transmit the data voltage Vdata to the first node N1 during the data writing phase under the control of the second scan signal on the second scan line S2. The storage coupling module 14 is connected to the control terminal of the driver module 12 and is configured to couple the voltage change of the first node N1 to the control terminal G1 of the driver module 12 during the data writing phase. During the light-emitting phase, the driver module 12 is configured to output a driving current based on the voltage at the control terminal of the driver module 12.

[0074] The data write module 11 includes a circuit device with a switching function. When the data write module 11 is turned on, it can transmit the data voltage value to the first node N1. The node reset module 19 and the compensation module 13 may also include circuit devices with a switching function. When the node reset module 19 is turned on, the node reset module 19 can connect the first power line to the first node N1, so that the first power supply voltage VDD charges the first node N1. When the compensation module 13 is turned on, the compensation module 13 connects the second terminal of the driver module 12 to the control terminal G1, and writes voltage information related to the threshold voltage of the driver module 12 to the control terminal G1 of the driver module 12.

[0075] The storage coupling module 14 has the functions of voltage storage and voltage coupling, and can realize the coupling and writing of information related to the data voltage to the control terminal G1 of the driving module 14 , and can realize the voltage storage of the control terminal G1 of the driving module 14 .

[0076] For example, the driving module 12 may include a driving transistor, and compensating for the threshold voltage of the driving module 12 is equivalent to compensating for the threshold voltage of the driving transistor.

[0077] like Figure 1 As shown, the working process of the pixel circuit includes:

[0078] During the compensation phase, the driver module 12, compensation module 13, and node reset module 19 are turned on, and the data writing module 11 is turned off. The first power supply voltage VDD of the first power line L1 is charged to the first node N1 via the node reset module 19, stabilizing its voltage at the first power supply voltage VDD. Simultaneously, the first power supply voltage VDD transmitted on the first power line L1 is written to the control terminal G1 of the driver module 12 via the compensation module 13 until the voltage at the control terminal G1 of the driver module 12 reaches VDD + Vth, where Vth is the threshold voltage of the driver transistor. VDD + Vth is voltage information related to the threshold voltage of the driver module 12. The storage coupling module 14 stores the voltage at the control terminal G1 of the driver module 12.

[0079] During the data writing phase, the data writing module 11 is turned on, while the compensation module 13 and the node reset module 19 are turned off. The data writing module 11 writes the data voltage Vdata to the first node N1. At this point, the voltage of the first node N1 jumps from the first power supply voltage VDD to the data voltage Vdata. Under the coupling action of the storage coupling module 14, the voltage change of the first node N1 is coupled to the control terminal G1 of the driving module 12, thereby implementing data writing. The data voltage Vdata can be provided by a data line.

[0080] The voltage variation at the first node N1 is ΔV = Vdata - VDD. Due to the coupling effect of the storage coupling module 14, the voltage at the control terminal of the driver module 12 is Vg = VDD + Vth + ΔV = VDD + Vth + Vdata - VDD = Vdata + Vth. Therefore, in this embodiment, the storage coupling module 14 can directly couple the voltage variation at the first node N1 to the control terminal of the driver module 12. During this process, the data voltage Vdata does not need to be multiplied by a coefficient, ensuring that there is no voltage loss in the data voltage.

[0081] During the light-emitting phase, the data writing module 11, the compensation module 13, and the node reset module 19 are turned off. The driving module 12 is used to generate a driving current according to the potential of its control terminal G1 to drive the light-emitting device to emit light during the light-emitting phase. The driving current I can be expressed as:

[0082]

[0083] Where, μ is the electron mobility of the driving transistor, C ox is the channel capacitance per unit area of the driver transistor, and W / L is the width-to-length ratio of the driver transistor.

[0084] The pixel circuit provided in an embodiment of the present invention separates the compensation phase from the data writing phase. This ensures that the threshold voltage compensation of the driver module and the data voltage writing process do not restrict each other, allowing the driver module's threshold voltage to be fully compensated, thereby improving the compensation effect. Because the threshold voltage compensation and data writing do not affect each other, the driver module's threshold voltage can be fully compensated even at high refresh rates, thereby improving display brightness variations, enhancing the uniformity of the displayed image, and enhancing the display quality. Furthermore, in this embodiment, the storage coupling module can directly couple the voltage change of the first node to the control terminal of the driver module, ensuring that the data voltage is free of voltage loss.

[0085] Figure 2 is a schematic diagram of another pixel circuit provided by an embodiment of the present invention, referring to Figure 2On the basis of the above technical solution, optionally, the storage coupling module 14 includes a storage unit 141 and a coupling unit 142, a first end of the storage unit 141 is connected to the first power line L1, a second end of the storage unit 141 and a first end of the coupling unit 142 are connected to the first node N1, and a second end of the coupling unit 142 is electrically connected to the control end G1 of the driving module 12.

[0086] Specifically, coupling unit 142 is used to couple the voltage variation at first node N1 to control terminal G1 of driver module 12 during the data writing phase to implement data writing. By providing coupling unit 142 in this embodiment, after the data voltage Vdata is transmitted to first node N1, the voltage variation at first node N1 is directly coupled to control terminal G1 of driver module 12, eliminating voltage loss and facilitating high brightness. During the light-emitting phase, storage unit 141 and coupling unit 142 can jointly store the voltage difference between first power supply voltage VDD and control terminal G1 of driver module 12, ensuring consistent brightness during the light-emitting phase.

[0087] Figure 3 is a schematic diagram of another pixel circuit provided by an embodiment of the present invention, referring to Figure 3 Optionally, the storage unit 141 includes a first capacitor C1, and the coupling unit 142 includes a second capacitor C2. The first end of the first capacitor C1 serves as the first end of the storage unit 141, and the second end of the first capacitor C1 serves as the second end of the storage unit 141. The first end of the second capacitor C2 serves as the first end of the coupling unit 142, and the second end of the second capacitor C2 serves as the second end of the coupling unit 142. In this embodiment, the output storage unit 141 and the coupling unit 142 are each composed of a single capacitor, which makes the storage unit 141 and the coupling unit 142 simple in structure and easy to implement.

[0088] Figure 4 is a schematic diagram of another pixel circuit provided by an embodiment of the present invention, referring to Figure 4 Optionally, the node reset module 19 includes a first switch unit 131, a first end of the first switch unit 131 is connected to the first node N1, a second end of the first switch unit 132 is connected to the first end of the driving module 12 and the first power line L1, and a control end of the first switch unit 131 is connected to the first scan line S1. The first switch unit 131 is used to respond to the valid level of the first scan signal on the first scan line S1 during the compensation stage, turn on, and transmit the first power supply voltage VDD to the first node N1; and to respond to the invalid level of the first scan signal on the first scan line S1 during the data writing stage.

[0089] The compensation module 13 includes a second switch unit 132. A first end of the second switch unit 132 is connected to the second end of the driving module 12, a second end of the second switch unit 132 is connected to the control end of the driving module 12, and the control end of the second switch unit 132 is connected to the first scan line S1. The second switch unit 132 is configured to be turned on in response to the valid level of the first scan signal during the compensation phase and to write voltage information related to the threshold voltage of the driving module 12 to the control end G1 of the driving module 12 based on the first power supply voltage VDD; and to be turned off in response to the invalid level of the first scan signal during the data writing phase.

[0090] Specifically, the first scan signal includes an active level and an inactive level. The active level is a control signal that turns on the transistor controlled by the first scan line S1. The inactive level is a control signal that turns off the transistor controlled by the first scan line S1. Optionally, when the transistor controlled by the first scan line S1 is a P-type transistor, the active level is a low-level signal and the inactive level is a high-level signal; when the transistor controlled by the first scan line S1 is an N-type transistor, the active level is a high-level signal and the inactive level is a low-level signal.

[0091] The pulse width of the effective level of the first scan signal on the first scan line is greater than or equal to 1 divided by a set value, and the set value is equal to the product of the number of rows of pixel circuits included in the display panel where the pixel circuits are located and the refresh frequency.

[0092] Specifically, 1 divided by the refresh rate represents the period of one frame of display image, and this period divided by the number of rows of pixel circuits equals the line time corresponding to each row of pixel circuits, that is, 1 divided by the set value represents the line time corresponding to a row of pixel circuits. The pulse width duration of the effective level of the first scanning signal on the first scanning line S1 is greater than or equal to this time, which means that the time of the compensation phase can be longer. Such a setting can ensure that in a high refresh frequency scenario, even if the line time is shortened, by ensuring the pulse width duration of the effective level of the first scanning signal, the compensation module 13 has sufficient time to complete the compensation of the threshold voltage of the driving module 12, thereby avoiding the problem of insufficient threshold voltage compensation due to insufficient compensation time, thereby improving the uniformity of display brightness.

[0093] During the compensation phase, the first scan line S1 outputs an active voltage, and the first and second switch units 131 and 132 are turned on. The first power supply voltage VDD on the first power line L1 is charged to the first node N1 via the first switch unit 131, stabilizing the voltage at the first node N1 to the first power supply voltage VDD. Simultaneously, the first power supply voltage VDD is written to the control terminal G1 of the driver module 12 via the driver module 12 and the second switch unit 132. When the gate voltage of the driver transistor DTFT reaches VDD + Vth, the driver module 12 is turned off, and the compensation phase ends. The storage coupling module 14 stores the voltage at the control terminal G1 of the driver module 12.

[0094] During the data writing phase, the first scan line S1 outputs an inactive level, and the first and second switch units 131 and 132 are turned off. When the first switch unit 131 is turned off, the first node N1 is disconnected from the first power supply voltage VDD, and the data voltage Vdata is inputted by the data writing module 11. When the second switch unit 132 is turned off, the control terminal G1 of the driver module 12 is disconnected from the second terminal of the driver module 12. At this point, the voltage at the control terminal G1 of the driver module 12 is controlled by the storage coupling module 14, which couples the voltage change at the first node N1 to the control terminal G1 of the driver module 12 through coupling.

[0095] This embodiment uses the first scan signal to independently control the switching of compensation module 13, completely separating the timing of threshold voltage compensation and data writing. This avoids the inadequate compensation caused by simultaneous execution of both in conventional solutions. Because the compensation time is independent of the data writing time, even at high refresh rates (shortened row times), the effective signal pulse width during the compensation phase can be extended to ensure adequate threshold voltage compensation, avoiding the inadequate compensation caused by insufficient row times in conventional solutions.

[0096] Figure 5 is a schematic diagram of another pixel circuit provided by an embodiment of the present invention, referring to Figure 5 Optionally, the first switching unit 131 includes a first transistor T1, the gate of the first transistor T1 serves as the control end of the first switching unit 131, the first electrode of the first transistor T1 serves as the first end of the first switching unit 131, and the second electrode of the first transistor T1 serves as the second end of the first switching unit 131.

[0097] Continue to refer Figure 5 Optionally, the second switch unit 132 includes a second transistor T2, the gate of the second transistor T2 serves as the control terminal of the second switch unit 132, the first electrode of the second transistor T2 serves as the first terminal of the second switch unit 132, and the second electrode of the second transistor T2 serves as the second terminal of the second switch unit 132. In this embodiment, the first output switch unit 131 and the second output switch unit 132 are each composed of a single transistor, so that the first output switch unit 131 and the second output switch unit 132 are simple in structure and easy to implement.

[0098] Figure 6 is a schematic diagram of another pixel circuit provided by an embodiment of the present invention, referring to Figure 6Optionally, a control end of the data writing module 11 is connected to the second scan line S2, a first end of the data writing module 11 is connected to the data line, and a second end of the data writing module 11 is connected to the first node N1. The data writing module 11 is configured to be turned on in response to an active level of the second scan signal on the second scan line S2 during a data writing phase. Optionally, the data writing module 11 is further configured to be turned off in response to an inactive level of the second scan signal on the second scan line S2 during a compensation phase and a light emitting phase. Optionally, the compensation phase is performed before the data writing phase.

[0099] Specifically, the second scan signal includes an active level of the second scan signal and an inactive level of the second scan signal. The active level of the second scan signal is a control signal that turns on the transistor controlled by the second scan line S2. The inactive level of the second scan signal is a control signal that turns off the transistor controlled by the second scan line S2. Optionally, when the transistor controlled by the second scan line S2 is a P-type transistor, the active level of the second scan signal is a low-level signal, and the inactive level of the second scan signal is a high-level signal; when the transistor controlled by the second scan line S2 is an N-type transistor, the active level of the second scan signal is a high-level signal, and the inactive level of the second scan signal is a low-level signal.

[0100] During the data writing phase, the data writing module 11 is turned on, and the data voltage Vdata on the data line is written to the first node N1 via the second terminal of the data writing module 11, causing the voltage of the first node N1 to jump from the first power supply voltage VDD during the compensation phase to the data voltage Vdata. The storage coupling module 14 couples the voltage change at the first node N1 to the control terminal G1 of the driving module, thereby indirectly writing the data voltage.

[0101] Optionally, the effective level of the second scanning signal does not overlap with the effective level of the first scanning signal on the first scanning line S1. This arrangement allows the compensation phase and the data writing phase to be completely separated in terms of timing, ensuring the accuracy of the threshold voltage compensation of the driver module 12 and the reliability of the data voltage writing, thereby improving the consistency of the pixel circuit drive current and the uniformity of the displayed image.

[0102] Optionally, the effective level of the second scanning signal is the same as the effective level of the first scanning signal, and the pulse width duration of the effective level of the second scanning signal is equal to the pulse width duration of the effective level of the first scanning signal.

[0103] In some embodiments, the second scan line S2 and the first scan line S1 are connected to the same scanning circuit. The scanning circuit includes multiple cascaded shift registers. The data writing module 11 and the compensation module 13 in the same pixel circuit are connected to the output terminals of different shift registers. This arrangement allows the multi-stage shift registers in the same scanning circuit to output scanning signals with controllable timing, allowing the scanning signals of the data writing module 11 and the compensation module 13 to be naturally staggered in time, thereby reducing the bezel of the display panel.

[0104] Optionally, the data writing module 11 includes a third transistor T3, the gate of the third transistor T3 serves as the control end of the data writing module 11, the first electrode of the third transistor T3 serves as the first end of the data writing module 11, and the second electrode of the third transistor T3 serves as the second end of the data writing module 11.

[0105] Figure 7 is a schematic diagram of another pixel circuit provided by an embodiment of the present invention, referring to Figure 7 Optionally, the pixel circuit further includes a light-emission control module 15. A control end of the light-emission control module 15 is connected to the light-emission control signal line EM. A first end of the light-emission control module 15 is connected to the second end of the driver module 12. A second end of the light-emission control module 15 is connected to a first end of a light-emission module 16. A second end of the light-emission control module 16 is connected to a second power line L2. The light-emission control module 15 is configured to be turned on in response to an active level of the light-emission control signal on the light-emission control signal line EM during a light-emission phase under the control of the light-emission control signal.

[0106] Specifically, light-emitting module 180 includes a light-emitting device. The light-emitting device can be an organic light-emitting device or an inorganic light-emitting device, which is not specifically limited in this embodiment. Exemplarily, the light-emitting device is an OLED device. The first end of light-emitting module 180 can be an anode of the light-emitting device, and the second end of light-emitting module 180 can be a cathode of the light-emitting device.

[0107] The first power line L1 is used to transmit a first power supply voltage VDD, and the second power line L2 is used to transmit a second power supply voltage VSS. The driving module 12, the light control module 15 and the light emitting module 16 are connected between the first power line L1 and the second power line L2. The driving module 12 is used to drive the light emitting module 16 to emit light during the light emitting phase within the display cycle according to the voltage between its control terminal G1 and the first terminal when the light control module 15 is turned on.

[0108] Optionally, the light emitting control module 15 is further configured to be turned off in response to an invalid level of the light emitting control signal during the compensation phase and the data writing phase.

[0109] Optionally, the light control module 15 includes a fourth transistor T4, the gate of the fourth transistor T4 serves as the control end of the light control module 15, the first electrode of the fourth transistor T4 serves as the first end of the light control module 15, and the second electrode of the fourth transistor T4 serves as the second end of the light control module 15.

[0110] Figure 8 is a schematic diagram of another pixel circuit provided by an embodiment of the present invention, referring to Figure 8 Optionally, the pixel circuit further includes a first initialization module 17 , the first initialization module 17 is connected to the first initialization signal line Vref1 , and the first initialization module 17 is used to initialize the first end of the light emitting module 16 during the initialization phase.

[0111] Optionally, the control end of the first initialization module 17 is connected to the third scan line S3 , the first end of the first initialization module 17 is connected to the first initialization signal line Vref1 , and the second end of the first initialization module 17 is connected to the first end of the light emitting module 16 .

[0112] Specifically, in the initialization stage, when the first initialization module 17 responds to the effective level of the third scanning signal on the third scanning line S3 and is turned on, the voltage on the first initialization signal line Vref1 is transmitted to the first end of the light-emitting module 16, initializing the potential of the first end of the light-emitting module 16, which can clear the voltage signal of the previous frame of the light-emitting module 16 and improve the display effect.

[0113] Optionally, the first initialization module 17 includes a fifth transistor T5, the gate of the fifth transistor T5 serves as the control end of the first initialization module 17, the first electrode of the fifth transistor T5 serves as the first end of the first initialization module 17, and the second electrode of the fifth transistor T5 serves as the second end of the first initialization module 17.

[0114] Optional, continue to refer to Figure 8 The pixel circuit further includes a second initialization module 18, which is used to initialize the control end of the driving module 12 during the initialization phase.

[0115] Optionally, the control end of the second initialization module is connected to the third scan line S3, the first end of the second initialization module 18 is connected to the second initialization signal line Vref2, and the second initialization module 18 is used to respond to the effective level of the third scan signal on the third scan line S3 during the initialization phase and turn on.

[0116] Specifically, during the initialization phase, the second initialization module 18 is turned on in response to the signal on the third scan line S3, and the voltage on the second initialization signal line Vref2 is transmitted to the control terminal G1 of the driving module 12 via the turned-on second initialization module 18, so as to initialize the control terminal G1 of the driving module 12. This can clear the voltage of the control terminal G1 of the driving module 12 in the previous frame, so that after the initialization phase is completed, the potential of the control terminal G1 of the driving module 12 is the second initialization voltage.

[0117] In this embodiment, a first initialization module 17 is connected to a first initialization signal line Vref1, and a second initialization module 18 is connected to a second initialization signal line Vref2. The first initialization voltage on the first initialization signal line Vref1 and the second initialization voltage on the second initialization signal line Vref2 can be the same or different. In other embodiments, the first initialization module 17 and the second initialization module 18 can be connected to the same initialization signal line.

[0118] Optionally, the effective level of the third scan signal is the same as the effective level of the second scan signal, and the pulse width duration of the effective level of the third scan signal is equal to the pulse width duration of the effective level of the second scan signal. In some embodiments, the third scan line S3 and the first scan line S1 are connected to the same scan circuit, and accordingly, the third scan line S3 and the second scan line S2 are connected to the same scan circuit. In this embodiment, by connecting the third scan line S3, the second scan line S2, and the first scan line S1 to the same scan circuit, the wiring complexity and border width of the display panel can be reduced.

[0119] Optionally, the initialization phase is performed before the compensation phase. This configuration allows the residual voltage of the previous frame on the control terminal of the driving module 12 to be cleared before the compensation phase, ensuring compensation accuracy and thus improving display uniformity and picture quality.

[0120] Optionally, the second initialization module 18 includes a sixth transistor T6, the gate of the sixth transistor T6 serves as the control end of the second initialization module 18, the first electrode of the sixth transistor T6 serves as the first end of the second initialization module 18, and the second electrode of the sixth transistor T6 serves as the second end of the second initialization module 18.

[0121] Optionally, the start time of the effective level of the first scanning signal is before the end time of the effective level of the third scanning signal, and the end time of the effective level of the first scanning signal is after the end time of the effective level of the third scanning signal. Specifically, since it takes a certain amount of time for the first scanning signal and the third scanning signal to jump to different levels, through the above setting, the jump edge of the first scanning signal from the invalid level of the first scanning signal to the valid level of the first scanning signal can be completed within the time period corresponding to the valid level of the third scanning signal, thereby making it possible for the compensation module 13 to be turned on under the control of the valid level of the first scanning signal after the initialization stage. Compared with the timing of the first scanning signal starting from the invalid level of the first scanning signal to the valid level of the first scanning signal after the valid level of the third scanning signal ends, the threshold voltage compensation time can be extended, thereby ensuring sufficient compensation for the threshold voltage of the driving module 12. Among them, the advance time of the start time of the effective level of the first scanning signal relative to the end time of the effective level of the third scanning signal is adjustable.

[0122] In another embodiment, the effective level of the first scanning signal does not overlap with the effective level of the third scanning signal. By setting the initialization phase and the compensation phase to have no temporal overlap, the initialization phase and the compensation phase can be strictly separated, signal crosstalk can be avoided, and the accuracy of threshold voltage compensation can be ensured.

[0123] Optionally, the active level of the second scanning signal does not overlap with the active levels of the first scanning signal and the third scanning signal. By setting the active levels of the second scanning signal, the first scanning signal, and the third scanning signal to have completely non-overlapping timing, the data writing phase can be ensured to operate independently, avoiding interference with voltage operations in the initialization phase and the compensation phase.

[0124] Figure 9 is a schematic diagram of another pixel circuit provided by an embodiment of the present invention, referring to Figure 9 Optionally, the control end of the first initialization module 17 is connected to the first scan line S1, the first end of the first initialization module 17 is connected to the first initialization signal line Vref1, and the second end of the first initialization module 17 is connected to the first end of the light-emitting module 16; the first initialization module Vref1 is used to respond to the effective level of the first scan signal on the first scan line S1 and turn on during the initialization stage.

[0125] Optionally, the compensation module 13 is further configured to be turned on in response to the effective level of the first scanning signal during the initialization phase; the light-emitting control module 15 is further configured to be turned on in response to the effective level of the light-emitting control signal during the initialization phase, so that the first initialization voltage on the first initialization signal line Vref1 is transmitted to the control terminal G1 of the driving module 12 through the first initialization module 17, the light-emitting control module 15 and the compensation module 13.

[0126] Specifically, in the initialization stage, when the compensation module 13, the first initialization module 17 and the light control module 15 are turned on at the same time, the first initialization module 13 can initialize the potential of the first end of the light emitting module 16 and clear the voltage signal of the previous frame of the light emitting module 105, so that the light emitting module 105 can better display the brightness to be displayed according to the driving current; and the voltage on the first initialization signal line Vref1 can be written to the control end G1 of the driving module 12 via the first initialization module 17, the light control module 15 and the compensation module 13. By using the first initialization module 17 to initialize the driving module 12, there is no need to set a separate initialization module for the control end of the driving module 12, that is, the control end G1 of the driving module 12 does not need to be connected to the initialization module, thereby reducing the path for the control end G1 of the driving module 12 to leak through the initialization module, thereby reducing a leakage path, effectively reducing the leakage current of the driving module 12, and ensuring the stability of the voltage at the control end G1 of the driving module 12, thereby ensuring that the driving module 12 generates a stable driving current, so that the light emitting module 16 can emit light stably, achieving the effect of improving the display uniformity of the display panel.

[0127] Figure 10 is a schematic diagram of another pixel circuit provided by an embodiment of the present invention, referring to Figure 10 The pixel circuit includes: a data writing module 11, a driving module 12, a compensation module 13, a node resetting module 19 and a storage coupling module 14.

[0128] Optionally, the storage coupling module 14 includes a storage unit 141 and a coupling unit 142 , the storage unit 141 includes a first capacitor C1 , and the coupling unit 142 includes a second capacitor C2 .

[0129] Optionally, the storage unit 141 includes a first capacitor C1, and the coupling unit 142 includes a second capacitor C2. Optionally, the node reset module 19 includes a first switch unit 131, and the first switch unit 131 includes a first transistor T1. Optionally, the compensation module 13 includes a second switch unit 132, and the second switch unit 132 includes a second transistor T2.

[0130] Optionally, the data writing module 11 includes a third transistor T3. Optionally, the pixel circuit further includes a light emitting control module 15. Optionally, the light emitting control module 15 includes a fourth transistor T4.

[0131] Optionally, the pixel circuit further includes a first initialization module 17. Optionally, a control terminal of the first initialization module 17 is connected to the third scan line S3, a first terminal of the first initialization module 17 is connected to the first initialization signal line Vref1, and a second terminal of the first initialization module 17 is connected to the first terminal of the light-emitting module 16. Optionally, the first initialization module 17 includes a fifth transistor T5.

[0132] Optionally, the pixel circuit further includes a second initialization module 18. Optionally, the second initialization module 18 includes a sixth transistor T6.

[0133] Optionally, the driving module 12 includes a driving transistor DTFT, the first terminal of the driving module 12 may be a source of the driving transistor DTFT, and the second terminal A2 of the driving module 12 may be a drain of the driving transistor DTFT.

[0134] Figure 11a This is a driving timing waveform diagram of a pixel circuit provided by an embodiment of the present invention. The driving timing can be used for Figure 10 The pixel circuit shown. Figure 10 and Figure 11a The working process of the pixel circuit includes an initialization phase P1, a compensation phase P2, a data writing phase P3 and a light emitting phase P4.

[0135] During initialization phase P1, the light-emission control signal on the light-emission control signal line EM is at a high level, the first scan signal on the first scan line S1 is at a high level, the second scan signal on the second scan line S2 is at a high level, and the third scan signal on the third scan line S3 is at a low level. Therefore, the sixth transistor T6 is turned on in response to the low-level third scan signal, and the second initialization voltage is written to the gate of the drive transistor DTFT via the sixth transistor T6, thereby initializing the gate of the drive transistor DTFT. The fifth transistor T5 is turned on in response to the low-level third scan signal, and the first initialization voltage is written to the first terminal of the light-emitting module 16 via the fifth transistor T5, thereby initializing the first terminal of the light-emitting module 16.

[0136] During compensation phase P2, the light-emission control signal on the light-emission control signal line EM is at a high level, the first scan signal on the first scan line S1 is at a low level, the second scan signal on the second scan line S2 is at a high level, and the third scan signal on the third scan line S3 is at a high level. Consequently, the first transistor T1 and the second transistor T2 are turned on in response to the low-level first scan signal. The first power supply voltage VDD on the first power line L1 is charged to the first node N1 via the first transistor T1, thereby stabilizing the potential of the first node N1. Simultaneously, the first power supply voltage VDD is written to the gate of the driving transistor DTFT via the second transistor DTFT and T2. When the gate voltage of the driving transistor DTFT reaches VDD + Vth, the driving transistor DTFT is turned off, and compensation phase P2 ends. Vth is the threshold voltage of the driving transistor DTFT.

[0137] During the data writing phase P3, the light-emitting control signal on the light-emitting control signal line EM is at a high level, the first scan signal on the first scan line S1 is at a high level, the second scan signal on the second scan line S2 is at a low level, and the third scan signal on the third scan line S3 is at a high level. Therefore, the third transistor T3 is turned on, and the data voltage Vdata is written to the first node N1 via the third transistor T3. The potential of the first node N1 jumps from the first power supply voltage VDD to the data voltage Vdata. Under the coupling effect of the second capacitor C2, the gate potential of the driving transistor DTFT (i.e., the potential at point G1) becomes VDD + Vth + Vdata - VDD = Vdata + Vth, thereby writing the data voltage Vdata to the gate of the driving transistor DTFT.

[0138] In the light-emitting phase P4, the light-emitting control signal on the light-emitting control signal line EM is at a low level, the first scan signal on the first scan line S1 is at a high level, the second scan signal on the second scan line S2 is at a high level, and the third scan signal on the third scan line S3 is at a high level. Therefore, the fourth transistor T4 is turned on, and the driving transistor DTFT generates a driving current I based on the voltage at the point G1 and the voltage at its first electrode, thereby driving the light-emitting module 16 to emit light.

[0139] By separating the threshold compensation from the data writing time, the compensation stage P2 and the data writing stage P3 do not affect each other, so that the threshold compensation time is not affected by the data writing stage. Even at a high refresh rate, the threshold voltage of the driving transistor DTFT can be fully compensated, which is beneficial to improving the difference in display brightness and improving the uniformity of display quality.

[0140] Figure 11b This is another driving timing waveform diagram of a pixel circuit provided by an embodiment of the present invention. The driving timing waveform can be used for Figure 10 The pixel circuit shown. Figure 11b In one frame, the working process of the pixel circuit includes at least two groups of non-luminous stages performed successively, each group of non-luminous stages includes an initialization stage P1, a compensation stage P2 and a data writing stage P3; the setting of the two groups of non-luminous stages enables the initialization stage P1, the compensation stage P2 and the data writing stage P3 to be executed at a higher frequency within one frame.

[0141] In one frame, the time interval between the first active level of the third scan signal and the second active level of the third scan signal is greater than the time interval between the first active level of the first scan signal and the second active level of the first scan signal, and greater than the time interval between the first active level of the second scan signal and the second active level of the second scan signal. That is, the time interval between the active level of the third scan signal corresponding to the initialization phase in the first group of non-luminous phases and the active level of the third scan signal corresponding to the initialization phase in the second group of non-luminous phases is greater than the time interval between the active level of the first scan signal corresponding to the compensation phase in the first group of non-luminous phases and the active level of the first scan signal corresponding to the compensation phase in the second group of non-luminous phases; and greater than the time interval between the active level of the second scan signal corresponding to the data writing phase in the first group of non-luminous phases and the active level of the second scan signal corresponding to the data writing phase in the second group of non-luminous phases. This helps ensure sufficient initialization of the control terminal of the driver module, thereby improving display quality.

[0142] Optionally, within a frame, the time interval between the first valid level of the first scanning signal and the first valid level of the third scanning signal is greater than the time interval between the first valid level of the second scanning signal and the first valid level of the first scanning signal.

[0143] The third scan signal controls the first and second initialization modules 17 and 18 to clear any residual voltage at the driver module control terminal G1 and the light-emitting module 16. Extending the interval between the active levels of the first and third scan signals ensures sufficient time for the circuit node potentials to stabilize to the initialization voltage during the initialization phase P1. If this interval is too short, the compensation module 13 may be activated before initialization is complete, causing the initialization voltage to overlap with the first power supply voltage VDD during the compensation phase P2, affecting the accuracy of the potential at the driver module control terminal G1.

[0144] Optionally, within a frame, in the kth non-luminous stage, the time interval between the effective level of the first scanning signal and the effective level of the third scanning signal is equal to the time interval between the effective level of the second scanning signal and the effective level of the first scanning signal, where k is a positive integer greater than or equal to 2.

[0145] Optionally, the third scan line and the first scan line are connected to different scan circuits; the effective level of the first scan signal and the effective level of the third scan signal do not overlap. This configuration avoids timing drift caused by signal transmission delay within the same scan circuit. Especially in high-resolution display panels, different groups of scan circuits can process timing control for different rows of pixels in parallel, improving overall scanning efficiency.

[0146] Figure 12 is a schematic diagram of another pixel circuit provided by an embodiment of the present invention, referring to Figure 12 The pixel circuit includes: a data writing module 11, a driving module 12, a compensation module 13, a node resetting module 19 and a storage coupling module 14.

[0147] Optionally, the storage coupling module 14 includes a storage unit 141 and a coupling unit 142 , the storage unit 141 includes a first capacitor C1 , and the coupling unit 142 includes a second capacitor C2 .

[0148] Optionally, the storage unit 141 includes a first capacitor C1, and the coupling unit 142 includes a second capacitor C2. Optionally, the first switch unit 131 includes a first transistor T1, and optionally, the second switch unit 132 includes a second transistor T2.

[0149] Optionally, the data writing module 11 includes a third transistor T3. Optionally, the pixel circuit further includes a light emitting control module 15. Optionally, the light emitting control module 15 includes a fourth transistor T4.

[0150] Optionally, the pixel circuit further includes a first initialization module 17. Optionally, a control terminal of the first initialization module 17 is connected to the first scan line S1, a first terminal of the first initialization module 17 is connected to the first initialization signal line Vref1, and a second terminal of the first initialization module 17 is connected to the first terminal of the light-emitting module 16. Optionally, the first initialization module 17 includes a fifth transistor T5.

[0151] Optionally, the driving module 12 includes a driving transistor DTFT, the first terminal of the driving module 12 may be a source of the driving transistor DTFT, and the second terminal A2 of the driving module 12 may be a drain of the driving transistor DTFT.

[0152] The light emitting module 16 includes a light emitting diode D1 , wherein the anode of the light emitting diode D1 serves as a first end of the light emitting module 16 , and the cathode of the light emitting module 16 serves as a second end of the light emitting diode D1 .

[0153] Figure 13 This is another driving timing waveform diagram of a pixel circuit provided by an embodiment of the present invention. The driving timing waveform can be used for Figure 12 The pixel circuit shown. Figure 12 and Figure 13 The working process of the pixel circuit includes an initialization phase P1, a compensation phase P2, a data writing phase P3 and a light emitting phase P4.

[0154] During initialization phase P1, the light-emission control signal on the light-emission control signal line EM is at a low level, the first scan signal on the first scan line S1 is at a low level, and the second scan signal on the second scan line S2 is at a high level. Consequently, the first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on in response to the low-level first scan signal, and the fourth transistor T4 is turned on in response to the light-emission control signal. The first initialization voltage is written to the gate of the drive transistor DTFT via the fifth transistor T5, the fourth transistor T4, and the second transistor T2, thereby initializing the gate of the drive transistor DTFT. Simultaneously, the first power supply voltage VDD is written to the first node N1 via the first transistor T1. Simultaneously, the first initialization voltage is written to the first terminal of the light-emitting module 16 via the fifth transistor T5, thereby initializing the first terminal of the light-emitting module 16.

[0155] During compensation phase P2, the light-emission control signal on the light-emission control signal line EM is at a high level, the first scan signal on the first scan line S1 is at a low level, and the second scan signal on the second scan line S2 is at a high level. Therefore, in response to the low-level first scan signal, the first transistor T1 and the second transistor T2 are turned on. The first power supply voltage VDD on the first power line L1 is charged to the first node N1 via the first transistor T1, thereby stabilizing the potential of the first node N1. Simultaneously, the first power supply voltage VDD is written to the gate of the driving transistor DTFT via the driving transistor DTFT and the second transistor T2. When the gate voltage of the driving transistor DTFT reaches VDD + Vth, the driving transistor DTFT is turned off, and compensation phase P2 ends. Here, Vth is the threshold voltage of the driving transistor DTFT. Since the data voltage Vdata is not written to the gate of the driving transistor DTFT, the threshold compensation process of the driving transistor DTFT is not affected by the data write time. This allows point G1 to be fully written to VDD + Vth, ensuring that the threshold voltage of the driving transistor DTFT is fully compensated.

[0156] During the data writing phase P3, the light-emitting control signal on the light-emitting control signal line EM is at a high level, the first scan signal on the first scan line S1 is at a high level, and the second scan signal on the second scan line S2 is at a low level. Therefore, the third transistor T3 is turned on, and the data voltage Vdata is written to the first node N1 via the third transistor T3. The potential of the first node N1 jumps from the first power supply voltage VDD to the data voltage Vdata. Under the coupling effect of the second capacitor C2, the gate potential of the drive transistor DTFT (i.e., the potential at point G1) becomes VDD + Vth + (Vdata - VDD), thereby writing the data voltage Vdata to the gate of the drive transistor DTFT.

[0157] In the light-emitting phase P4, the light-emitting control signal on the light-emitting control signal line EM is at a low level, the first scan signal on the first scan line S1 is at a high level, the second scan signal on the second scan line S2 is at a high level, and the third scan signal on the third scan line S3 is at a high level. Therefore, the fourth transistor T4 is turned on, and the driving transistor DTFT generates a driving current based on the voltage at the point G1 and the voltage at its first electrode, thereby driving the light-emitting module 16 to emit light.

[0158] Based on the same inventive concept, an embodiment of the present invention further provides an array substrate, comprising a plurality of pixel circuits provided by any embodiment of the present invention. Figure 14 FIG. 1 is a structural diagram of an array substrate provided by an embodiment of the present invention. Figure 14 As shown, a plurality of pixel circuits 20 are arranged in an array.

[0159] The display panel further includes a first scanning circuit 100 , which includes a multi-stage cascaded first shift register 10 ; the data writing module and the compensation module in the same pixel circuit 20 are connected to the output ends of different stages of the first shift register of the first scanning circuit 100 .

[0160] Specifically, the pixel circuit 20 is disposed in the display area AA of the display panel, and the scanning circuit 100 is disposed in the non-display area NAA of the display panel.

[0161] The output terminals of the first shift registers 10 at different stages can be connected to the same row of pixel circuits 20. For example, Figure 14 , the scan signal output by the j-th stage first shift register 10 can be set as the first scan signal S11 required by the j-th row pixel circuit 20, and as the second scan signal S21 required by the j-th row pixel circuit 20. j is an integer greater than or equal to (i+1), and i is an integer greater than or equal to 1.

[0162] It should be noted that Figure 14Schematically shows that the j-th stage first shift register 10 transmits the first scanning signal S11 to the j-th row pixel circuit 20 through the first scanning signal line L1, and transmits the second scanning signal S21 to the j-th row pixel circuit 20 through the second scanning signal line L2.

[0163] In some other embodiments, the first scanning signal line L1 connected to the (j+i)th stage first shift register 10 serves as the second scanning signal line L2 connected to the jth stage first shift register.

[0164] Optionally, the pixel circuit further includes a first initialization module. Optionally, the effective levels of the scanning signals output by two adjacent stages of the first shift registers partially overlap or do not overlap, and in the same pixel circuit, the shift register connected to the compensation module is a subsequent stage of the first shift register connected to the first initialization module.

[0165] Specifically, the initialization phase and the compensation phase follow each other in timing (the output signal of the subsequent shift register immediately follows the output signal of the previous stage), ensuring that the compensation phase begins immediately after initialization is completed, avoiding any timing gaps in between. For example, the first initialization module is controlled by the first shift register of stage i, and the compensation module is controlled by stage i+1. After the jth stage signal ends, the i+1th stage signal takes effect immediately. This allows the compensation module to promptly compensate for the threshold voltage of the driver module after the initialization operations of the light-emitting module and the driver module are completed, reducing overall row time waste and improving the operating efficiency of the pixel circuit.

[0166] Optionally, the effective levels of the scanning signals output by two adjacent first shift registers partially overlap, and the first shift register connected to the data writing module is the last T stages of the shift register connected to the compensation module, where T is greater than or equal to 2.

[0167] Specifically, when the effective levels of the scan signals output by two adjacent first shift registers partially overlap, the setting of T≥2 ensures that the control signals of the data writing module and the compensation module are separated in time by at least two output cycles of the first shift registers, ensuring that the compensation phase and the data writing phase are sufficiently separated in time, and avoiding phase overlap interference caused by excessively fast switching of signals between adjacent stages. For example, when the compensation module is controlled by the kth first shift register, and the data writing module is controlled by the i+2th and subsequent first shift registers, the intermediate i+1th signal cycle can serve as a timing buffer, preventing the operations of the two stages from overlapping in time and ensuring the independent execution of threshold voltage compensation and data writing.

[0168] Optionally, the effective levels of the scanning signals output by two adjacent first shift registers do not overlap, and the first shift register connected to the data writing module is the next n stages of the first shift register connected to the compensation module, where n is greater than or equal to 1.

[0169] Specifically, when the effective levels of the scan signals of the adjacent first shift registers do not overlap, the compensation phase and the data writing phase can be ensured to be completely independent in time. When the shift register connected to the data writing module is the last n stages (n≥1) of the compensation module, the control signals of the two stages form a clear time interval in terms of timing (for example, when n=1, the compensation module is controlled by the i-th stage, and the data writing module is controlled by the i+1-th stage, and the two-stage signals do not overlap), avoiding the superposition interference of the first power supply voltage and the data voltage at the first node, ensuring the accuracy of the threshold voltage compensation and the reliability of data writing. For example, after the compensation phase ends, the scan signal of the previous stage is completely invalid, and the signal of the next stage triggers the data writing, effectively avoiding the conflict of stage operations caused by signal overlap.

[0170] Specifically, refer to Figure 10 and Figure 11a The scan signal output by the first shift register 10 at the i-th stage can be set as the third scan signal required by the first initialization module 17 in the i-th row of pixel circuits 20, the scan signal output by the first shift register 10 at the i+1-th stage can be set as the first scan signal required by the compensation module 13 in the i-th row of pixel circuits 20, and the scan signal output by the first shift register 10 at the i+3-th stage can be set as the second scan signal required by the data writing module 11 in the i-th row of pixel circuits 20. The signals at each stage are non-overlapping, preventing interference between the first initialization voltage, the first power supply voltage in the compensation phase, and the data voltage in the data writing phase in the circuit. This ensures the stability of the initialization potential of the light-emitting module 16 and prevents the threshold compensation or data writing process of the driver module 12 from being affected by the initialization operation, thereby improving the reliability of each stage.

[0171] In some embodiments, the effective levels of the scanning signals output by two adjacent first shift registers do not overlap, and within one frame, the scanning signal output by the first shift register includes at least two effective levels; the array substrate also includes a second scanning circuit, the second scanning circuit includes a multi-stage cascaded second shift register, and the first initialization module is connected to the output end of the second shift register; within one frame, the output end of the second shift register outputs at least two effective levels; within one frame, the time interval between the first effective level and the second effective level output by the second shift register is greater than the time interval between the first effective level and the second effective level output by the first shift register.

[0172] refer to Figure 12 and Figure 13When the first initialization module 17 is connected to the output end of the second shift register, the interval between two valid levels output by the second shift register is longer, ensuring that there is sufficient time to clear the residual voltage at the control end of the driving module 12 and the first end of the light-emitting module 16 during the initialization phase, thereby preventing the residual voltage from affecting the accuracy of subsequent compensation and data writing.

[0173] An embodiment of the present invention further provides a display panel, comprising the array substrate provided by any embodiment of the present invention, and having the same functional modules and beneficial effects as the array substrate, which will not be described in detail in this embodiment.

[0174] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A pixel circuit, characterized in that: include: Data writing module, driving module, compensation module, node reset module and storage coupling module; The node reset module is connected to the first node together with the data writing module and the storage coupling module. The node reset module is also connected to the first end of the driving module and the first power line, and is configured to charge the first node according to the first power supply voltage on the first power line during a compensation phase under the control of the first scan signal on the first scan line; The compensation module is connected between the control terminal of the driving module and the second terminal of the driving module, and is used to write voltage information related to the threshold voltage of the driving module to the control terminal of the driving module according to the first power supply voltage; The data writing module is used to transmit a data voltage to the first node during a data writing phase under the control of a second scanning signal on a second scanning line; The storage coupling module is connected to the control terminal of the driving module and is used to couple the voltage change of the first node to the control terminal of the driving module during the data writing phase; The driving module is used to output a driving current according to the voltage of the control terminal of the driving module during the light-emitting stage.

2. The pixel circuit according to claim 1, wherein: The storage coupling module includes a storage unit and a coupling unit, wherein a first end of the storage unit is connected to the first power line, a second end of the storage unit and the first end of the coupling unit are connected to the first node, and a second end of the coupling unit is electrically connected to the control end of the driving module; Preferably, the storage unit includes a first capacitor; the coupling unit includes a second capacitor; The first end of the first capacitor serves as the first end of the storage unit, and the second end of the first capacitor serves as the second end of the storage unit; The first end of the second capacitor serves as the first end of the coupling unit, and the second end of the second capacitor serves as the second end of the coupling unit; Preferably, the pulse width of the effective level of the first scanning signal on the first scanning line is greater than or equal to 1 divided by a set value, and the set value is equal to the product of the number of rows of the pixel circuit included in the display panel where the pixel circuit is located and the refresh frequency.

3. The pixel circuit according to claim 1, wherein: The node reset module includes a first switch unit, wherein a first end of the first switch unit is connected to the first node, a second end of the first switch unit is connected to the first end of the driving module and the first power line, and a control end of the first switch unit is connected to the first scan line. The first switch unit is configured to be turned on in response to an active level of a first scan signal on the first scan line during the compensation phase, and transmit the first power supply voltage to the first node; and in the data writing phase, shutting down in response to the invalid level of the first scanning signal of the first scanning line; The compensation module includes a second switch unit, wherein a first end of the second switch unit is connected to a second end of the driving module, a second end of the second switch unit is connected to a control end of the driving module, and the control end of the second switch unit is connected to the first scan line. The second switch unit is configured to be turned on in response to an effective level of the first scan signal during a compensation phase, and to write voltage information related to a threshold voltage of the driving module to the control end of the driving module according to the first power supply voltage; and for shutting down in response to an invalid level of the first scanning signal during the data writing phase; Preferably, the first switch unit includes a first transistor, the gate of the first transistor serves as the control terminal of the first switch unit, the first electrode of the first transistor serves as the first terminal of the first switch unit, and the second electrode of the first transistor serves as the second terminal of the first switch unit; Preferably, the second switching unit includes a second transistor, the gate of the second transistor serves as the control end of the second switching unit, the first electrode of the second transistor serves as the first end of the second switching unit, and the second electrode of the second transistor serves as the second end of the second switching unit.

4. The pixel circuit according to any one of claims 1 to 3, wherein: The control end of the data writing module is connected to the second scan line, the first end of the data writing module is connected to the data line, and the second end of the data writing module is connected to the first node. The data writing module is configured to be turned on in response to an effective level of a second scan signal on the second scan line during a data writing phase; Preferably, the data writing module is further configured to be turned off in response to an invalid level of the second scanning signal on the second scanning line during the compensation phase and the light emitting phase; Preferably, the effective level of the second scanning signal does not overlap with the effective level of the first scanning signal on the first scanning line; Preferably, the effective level of the second scanning signal is the same as the effective level of the first scanning signal, and the pulse width duration of the effective level of the second scanning signal is equal to the pulse width duration of the effective level of the first scanning signal; Preferably, the compensation phase is performed before the data writing phase; Preferably, the data writing module includes a third transistor, the gate of the third transistor serves as the control terminal of the data writing module, the first electrode of the third transistor serves as the first terminal of the data writing module, and the second electrode of the third transistor serves as the second terminal of the data writing module; Preferably, the pixel circuit further comprises a light-emitting control module, wherein a control end of the light-emitting control module is connected to a light-emitting control signal line, a first end of the light-emitting control module is connected to a second end of the driving module, a second end of the light-emitting control module is used to be connected to a first end of the light-emitting module, and a second end of the light-emitting control module is connected to a second power line; the light-emitting control module is configured to be turned on in response to an effective level of the light-emitting control signal during the light-emitting phase under the control of a light-emitting control signal on the light-emitting control signal line; Preferably, the light emitting control module is further configured to shut down in response to an invalid level of the light emitting control signal during the compensation phase and the data writing phase; Preferably, the light emitting control module includes a fourth transistor, the gate of the fourth transistor serves as the control terminal of the light emitting control module, the first electrode of the fourth transistor serves as the first terminal of the light emitting control module, and the second electrode of the fourth transistor serves as the second terminal of the light emitting control module; Preferably, the pixel circuit further includes a first initialization module, the first initialization module is connected to a first initialization signal line, and the first initialization module is used to initialize the first end of the light emitting module during an initialization phase; Preferably, the first initialization module includes a fifth transistor, the gate of the fifth transistor serves as the control end of the first initialization module, the first electrode of the fifth transistor serves as the first end of the first initialization module, and the second electrode of the fifth transistor serves as the second end of the first initialization module.

5. The pixel circuit according to claim 4, wherein: It also includes a second initialization module, wherein the second initialization module is used to initialize the control end of the driving module during the initialization phase; Preferably, the control end of the second initialization module is connected to the third scan line, the first end of the second initialization module is connected to the second initialization signal line, and the second initialization module is configured to be turned on in response to the effective level of the third scan signal on the third scan line during the initialization phase; Preferably, the effective level of the third scanning signal is the same as the effective level of the second scanning signal, and the pulse width duration of the effective level of the third scanning signal is equal to the pulse width duration of the effective level of the second scanning signal; Preferably, the initialization phase is performed before the compensation phase; Preferably, the control end of the first initialization module is connected to the third scan line, the first end of the first initialization module is connected to the first initialization signal line, and the second end of the first initialization module is connected to the first end of the light emitting module; Preferably, the second initialization module includes a sixth transistor, the gate of the sixth transistor serves as the control end of the second initialization module, the first electrode of the sixth transistor serves as the first end of the second initialization module, and the second electrode of the sixth transistor serves as the second end of the second initialization module.

6. The pixel circuit according to claim 5, wherein: The start time of the effective level of the first scanning signal is before the end time of the effective level of the third scanning signal, and the end time of the effective level of the first scanning signal is after the end time of the effective level of the third scanning signal; Alternatively, the effective level of the first scanning signal does not overlap with the effective level of the third scanning signal; Preferably, the effective level of the second scanning signal does not overlap with the effective level of the first scanning signal and the effective level of the third scanning signal.

7. The pixel circuit according to claim 5, wherein: The effective level of the first scanning signal does not overlap with the effective level of the third scanning signal; Preferably, within one frame, the working process of the pixel circuit includes at least two groups of non-luminous phases performed successively, and each group of the non-luminous phases includes the initialization phase, the compensation phase, and the data writing phase; Wherein, within one frame, a time interval between a first valid level of the third scanning signal and a second valid level of the third scanning signal is greater than a time interval between a first valid level of the first scanning signal and a second valid level of the first scanning signal, and greater than a time interval between a first valid level of the second scanning signal and a second valid level of the second scanning signal; Preferably, within one frame, a time interval between a first valid level of the first scanning signal and a first valid level of the third scanning signal is greater than a time interval between a first valid level of the second scanning signal and a first valid level of the first scanning signal; Preferably, within a frame, in the kth non-luminous stage, the time interval between the effective level of the first scanning signal and the effective level of the third scanning signal is equal to the time interval between the effective level of the second scanning signal and the effective level of the first scanning signal, where k is a positive integer greater than or equal to 2.

8. The pixel circuit according to claim 4, wherein: The control end of the first initialization module is connected to the first scan line, the first end of the first initialization module is connected to the first initialization signal line, and the second end of the first initialization module is connected to the first end of the light-emitting module; the first initialization module is configured to be turned on in response to an effective level of the first scan signal on the first scan line during the initialization phase; Preferably, the compensation module is also used to turn on in response to the effective level of the first scanning signal during the initialization stage; the light-emitting control module is also used to turn on in response to the effective level of the light-emitting control signal during the initialization stage, so that the first initialization voltage on the first initialization signal line is transmitted to the control end of the driving module through the first initialization module, the light-emitting control module and the compensation module.

9. An array substrate, characterized in that: Comprising a plurality of pixel circuits according to any one of claims 1 to 8; preferably, the plurality of pixel circuits are arranged in an array; The display panel further includes a first scanning circuit, which includes a multi-stage cascaded first shift register; the data writing module and the compensation module in the same pixel circuit are connected to output ends of the first shift registers at different stages of the first scanning circuit; Preferably, the effective levels of the scanning signals output by two adjacent stages of the first shift register partially overlap, the first shift register to which the data writing module is connected is the next T stages of the first shift register to which the compensation module is connected, and T is greater than or equal to 2; Preferably, the effective levels of the scanning signals output by two adjacent stages of the first shift register do not overlap, and the first shift register to which the data writing module is connected is the next n stages of the first shift register to which the compensation module is connected, where n is greater than or equal to 1; Preferably, the pixel circuit further includes a first initialization module; Preferably, effective levels of scanning signals output by two adjacent stages of the first shift registers partially overlap or do not overlap, and in the same pixel circuit, the first shift register connected to the compensation module is a subsequent stage of the first shift register connected to the first initialization module; Alternatively, the effective levels of the scanning signals output by two adjacent stages of the first shift register do not overlap, and within one frame, the scanning signals output by the first shift register include at least two effective levels; the array substrate further includes a second scanning circuit, the second scanning circuit includes a multi-stage cascaded second shift register, the first initialization module is connected to the output end of the second shift register; within one frame, the output end of the second shift register outputs at least two effective levels; In one frame, a time interval between a first valid level and a second valid level output by the second shift register is greater than a time interval between a first valid level and a second valid level output by the first shift register.

10. A display panel, characterized in that: Including the array substrate according to claim 9.

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