Driving circuit of display panel and display device

Abstract

The invention provides a driving circuit of a display panel and a display device.The driving circuit of the display panel comprises a gate driving circuit and a compensation circuit, the compensation circuit comprises an OR gate circuit, an inverter circuit and a digital-to-analog conversion circuit, the OR gate circuit performs OR operation on signals on multiple gate connecting lines, so that corresponding level signals are output, and the digital-to-analog conversion circuit performs digital-to-analog conversion on the gate connecting lines. The inverting circuit and the digital-to-analog conversion circuit are used for performing inverting and digital-to-analog conversion on the level signal in sequence, so that a corresponding row opening signal and a row closing signal are output to a scanning line connected with an abnormal grid connecting line, and signal compensation is realized; according to the invention, one or more abnormal gate connecting lines or gate driving units can be determined, and through the arrangement of the phase inverting circuit and the digital-to-analog conversion circuit, signals on the abnormal gate connecting lines can be directly converted into compensation signals and supplied to the corresponding scanning lines, so that signal compensation is realized, dark lines or weak lines are avoided, and the reliability of the system is improved. The display effect is improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of display panel, and particularly relates to a driving circuit of a display panel and a display device. BACKGROUND

[0002] The driving circuit of the display panel usually comprises a gate driving circuit, the gate driving circuit comprises a plurality of cascaded gate driving units and is connected with scan lines of the display panel, and when driving the scan, the cascaded gate driving units output row scan signals line by line to perform line-by-line scanning on the display panel.

[0003] Among them, the gate driving unit is connected with the scan line of the display panel through a gate connection line, and due to process reasons, the connection line between the gate driving unit and the scan line of the display panel may form an open circuit, poor contact and the like, resulting in display defects such as bright spots, dark spots and flashing points of the display panel. Among them, the gate driving unit related defect accounts for a high proportion, and the short circuit of the gate connection line will cause the thin film transistor of the pixel unit of the current line to be unable to normally open, resulting in dark lines or weak lines of the display panel. Due to abnormal display of the display panel, if it cannot be repaired, it will cause not small economic loss. SUMMARY

[0004] The purpose of the present application is to provide a driving circuit of a display panel, aiming at solving the problem that the traditional gate driving unit appears connection line related defects, resulting in dark lines or weak lines of the display picture.

[0005] The first aspect of the embodiment of the present application proposes a driving circuit of a display panel, comprising:

[0006] A gate driving circuit comprises a plurality of sequentially connected gate driving units, and a plurality of gate connection lines are connected with a plurality of scan lines of the display panel, and a plurality of gate driving units are used for outputting row scan signals line by line.

[0007] A compensation circuit comprises:

[0008] An OR gate circuit is connected with a plurality of gate connection lines respectively, and the OR gate circuit is used for performing OR operation on signals on a plurality of gate connection lines and sequentially outputting a plurality of level signals, and the plurality of level signals comprise high level signals and / or low level signals.

[0009] An inverting circuit is connected with the OR gate circuit and is used for sequentially inverting a plurality of level signals and sequentially outputting the inverted level signals.

[0010] Analog-digital conversion circuit, connected with the inverting circuit and the target scan line, for analog-digital conversion of the high-level signal after inversion and conversion into the row opening signal, or analog-digital conversion of the low-level signal after inversion into the row closing signal, and corresponding output of the row opening signal or the row closing signal to the target scan line, which is a scan line connected with the disconnected gate connection line or a scan line connected with the abnormal gate drive unit.

[0011] Optionally, the OR gate circuit comprises a plurality of first diodes.

[0012] The anode of each first diode is connected with a gate connection line, and the cathodes of the plurality of first diodes are connected to constitute the output end of the OR gate circuit.

[0013] Optionally, the OR gate circuit comprises a plurality of thin film transistors.

[0014] The drain and gate of each thin film transistor are connected with a gate connection line, and the sources of the plurality of thin film transistors are connected to constitute the output end of the OR gate circuit.

[0015] Optionally, the inverting circuit comprises a first resistor, a transistor and a second diode.

[0016] The first end of the first resistor is connected with a positive voltage end, the second end of the first resistor, the collector of the transistor and the anode of the second diode are connected, the cathode of the second diode constitutes the output end of the inverting circuit, the base of the transistor constitutes the input end of the inverting circuit, and the emitter of the transistor is grounded.

[0017] Optionally, the compensation circuit further comprises:

[0018] A voltage dividing circuit connected with the output end of the OR gate circuit and a first reference voltage end, for proportional voltage division of the voltage difference between the output signal of the OR gate circuit and the first reference voltage of the first reference voltage end, and output of the voltage signal after voltage division to the inverting circuit, the first reference voltage being smaller than the voltage of the row opening signal and greater than the voltage of the row closing signal.

[0019] Optionally, the voltage dividing circuit comprises a second resistor, a third resistor and a capacitor.

[0020] The first end of the second resistor and the first end of the capacitor are connected to constitute the input end of the voltage dividing circuit, the second end of the second resistor, the second end of the capacitor and the first end of the third resistor are connected to constitute the output end of the voltage dividing circuit, and the second end of the third resistor is connected with the reference voltage end.

[0021] Optionally, the analog-digital conversion circuit comprises:

[0022] a comparator, a positive input terminal of the comparator constituting an input terminal of the digital-to-analog conversion circuit, an inverting input terminal of the comparator being used for inputting a second reference voltage, a positive power supply terminal of the comparator being used for inputting the row-on signal, a negative power supply terminal of the comparator being used for inputting the row-off signal, and an output terminal of the comparator constituting an output terminal of the digital-to-analog conversion circuit, the second reference voltage being less than a voltage of the row-on signal;

[0023] a first repair line connected with the output terminal of the comparator and a first terminal of the target scan line.

[0024] Optionally, the digital-to-analog conversion circuit further comprises:

[0025] a second repair line connected with the output terminal of the comparator and a second terminal of the target scan line.

[0026] Optionally, the compensation circuit further comprises:

[0027] a plurality of switches, the digital-to-analog conversion circuit being connected to a plurality of the scan lines through the plurality of switches, the switches being triggered to be turned on by a first switch signal and triggered to be turned off by a second switch signal.

[0028] a switch control circuit connected with the OR gate circuit and the plurality of switches respectively, the switch control circuit being used for:

[0029] dividing each frame scanning time into a plurality of unit time periods, each unit time period corresponding to an output time period of the row-on signal, and detecting the output signal of the OR gate circuit in each unit time period when receiving a frame start signal;

[0030] outputting a plurality of the second switch signals to the plurality of switches when detecting a high-level signal in the i-th unit time period.

[0031] outputting one of the first switch signals to the switch corresponding to the i-th gate drive unit and outputting a plurality of the second switch signals to other switches continuously in the unit time period when detecting a low-level signal in the i-th unit time period.

[0032] A second aspect of the embodiment of the present application provides a display device, comprising a display panel and a driving circuit of the display panel as described above, the driving circuit of the display panel being connected with the display panel.

[0033] The beneficial effects of the embodiment of the present application compared with the prior art are: the driving circuit of the display panel comprises a gate driving circuit and a compensation circuit, the compensation circuit comprises an OR gate circuit, an inverting circuit and a digital-to-analog conversion circuit, the gate driving circuit comprises a plurality of gate driving units connected in sequence, the gate driving units are connected with the scan lines of the display panel through gate connection lines, the OR gate circuit performs OR operation on the signals on the plurality of gate connection lines, thereby outputting corresponding level signals, the inverting circuit and the digital-to-analog conversion circuit sequentially invert and digitally-to-analog convert the level signals, thereby outputting corresponding row opening signals and row closing signals to the scan lines connected with the abnormal gate connection lines, signal compensation is realized, through OR operation, the plurality of gate connection lines and the corresponding gate driving units can be operated synchronously, thereby determining one or more abnormal gate connection lines or gate driving units, and through the setting of the inverting circuit and the digital-to-analog conversion circuit, the signals on the abnormal gate connection lines can be directly converted into compensation signals and provided to the corresponding scan lines, signal compensation is realized, thereby avoiding the appearance of dark lines or weak lines and improving the display effect. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 The first structure schematic diagram of the display panel and the driving circuit of the display panel provided for the embodiment of the present application is provided.

[0035] Figure 2 The second structure schematic diagram of the display panel and the driving circuit of the display panel provided for the embodiment of the present application is provided.

[0036] Figure 3 The waveform timing diagram of the row scan signal provided for the embodiment of the present application is provided.

[0037] Figure 4 The signal schematic diagram of the gate connection line provided for the embodiment of the present application is provided.

[0038] Figure 5 The output signal schematic diagram of the OR gate circuit provided for the embodiment of the present application is provided.

[0039] Figure 6 The first circuit schematic diagram of the OR gate circuit provided for the embodiment of the present application is provided.

[0040] Figure 7 The second circuit schematic diagram of the OR gate circuit provided for the embodiment of the present application is provided.

[0041] Figure 8 The circuit schematic diagram of the inverting circuit provided for the embodiment of the present application is provided.

[0042] Figure 9 The structure schematic diagram of the compensation circuit provided for the embodiment of the present application is provided.

[0043] Figure 10 A circuit schematic diagram of the voltage dividing circuit and the inverting circuit provided for the first embodiment of the present application is shown in Figure 1.

[0044] Figure 11 A circuit schematic diagram of the digital-to-analog conversion circuit provided for the first embodiment of the present application is shown in Figure 2.

[0045] Figure 12 A third structural schematic diagram of the display panel and the driving circuit of the display panel provided for the first embodiment of the present application is shown in Figure 3.

[0046] Figure 13 A structural schematic diagram of the display panel and the driving circuit of the display panel provided for the second embodiment of the present application is shown in Figure 4.

[0047] Figure 14 A structural schematic diagram of the display device provided for the third embodiment of the present application is shown in Figure 5.

[0048] In the drawings, various reference numerals are used throughout the drawings. As used in the description of the drawings, the following numbers represent the following elements:

[0049] 1, flexible circuit board; 2, chip on film; 100, display panel; 200, driving circuit of the display panel; 210, gate driving circuit; 220, compensation circuit; 211, gate driving unit; 221, or gate circuit; 222, inverting circuit; 223, digital-to-analog conversion circuit; 224, voltage dividing circuit; 225, switch control circuit;

[0050] L1, gate connection line; L2, first repair line; L3, second repair line; D1, first diode; D11, second diode; R1, first resistor; R2, second resistor; R3, third resistor; C1, capacitor; K1, triode; T1, thin film transistor; Q1, switch; U1, comparator;

[0051] Vgh, row on signal; Vgl, row off signal; Vout1, output signal of the or gate circuit; Vout2, output signal of the inverting circuit; Vout3, output signal of the digital-to-analog conversion circuit; Vref1, first reference voltage; Vref2, second reference voltage. DETAILED DESCRIPTION

[0052] In order to make the technical problems to be solved by the present application, the technical solutions and the beneficial effects more clearly understood, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0053] The terms "first", "second", "third", etc. are used only for descriptive purposes and do not denote or imply relative importance or a number of the technical features indicated. Thus, the features defined with "first", "second", etc. can include one or more of the features explicitly or implicitly. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly and specifically limited.

[0054] Embodiment one

[0055] The first aspect of the embodiment of the present application proposes a driving circuit 200 of a display panel, as shown in Figure 1 and Figure 2 comprising:

[0056] a gate driving circuit 210, comprising a plurality of sequentially connected gate driving units 211, the plurality of gate driving units 211 being connected with a plurality of scan lines of the display panel 100 through a plurality of gate connection lines L1, the plurality of gate driving units 211 being configured to output row scanning signals line by line;

[0057] a compensation circuit 220, the compensation circuit 220 comprising:

[0058] an OR gate circuit 221 connected with the plurality of gate connection lines L1 respectively, the OR gate circuit 221 being configured to perform OR operation on signals on the plurality of gate connection lines L1 and sequentially output a plurality of level signals, the plurality of level signals comprising high level signals and / or low level signals;

[0059] an inverting circuit 222 connected with the OR gate circuit 221, configured to sequentially invert the plurality of level signals and sequentially output the inverted level signals;

[0060] a digital-to-analog conversion circuit 223 connected with the inverting circuit 222 and a target scan line, configured to perform digital-to-analog conversion on the inverted high level signals and convert them into a row opening signal Vgh, or perform digital-to-analog conversion on the inverted low level signals and convert them into a row closing signal Vgl, and output the row opening signal Vgh or the row closing signal Vgl to the target scan line corresponding, the target scan line being a scan line connected with a broken gate connection line L1 or a scan line connected with an abnormal gate driving unit 211.

[0061] In the embodiment, the gate driving circuit 210 is a GOA (Gate Driver on Array) circuit, the GOA circuit integrates TFTs (Thin Film Transistors) in the gate driving circuit 210 on an array substrate, thereby saving the gate driving integrated circuit part originally arranged outside the array substrate, and reducing the cost of the product from the aspects of material cost and process steps.

[0062] When the GOA circuit is adopted, the GOA circuit is bonded in the non-display area of the display panel 100, the display area 110 of the display panel 100 is provided with a plurality of data lines, a plurality of scan lines and a plurality of pixel units arranged in an array, the pixel unit is connected with a corresponding data line and a scan line, and the pixel unit is composed of a corresponding thin film transistor T1, a liquid crystal capacitor and a storage capacitor.

[0063] The driving circuit 200 of the display panel can further include a source driving circuit and a timing controller, the timing controller outputs a control signal to the source driving circuit and the gate driving circuit 210 to control the source driving circuit to output a data signal and control the gate driving circuit 210 to output a row scan signal.

[0064] As shown in Figure 1 , the source driving circuit can be composed of a plurality of flip chips 2, each flip chip 2 is provided with a driving chip and a transmission channel, and the flip chip 2 can be connected with a flexible circuit board 1, and the flexible circuit board 1 can be provided with a corresponding timing controller and a power management integrated circuit.

[0065] The gate driving circuit 210 includes a plurality of cascaded gate driving units 211, and the gate driving unit 211 can be a shift register structure, and the plurality of cascaded gate driving units 211 output row scan signals line by line.

[0066] The gate driving circuit 210 can be a double-sided driving as shown in Figure 1 or a single-sided driving as shown in Figure 2 , when the double-sided driving is adopted, the two sides of the display panel 100 are respectively provided with the gate driving circuit 210, and the row scan signals are generated at the same time, which can improve the driving capability, when the single-sided driving is adopted, one side of the display panel 100 is provided with the gate driving circuit 210, and the row scan signals are output line by line.

[0067] The row scan signal is composed of a row opening signal Vgh and a row closing signal Vgl, when scanning to one row, the corresponding gate driving unit 211 outputs the row opening signal Vgh to the scan line of the row through the gate connection line L1, the thin film transistor T1 of each pixel unit of the row is opened and inputs the data signal, the pixel unit of the row displays the corresponding display information, and the other gate driving units 211 output the row closing signal Vgl to the scan lines of the other rows through the gate connection line L1, the thin film transistor T1 of each pixel unit of the other rows is closed and has no display information.

[0068] In each frame, the row opening signal Vgh is output line by line, so as to open the pixel units of each row line by line, and display the display picture of the current frame.

[0069] As shown in Figure 3As shown, each frame can be time-divided according to the output period of the row enable signal Vgh, and each frame scanning time is divided into a plurality of unit periods t0, each unit period t0 corresponds to an output period of the row enable signal Vgh, when the gate driving unit 211 normally outputs each row scanning signal, the phases of each row scanning signal are different by a unit phase, the row scanning signal of the previous stage gate driving unit 211 is ahead of the gate driving unit 211 of the next stage, and the output time length of each row scanning signal is the same, and the time of the unit phase is equal to the output time length of each row scanning signal.

[0070] During the process or use, the gate connection line L1 is disconnected, the gate driving unit 211 is abnormal, such as Figure 4 As shown in the waveform diagram on the left side, when the gate driving unit 211 is normal and the gate connection line L1 is not disconnected or short-circuited, the gate driving unit 211 outputs the row scanning signal composed of the row enable signal Vgh and the row disable signal Vgl to the scanning line, when the gate driving unit 211 is abnormal, such as Figure 4 As shown in the waveform diagrams in the middle and on the right side, there may be insufficient output voltage or no output voltage, which causes the pixel units of the corresponding row of the display panel 100 to not work normally, and further causes the display panel 100 to display abnormally.

[0071] In order to solve the problem, the driving circuit 200 of the display panel is further provided with a compensation circuit 220, which compensates the output in a signal detection, signal compensation and voltage compensation manner.

[0072] Firstly, the OR circuit 221 is connected to each gate connection line L1, and performs OR operation on the multiple signals output by the multiple gate driving units 211, so as to identify the target scanning line that needs to be compensated, when each gate driving unit 211 normally outputs the row scanning signal and the gate connection line L1 is not disconnected, one of the gate driving units 211 outputs the row enable signal Vgh, and the remaining gate driving units 211 maintain output of the row disable signal Vgl, and the OR circuit 221 outputs a high-level signal in turn when scanning each row.

[0073] When one of the gate driving units 211 is abnormal or one of the gate connection lines L1 is disconnected, when the row scanning reaches the row, the voltage of the corresponding gate connection line L1 is insufficient or low, and the remaining gate driving units 211 maintain output of the row disable signal Vgl, and the OR circuit 221 outputs a low-level signal when scanning the row.

[0074] For example, assuming that the position of abnormal output is at line 82, when scanning the first line to line 81, the OR gate 221 outputs high level signals in turn according to the unit time period t0, when scanning to line 82, the OR gate 221 outputs a low level signal, the gate connection line L1 corresponding to line 82 or the gate drive unit 211 is a module to be repaired and replaced, and line 82 is an object to be compensated for output.

[0075] Through the OR gate 221, the abnormal position can be determined, and then the abnormal signal is screened and compensated for output through the inverter circuit 222 and the digital-to-analog conversion circuit 223 in the compensation link.

[0076] In order to realize normal output, for the level signal output by the front-end OR gate 221, the inverter circuit 222 is used to invert the level signal output by the front end, convert the high level signal output by the OR gate 221 into a low level signal, and convert the low level signal output by the OR gate 221 into a high level signal, so as to screen the abnormal signal to be processed.

[0077] The output end of the OR gate 221 or the inverter circuit 222 can also be connected to a corresponding processor or display, and the maintenance personnel can determine the gate connection line L1 of the abnormal position or the abnormal gate drive unit 211 according to the output signal Vout1 of the OR gate 221 or the output signal Vout2 of the inverter circuit 222, such as when a low level signal output by the OR gate 221 is obtained, or when a high level signal output by the inverter circuit 222 is obtained, the abnormal position can be determined according to the display information or time information.

[0078] Then, the maintenance personnel can connect the digital-to-analog conversion circuit 223 to the scanning line at the corresponding position by means of laser radiation and the like, such as Figure 5 As shown in the figure, assuming that Gm is the scanning line of line 82, and the gate connection line L1 connected with the scanning line is disconnected, at this time, first, the gate connection line L1 is disconnected from the scanning line by means of laser radiation, wherein × represents the disconnection point, and the output end of the digital-to-analog conversion circuit 223 is connected to the scanning line by means of laser radiation and the like.

[0079] When the gate connection line L1 of line 82 is disconnected, the OR gate 221 outputs a low level signal when scanning to line 82, the inverter circuit 222 inverts and outputs a high level signal, the high level signal is converted into a row opening signal Vgh by the digital-to-analog conversion circuit 223 and output to the scanning line of line 82, signal compensation is realized, the row opening signal Vgh is normally output to the thin film transistor T1 of the pixel unit corresponding to line 82, the thin film transistor T1 is opened, and normal display is realized, thereby avoiding dark lines or weak lines in line 82, and improving the display effect.

[0080] Then, when scanning to other rows, the OR gate circuit 221 normally outputs a high-level signal, the inverting circuit 222 inverts and outputs a low-level signal, and converts and outputs the row-off signal Vgl through the digital-to-analog conversion circuit 223. The row-off signal Vgl is output to the scanning line of the 82nd row, and the row-off signal Vgl is normally output to the thin-film transistor T1 of the pixel unit corresponding to the 82nd row. The thin-film transistor T1 is turned off, and the pixel unit corresponding to the 82nd row can normally receive the row scanning signal and display and stop displaying normally.

[0081] The OR gate circuit 221 may use corresponding logic gates, components, etc. In an optional embodiment, as shown in FIG. Figure 6 As shown, the OR gate circuit 221 includes a plurality of first diodes D1;

[0082] The anode of each first diode D1 is connected to a gate connection line L1 , and the cathodes of the plurality of first diodes D1 are connected to form an output end of the OR gate circuit 221 .

[0083] In this embodiment, when the corresponding gate driving unit 211 and the corresponding gate connection line L1 are normal, during row-by-row scanning, one of the gate driving units 211 outputs a row-on signal Vgh, and the remaining gate driving units 211 output a row-off signal Vgl. Then, after the multiple first diodes D1 are connected in parallel, the multiple first diodes D1 output high-level signals.

[0084] Alternatively, when one of the gate driving units 211 is abnormal or the connected gate connection line L1 is broken, when scanning to that row, the corresponding first diode D1 outputs a low-level signal, and the remaining first diodes D1 also output low-level signals, then multiple first diodes D1 connected in parallel output low-level signals, and the position of the abnormal gate driving unit 211 or the abnormal gate connection line L1 can be determined based on the timing of the occurrence of the low-level signals.

[0085] like Figure 7 As shown, in another optional embodiment, the OR gate circuit 221 includes a plurality of thin film transistors T1;

[0086] The drain and gate of each thin film transistor T1 are connected to a gate connection line L1 , and the sources of the plurality of thin film transistors T1 are connected to form an output end of the OR gate circuit 221 .

[0087] In this embodiment, when the corresponding gate driving unit 211 and the corresponding gate connection line L1 are normal, during row-by-row scanning, one of the gate driving units 211 outputs a row-on signal Vgh, and the remaining gate driving units 211 output a row-off signal Vgl. Then, after the multiple first diodes D1 are connected in parallel, the multiple first diodes D1 output high-level signals.

[0088] Or, when one of the gate drive units 211 is abnormal or the connected gate connection line L1 is disconnected, when scanning to the row, the corresponding first diode D1 outputs a low level signal, and the remaining first diodes D1 also output low level signals, then the parallelly connected multiple first diodes D1 output low level signals, and the position of the abnormal gate drive unit 211 or the abnormal gate connection line L1 can be determined according to the time sequence of the low level signal.

[0089] The inverter circuit 222 can adopt an inverter and a corresponding switch circuit, and in an optional embodiment, as shown in Figure 8 the inverter circuit 222 includes a first resistor R1, a transistor K1 and a second diode D11.

[0090] The first end of the first resistor R1 is connected with the positive voltage end, the second end of the first resistor R1, the collector of the transistor K1 and the anode of the second diode D11 are connected, the cathode of the second diode D11 constitutes the output end of the inverter circuit 222, the base of the transistor K1 constitutes the input end of the inverter circuit 222, and the emitter of the transistor K1 is grounded.

[0091] In the embodiment, Vout1 is the output signal of the or circuit 221, and Vout2 is the output signal of the inverter circuit 222. When the or circuit 221 outputs a high level, the transistor K1 in the inverter circuit 222 is turned on and outputs a low level signal to the digital-to-analog conversion circuit 223, and when the or circuit 221 outputs a low level, the transistor K1 in the inverter circuit 222 is turned off, and the inverter circuit 222 maintains outputting a high level signal to the digital-to-analog conversion circuit 223.

[0092] The second diode D11 realizes unidirectional transmission of the level signal, which can avoid damage of the device caused by reverse transmission of the signal from the digital-to-analog conversion circuit 223 to the inverter circuit 222.

[0093] Further, when the gate drive unit 211 is abnormal, the output voltage is insufficient, but a high level signal output by the or circuit 221 can still be triggered, which can cause the transistor K1 to be turned on, the inverter circuit 222 to output a low level signal, and the effective abnormal signal and the abnormal position to be unable to be recognized.

[0094] Therefore, as shown in Figure 9 in an optional embodiment, the compensation circuit 220 further includes:

[0095] The voltage dividing circuit 224 is connected to the output terminal of the OR gate circuit 221 and the first reference voltage Vref1 terminal. The voltage dividing circuit 224 is used to proportionally divide the voltage difference between the output signal Vout1 of the OR gate circuit 221 and the first reference voltage Vref1 of the first reference voltage Vref1 terminal, and output the voltage signal after voltage division to the inverter circuit 222. The first reference voltage Vref1 is less than the voltage of the row opening signal Vgh and greater than the voltage of the row closing signal Vgl.

[0096] In this embodiment, the voltage dividing circuit 224 divides the output signal Vout1 of the OR gate circuit 221 and the first reference voltage Vref1. When the gate drive unit 211 has an output voltage less than the row opening signal Vgh, the OR gate circuit 221 still outputs a high-level signal. At this time, the voltage of the high-level signal is equal to the output voltage of the abnormal gate drive unit 211. After voltage division, the voltage signal received by the transistor K1 is less than the threshold voltage, and the transistor K1 cannot be turned on. The inverter circuit 222 can normally output a high-level signal, so that the abnormal position can be determined according to the output signal Vout2 of the inverter circuit 222.

[0097] The voltage dividing circuit 224 can use corresponding voltage dividing resistors, such as Figure 10 As shown in an optional embodiment, the voltage dividing circuit 224 includes a second resistor R2, a third resistor R3, and a capacitor C1.

[0098] The first end of the second resistor R2 and the first end of the capacitor C1 are connected to form the input terminal of the voltage dividing circuit 224. The second end of the second resistor R2, the second end of the capacitor C1, and the first end of the third resistor R3 are connected to form the output terminal of the voltage dividing circuit 224. The second end of the third resistor R3 is connected to the reference voltage terminal.

[0099] In this embodiment, the second resistor R2 and the third resistor R3 form the voltage dividing circuit 224, and divide the voltage difference between the output signal Vout1 of the OR gate circuit 221 and the first reference voltage Vref1, so as to determine the abnormal gate drive unit 211.

[0100] At the same time, the capacitor C1 is connected in parallel across the second resistor R2. When the OR gate circuit 221 outputs a level signal, the voltage across the capacitor C1 cannot be suddenly changed. The level signal can be quickly fed back to the transistor K1 and the third resistor R3, thereby reducing the time delay of the compensation circuit 220.

[0101] The digital-to-analog conversion circuit 223 can use corresponding digital-to-analog converters, comparators, etc. In an optional embodiment, as shown in Figure 2 and Figure 11 The digital-to-analog conversion circuit 223 includes:

[0102] The comparator U1, the non-inverting input of the comparator U1 constitutes the input of the digital-to-analog conversion circuit 223, the inverting input of the comparator U1 is used for inputting the second reference voltage Vref2, the positive power supply end of the comparator U1 is used for inputting the row opening signal Vgh, the negative power supply end of the comparator U1 is used for inputting the row closing signal Vgl, and the output of the comparator U1 constitutes the output of the digital-to-analog conversion circuit 223, and the second reference voltage Vref2 is less than the voltage of the row opening signal Vgh.

[0103] The first repair line L2 is connected with the output of the comparator U1 and the first end of the target scanning line.

[0104] In the embodiment, Vout3 is the output signal of the digital-to-analog conversion circuit 223, when the or gate circuit 221 inputs a high-level signal, the inverting circuit 222 outputs a low-level signal with a voltage of zero, which cannot be used as the row closing signal Vgl to drive the pixel unit to be closed. Therefore, the comparator U1 and the first repair line L2 are further arranged between the inverting circuit 222 and the corresponding scanning line of the display panel 100. Similarly, when the or gate circuit 221 inputs a low-level signal, the inverting circuit 222 outputs a high-level signal with a positive voltage, which may not be equal to the voltage of the row opening signal Vgh, so that the pixel unit cannot be normally opened.

[0105] Therefore, the comparator U1 is further arranged to convert the signal, when one of the gate connection lines L1 is disconnected, the or gate circuit 221 outputs a low-level signal, and the inverting circuit 222 outputs a high-level signal with a positive voltage. At this time, the high-level signal is greater than the second reference voltage Vref2, the comparator U1 outputs the row opening signal Vgh of the positive power supply end to the first repair line L2, and transmits the row opening signal Vgh to the scanning line corresponding to the abnormal position through the first repair line L2.

[0106] When scanning to other normal lines, the or gate circuit 221 outputs a high-level signal, and the inverting circuit 222 outputs a low-level signal with a voltage of zero to the comparator U1. The low-level signal is less than the second reference voltage Vref2, the comparator U1 outputs the row closing signal Vgl of the negative power supply end to the first repair line L2, and transmits the row closing signal Vgl to the scanning line corresponding to the position through the first repair line L2, so that the scanning line receives the normal row opening signal Vgh and the row closing signal Vgl.

[0107] Further, in order to improve the driving capability, as shown in the figure, the digital-to-analog conversion circuit 223 further comprises: Figure 1

[0108] The second repair line L3 is connected with the output of the comparator U1 and the second end of the target scanning line.

[0109] ​In the embodiment, the gate drive circuit 210 adopts double-side driving and is arranged at two sides of the display area 110 respectively, the output end of the comparator U1 is connected with the first repair line L2 and the second repair line L3 respectively, the first repair line L2 is connected with the first end of the scan line corresponding to the abnormal position, the second repair line L3 is connected with the second end of the scan line corresponding to the abnormal position, and after the laser breaks the scan line and the gate connecting line L1, the comparator U1 outputs the normal row opening signal Vgh and the row closing signal Vgl to the two ends of the scan line corresponding to the display panel 100, and double-side driving is realized.

[0110] Compared with the prior art, the embodiment of the present application has the beneficial effects that: the driving circuit 200 of the display panel includes the gate drive circuit 210 and the compensation circuit 220, the compensation circuit 220 includes the OR gate circuit 221, the inverting circuit 222 and the digital-to-analog conversion circuit 223, the gate drive circuit 210 includes a plurality of gate drive units 211 connected in series, the gate drive unit 211 is connected with the scan line of the display panel 100 through the gate connecting line L1, the OR gate circuit 221 performs OR operation on the signals on the plurality of gate connecting lines L1, thereby outputting the corresponding level signal, the inverting circuit 222 and the digital-to-analog conversion circuit 223 perform inverting and digital-to-analog conversion on the level signal in sequence, thereby outputting the corresponding row opening signal Vgh and row closing signal Vgl to the scan line connected with the abnormal gate connecting line L1, signal compensation is realized, through OR operation, the plurality of gate connecting lines L1 and the corresponding gate drive units 211 can be operated synchronously, thereby determining one or more abnormal gate connecting lines L1 or gate drive units 211, and through the setting of the inverting circuit 222 and the digital-to-analog conversion circuit 223, the signal on the abnormal gate connecting line L1 can be directly converted into a compensation signal and provided to the corresponding scan line, signal compensation is realized, thereby avoiding the occurrence of dark lines or weak lines and improving the display effect.

[0111] Embodiment two

[0112] When the scheme of embodiment one is adopted, signal compensation cannot be performed on the plurality of abnormal position gate connecting lines L1, for example, when the gate connecting line L1 of the 82nd row and the 100th row both appear to be broken, the compensation circuit 220 is connected to the scan lines of the 82nd row and the 100th row through the repair line, when scanning to the 82nd row line by line, at this time, the digital-to-analog conversion circuit 223 outputs the row opening signal Vgh to the scan lines of the 82nd row and the 100th row, which causes the pixel units of the 100th row to start displaying in advance, resulting in the occurrence of horizontal lines in the picture, then, when scanning to the 100th row line by line, at this time, the digital-to-analog conversion circuit 223 outputs the row opening signal Vgh to the scan lines of the 82nd row and the 100th row, which causes the pixel units of the 82nd row to start displaying again, resulting in abnormal picture display.

[0113] In order to solve the problem, as shown inFigure 13 As shown in an optional embodiment, the compensation circuit 220 further comprises:

[0114] A plurality of switches Q1, the digital-to-analog conversion circuit 223 is connected to a plurality of scan lines through the plurality of switches Q1, the switch Q1 is triggered to turn on by the first switch signal, and is triggered to turn off by the second switch signal;

[0115] The switch control circuit 225 is connected with the or gate circuit 221 and the plurality of switches Q1 respectively, and the switch control circuit 225 is used for:

[0116] Dividing each frame scanning time into a plurality of unit time periods t0, each time period corresponds to an output time period of the row enable signal Vgh, and detecting the output signal Vout1 of the or gate circuit 221 in each unit time period t0 when receiving the frame start signal;

[0117] When detecting a high-level signal in the i-th unit time period t0, outputting a plurality of second switch signals to the plurality of switches Q1;

[0118] When detecting a low-level signal in the i-th unit time period t0, continuously outputting a first switch signal to the switch Q1 connected to the i-th gate drive unit 211 in the unit time period t0, and outputting a plurality of second switch signals to the other switches Q1.

[0119] In this embodiment, the switch signal can divide each frame time into a plurality of unit time periods t0 according to the frame time and the number of the gate drive units 211, output a row enable signal Vgh in each time period, and take the frame start signal as a trigger signal to realize detection of each signal and control of the switch Q1.

[0120] When the i-th gate drive unit 211 is abnormal or the connection line connected with the scan line is abnormal, the switch control circuit 225 detects a low-level signal in the i-th time period through the or gate circuit 221, at this time, the first switch signal is output to control the switch Q1 corresponding to the i-th gate drive unit 211 to turn on, and the second switch signal is output to control the other switches Q1 to turn off, the digital-to-analog conversion circuit 223 converts and outputs the row enable signal Vgh to be normally output to the i-th row of scan lines through the switch Q1, and the scan lines of other rows are provided with the row disable signal Vgl by other gate drive units 211.

[0121] For example, the gate connection line L1 of the 82nd row and the 100th row is abnormal, a low-level signal is detected in the 82nd time period, the switch control circuit 225 controls the switch Q1 corresponding to the 82nd gate drive unit 211 to turn on, and controls the other switches Q1 to turn off, the digital-to-analog conversion circuit 223 converts and outputs the row enable signal Vgh to be normally output to the 82nd row of scan lines through the switch Q1, and will not be output to the ground 100th row of scan lines.

[0122] And when a low-level signal is detected in the 100th period, the switch control circuit 225 controls the switch Q1 corresponding to the 100th gate driving unit 211 to be turned on, and controls other switches Q1 to be turned off. The row start signal Vgh converted and output by the digital-to-analog conversion circuit 223 is normally output to the scan line of the 100th row through the switch Q1, and is not output to the scan line of the 82nd row, thereby avoiding affecting other rows and realizing signal compensation for all abnormal gate driving units 211 or gate connection lines L1.

[0123] Each switch Q1 may be disposed on the display panel 100 or on the flexible circuit board 1 , and the specific location is not limited.

[0124] The switch control circuit 225 can adopt corresponding timers and detection units. In an optional embodiment, the switch control circuit 225 is a timing controller. The timing controller performs signal detection and switch Q1 control on the one hand, and outputs control signals to the source drive circuit and the gate drive circuit 210 on the other hand to control the source drive circuit to output data signals and control the gate drive circuit 210 to output row scan signals.

[0125] Example 3

[0126] A second aspect of the embodiments of the present invention provides a display device, such as Figure 14 As shown, the display device includes a display panel 100 and a display panel driving circuit 200. The specific structures of the display panel 100 and the display panel driving circuit 200 are referred to the above embodiments. Since the present display device adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described in detail here. The display panel driving circuit 200 is connected to the display panel 100.

[0127] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention, and should all be included in the scope of protection of the present invention.

Claims

1. A driving circuit for a display panel, characterized in that: include: A gate driving circuit comprising a plurality of gate driving units connected in sequence, wherein the plurality of gate driving units are connected to a plurality of scan lines of the display panel via a plurality of gate connection lines, and the plurality of gate driving units are configured to output row scan signals row by row; A compensation circuit, the compensation circuit comprising: an OR gate circuit, connected to the plurality of gate connection lines respectively, and configured to perform an OR operation on the signals on the plurality of gate connection lines and sequentially output a plurality of level signals, wherein the plurality of level signals include a high level signal and / or a low level signal; an inverting circuit connected to the OR gate circuit, configured to sequentially invert the plurality of level signals and sequentially output the inverted level signals; A digital-to-analog conversion circuit is connected to the inverting circuit and the target scan line, and is used to perform digital-to-analog conversion on the inverted high-level signal and convert it into the row-on signal, or to perform digital-to-analog conversion on the inverted low-level signal into a row-off signal, and to output the row-on signal or the row-off signal to the target scan line accordingly, where the target scan line is a scan line connected to the broken gate connection line or a scan line connected to the abnormal gate drive unit.

2. The driving circuit of the display panel according to claim 1, wherein: The OR gate circuit includes a plurality of first diodes; The anode of each first diode is connected to one of the gate connection lines, and the cathodes of a plurality of the first diodes are connected to form an output end of the OR gate circuit.

3. The driving circuit of the display panel according to claim 1, wherein: The OR gate circuit includes a plurality of thin film transistors; The drain and gate of each thin film transistor are connected to a gate connection line, and the sources of a plurality of thin film transistors are connected to form the output end of the OR gate circuit.

4. The driving circuit of the display panel according to claim 1, wherein: The inverting circuit includes a first resistor, a transistor and a second diode; The first end of the first resistor is connected to the positive voltage end, the second end of the first resistor, the collector of the transistor and the anode of the second diode are connected, the cathode of the second diode constitutes the output end of the inverter circuit, the base of the transistor constitutes the input end of the inverter circuit, and the emitter of the transistor is grounded.

5. The driving circuit of the display panel according to claim 1, wherein: The compensation circuit further includes: A voltage divider circuit is connected to the output end of the OR gate circuit and the first reference voltage end. The voltage divider circuit is used to proportionally divide the voltage difference between the output signal of the OR gate circuit and the first reference voltage of the first reference voltage end, and output the divided voltage signal to the inverting circuit. The first reference voltage is less than the voltage of the row-on signal and greater than the voltage of the row-off signal.

6. The driving circuit of the display panel according to claim 5, wherein: The voltage divider circuit includes a second resistor, a third resistor and a capacitor; The first end of the second resistor and the first end of the capacitor are connected to form the input end of the voltage divider circuit, the second end of the second resistor, the second end of the capacitor and the first end of the third resistor are connected to form the output end of the voltage divider circuit, and the second end of the third resistor is connected to the reference voltage end.

7. The driving circuit of the display panel according to claim 1, wherein: The digital-to-analog conversion circuit comprises: a comparator, wherein a non-inverting input terminal of the comparator constitutes an input terminal of the digital-to-analog conversion circuit, an inverting input terminal of the comparator is used to input a second reference voltage, a positive power supply terminal of the comparator is used to input the row-on signal, a negative power supply terminal of the comparator is used to input the row-off signal, an output terminal of the comparator constitutes an output terminal of the digital-to-analog conversion circuit, and the second reference voltage is less than a voltage of the row-on signal; The first repair line is connected to the output end of the comparator and the first end of the target scan line.

8. The driving circuit of the display panel according to claim 7, wherein: The digital-to-analog conversion circuit further includes: The second repair line is connected to the output end of the comparator and the second end of the target scan line.

9. The display panel driving circuit according to any one of claims 1 to 8, wherein: The compensation circuit further includes: a plurality of switches, wherein the digital-to-analog conversion circuit is respectively connected to the plurality of scan lines via the plurality of switches, wherein the switches are triggered to be turned on by a first switching signal and to be turned off by a second switching signal; A switch control circuit is connected to the OR gate circuit and the plurality of switches, and the switch control circuit is used to: Dividing each frame scanning time into a plurality of unit time periods, each unit time period corresponds to an output time period of the row start signal, and detecting the output signal of the OR gate circuit in each unit time period when a frame start signal is received; When a high-level signal is detected in the i-th unit period, outputting multiple second switch signals to the multiple switches; When a low level signal is detected in the i-th unit period, one channel of the first switching signal is continuously output to the switch corresponding to the i-th gate driving unit, and multiple channels of the second switching signals are output to other switches.

10. A display device, characterized in that: The device comprises a display panel and a display panel driving circuit according to any one of claims 1 to 9, wherein the display panel driving circuit is connected to the display panel.

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