Display apparatus

Abstract

To provide a display apparatus that can sufficiently secure a time for writing a video signal to pixels and does not increase the number of signal lines.SOLUTION: A display apparatus includes: a plurality of scanning lines; a plurality of signal lines arranged in groups of three; and a plurality of pixels provided at intersections of the plurality of scanning lines and the plurality of signal lines. One signal line among the signal lines arranged in groups of three is connected to pixels of a predetermined row, and the other two signal lines among the signal lines arranged in groups of three are connected to pixels in two different rows that are in the same column as the pixels of the predetermined row.SELECTED DRAWING: Figure 11

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a display device. [Background technology]

[0002] Liquid crystal display devices using polymer dispersed liquid crystal (PDLC) have been developed. Liquid crystal display devices using PDLC can display images by combining a transparent state and a dispersed state.

[0003] In liquid crystal display devices using PDLC, color display is performed using field sequential driving. For example, color display can be performed by dividing one frame into three frames of red (R), green (G), and blue (B).

[0004] However, in the field sequential driving, the time required to write a video signal to a pixel is short, so the video signal must be written at high speed.

[0005] To solve the above problem, for example, two signal lines are provided between adjacent pixels. This makes it possible to simultaneously select two scanning lines and write video signals to two rows of pixels. A display device with this pixel configuration can be driven at higher speeds. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Patent No. 7240921 Summary of the Invention [Problem to be solved by the invention]

[0007] This embodiment provides a display device that ensures sufficient time for writing video signals to pixels and does not increase the number of signal lines. [Means for solving the problem]

[0008] A display device according to an embodiment includes: a plurality of scanning lines extending along a first direction and arranged along a second direction intersecting the first direction; a plurality of signal lines extending along the second direction and arranged in groups of three along the first direction; a plurality of pixels provided at intersections of the plurality of scanning lines and the plurality of signal lines, and arranged in a matrix with a plurality of rows arranged side by side along the second direction and a plurality of columns arranged side by side along the first direction; a plurality of switching elements included in the plurality of pixels; a plurality of semiconductor layers included in the plurality of switching elements; Equipped with One of the signal lines arranged in groups of three is connected to pixels in a predetermined row, The other two of the three signal lines arranged in groups are connected to pixels in the same column as the pixel in the predetermined row but in two different rows. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a plan view showing a schematic configuration of a display device according to an embodiment. [Figure 2] FIG. 2 is a plan view showing a schematic configuration of the display area of ​​the display device of FIG. [Figure 3] FIG. 3 is a cross-sectional view showing an example of a configuration that can be applied to the display panel shown in FIG. [Figure 4] FIG. 4 is a cross-sectional view showing an example of a schematic configuration of a display panel. [Figure 5] FIG. 5 is a plan view showing an example of a schematic configuration of the display device according to the embodiment. [Figure 6] FIG. 6 is a plan view showing an example of a schematic configuration of a display device according to an embodiment. [Figure 7] FIG. 7 is a partially enlarged view of FIG. [Figure 8] FIG. 8 is a cross-sectional view of the display device taken along line A1-A2 shown in FIG. [Figure 9] FIG. 9 is a cross-sectional view of the display device taken along line B1-B2 shown in FIG. [Figure 10] FIG. 10 is a cross-sectional view of the display device taken along line C1-C2 shown in FIG. [Figure 11] FIG. 11 is a plan view showing an example of the connection relationship between pixels and signal lines. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. The disclosure is merely an example, and appropriate modifications that a person skilled in the art can easily conceive while maintaining the gist of the invention are naturally included within the scope of the present invention. Furthermore, in order to clarify the explanation, the drawings may show the width, thickness, shape, etc. of each part schematically compared to the actual embodiment, but these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each drawing, elements similar to those described above with reference to the previous drawings may be designated by the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0011] The embodiments described in this specification are not general but are embodiments that describe the same or corresponding special technical features of the present invention. Hereinafter, a display device according to an embodiment will be described in detail with reference to the drawings.

[0012] In this embodiment, the first direction X, the second direction Y, and the third direction Z are perpendicular to one another, but may intersect at an angle other than 90 degrees. The direction toward the tip of the arrow of the third direction Z is defined as up or upward, and the direction opposite to the direction toward the tip of the arrow of the third direction Z is defined as down or downward. The first direction X, the second direction Y, and the third direction Z may also be referred to as the X direction, the Y direction, and the Z direction, respectively.

[0013] Furthermore, when the terms "second member above the first member" and "second member below the first member" are used, the second member may be in contact with the first member or may be located apart from the first member. In the latter case, a third member may be interposed between the first and second members. On the other hand, when the terms "second member above the first member" and "second member below the first member" are used, the second member is in contact with the first member.

[0014] Furthermore, it is assumed that an observation position for observing the display device is located at the tip of the arrow in the third direction Z, and viewing from this observation position toward the XY plane defined by the first direction X and the second direction Y is called planar view. Viewing a cross section of the display device in the XZ plane defined by the first direction X and the third direction Z, or in the YZ plane defined by the second direction Y and the third direction Z, is called cross-sectional view.

[0015] [Embodiment] Fig. 1 is a plan view showing a schematic configuration of a display device in an embodiment. Fig. 2 is a plan view showing a schematic configuration of a display area of ​​the display device in Fig. 1. In this embodiment, the first direction X and the second direction Y correspond to directions parallel to the main surfaces of the substrates constituting the display device DSP.

[0016] In this embodiment, a liquid crystal display device using a polymer dispersed liquid crystal (PDLC) is disclosed as a display device DSP. The display device DSP includes a display panel PNL, a wiring board FPC, an IC chip ICP (drive circuit), and a plurality of light sources LS.

[0017] The display panel PNL includes a substrate SUB1 (array substrate), a substrate SUB2 (counter substrate), a liquid crystal layer LC, and a sealing material SAL. The substrates SUB1 and SUB2 are formed in the shape of flat plates parallel to the XY plane and face each other in the third direction Z. The liquid crystal layer LC is disposed between the substrates SUB1 and SUB2.

[0018] The display panel PNL has a display area DA that displays an image and a frame-shaped peripheral area PA that surrounds the display area DA. A sealant SAL is arranged surrounding the display area DA. The display area DA has a plurality of pixels PX arranged in a matrix in a first direction X and a second direction Y. The pixels PX can also be said to be arranged in a plurality of rows that are aligned along the second direction Y and a plurality of columns that are aligned along the first direction X. Each of the plurality of rows has a plurality of pixels PX that are aligned along the first direction X. Each of the plurality of columns has a plurality of pixels PX that are aligned along the second direction Y.

[0019] The sealant SAL is made of a cured mixture of a photocurable resin and a thermosetting resin. For example, an acrylic resin is used as the photocurable resin. For example, an epoxy resin is used as the thermosetting resin. The acrylic resin is cured by ultraviolet light (UV), and the epoxy resin is cured by heat.

[0020] The display area DA is provided with a plurality of scanning lines GL that extend along a first direction X and are arranged side by side along a second direction Y. A plurality of signal lines SL that are arranged side by side along the first direction X and extend along the second direction Y are also provided. Pixels PX are provided at the intersections of the plurality of scanning lines GL and the plurality of signal lines SL. One pixel PX is located in an area surrounded by two scanning lines GL and two signal lines SL.

[0021] Each of the pixels PX includes a switching element SW, a pixel electrode PE, and a common electrode CE. The switching element SW is formed of, for example, a thin film transistor (TFT) and is electrically connected to one scanning line GL and one signal line SL. The scanning line GL is electrically connected to the switching element SW in each of the pixels PX aligned in the first direction X. The signal line SL is electrically connected to the switching element SW in each of the pixels PX aligned in the second direction Y.

[0022] The pixel electrodes PE are electrically connected to the switching elements SW. A common electrode CE is provided in common to the plurality of pixel electrodes PE. The liquid crystal layer LC is driven by an electric field generated between the pixel electrodes PE and the common electrode CE. A capacitance CS is formed, for example, between an electrode having the same potential as the common electrode CE and an electrode having the same potential as the pixel electrodes PE.

[0023] The scanning lines GL, signal lines SL, switching elements SW, and pixel electrodes PE are provided on a substrate SUB1, and the common electrode CE is provided on a substrate SUB2. The scanning lines GL extend into the peripheral area PA and are electrically connected to the IC chip GIC. The signal lines SL extend into the peripheral area PA and are electrically connected to the IC chip SIC. When the IC chip GIC and the IC chip SIC are not distinguished, they are referred to as an IC chip ICP (drive circuit).

[0024] The IC chip ICP is electrically connected to the wiring board FPC. The IC chip ICP has built-in components such as a display driver that outputs signals necessary for image display. The IC chip ICP may also be mounted on the wiring board FPC.

[0025] The wiring board FPC is electrically connected to terminals arranged on the extension portion Ex of the board SUB1. The extension portion Ex corresponds to a portion of the board SUB1 that does not face the board SUB2. For example, the wiring board FPC is a flexible printed wiring board.

[0026] The plurality of light sources LS overlaps the extension portion Ex. The light sources LS are arranged at intervals along the first direction X. Each of the plurality of light sources LS includes, for example, a light-emitting element that emits red (R) light, a light-emitting element that emits green (G) light, and a light-emitting element that emits blue (B) light. These light-emitting elements may be, for example, light-emitting diodes (LEDs), but are not limited to this example.

[0027] Fig. 3 is a cross-sectional view showing an example of a configuration applicable to the display panel shown in Fig. 1. The substrate SUB1 includes a base material BA1, insulating layers INS1 and INS2, a capacitive electrode YE, an alignment film AL1, a switching element SW, and a pixel electrode PE. The base material BA1 has a surface BA1a and a surface BA1b located on the opposite side of the surface BA1a along the third direction Z. The surfaces BA1a and BA1b are also referred to as the lower surface and upper surface of the base material BA1, respectively.

[0028] The switching element SW is disposed on the surface BA1b. The insulating layer INS1 covers the switching element SW. Although the switching element SW is simplified in FIG. 3, in reality, the switching element SW includes a semiconductor layer and various electrodes. Furthermore, the scanning lines GL and signal lines SL shown in FIG. 1 are disposed between the base material BA1 and the insulating layer INS1, but are not shown in FIG. 3.

[0029] The capacitance electrode YE is disposed between the insulating layers INS1 and INS2. The pixel electrode PE is disposed for each pixel PX between the insulating layer INS2 and the alignment film AL1. The pixel electrode PE is electrically connected to the switching element SW through an opening OP in the capacitance electrode YE. The pixel electrode PE faces the capacitance electrode YE to form the above-mentioned capacitance CS. The alignment film AL1 covers the pixel electrode PE. The capacitance CS may be formed between other electrodes, rather than between the pixel electrode PE and the capacitance electrode YE.

[0030] The substrate SUB2 includes a base material BA2, a light-shielding layer LB, an overcoat layer (insulating layer) OC, an alignment film AL2, and a common electrode CE. The substrate BA2 has a surface BA2a facing the substrate SUB1 and a surface BA2b located on the opposite side of the surface BA2a along the third direction Z. The surfaces BA2a and BA2b are also referred to as the lower surface and upper surface of the substrate BA2, respectively.

[0031] In the present disclosure, the substrates BA1 and BA2 are also referred to as the first substrate and the second substrate, respectively, and the alignment films AL1 and AL2 are also referred to as the first alignment film and the second alignment film, respectively.

[0032] The light-shielding layer LB and the common electrode CE are disposed on the surface BA2a side. For example, the light-shielding layer LB faces the switching elements SW, the scanning lines GL, and the signal lines SL. The common electrode CE is disposed across the plurality of pixels PX and faces the plurality of pixel electrodes PE in the third direction Z. The common electrode CE also covers the light-shielding layer LB. The common electrode CE has the same potential as the capacitive electrode YE. An overcoat layer OC covers the common electrode CE. An alignment film AL2 covers the overcoat layer OC. The liquid crystal layer LC is disposed between the alignment films AL1 and AL2 and is in contact with these alignment films AL1 and AL2. Note that the overcoat layer OC may not be provided, and the alignment film AL2 may cover the common electrode CE.

[0033] The common electrode CE may be included in the substrate SUB1 instead of the substrate SUB2. When the common electrode CE is provided on the substrate SUB1, the common electrode CE may be disposed so that a horizontal electric field is generated between the pixel electrodes PE and the common electrode CE.

[0034] As described above, the light source LS and the wiring board FPC are provided on the extension portion Ex on the substrate SUB1 (on the base material BA1). The light source LS does not have to be provided on the extension portion Ex. The light source LS may be disposed outside the display panel PNL, on the opposite side of the extension portion Ex along the direction opposite to the second direction Y.

[0035] The substrates BA1 and BA2 are transparent insulating substrates such as glass substrates or plastic substrates. The insulating layer INS1 is formed of a transparent insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or acrylic resin. In one example, the insulating layer INS1 includes an inorganic insulating film and an organic insulating film. The insulating layer INS2 is an inorganic insulating film such as silicon nitride. The capacitive electrode YE, the pixel electrode PE, and the common electrode CE are transparent electrodes formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0036] The configuration of the display panel PNL is not limited to the examples in Figures 1 and 2. For example, the substrate SUB1 may not include the capacitive electrode YE, and the substrate SUB2 may not include the light-shielding layer LB.

[0037] The display device DSP does not include a polarizing plate. That is, no polarizing plate is provided on the surface BA1a of the substrate SUB1 of the display panel PNL, and no polarizing plate is provided on the surface BA2b of the substrate SUB2.

[0038] 4 is a cross-sectional view showing an example of a schematic configuration of a display panel. The display panel PNL has a liquid crystal layer LC between a substrate SUB1 and a substrate SUB2. In this embodiment, the liquid crystal layer LC is a polymer dispersed liquid crystal (PDLC) and has a polymer PM containing polymer chains and liquid crystal molecules MC. The liquid crystal molecules MC are dispersed in the gaps between the polymer PM.

[0039] The substrate SUB1 shown in FIG. 4 includes a base material BA1, an insulating layer L1, an insulating layer INS1, a signal line SL, an insulating layer INS2, a capacitive electrode YE, a pixel electrode PE, and an alignment film AL1.

[0040] The insulating layer L1 is provided on the surface BA1b of the base material BA1. The signal line SL is provided on the insulating layer L1 and covered by the insulating layer INS1. The capacitive electrode YE is provided on the insulating layer L1 in an opening OP of the insulating layer INS1 and covered by the insulating layer INS2. The capacitive electrode YE overlaps the insulating layer INS1 and faces the signal line SL.

[0041] The pixel electrode PE is provided on the insulating layer INS2 in the opening OP and is covered with an alignment film AL1. That is, the capacitance electrode YE is provided between the base material BA1 and the pixel electrode PE. The pixel electrode PE faces the capacitance electrode YE with the insulating layer INS2 sandwiched therebetween, forming a capacitance CS of the pixel PX. The alignment film AL1 is in contact with the liquid crystal layer LC.

[0042] The substrate SUB2 includes a base material BA2, a common electrode CE, and an alignment film AL2. As in Fig. 3, an overcoat layer may be provided between the common electrode CE and the alignment film AL2. The common electrode CE is provided in contact with a surface BA2a of the base material BA2 and is covered with the alignment film AL2.

[0043] In addition, on the substrate SUB2, a light-shielding layer (light-shielding layer LB shown in FIG. 3) may be provided directly above each of the switching elements SW, the scanning lines GL, and the signal lines SL. In addition, a transparent insulating layer (overcoat layer) may be provided between the base material BA2 and the common electrode CE. The common electrode CE faces a plurality of pixel electrodes PE. In addition, the common electrode CE is electrically connected to the capacitive electrode YE and has the same potential as the capacitive electrode YE. The alignment film AL2 is in contact with the liquid crystal layer LC.

[0044] The polymer PM and the liquid crystal molecules MC each have optical anisotropy or refractive index anisotropy. The response of the polymer PM to an electric field is lower than that of the liquid crystal molecules MC. For example, the alignment direction of the polymer PM hardly changes regardless of the electric field between the pixel electrode PE and the common electrode CE. On the other hand, the alignment direction of the liquid crystal molecules MC changes depending on the electric field.

[0045] When no electric field is applied to the liquid crystal layer LC or when the electric field is extremely weak, the optical axes of the polymer PM and the liquid crystal molecules MC are approximately parallel to each other. The refractive indices of the liquid crystal molecules MC and the polymer PM are substantially equal. In other words, the difference in refractive index between the liquid crystal molecules MC and the polymer PM is substantially eliminated. Therefore, light incident on the liquid crystal layer LC is transmitted through the liquid crystal layer LC with almost no scattering within the liquid crystal layer LC. Hereinafter, this state will be referred to as the transparent state. The voltage applied to the pixel electrode PE to achieve the transparent state will be referred to as the transparent voltage. The transparent voltage may be the same as the common voltage applied to the common electrode CE, or it may be a voltage slightly different from the common voltage.

[0046] On the other hand, when a sufficient electric field is applied to the liquid crystal layer LC, the optical axes of the polymer PM and the liquid crystal molecules MC intersect with each other. Therefore, light incident on the liquid crystal layer LC is scattered within the liquid crystal layer LC. This state is hereinafter referred to as the scattering state. The voltage applied to the pixel electrode PE to achieve the scattering state is called the scattering voltage. The scattering voltage is a voltage that creates a larger potential difference with the common electrode CE than the transparent voltage.

[0047] As described above, in a display device that uses a polymer dispersed liquid crystal (PDLC) as the liquid crystal layer LC, the pixels PX are driven by field sequential driving. To drive the display device at higher speed, multiple signal lines SL are provided between adjacent pixels PX. This makes it possible to simultaneously write video signals to pixels on multiple rows.

[0048] When four signal lines are provided between adjacent pixels, the time required to write a video signal to the pixel can be four times longer than when there is only one signal line. However, while this saves time, the number of signal lines required is four times the number of pixels per row. This requires four times the output of the IC chip to drive the signal lines. Depending on the size of the display device, there is a risk that it may not be possible to mount an IC chip to drive the signal lines and an IC chip to drive the scanning lines.

[0049] When two signal lines are provided between adjacent pixels, the writing time can be doubled compared to when there is one signal line. Compared to when there are four signal lines, when there are two signal lines, the writing time is shorter and the number of signal lines can be reduced.

[0050] In this embodiment, the number of signal lines provided between adjacent pixels is set to 3. This makes it possible to obtain a display device that ensures sufficient time for writing video signals to the pixels and does not increase the number of signal lines.

[0051] Fig. 5 is a plan view showing an example of a schematic configuration of a display device according to an embodiment. The display device DSP shown in Fig. 5 has m scanning lines GL and 3 x n (expressed as 3n) signal lines SL. Note that m and n are natural numbers.

[0052] Of the m scanning lines GL, scanning lines GL1 to GL6 are shown in Fig. 5. Of the 3n signal lines SL, 15 signal lines SL are shown in Fig. 5, and only signal lines SL3n-2, SL3n-1, and SL3n are labeled. Three signal lines SL are arranged between each column of pixels PX.

[0053] Every third scanning line GL is connected to one wiring. For example, scanning lines GL1, GL2, and GL3 are connected to wiring GP1. Scanning lines GL4, GL5, and GL6 are connected to wiring GP2.

[0054] A pixel PX is provided at the intersection of one scanning line GL and three signal lines SL. For example, the pixel PX corresponding to the scanning line GL1, and the signal lines SL3n-2, SL3n-1, and SL3n is referred to as pixel PX(1, n).

[0055] Each of the plurality of pixels PX has a switching element SW. The gate of the switching element SW is connected to a scanning line GL. The source of the switching element SW is connected to a corresponding one of the three signal lines SL. The drain of the switching element SW is connected to a pixel electrode (not shown).

[0056] The multiple pixels PX shown in Figure 5 select three rows of scanning lines GL (three scanning lines GL) at a time and simultaneously write three rows of video signals. This makes it possible to shorten the writing time by 1.5 times compared to when two signal lines are provided between adjacent pixels. Also, it makes it possible to shorten the number of signal lines by 3 / 4 times compared to when four signal lines are provided between adjacent pixels.

[0057] Among the pixels PX shown in Figure 5, the signal line SL connected to the pixels PX in a given row is different from the signal line SL connected to the pixels PX arranged in a row adjacent to the pixel PX in the given row. For example, compare the pixel PX connected to the scanning line GL2 and the signal line SL3n-1 with the pixel PX in the same column and adjacent row, i.e., connected to the scanning line GL1 and the scanning line GL3. The pixel PX connected to the scanning line GL1 is connected to a signal line SL different from the signal line SL3n-1. The pixel PX connected to the scanning line GL3 is connected to a signal line SL different from the signal line SL3n-1.

[0058] 5, signal line SL3n-2, which is one of signal lines SL3n-2, SL3n-1, and SL3n, is connected to pixel PX connected to scanning line GL4, which is not adjacent to scanning line GL2. Signal line SL3n is connected to pixel PX connected to scanning line GL6, which is not adjacent to scanning line GL2.

[0059] Fig. 6 is a plan view showing an example of a schematic configuration of a display device according to an embodiment. The display device DSP shown in Fig. 6 has scanning lines GLa, GLa+1, signal lines SLb-2, SLb-1, SLb, SLb+1, SLb+2, and SLb+3. When there is no need to distinguish between the scanning lines GLa and GLa+1, they are referred to as scanning lines GL. When there is no need to distinguish between the signal lines SLb-2, SLb-1, SLb, SLb+1, SLb+2, and SLb+3, they are referred to as signal lines SL.

[0060] Note that a is a natural number between 1 and m-1 (1≦a≦m-1), and b is a natural number between 3 and 3n-3 (3≦b≦3n-3).

[0061] The scanning line GLa and the scanning line GLa+1 extend along the first direction X and are provided along the second direction Y so as to be spaced apart from each other.

[0062] The signal lines SL extend along the second direction Y and are arranged in groups of three along the first direction X. In Fig. 6, for example, the signal lines SLb-2, SLb-1, and SLb are arranged adjacent to each other. The signal lines SLb+1, SLb+2, and SLb+3 are arranged adjacent to each other. The three signal lines SL, SLb-2, SLb-1, and SLb, and the three signal lines, SLb+1, SLb+2, and SLb+3, are arranged spaced apart along the first direction X.

[0063] Four semiconductor layers SCO(a, b) are provided along the second direction Y in the region where the scanning lines GLa and the signal lines SLb intersect. The number of semiconductor layers is not limited to four, and may be three or less, or five or more. The semiconductor layers SCO(a, b) are formed of oxide semiconductors.

[0064] Each semiconductor layer SCO(a,b) overlaps a part of the scanning line GLa, one end overlaps the signal line SLb, and the other end overlaps the drain electrode DE(a,b). The semiconductor layer SCO(a,b), the scanning line GLa, the signal line SLb, and the drain electrode DE(a,b) constitute a switching element SW(a,b).

[0065] Switching element SW(a+1, b-1) is provided at a distance from switching element SW(a, b) in the second direction Y. Switching element SW(a+1, b-1) is composed of a scanning line GLa+1, a signal line SLb-1, a semiconductor layer SCO(a+1, b-1), and a drain electrode DE(a+1, b-1).

[0066] 6, four semiconductor layers SCO(a+1, b-1) are provided along the second direction Y. The number of semiconductor layers SCO(a+1, b-1) is not limited to four, similar to the number of semiconductor layers SCO(a, b).

[0067] The semiconductor layer SCO(a+1, b-1) overlaps a part of the scanning line GLa+1, one end overlaps the signal line SLb-1, and the other end overlaps the drain electrode DE(a+1, b-1).

[0068] Switching element SW(a, b+3) is provided at a distance from switching element SW(a, b) along the first direction X. Switching element SW(a, b+3) is composed of a scanning line GLa, a signal line SLb+3, a semiconductor layer SCO(a, b+3), and a drain electrode DE(a, b+3).

[0069] 6, four semiconductor layers SCO(a, b+3) are provided along the second direction Y. The number of semiconductor layers SCO(a, b+3) is not limited to four, similar to the number of semiconductor layers SCO(a, b).

[0070] The semiconductor layer SCO(a,b+3) overlaps a part of the scanning line GLa, one end overlaps the signal line SLb+3, and the other end overlaps the drain electrode DE(a,b+3).

[0071] Switching element SW(a+1, b+2) is provided at a distance from switching element SW(a, b+3) in the second direction Y. Switching element SW(a+1, b+2) is composed of a scanning line GLa+1, a signal line SLb+2, a semiconductor layer SCO(a+1, b+2), and a drain electrode DE(a+1, b+2).

[0072] 6, four semiconductor layers SCO(a+1, b+2) are provided along the second direction Y. The number of semiconductor layers SCO(a+1, b+2) is not limited to four, similar to the number of semiconductor layers SCO(a, b).

[0073] The semiconductor layer SCO(a+1, b+2) overlaps a part of the scanning line GLa+1, one end overlaps the signal line SLb+2, and the other end overlaps the drain electrode DE(a+1, b+2). The pixel PX in which the semiconductor layer SCO(a+1, b+2) is provided is referred to as pixel PX(a+1, b+2).

[0074] When there is no particular distinction between the semiconductor layers SCO(a,b), SCO(a+1,b-1), SCO(a,b+3), and SCO(a+1,b+2), they are referred to as the semiconductor layers SCO. When there is no particular distinction between the drain electrodes DE(a,b), DE(a+1,b-1), DE(a,b+3), and DE(a+1,b+2), they are referred to as the drain electrodes DE.

[0075] The signal line SLb-2 will be described along the second direction Y from the scanning line GLa toward the scanning line GLa+1. In an area adjacent to the scanning line GLa, the signal line SLb-2 is adjacent to the signal line SLb-1 in the opposite direction to the first direction X. In an area adjacent to the scanning line GLa, the signal line SLb-2 is connected to the connection electrode GUEb-2. The connection electrode GUEb-2 intersects with the scanning line GLa above the scanning line GLa. The connection electrode GUEb-2 is again connected to the signal line SLb-2. ​​That is, both ends of the connection electrode GUEb-2 are connected to the signal line SLb-2.

[0076] In the region where the signal line SLb-2 intersects with the connection electrode GCEb-1, the signal line SLb-2 extends at an angle with respect to the second direction Y. Therefore, the signal line SLb-2 is disposed to the right of the signal line SLb-1 on the paper surface, that is, along the first direction X.

[0077] In an area adjacent to the scanning line GLa+1, the signal line SLb-2 is connected to the connection electrode GUEb-2. The connection electrode GUEb-2 intersects with the scanning line GLa+1 above the scanning line GLa+1. The connection electrode GUEb-2 is connected to the connection electrode SCEb-2. The connection electrode SCEb-2 is connected to the connection electrode GCEb-2, which is again connected to the signal line SLb-2.

[0078] The signal line SLb-1 will be described along the second direction Y, from the scanning line GLa toward the scanning line GLa+1. In the region adjacent to the scanning line GLa, the signal line SLb-1 is adjacent to the signal line SLb in the direction opposite to the first direction X, and is adjacent to the signal line SLb-2 in the first direction X. In the region adjacent to the scanning line GLa, the signal line SLb-1 is connected to the connection electrode GUEb-1. The connection electrode GUEb-1 is further connected to the connection electrode SCEb-1. The connection electrode SCEb-1 is connected to the connection electrode GCEb-1. The connection electrode GCEb-1 is again connected to the signal line SLb-1.

[0079] The connection electrode GCEb-1 extends at an angle with respect to the second direction Y. The connection electrode GCEb-1 extends below the signal line SLb-2. ​​Therefore, the signal line SLb-1 that reconnects to the connection electrode GCEb-1 is disposed to the left of the signal line SLb-2 on the paper, that is, along the direction opposite to the first direction X.

[0080] In a region adjacent to the scanning line GLa+1, the signal line SLb-1 overlaps one end of the semiconductor layer SCO(a+1, b-1) and extends along the second direction Y.

[0081] The signal line SLb will be described from the scanning line GLa to the scanning line GLa+1 along the second direction Y. In the region adjacent to the scanning line GLa, the signal line SLb overlaps one end of the semiconductor layer SCO(a, b) and extends along the second direction Y.

[0082] In the region adjacent to the scanning line GLa+1, the signal line SLb is connected to the connection electrode GUEb. The connection electrode GUEb is again connected to the signal line SLb across the scanning line GLa+1. That is, both ends of the connection electrode GUEb are connected to the signal line SLb.

[0083] The connection electrodes GCEb-1 and GCEb-2 are provided in the same layer as the scanning lines GL. The connection electrodes SCEb-1 and SCEb-2 are provided in the same layer as the signal lines SL. The connection electrodes GUEb-2, GUEb-1, and GUEb are provided above the scanning lines GL and the signal lines SL, and are separated from each other by an insulating layer.

[0084] The signal line SLb+1 will be described along the second direction Y, from the scanning line GLa toward the scanning line GLa+1. In an area adjacent to the scanning line GLa, the signal line SLb+1 is adjacent to the signal line SLb+2 in the direction opposite to the first direction X. The connection electrode GUEb+1 intersects with the scanning line GLa above the scanning line GLa. In an area adjacent to the scanning line GLa, the signal line SLb+1 is connected to the connection electrode GUEb+1. The connection electrode GUEb+1 is again connected to the signal line SLb+1. That is, both ends of the connection electrode GUEb+1 are connected to the signal line SLb+1.

[0085] In the region where the signal line SLb+1 intersects with the connection electrode GCEb+2, the signal line SLb+1 extends at an angle with respect to the second direction Y. Therefore, the signal line SLb+1 is disposed to the right of the signal line SLb+2 on the paper surface, that is, along the first direction X.

[0086] In an area adjacent to the scanning line GLa+1, the signal line SLb+1 is connected to the connection electrode GUEb+1. The connection electrode GUEb+1 intersects with the scanning line GLa+1 above the scanning line GLa+1. The connection electrode GUEb+1 is connected to the connection electrode SCEb+1. The connection electrode SCEb+1 is connected to the connection electrode GCEb+1, which is again connected to the signal line SLb+1.

[0087] The signal line SLb+2 will be described along the second direction Y from the scanning line GLa toward the scanning line GLa+1. In an area adjacent to the scanning line GLa, the signal line SLb+2 is adjacent to the signal line SLb+1 in the first direction X. The signal line SLb+2 is connected to the connection electrode GUEb+2 in an area adjacent to the scanning line GLa. The connection electrode GUEb+2 intersects with the scanning line GLa above the scanning line GLa. The connection electrode GUEb+2 is further connected to the connection electrode SCEb+2. The connection electrode SCEb+2 is connected to the connection electrode GCEb+2. The connection electrode GCEb+2 is again connected to the signal line SLb+2.

[0088] The connection electrode GCEb+2 extends at an angle with respect to the second direction Y. The connection electrode GCEb+2 extends below the signal line SLb+1. Therefore, the signal line SLb+2 that reconnects to the connection electrode GCEb+2 is disposed to the left of the signal line SLb+1 on the paper, that is, along the direction opposite to the first direction X.

[0089] In a region adjacent to the scanning line GLa+1, the signal line SLb+2 overlaps one end of the semiconductor layer SCO(a+1, b+2) and extends along the second direction Y.

[0090] The signal line SLb+3 will be described from the scanning line GLa to the scanning line GLa+1 along the second direction Y. In the region adjacent to the scanning line GLa, the signal line SLb+3 overlaps one end of the semiconductor layer SCO(a, b+3) and extends along the second direction Y.

[0091] In an area adjacent to the scanning line GLa+1, the signal line SLb+3 is connected to the connection electrode GUEb+3. The connection electrode GUEb+3 intersects with the scanning line GLa+1 above the scanning line GLa+1. The connection electrode GUEb+3 is again connected to the signal line SLb+3 across the scanning line GLa+1. That is, both ends of the connection electrode GUEb+3 are connected to the signal line SLb+3.

[0092] The connection electrodes GCEb+1 and GCEb+2 are provided in the same layer as the scanning lines GL. The connection electrodes SCEb+1 and SCEb+2 are provided in the same layer as the signal lines SL. The connection electrodes GUEb+1, GUEb+2, and GUEb+3 are provided above the scanning lines GL and the signal lines SL, and are separated from each other by an insulating layer.

[0093] The drain electrode DE of the switching element SW is connected to a pixel electrode (not shown). The drain electrode DE may be connected to the pixel electrode directly or via a relay electrode.

[0094] The scan lines GL, signal lines SL, and drain electrodes DE may be made of a metal material, such as aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), tantalum (Ta), copper (Cu), silver (Ag), or the like, in the form of a single element, a laminate, or an alloy.

[0095] When there is no need to distinguish between the connection electrodes GCEb-2, GCEb-1, GCEb+1, and GCEb+2, they are referred to as connection electrodes GCE. The connection electrodes GCE are formed from the same material and in the same process as the scanning lines GL. That is, the connection electrodes GCE and the scanning lines GL are formed in the same layer.

[0096] When there is no need to distinguish between the connection electrodes SCEb-2, SCEb-1, SCEb+1, and SCEb+2, they are referred to as connection electrodes SCE. The connection electrodes SCE are formed from the same material and in the same process as the signal lines SL. That is, the connection electrodes SCE and the signal lines SL are formed in the same layer.

[0097] When there is no particular need to distinguish between the connection electrodes GUEb-2, GUEb-1, GUEb, GUEb+1, GUEb+2, and GUEb+3, they are referred to as the connection electrodes GUE. The connection electrodes GUE may be formed from the above-mentioned metal materials.

[0098] Fig. 7 is a partially enlarged view of Fig. 6. Fig. 7 mainly shows the region where the signal lines SLb-2, SLb-1, and SLb intersect with the scanning line GLa.

[0099] Of the contact holes for connecting the signal line SLb-2 and the connection electrode GUEb-2, the contact hole on the upper side of the paper surface is referred to as contact hole CHsu1, and the contact hole on the lower side of the paper surface is referred to as contact hole CHsu2.

[0100] The contact hole for connecting the signal line SLb-1 and the connection electrode GUEb-1 is referred to as contact hole CHsu3. The contact hole for connecting the connection electrode GUEb-1 and the connection electrode SCEb-1 is referred to as contact hole CHsu4. The contact hole for connecting the connection electrode SCEb-1 and the connection electrode GCEb-1 is referred to as contact hole CHgs1. The contact hole for connecting the connection electrode GCEb-1 and the signal line SLb-1 is referred to as contact hole CHgs2.

[0101] The contact hole for connecting the drain electrode DE(a, b) and the pixel electrode (not shown in FIG. 7) is referred to as a contact hole CHdp.

[0102] Fig. 8 is a cross-sectional view of the display device taken along line A1-A2 shown in Fig. 7. The display device DSP shown in Fig. 8 includes a substrate BA1, a scanning line GLa, an insulating layer GI, a semiconductor layer SCO(a, b), an insulating layer IL1, a signal line SLb, a drain electrode DE(a, b), an insulating layer IL2, an insulating layer INS1, an insulating layer INS2, a pixel electrode PE(a, b), a capacitive electrode YE, and an electrode TME.

[0103] The scanning line GLa is provided on the base material BA1. An insulating layer GI is provided to cover the base material BA1 and the scanning line GLa. The semiconductor layers SCO(a, b) are provided on the scanning line GLa with the insulating layer GI sandwiched therebetween.

[0104] An insulating layer IL1 is provided to cover the insulating layer GI and the semiconductor layers SCO(a, b). A signal line SLb is provided on the insulating layer IL1 so as to overlap a portion of the semiconductor layer SCO(a, b). A drain electrode DE(a, b) is provided on the insulating layer IL1 so as to overlap another portion of the semiconductor layer SCO(a, b).

[0105] An insulating layer IL2 is provided to cover the insulating layer IL1, the signal line SLb, and the drain electrode DE(a, b). An insulating layer INS1 is provided to cover the insulating layer IL2.

[0106] The capacitance electrode YE and the electrode TME are provided on the insulating layer INS1. The capacitance electrode YE, like the pixel electrodes PE(a, b), is a transparent electrode made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The electrode TME is an electrode made of a metal material. Examples of such metal materials include the metal materials described above. Although not shown in FIGS. 6 and 7, the capacitance electrode YE and the electrode TME are provided along the scanning lines GL and the signal lines SL.

[0107] An insulating layer INS2 is provided covering the insulating layer INS1, the capacitive electrode YE, and the electrode TME. A pixel electrode PE(a, b) is provided on the insulating layer INS2, spaced apart from the capacitive electrode YE and the electrode TME. The pixel electrode PE(a, b) is connected to the drain electrode DE(a, b) via a contact hole CHdp provided in the insulating layer IL2, the insulating layer INS1, and the insulating layer INS2. Although not shown in FIGS. 6 and 7, the pixel electrode PE does not overlap the scanning line GL and the signal line SL in a plan view.

[0108] The insulating layers GI, IL1, IL2, and INS2 are formed of, for example, an inorganic insulating material. More specifically, the insulating layers GI, IL1, IL2, and INS2 may be formed of silicon oxide or silicon nitride. The insulating layer INS1 is formed of, for example, an organic insulating material. More specifically, the insulating layer INS1 may be formed of polyimide resin, acrylic resin, or the like. The insulating layer INS1 also functions as a planarizing film.

[0109] Fig. 9 is a cross-sectional view of the display device taken along line B1-B2 shown in Fig. 7. The display device DSP shown in Fig. 9 includes a substrate BA1, a scanning line GLa, a connection electrode GCEb-1, an insulating layer GI, an insulating layer IL1, a signal line SLb-2, an insulating layer IL2, an electrode GUEb-2, an insulating layer INS1, and an insulating layer INS2.

[0110] A scanning line GLa is provided on a base material BA1. An insulating layer IL1 is provided covering the base material BA1 and the scanning line GLa. Two signal lines SLb-2 are provided on the insulating layer IL1. The two signal lines SLb-2 are provided at a distance from each other with the scanning line GLa sandwiched therebetween.

[0111] An insulating layer IL2 is provided covering the signal line SLb-2 and the insulating layer IL1. An electrode GUEb-2 is provided above the scanning line GLa, sandwiching the insulating layer IL2. The electrode GUEb-2 is connected to the two signal lines SLb-2 via contact holes CHsu1 and CHsu2, respectively, provided in the insulating layer IL2.

[0112] An insulating layer INS1 is provided to cover the insulating layer IL1 and the electrode GUEb-2. An insulating layer INS2 is provided on the insulating layer INS1.

[0113] Fig. 10 is a cross-sectional view of the display device taken along line C1-C2 shown in Fig. 7. The display device DSP shown in Fig. 10 includes a base material BA1, a scanning line GLa, a connection electrode GCEb-1, an insulating layer GI, an insulating layer IL1, a signal line SLb-1, a connection electrode SCEb-1, a signal line SLb-2, an insulating layer IL2, a connection electrode GUEb-1, an insulating layer INS1, and an insulating layer INS2.

[0114] The scanning line GLa and the connection electrode GCEb-1 are provided on the base material BA1. The scanning line GLa and the connection electrode GCEb-1 are spaced apart from each other. An insulating layer GI is provided to cover the base material BA1, the scanning line GLa, and the connection electrode GCEb-1.

[0115] An insulating layer IL1 is provided to cover the insulating layer GI. A connection electrode SCEb-1 and two signal lines SLb-1 are provided on the insulating layer IL1. An insulating layer IL2 is provided to cover the insulating layer IL1, the connection electrode SCEb-1, and the two signal lines SLb-1.

[0116] An electrode GUEb-1 is provided above the scan line GLa with an insulating layer IL2 sandwiched therebetween. An insulating layer INS1 is provided covering the insulating layer IL2 and the electrode GUEb-1. An insulating layer INS2 is provided on the insulating layer INS1.

[0117] The connection electrode GUEb-1 is connected to the signal line SLb-1 via a contact hole CHsu3 provided in the insulating layer IL2. The connection electrode GUEb-1 is connected to the connection electrode SCEb-1 via a contact hole CHsu4 provided in the insulating layer IL2.

[0118] The connection electrode SCEb-1 is connected to the connection electrode GCEb-1 via a contact hole CHgs1 provided in the insulating layers GI and IL1, and to the signal line SLb-1 via a contact hole CHgs2 provided in the insulating layers GI and IL1.

[0119] The signal line SLb-2, the connection electrode GUEb-2, the connection electrode SCEb-2, and the connection electrode GCEb-2 are connected to each other and function as a single signal line. Therefore, the signal line SLb-2, the connection electrode GUEb-2, the connection electrode SCEb-2, and the connection electrode GCEb-2 can all be collectively referred to as the signal line SLb-2.

[0120] The signal line SLb-1, the connection electrode GUEb-1, the connection electrode SCEb-1, and the connection electrode GCEb-1 are connected to each other and function as a single signal line. Therefore, the signal line SLb-1, the connection electrode GUEb-1, the connection electrode SCEb-1, and the connection electrode GCEb-1 can all be collectively referred to as the signal line SLb-1.

[0121] The signal line SLb and the connection electrode GUEb are connected to each other and function as one signal line. Therefore, the signal line SLb and the connection electrode GUEb together can be said to be the signal line SLb.

[0122] The signal line SLb+1, the connection electrode GUEb+1, the connection electrode SCEb+1, and the connection electrode GCEb+1 are connected to each other and function as a single signal line. Therefore, the signal line SLb+1, the connection electrode GUEb+1, the connection electrode SCEb+1, and the connection electrode GCEb+1 can all be collectively referred to as the signal line SLb+1.

[0123] The signal line SLb+2, the connection electrode GUEb+2, the connection electrode SCEb+2, and the connection electrode GCEb+2 are connected to each other and function as a single signal line. Therefore, the signal line SLb+2, the connection electrode GUEb+2, the connection electrode SCEb+2, and the connection electrode GCEb+2 can all be collectively referred to as the signal line SLb+2.

[0124] The signal line SLb+3 and the connection electrode GUEb+3 are connected together and function as one signal line. Therefore, the signal line SLb+3 and the connection electrode GUEb+3 together can be said to be the signal line SLb+3.

[0125] As shown in Figures 6, 7, 8, 9, and 10, by arranging the signal lines SL, the connection electrodes GCE, the connection electrodes SCE, and the connection electrodes GUE, three adjacent signal lines SL can be arranged without short-circuiting.

[0126] Fig. 11 is a plan view showing an example of the connection relationship between pixels and signal lines. In the example shown in Fig. 11, pixels PX are arranged in 9 rows and 3 columns. However, the embodiment is not limited to this, and it is sufficient if the pixel has any number of rows and any number of columns. In the explanation of Fig. 11, k is a natural number equal to or greater than 2.

[0127] In the example shown in Fig. 11, the pixels PX arranged in the first row are, from left to right on the page, pixel PX(a-1, 3k+2), pixel PX(a-1, 3(k+1)+2), and pixel PX(a-1, 3(k+2)+2). Although not shown to make the drawing easier to understand, pixel PX(a-1, 3k+2), pixel PX(a-1, 3(k+1)+2), and pixel PX(a-1, 3(k+2)+2) are connected to the same scanning line.

[0128] The pixels PX on the second row are, from left to right on the page, pixel PX(a,3(k-1)+1), pixel PX(a,3k+1), and pixel PX(a,3(k+1)+1). Pixels PX(a,3(k-1)+1), pixel PX(a,3k+1), and pixel PX(a,3(k+1)+1) are connected to the same scanning line.

[0129] The pixels PX on the third row are, from left to right on the page, pixel PX(a+1,3k), pixel PX(a+1,3(k+1)), and pixel PX(a+1,3(k+2)). Pixels PX(a+1,3k), pixel PX(a+1,3(k+1)), and pixel PX(a+1,3(k+2)) are connected to the same scanning line.

[0130] The pixels PX on the fourth row are, from left to right on the page, pixel PX(a+2,3(k-1)+2), pixel PX(a+2,3k+2), and pixel PX(a+2,3(k+1)+2). Pixels PX(a+2,3(k-1)+2), pixel PX(a+2,3k+2), and pixel PX(a+2,3(k+1)+2) are connected to the same scanning line.

[0131] The pixels PX on the fifth row are, from left to right on the page, pixel PX(a+3,3k+1), pixel PX(a+3,3(k+1)+1), and pixel PX(a+3,3(k+2)+1). Pixels PX(a+3,3k+1), pixel PX(a+3,3(k+1)+1), and pixel PX(a+3,3(k+2)+1) are connected to the same scanning line.

[0132] The pixels PX on the sixth row are, from left to right on the page, pixel PX(a+4,3(k-1)), pixel PX(a+4,3k), and pixel PX(a+4,3(k+1)). Pixels PX(a+4,3(k-1)), pixel PX(a+4,3k), and pixel PX(a+4,3(k+1)) are connected to the same scanning line.

[0133] The pixels PX on the seventh row are, from left to right on the page, pixel PX(a+5,3k+2), pixel PX(a+5,3(k+1)+2), and pixel PX(a+5,3(k+2)+2). Pixels PX(a+5,3k+2), pixel PX(a+5,3(k+1)+2), and pixel PX(a+5,3(k+2)+2) are connected to the same scanning line.

[0134] The pixels PX on the 8th row are, from left to right on the page, pixel PX(a+6,3(k-1)+1), pixel PX(a+6,3k+1), and pixel PX(a+6,3(k+1)+1). Pixels PX(a+6,3(k-1)+1), pixel PX(a+6,3k+1), and pixel PX(a+6,3(k+1)+1) are connected to the same scanning line.

[0135] The pixels PX on the 9th row are, from left to right on the page, pixel PX(a+7,3k), pixel PX(a+7,3(k+1)), and pixel PX(a+7,3(k+2)). Pixels PX(a+7,3k), pixel PX(a+7,3(k+1)), and pixel PX(a+7,3(k+2)) are connected to the same scanning line.

[0136] In other words, in the first column, which is the far left on the paper, from the top (first row) to the bottom (ninth row) of the paper, there are pixels PX(a-1, 3k+2), PX(a, 3(k-1)+1), PX(a+1, 3k), PX(a+2, 3(k-1)+2), PX(a+3, 3k+1), PX(a+4, 3(k-1)), PX(a+5, 3k+2), PX(a+6, 3(k-1)+1), and PX(a+7, 3k).

[0137] In the second column, from the first row to the ninth row, there are provided pixels PX(a-1, 3(k+1)+2), PX(a, 3k+1), PX(a+1, 3(k+1)), PX(a+2, 3k+2), PX(a+3, 3(k+1)+1), PX(a+4, 3k), PX(a+5, 3(k+1)+2), PX(a+6, 3k+1), and PX(a+7, 3(k+1).

[0138] In the third column, from the first row to the ninth row, there are pixels PX(a-1, 3(k+2)+2), pixel PX(a, 3(k+1)+1), pixel PX(a+1, 3(k+2)), pixel PX(a+2, 3(k+1)+2), pixel PX(a+3, 3(k+2)+1), pixel PX(a+4, 3(k+1)), pixel PX(a+5, 3(k+2)+2), pixel PX(a+6, 3(k+1)+1), and pixel PX(a+7, 3(k+2)).

[0139] In the example shown in FIG. 11, signal line SL(3(k-1)) is connected to pixel PX(a+4, 3(k-1)). Signal line SL(3(k-1)+1) is connected to pixel PX(a, 3(k-1)+1) and pixel PX(a+6, 3(k-1)+1). Signal line SL(3(k-1)+2) is connected to pixel PX(a+2, 3(k-1)+2).

[0140] The signal line SL(3k) is connected to the pixels PX(a+1,3k), PX(a+4,3k), and PX(a+7,3k). The signal line SL(3k+1) is connected to the pixels PX(a,3k+1), PX(a+3,3k+1), and PX(a+6,3k+1). The signal line SL(3k+2) is connected to the pixels PX(a-1,3k+2), PX(a+2,3k+2), and PX(a+5,3k+2).

[0141] The signal line SL(3(k+1)) is connected to the pixel PX(a+1,3(k+1)), the pixel PX(a+4,3(k+1)), and the pixel PX(a+7,3(k+1)). The signal line SL(3(k+1)+1) is connected to the pixel PX(a,3(k+1)+1), the pixel PX(a+3,3(k+1)+1), and the pixel PX(a+6,3(k+1)+1). The signal line SL(3(k+1)+2) is connected to the pixel PX(a-1,3(k+1)+2), the pixel PX(a+2,3(k+1)+2), and the pixel PX(a+5,3(k+1)+2).

[0142] The signal line SL(3(k+2)) is connected to the pixel PX(a+1, 3(k+2)) and the pixel PX(a+7, 3(k+2)). The signal line SL(3(k+2)+1) is connected to the pixel PX(a+3, 3(k+2)+1). The signal line SL(3(k+2)+2) is connected to the pixel PX(a-1, 3(k+2)+2) and the pixel PX(a+5, 3(k+2)+2).

[0143] Among the multiple pixels PX shown in FIG. 11, the signal line SL connected to the pixel PX in a specific row is different from the signal line SL connected to the pixel PX arranged in a row adjacent to the pixel PX in the specific row. For example, pixel PX(a, 3k+1) is compared with pixels in the same column and adjacent row, i.e., pixel PX(a-1, 3(k+1)+2) and pixel PX(a+1, 3(k+1)). Pixel PX(a-1, 3(k+1)+2) is connected to signal line SL(3(k+1)+2) which is different from signal line SL(3k+1). Pixel PX(a+1, 3(k+1)) is connected to signal line SL(3(k+1)) which is different from signal line SL(3k+1).

[0144] 11, signal line SL(3k), which is one of signal lines SL(3k), signal line SL(3k+1), and signal line SL(3k+2), is connected to pixel PX(a+4,3k) in the same column as pixel PX(a,3k+1) but in a non-adjacent row. Signal line SL(3k+2) is connected to pixel PX(a+2,3k+2) in the same column as pixel PX(a,3k+1) but in a non-adjacent row.

[0145] According to the embodiment, it is possible to obtain a display device that ensures sufficient time for writing video signals to pixels and does not increase the number of signal lines.

[0146] In this specification, the connection electrode GUE, the connection electrode SCE, and the connection electrode GCE are also referred to as the first connection electrode, the second connection electrode, and the third connection electrode, respectively.

[0147] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0148] DSP...display device, GCE...connecting electrode, GL...scanning line, GUE...connecting electrode, PX...pixel, PXB...pixel, PXG...pixel, PXR...pixel, SCE...connecting electrode, SL...signal line, SLB...signal line, SLG...signal line, SLR...signal line, SW...switching element.

Claims

1. a plurality of scanning lines extending along a first direction and arranged along a second direction intersecting the first direction; a plurality of signal lines extending along the second direction and arranged in groups of three along the first direction; a plurality of pixels provided at intersections of the plurality of scanning lines and the plurality of signal lines, and arranged in a matrix with a plurality of rows arranged side by side along the second direction and a plurality of columns arranged side by side along the first direction; a plurality of switching elements included in the plurality of pixels; a plurality of semiconductor layers included in the plurality of switching elements; Equipped with One of the signal lines arranged in groups of three is connected to pixels in a predetermined row, The display device, wherein the other two signal lines of the three signal lines arranged in groups are connected to pixels in the same column as the pixels in the predetermined row but in two different rows.

2. 2. The display device according to claim 1, wherein the signal lines include a first connection electrode provided in a layer different from the scanning lines, a second connection electrode provided in the same layer as the signal lines, and a third connection electrode provided in the same layer as the scanning lines.

3. The display device according to claim 1 , wherein the plurality of scanning lines are connected in groups of three.

Images