Display panel and display device including the same

Abstract

The present disclosure relates to a display panel and a display device including the same, in which each pixel includes: sub-pixels of a first color including a first sub-pixel and a first second sub-pixel; the sub-pixels of the second color comprise second first sub-pixels and second second sub-pixels; and sub-pixels of a third color including a third first sub-pixel and a third second sub-pixel. The gate line includes: a first EM line connected to a sub-pixel of a first color and to which a first light emission signal is applied; and a second EM line connected to the sub-pixel of the second color and to which a second light emission signal is applied.

Description

Technical Field

[0001] The present disclosure relates to a display panel and a display device including the display panel. Background Art

[0002] Various flat panel display devices are known, such as liquid crystal display devices and electroluminescent display devices. Electroluminescent display devices use a light-emitting element arranged in each pixel to emit light, eliminating the need for a backlight, thereby displaying an input image. The light-emitting elements of electroluminescent display devices can be categorized as organic or inorganic, depending on the material used in the light-emitting layer.

[0003] Recently, display devices using light-emitting diodes (LEDs), which are inorganic light-emitting elements, as pixel light-emitting elements have attracted attention as next-generation display devices. Because LEDs are made of inorganic materials, they do not require a separate encapsulation layer to protect the organic material from moisture and have excellent reliability and long life compared to organic light-emitting diodes (OLEDs). In addition, LEDs have a fast lighting speed, excellent luminous efficiency, and impact resistance.

[0004] For inorganic light-emitting devices such as micro-LEDs, the luminous efficiency of the light-emitting element can vary depending on the wavelength of the light emitted by the light-emitting element, depending on the material properties of the light-emitting layer. Luminous efficiency is the efficiency expressed as brightness relative to the current applied to the light-emitting element.

[0005] Within a frame period, the pixel circuit's drive period can be divided into a light-emitting period and a period for writing pixel data for the input image. Certain light-emitting elements have peak efficiency bands at higher voltages, but as the voltage increases, the brightness can become too high, causing color coordinates and white balance to deviate from target values, resulting in degraded image quality. Summary of the Invention

[0006] The present disclosure is directed to addressing the above-mentioned needs and / or problems.

[0007] The present disclosure provides a display panel capable of driving each light emitting element in a maximum efficiency region without deteriorating image quality, and a display device including the display panel.

[0008] Problems to be solved by the present disclosure are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

[0009] A display panel according to one embodiment of the present disclosure includes: a plurality of data lines; a plurality of gate lines intersecting the data lines; a plurality of power lines; and a plurality of pixels connected to their corresponding data lines, gate lines, and power lines. Each pixel includes a subpixel of a first color, including a first subpixel, a first second subpixel, and a second subpixel; a subpixel of a second color, including a second first subpixel and a second second subpixel; and a subpixel of a third color, including a third first subpixel and a third second subpixel. The gate lines include a first EM line and a second EM line. The first EM line is connected to the subpixel of the first color and is applied with a first luminescence signal, and the second EM line is connected to the subpixel of the second color and is applied with a second luminescence signal.

[0010] The light emission signal may have a duty ratio independently set for each color of the sub-pixel.

[0011] The second EM line may be connected to the sub-pixel of the second color and the sub-pixel of the third color.

[0012] The gate line may further include a third EM line connected to a sub-pixel of a third color and applied with a third EM signal.

[0013] The first first sub-pixel and the first second sub-pixel may be connected to a common data line or to different data lines. The second first sub-pixel and the second second sub-pixel may be connected to a common data line or to different data lines. The third first sub-pixel and the third second sub-pixel may be connected to a common data line or to different data lines.

[0014] The gate line may further include a scan line connected to the first first sub-pixel, the first second sub-pixel, the second first sub-pixel, the second second sub-pixel, the third first sub-pixel, and the third second sub-pixel and to which a scan signal is applied.

[0015] The scan lines may include: a first scan line configured to apply a first scan signal to the first first subpixel, the first second subpixel, the second first subpixel, the second second subpixel, the third first subpixel and the third second subpixel; and a second scan line configured to apply a second scan signal to the first first subpixel, the first second subpixel, the second first subpixel, the second second subpixel, the third first subpixel and the third second subpixel.

[0016] The gate lines may include a first group of gate lines connected to the first first sub-pixel, the second first sub-pixel, and the third first sub-pixel; and a second group of gate lines connected to the first second sub-pixel, the second second sub-pixel, and the third second sub-pixel. The first group of gate lines may include scan lines configured to apply scan signals to the first first sub-pixel, the second first sub-pixel, and the third first sub-pixel. The second group of gate lines may include scan lines configured to apply scan signals to the first second sub-pixel, the second second sub-pixel, and the third second sub-pixel.

[0017] The first group of gate lines may include: a first scan line configured to apply a first scan signal to the first first sub-pixel, the second first sub-pixel, and the third first sub-pixel; and a second scan line configured to apply a second scan signal to the first first sub-pixel, the second first sub-pixel, and the third first sub-pixel. The second group of gate lines may include: a first scan line configured to apply a first scan signal to the first second sub-pixel, the second second sub-pixel, and the third second sub-pixel; and a second scan line configured to apply a second scan signal to the first second sub-pixel, the second second sub-pixel, and the third second sub-pixel.

[0018] Each of the first and second subpixels may include a light emitting element and a driving transistor configured to drive the light emitting element. A channel ratio of the driving transistor provided in the first second subpixel is smaller than a channel ratio of the driving transistor provided in the first first subpixel.

[0019] A display device according to one embodiment of the present disclosure includes: a display panel in which a plurality of data lines, a plurality of gate lines, a plurality of power lines, and a plurality of pixels are arranged; a data driver configured to output data voltages to the data lines; and a gate driver configured to output gate signals to the gate lines. Each of the pixels includes a sub-pixel of a first color, a sub-pixel of a second color, and a sub-pixel of a third color.

[0020] Only one of the first subpixel and the first second subpixel may be driven.The first first subpixel and the first second subpixel may be alternately driven with a cycle of a predetermined period, or the first first subpixel and the first second subpixel may be driven simultaneously.

[0021] When only one of the first and second subpixels is driven, pixel data of an input image may be written into one of the first and second subpixels, and black grayscale data may be written into the other subpixel.

[0022] During the n-th frame period (where n is a natural number), pixel data of the n-th frame image can be written into the first first sub-pixel, the second first sub-pixel, and the third first sub-pixel, a first light-emitting signal can be applied to the first second sub-pixel, and a second light-emitting signal can be applied to the second second sub-pixel and the third second sub-pixel, so that the first second sub-pixel, the second second sub-pixel, and the third second sub-pixel emit light. During the (n+1)-th frame period, pixel data of the (n+1)-th frame image can be written into the first second sub-pixel, the second second sub-pixel, and the third second sub-pixel, a first light-emitting signal can be applied to the first first sub-pixel, and a second light-emitting signal can be applied to the second first sub-pixel and the third first sub-pixel, so that the first first sub-pixel, the second first sub-pixel, and the third first sub-pixel emit light.

[0023] The duty ratio of the first light emitting signal may be different from the duty ratio of the second light emitting signal.

[0024] Each of the sub-pixels may include a light emitting element including an anode to which a pixel driving voltage is applied; a switching transistor to which a ground voltage is applied; and a driving transistor connected between a cathode of the light emitting element and the switching transistor.

[0025] Each of the sub-pixels may include a light emitting element including a cathode to which a ground voltage is applied; a driving transistor to which a pixel driving voltage is applied; and a switching transistor connected between the driving transistor and an anode of the light emitting element.

[0026] A display panel according to another embodiment of the present disclosure includes a plurality of data lines; a plurality of gate lines intersecting the plurality of data lines, the plurality of gate lines including a first light-emitting line applying a first light-emitting signal and a second light-emitting line applying a second light-emitting signal; and a plurality of pixels connected to the plurality of data lines and the plurality of gate lines. Each of the plurality of pixels includes a subpixel of a first color, the subpixel of the first color including a first-first subpixel and a second-first subpixel; a subpixel of a second color including a primary-second subpixel and a secondary-second subpixel; and a subpixel of a third color including a primary-third subpixel and a secondary-third subpixel. The first light-emitting line is connected to the subpixel of the first color, and the second light-emitting line is connected to the subpixel of the second color. The maximum possible voltage of the first data voltage applied to the subpixel of the first color is greater than the maximum possible voltage of the subpixel of the second color and the subpixel of the third color, and the first duty cycle of the first light-emitting signal is less than the second duty cycle of the second light-emitting signal.

[0027] The second light emitting line may be connected to the sub-pixel of the second color and the sub-pixel of the third color.

[0028] The plurality of gate lines may further include a third light emitting line to which a third light emitting signal is applied, the third light emitting line being connected to a sub-pixel of a third color.

[0029] The primary first subpixel and the secondary first subpixel may be connected to a first data line among the plurality of data lines. The primary second subpixel and the secondary second subpixel may be connected to a second data line among the plurality of data lines. The primary third subpixel and the secondary third subpixel may be connected to a third data line among the plurality of data lines. The plurality of gate lines may include scan lines connected to the primary first subpixel, the secondary first subpixel, the primary second subpixel, the secondary second subpixel, the primary third subpixel, and the secondary third subpixel.

[0030] The primary first subpixel may be connected to a first data line from a plurality of data lines, and the secondary first subpixel may be connected to a second data line from the plurality of data lines. The primary second subpixel may be connected to a third data line from the plurality of data lines, and the secondary second subpixel may be connected to the third data line. The primary third subpixel and the secondary third subpixel may be connected to a fourth data line from the plurality of data lines. The plurality of gate lines may include scan lines connected to the primary first subpixel, the secondary first subpixel, the primary second subpixel, the secondary second subpixel, the primary third subpixel, and the secondary third subpixel.

[0031] The primary first subpixel may be connected to a first data line from a plurality of data lines, and the secondary first subpixel may be connected to a second data line from the plurality of data lines. The primary second subpixel may be connected to a third data line from the plurality of data lines, and the secondary second subpixel may be connected to a fourth data line from the plurality of data lines. The primary third subpixel and the secondary third subpixel may be connected to a fifth data line from the plurality of data lines. The plurality of gate lines include scan lines connected to the primary first subpixel, the secondary first subpixel, the primary second subpixel, the secondary second subpixel, the primary third subpixel, and the secondary third subpixel.

[0032] The primary first subpixel may be connected to a first data line from a plurality of data lines, and the secondary first subpixel may be connected to a second data line from the plurality of data lines. The primary second subpixel may be connected to a third data line from the plurality of data lines, and the secondary second subpixel may be connected to a fourth data line from the plurality of data lines. The primary third subpixel may be connected to a fifth data line from the plurality of data lines, and the secondary third subpixel may be connected to a sixth data line from the plurality of data lines. The plurality of gate lines may include scan lines connected to the primary first subpixel, the secondary first subpixel, the primary second subpixel, the secondary second subpixel, the primary third subpixel, and the secondary third subpixel.

[0033] The primary first subpixel and the secondary first subpixel may be connected to a first data line among the plurality of data lines. The primary second subpixel and the secondary second subpixel may be connected to a second data line among the plurality of data lines. The primary third subpixel and the secondary third subpixel may be connected to a third data line among the plurality of data lines. The plurality of gate lines may include a first scan line connected to the primary first subpixel, the primary second subpixel, and the primary third subpixel, and a second scan line connected to the secondary first subpixel, the secondary second subpixel, and the secondary third subpixel.

[0034] The primary first subpixel may be connected to a first data line from a plurality of data lines, and the secondary first subpixel may be connected to a second data line from the plurality of data lines. The primary second subpixel may be connected to a third data line from the plurality of data lines, and the secondary second subpixel may be connected to the third data line. The primary third subpixel and the secondary third subpixel may be connected to a fourth data line from the plurality of data lines. The plurality of gate lines may include a first scan line connected to the primary first subpixel, the primary second subpixel, and the primary third subpixel, and a second scan line connected to the secondary first subpixel, the secondary second subpixel, and the secondary third subpixel.

[0035] The primary first subpixel may be connected to a first data line from a plurality of data lines, and the secondary first subpixel may be connected to a second data line from the plurality of data lines. The primary second subpixel may be connected to a third data line from the plurality of data lines, and the secondary second subpixel may be connected to a fourth data line from the plurality of data lines. The primary third subpixel and the secondary third subpixel may be connected to a fifth data line from the plurality of data lines. The plurality of gate lines may include a first scan line connected to the primary first subpixel, the primary second subpixel, and the primary third subpixel, and a second scan line connected to the secondary first subpixel, the secondary second subpixel, and the secondary third subpixel.

[0036] The primary first subpixel may be connected to a first data line from a plurality of data lines, and the secondary first subpixel may be connected to a second data line from the plurality of data lines. The primary second subpixel may be connected to a third data line from the plurality of data lines, and the secondary second subpixel may be connected to a fourth data line from the plurality of data lines. The primary third subpixel may be connected to a fifth data line from the plurality of data lines, and the secondary third subpixel may be connected to a sixth data line from the plurality of data lines. The plurality of gate lines may include a first scan line connected to the primary first subpixel, the primary second subpixel, and the primary third subpixel, and a second scan line connected to the secondary first subpixel, the secondary second subpixel, and the secondary third subpixel.

[0037] Each of the primary first sub-pixel and the secondary first sub-pixel may include a light emitting element and a driving transistor configured to drive the light emitting element. A channel ratio of the driving transistor in the secondary first sub-pixel is smaller than a channel ratio of the driving transistor in the primary first sub-pixel.

[0038] According to an embodiment of the present disclosure, the life of the light-emitting element can be improved and the light-emitting element can be driven at low power by driving the light-emitting element with high efficiency and high brightness, and a pixel circuit capable of driving each light-emitting element in the maximum efficiency area without deteriorating image quality and a display device including the pixel circuit can be realized.

[0039] According to an embodiment of the present disclosure, multiple sub-pixels of the same color within one pixel can be arranged to effectively respond to the elimination of defects in a light emitting element or pixel circuit, thereby improving process optimization and yield of a display panel.

[0040] According to an embodiment of the present disclosure, image quality can be improved by driving sub-pixels of the same color within one pixel in various combinations.

[0041] According to an embodiment of the present disclosure, sub-pixels of the same color within a pixel may be alternately driven to prevent object image tearing or the appearance of boundaries within an object when displaying an image on a tiled display.

[0042] The effects of the present disclosure are not limited to the above-mentioned effects, and other effects not mentioned will be apparently understood by those skilled in the art from the following description and the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The above and other objects, features and advantages of the present disclosure will become more apparent to those skilled in the art by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0044] Figure 1A and Figure 1B is a block diagram illustrating a display device according to one embodiment of the present disclosure;

[0045] Figure 2 is a diagram showing an example of a tiled display;

[0046] Figure 3A 、 Figure 3B 、 Figure 3C 、 Figure 3D 、 Figure 4A 、 Figure 4B 、 Figure 4C 、 Figure 4D 、 Figure 5A 、 Figure 5B 、 Figure 5C and Figure 5Dis a diagram illustrating a unit pixel structure according to various embodiments of the present disclosure;

[0047] Figure 6 is a diagram schematically showing an example in which the channel ratios of driving transistors are different from each other;

[0048] Figure 7 、 Figure 8 and Figure 9 is a flowchart illustrating a method of driving a sub-pixel according to various embodiments of the present disclosure;

[0049] Figure 10 is a graph showing the difference in luminous efficiency of light-emitting elements of each color;

[0050] Figure 11 is a diagram showing an example of color-specific data voltages;

[0051] Figure 12A and Figure 12B is a diagram showing one example of a wiring structure for applying a color-specific light emission signal to a sub-pixel;

[0052] Figure 13 It shows Figure 12A and Figure 12B A waveform diagram of an example of a color-specific luminescence signal shown in FIG;

[0053] Figure 14A and Figure 14B is a diagram showing another example of a wiring structure for applying a color-specific light emitting signal to a sub-pixel;

[0054] Figure 15 It shows Figure 14A and Figure 14B A waveform diagram of an example of a color-specific luminescence signal is shown;

[0055] Figure 16 is a circuit diagram showing a pixel circuit according to one embodiment of the present disclosure;

[0056] Figure 17 It is shown that it is applicable to Figure 16 A circuit diagram of an example of a pixel circuit is shown;

[0057] Figure 18A and Figure 18B It shows Figure 16 FIG. 1 is a diagram of a first initialization step of a pixel circuit shown;

[0058] Figure 19A and Figure 19B It shows Figure 16 FIG. 1 is a diagram of a second initialization step of a pixel circuit shown;

[0059] Figure 20Aand Figure 20B It shows Figure 16 A diagram of the sampling steps of the pixel circuit shown;

[0060] Figure 21A and Figure 21B It shows Figure 16 FIG. 1 is a diagram showing a holding step of a pixel circuit shown;

[0061] Figure 22A and Figure 22B It shows Figure 16 FIG. 1 is a diagram illustrating a light emitting step of a pixel circuit shown;

[0062] Figure 23 is a circuit diagram showing a pixel circuit according to another embodiment of the present disclosure;

[0063] Figure 24 It is shown that it is applicable to Figure 23 A circuit diagram of an example of a pixel circuit is shown;

[0064] Figure 25A and Figure 25B It shows Figure 24 FIG. 1 is a diagram showing an initialization step of a pixel circuit;

[0065] Figure 26A and Figure 26B It shows Figure 24 A diagram of a first holding step of a pixel circuit shown;

[0066] Figure 27A and Figure 27B It shows Figure 24 A diagram of the sampling steps of the pixel circuit shown;

[0067] Figure 28A and Figure 28B It shows Figure 24 FIG2 is a diagram of a second holding step of a pixel circuit shown;

[0068] Figure 29A and Figure 29B It shows Figure 24 FIG. 1 is a diagram illustrating a light emitting step of a pixel circuit shown;

[0069] Figure 30 is a waveform diagram showing an example of alternately driving a main sub-pixel and a redundant sub-pixel in a cycle of a predetermined time period; and

[0070] Figure 31 Is shown by Figure 30 The diagram shows an example of an alternating driving method in which all pixels emit light simultaneously. DETAILED DESCRIPTION

[0071] The advantages and features of the present disclosure and the methods for achieving the advantages and features of the present disclosure will be more clearly understood from the embodiments described below with reference to the accompanying drawings. However, the present disclosure is not limited to the following embodiments, but can be implemented in a variety of different forms. On the contrary, the present embodiments will complete the disclosure of the present disclosure and allow those skilled in the art to fully understand the scope of the present disclosure. The present disclosure is limited only within the scope of the appended claims.

[0072] The shapes, sizes, ratios, angles, quantities, etc. shown in the drawings used to describe the embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout this specification, the same reference numerals generally represent the same elements. In addition, when describing the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure.

[0073] As used herein, terms such as "include," "comprising," "having," and "containing" are generally intended to allow for the addition of additional components unless such terms are used with the term "only." Any reference to the singular includes the plural unless expressly stated otherwise.

[0074] Even if not explicitly stated, the components are interpreted as including the ordinary error range.

[0075] When describing a position or interconnection relationship between two components, such as "on top of," "above," "below," "immediately adjacent," "connected or coupled to," "crossing," "intersecting," etc., one or more other components may be interposed between them unless "immediately" or "directly" is used.

[0076] When describing a temporal precedence relationship such as "after," "subsequently," "then," "next," "before," etc., it may not be continuous in time base unless "immediately" or "directly" is used.

[0077] Terms such as “first” and “second” may be used to distinguish elements from each other, but the function or structure of a component is not limited by the preceding sequence numbers or names of the components.

[0078] The following embodiments may be partially or completely combined or combined with each other, and may be technically linked and operated in various ways. The embodiments may be performed independently or in association with each other.

[0079] A pixel circuit in a display device may include multiple transistors. A transistor is a three-electrode element consisting of a gate, a source, and a drain. The source is the electrode that supplies carriers to the transistor. In a transistor, carriers begin flowing from the source. The drain is the electrode through which carriers exit the transistor. In a transistor, carriers flow from the source to the drain. In an n-channel transistor, since the carriers are electrons, the source voltage is lower than the drain voltage, allowing electrons to flow from the source to the drain. An n-channel transistor has a current flow direction from the drain to the source. In a p-channel transistor (p-channel metal oxide semiconductor (PMOS)), since the carriers are holes, the source voltage is higher than the drain voltage, allowing holes to flow from the source to the drain. In a p-channel transistor, since holes flow from the source to the drain, current flows from the source to the drain. It is important to note that the source and drain of a transistor are not fixed. For example, the source and drain can be changed depending on the applied voltage. Therefore, the present disclosure is not limited to the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as the first electrode and the second electrode.

[0080] The gate signal swings between a gate-on voltage and a gate-off voltage. The transistor turns on in response to the gate-on voltage and turns off in response to the gate-off voltage. In the case of an n-channel transistor, the gate-on voltage can be a gate high voltage VGH, and the gate-off voltage can be a gate low voltage VGL. In the case of a p-channel transistor, the gate-on voltage can be a gate low voltage VGL, and the gate-off voltage can be a gate high voltage VGH.

[0081] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0082] refer to Figure 1A and Figure 1B A display device according to one embodiment of the present disclosure includes a display panel 100, a display panel driving circuit for writing pixel data to pixels 101 of the display panel 100, and a power supply 140 for generating power required to drive the pixels 101 and the display panel driving circuit.

[0083] The substrate of the display panel 100 may be a plastic substrate, a thin glass substrate, or a metal substrate, but is not limited thereto. The display panel 100 may be a rectangular panel having a length in the X-axis direction (or the first direction), a width in the Y-axis direction (or the second direction), and a thickness in the Z-axis direction (or the third direction), but is not limited thereto. For example, at least a portion of the display panel 100 may have a curved periphery.

[0084] The display panel 100 can be implemented as a non-transmissive display panel or a transmissive display panel. A transmissive display panel can be applied to a transparent display device, where an image is displayed on a screen and real objects outside the display panel are visible. The display panel 100 can be manufactured as a flexible display panel. In addition, the display panel 100 can be manufactured as a stretchable panel that can be extended.

[0085] The display area AA of the display panel 100 includes a pixel array that displays an input image. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 intersecting the data lines 102, and pixels 101 arranged in a matrix. The display panel 100 may also include power lines commonly connected to the pixels 101. The power lines are commonly connected to the pixels 101 to supply the pixels with a constant voltage required to drive the pixels 101. The power lines can be implemented as long strips of wiring along the first direction or the second direction, or can be implemented as grid wiring in which wiring along the first direction is electrically connected to wiring along the second direction.

[0086] Each of the pixels 101 can be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel for color realization. Each of the pixels can also include a white sub-pixel. Each of the sub-pixels includes a pixel circuit for driving a light-emitting element. The pixel circuit is connected to a data line, a gate line, and a power line. Hereinafter, "pixel" may be interpreted as "sub-pixel."

[0087] The pixel array includes a plurality of pixel rows L1 to L(N). Each of the pixel rows L1 to L(N) includes a row of pixels arranged along the gate line direction (X-axis direction) in the pixel array of the display panel 100. The pixels arranged in one pixel row can share a gate line 103. Pixels arranged in the column direction (Y-axis direction) along the data line direction can share the same data line 102. One horizontal period is the time obtained by dividing one frame period by the total number of pixel rows L1 to L(N).

[0088] The power supply 140 uses a DC-DC converter to generate a constant voltage (or direct current (DC) voltage) required to drive the pixel array and display panel driving circuit of the display panel 100. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply 140 can adjust the level of the input voltage input from the host system 200 to output a constant voltage, such as a gamma reference voltage, a data drive voltage, a gate low voltage, a gate high voltage, a pixel drive voltage, and a pixel base voltage. The gamma reference voltage and the data drive voltage are provided to the data driver 110. The dynamic range of the data voltage output from the data driver 110 is determined by the voltage range of the gamma reference voltage. The dynamic range of the data voltage is the voltage range between the highest grayscale voltage and the lowest grayscale voltage. The data drive voltage is a voltage supplied from each of the channels of the data driver 110 to the VDD terminal of the output buffer to drive the output buffer.

[0089] The gate high voltage and the gate low voltage are supplied to the level shifter 150 and the gate driver 120. Constant voltages such as the pixel driving voltage and the pixel base voltage are supplied to the pixels 101 through power supply lines commonly connected to the pixels 101. The pixel driving voltage can be supplied to the display panel 100 from the main power supply of the host system 200. In this case, the power supply 140 does not need to output the pixel driving voltage.

[0090] The display panel driving circuit writes pixel data of an input image into pixels of the display panel 100 under the control of the timing controller 130. The display panel driving circuit includes a data driver 110 and a gate driver 120.

[0091] The display panel driving circuit may further include a touch sensor driver for driving the touch sensor. Figure 1A and Figure 1B The touch sensor driver is omitted. The data driver 110 and the touch sensor driver can be integrated into a single driver integrated circuit (IC). The timing controller 130, power supply 140, level shifter 150, data driver 110, touch sensor driver, etc. can also be integrated into the driver IC.

[0092] The data driver 110 receives pixel data of an input image as a digital signal from the timing controller 130 and outputs a data voltage. The data driver 110 converts the pixel data of the input image into a gamma compensation voltage using a digital-to-analog converter (DAC) and outputs the data voltage. The gamma reference voltage is divided into a gamma compensation voltage for each grayscale by a voltage divider circuit of the data driver 110 and supplied to the DAC. The DAC generates a data voltage having a gamma compensation voltage corresponding to the grayscale value of the pixel data. The data voltage output from the DAC is output to the data line 102 through an output buffer in each data output channel of the data driver 110.

[0093] The gate driver 120 may be formed in the display panel 100 together with the TFT array and wiring of the pixel array. The gate driver 120 may be disposed in the non-display area NA outside the display area AA of the display panel 100, or at least a portion thereof may be disposed in the display area AA. For example, the gate driver 120 may be embedded in the display area AA, as shown in FIG. Figure 1B In this case, the pixel circuit and the light emitting element of the pixel 101 may overlap with the circuit of the gate driver 120 in the Z-axis direction of the display panel 100 .

[0094] The gate driver 120 may be disposed in the left non-display area NA or the right non-display area NA outside the display area AA of the display panel 100 to provide a gate signal to the gate line 103 using a single feed method. In the single feed method, the gate signal is applied to one end of the gate line. The gate driver 120 may be disposed in the left non-display area NA and the right non-display area NA of the display panel 100 to apply a gate signal to the gate line 103 using a single feed method or a dual feed method. In the dual feed method, the gate signal is applied to both ends of the gate line 103 at the same time. At least some circuits of the gate driver 120 may be disposed within the display area AA.

[0095] The gate driver 120 may include a shift register and / or an edge trigger to output and shift the pulse of the gate signal under the control of the timing controller 130. The gate driver 120 may output a plurality of gate signals having different waveforms. In this case, the gate driver 120 may include a plurality of gate drivers that output different gate signals.

[0096] The strobe signal may include a scan signal SCAN and an EM signal (hereinafter referred to as "EM signal") EM. Figures 3A to 5D The scan signal SCAN may include a first scan signal SCAN1 and a second scan signal SCAN2. Figures 16 to 30 As shown. In this case, the gate driver may include a first gate driver that outputs a first scan signal SCAN1, a second gate driver that outputs a second scan signal SCAN2, and a third gate driver that outputs an EM signal. The EM signal may be independently set for each color of the subpixel to independently control the lighting time and extinguishing time of the light-emitting element for each color of the subpixel. Hereinafter, the EM signal independently set for each color of the subpixel will be referred to as an "EM signal for each color."

[0097] The timing controller 130 receives pixel data of an input image and timing signals synchronized with the pixel data from the host system 200. The timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE. The vertical synchronization signal Vsync indicates a frame period including a pulse generated once per frame period. The pulses of the horizontal synchronization signal Hsync and the data enable signal DE may be one horizontal period (1H). The timing controller 130 may determine a frame period (or vertical period) and a horizontal period by counting the data enable signal DE. In this case, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync may be omitted. The timing controller 130 may determine how many frame periods the current frame period is by counting the rising edge or falling edge of the pulses in the starting pulse of the timing signals Vsync, Hsync, and DE or the strobe timing signal.

[0098] The timing controller 130 can control the operation timing of the data driver 110 and the gate driver 120 based on the timing signals Vsync, Hsync, and DE received from the host system 200. The gate timing control signal includes a start pulse and a clock to control the operation timing of the gate driver 120. The gate timing control signal output from the timing controller 130 can be input to the shift register of the gate driver 120 through the level shifter 150 and can be used to control the pulse of the gate signal output from the gate driver 120. The level shifter 150 can receive the gate timing control signal and generate a clock to provide it to the gate driver 120. The level shifter 150 can be mounted on a control printed circuit board (PCB) together with the timing controller 130 and the power supply 140, or it can be mounted on a source PCB that is electrically connected to a chip on film (COF) on which the data driver 110 is mounted. The input signal of the level shifter 150 is a signal at a digital signal voltage level. The clock output from the level shifter 150 can swing between a gate high voltage and a gate low voltage. The data timing control signal generated from the timing controller 130 is transmitted to the data driver 110 .

[0099] The host system 200 may scale the image signal from the video source to match the resolution of the display panel 100 and may send it to the timing controller 130 along with the timing control signal.

[0100] The display device may be implemented as a tiled display (TD) in which a plurality of display panels are combined in the same plane to provide a wide screen, such as Figure 2 shown.

[0101] Reference Figure 2The widescreen tiled display TD includes a plurality of display panels PNL1 to PNL4 arranged on an XY plane. When the non-display area NA is minimized at the periphery of each display panel PNL1 to PNL4, a widescreen image can be reproduced without visible seams between adjacent display panels PNL1 to PNL4. The gate driver 120 can be embedded in the display area AA of the display panels PNL1 to PNL4, so that the peripheral non-display area NA of the display panels PNL1 to PNL4 can be minimized.

[0102] The display panels 100 can be assembled on a plane so that the distance D1 between the outermost pixels 101 adjacent at the boundaries between adjacent display panels PNL1 to PNL4 is substantially the same as the distance D2 between adjacent pixels 101 within the display area AA of each of the display panels PNL1 to PNL4. As a result, the distances D1 and D2 between the pixels 101 are the same throughout the entire widescreen display area of the tiled display TD, and thus the seam area is invisible.

[0103] The pixel 101 may include two sub-pixels for each color, such as Figures 3A to 5D shown.

[0104] Reference 3A to 5D Each of the pixels 101 includes a first subpixel S1 and a first second subpixel S4 adjacent to each other in a second direction Y parallel to the data lines 1021 to 1026 and having pixel data of a first color written therein, a second first subpixel S2 and a second second subpixel S5 adjacent to each other in the second direction Y and having pixel data of a second color written therein, and a third first subpixel S3 and a third second subpixel S6 adjacent to each other in the second direction Y and having pixel data of a third color written therein. The first color may be, but is not limited to, red, the second color may be green, and the third color may be blue. For example, the first first subpixel S1 and the first second subpixel S4 may be red subpixels SP_R to which a data voltage of red data is applied. The second first subpixel S2 and the second second subpixel S5 may be green subpixels SP_G to which a data voltage of green data is applied. The third first subpixel S3 and the third second subpixel S6 may be blue subpixels SP_B to which a data voltage of blue data is applied.

[0105] The first first sub-pixel S1, the second first sub-pixel S2, and the third first sub-pixel S3 may be interpreted as main sub-pixels. The first second sub-pixel S4, the second second sub-pixel S5, and the third second sub-pixel S6 may be interpreted as redundant sub-pixels or auxiliary sub-pixels. Figures 3A to 5D, reference numerals “ 1021 to 1026 ” denote data lines to which data voltages ( Vdata1 to Vdata6 ) are applied, and reference numerals “ 1031 to 1036 ” denote gate lines to which gate signals SCAN, EM_R, EM_G / B are applied.

[0106] The sub-pixels S1 and S4 of the first color may be as follows Figure 3A are connected to one data line 1021 to share the data line 1021, or can be connected to one data line 1021 to share the data line 1021 as shown. Figure 3B 、 Figure 3C and Figure 3D As shown, they are connected to different data lines 1021 and 1022 respectively.

[0107] The sub-pixels S1 and S4 of the first color may share the gate lines 1031 and 1032 to which the scan signal SCAN and the first EM signal EM_R are applied. Figures 3A to 3D shown.

[0108] The sub-pixels S2 and S5 of the second color can be as follows Figure 3A and Figure 3B are connected to one data line 1022 or 1023 as shown, or can be connected to one data line 1022 or 1023 as shown Figure 3C and Figure 3D As shown, they are connected to different data lines 1023 and 1024 respectively.

[0109] The sub-pixels S3 and S6 of the third color can be as follows Figures 3A to 3C connected to one of the data lines 1023, 1024 or 1025 as shown, or as Figure 3D As shown, they are connected to different data lines 1025 and 1026 respectively.

[0110] The sub-pixels S2, S3, S5, and S6 of the second and third colors may share the gate lines 1031 and 1033 to which the scan signal SCAN and the second EM signal EM_G / B are applied. Figures 3A to 3D shown.

[0111] like 4A to 5D As shown, the gate lines connected to sub-pixels of the same color can be separated for each pixel row. For example, sub-pixels S1, S2, and S3 arranged in the n-th pixel row L(n) (where n is a natural number) can be connected to the first group of gate lines 1031, 1032, and 1033, and sub-pixels S4, S5, and S6 arranged in the (n+1)-th pixel row L(n+1) can be connected to the second group of gate lines 1034, 1035, and 1036.

[0112] refer to 4A to 5DThe first group of gate lines 1031, 1032, and 1033 may include a first gate line (or scan line) 1031 to which a scan signal SCAN is applied, a second gate line 1032 to which a first EM signal EM_R is applied, and a third gate line 1033 to which a second EM signal EM_G / B is applied. The first gate line 1031 may include a gate line (or first scan line) to which a first scan signal SCAN1 is applied and a gate line (or second scan line) to which a second scan signal SCAN2 is applied. The third gate line 1033 may include a first EM line to which a first EM signal EM_R is applied and a second EM line to which a second EM signal EM_G / B is applied.

[0113] The second group of gate lines 1034, 1035, and 1036 may include a first gate line (or scan line) 1034 to which a scan signal SCAN is applied, a second gate line 1035 to which a first EM signal EM_R is applied, and a third gate line 1036 to which a second EM signal EM_G / B is applied. The first gate line 1034 may include a gate line (or first scan line) to which a first scan signal SCAN1 is applied and a gate line (or second scan line) to which a second scan signal SCAN2 is applied. The third gate line 1036 may include a first EM line to which a first EM signal EM_R is applied and a second EM line to which a second EM signal EM_G / B is applied.

[0114] The sub-pixels S1, S2, and S3 arranged in the n-th pixel row L(n) may be connected to the first group of gate lines 1031, 1032, and 1033, and the sub-pixels S4, S5, and S6 arranged in the (n+1)-th pixel row L(n+1) may be connected to the second group of gate lines 1034, 1035, and 1036. The gate lines 1032 and 1035 to which the first EM signal EM_R is applied may be connected to the sub-pixels S1 and S4 of the first color, respectively. The gate lines 1033 and 1036 to which the second EM signal EM_G / B is applied may be connected to the sub-pixels S2, S3, S5, and S6 of the second and third colors.

[0115] When the gate line is separated for each pixel row, the pixel row is time-division scanned because the pulse of the scan signal output from the gate driver 120 is shifted along the scan direction. In this case, pixel data can be sequentially written between sub-pixels of the same color within one pixel.

[0116] Since two sub-pixels are provided for each color within one pixel 101, it is possible to effectively respond to defects, and compensate for brightness and chromaticity.

[0117] The main sub-pixel and the redundant sub-pixel included in the sub-pixels of at least one color may be driven simultaneously, or only one of them may be driven. In addition, the main sub-pixel and the redundant sub-pixel may be driven alternately based on time.

[0118] In the case of micro-LEDs, defective sub-pixels may occur due to defective transfer of the micro-LEDs. In the case of micro-LEDs, micro-LED chips on a wafer may be transferred to a substrate on which pixel circuits are formed using a donor substrate without an LED binning process, which may result in contact defects among the micro-LEDs transferred to the substrate or uneven brightness characteristics of the micro-LEDs.

[0119] During a repair process before shipping a product, a sub-pixel that emits light equal to or less than a predetermined reference value of the brightness of the pixel when measured can be determined as a defective sub-pixel and can be converted into a dark spot. In one example, if the light-emitting element or the pixel circuit driving the light-emitting element of any of the first sub-pixel S1 or the first second sub-pixel S4 used to reproduce the pixel data of the first color is defective, a normally driven sub-pixel can be used to display the pixel data of the first color. The sub-pixel converted into a dark spot can be stored in a memory accessible to the timing controller 130 by recording its position information in a sub-pixel map. The pixel data can be weighted so that a normal sub-pixel having the same color as the sub-pixel converted into a dark spot can be driven at the target brightness.

[0120] The full white brightness of each of the sub-pixels can be measured, and a brightness conversion lookup table according to the grayscale of each of the pixels 101 can be created and stored in a memory accessible to the timing controller 130. In two adjacent pixels, one of the two sub-pixels S1 and S4 that emit light at the brightness of the same color (e.g., the first color) in the first pixel can emit light at the target brightness of the first color, while even if the maximum grayscale voltage is applied to each of the sub-pixels S1 and S4 in the second pixel, the brightness of the first color in the second pixel may not reach the target brightness. In this case, only one of the two sub-pixels S1 and S4 in the first pixel can be driven to emit light at the target brightness of the first color, and both of the two sub-pixels S1 and S4 in the second pixel can be driven to emit light at the target brightness of the first color.

[0121] Due to the characteristics of micro LEDs, when the current density is high, the luminous efficiency can be good. In this case, when the sub-pixels of the same color within a pixel are driven normally, only one of them can be selectively driven to increase the current density of the light-emitting element, thereby improving the luminous efficiency. When two sub-pixels of the same color that are driven normally are alternately driven with a cycle of a predetermined frame period (for example, an I frame period (where I is a natural number)), each sub-pixel can emit light with high luminous efficiency. For example, the light-emitting element of the first sub-pixel S1 can emit light during an odd frame period, and the light-emitting element of the first second sub-pixel S4 can emit light during an even frame period.

[0122] exist Figures 3A to 5D In the embodiment, the second EM signal EM_G / B is input to the sub-pixels S2, S3, S5 and S6 of the second and third colors, but is not limited thereto. Figure 14A 、 Figure 14B and Figure 15 As shown, the second EM signal EM_G may be input to the green sub-pixel SP_G, and the third EM signal EM_B may be input to the blue sub-pixel SP_B.

[0123] The third gate line may include a first EM line to which a first EM signal EM_R is applied and a second EM line to which a second EM signal EM_G / B is applied. The first EM signal EM_R may be supplied to the first first subpixel S1 and the first second subpixel S4 via a first EM line 1032 connected to the subpixels S1 and S4. The second EM signal EM_G / B may be supplied to the second first to third second subpixels S2, S3, S5, and S6 via a second EM line 1033 connected to the subpixels S2, S3, S5, and S6.

[0124] like 5A to 5D As shown, the sub-pixels of at least one color can be designed to be different from each other. For example, the driving transistor of the first second sub-pixel S4 can have a smaller channel ratio than the driving transistor of the first first sub-pixel S1. In this case, the low grayscale performance can be improved. For example, when the pixel data of the first color is low grayscale data within a predetermined low grayscale range, the first second sub-pixel S4 with a small channel current of the driving transistor can be driven. On the other hand, when the first first sub-pixel S1 with a large channel current of the driving transistor is driven at an intermediate grayscale and a high grayscale, the light-emitting element can emit light at a high brightness with high luminous efficiency. 8-bit pixel data has 256 grayscales ranging from 0 to 255. In this case, the low grayscale can be a grayscale with a grayscale value of 80 or less, but is not limited to this.

[0125] Figure 6 is a diagram schematically showing an example in which the channel ratios of driving transistors are different from each other.

[0126] Reference Figure 6 The driving transistor includes a gate G, an active pattern ACT made of a semiconductor, a first electrode S, and a second electrode D. When the driving transistor is turned on, current flows through a channel between the first electrode S and the second electrode D on the active pattern ACT. The current can be adjusted by the channel ratio W / L of the driving transistor.

[0127] The channel ratio W' / L' of the driving transistor provided in the pixel circuit having the first sub-pixel S1 may be greater than the channel ratio W / L of the driving transistor provided in the pixel circuit having the first second sub-pixel S4. Wherein W and W' are channel widths, and L and L' may be channel lengths. If the channel width W of the driving transistor provided in the first second sub-pixel S4 is reduced or the channel length L is increased, the channel current is reduced, which may allow the current density of the light-emitting element to be reduced at low grayscales of the pixel data.

[0128] Figures 7 to 9 is a flowchart illustrating a method of driving a sub-pixel according to various embodiments of the present disclosure.

[0129] Reference Figures 3A to 5D and Figure 7 , the sub-pixels to be driven and the sub-pixels not to be driven can be determined from the sub-pixels of the same color arranged in one pixel 101 before shipping the product (S71). The sub-pixels to be driven are sub-pixels into which the pixel data of the input image is written and which emit light at a target brightness corresponding to the grayscale of the corresponding pixel data. The pixels not to be driven are defective sub-pixels that are converted into dark spots or sub-pixels that are not allowed to be driven for other reasons. The position information of the pixels not to be driven can be recorded in a sub-pixel map accessible to the timing controller 130 and stored in a memory.

[0130] When the input image data is input to the timing controller 130, the timing controller 130 can read the sub-pixel map to determine whether the pixel data of the current input video is to be written to the sub-pixel to be driven or the sub-pixel not to be driven. The pixel data of the input image can be written to the sub-pixel to be driven, and the black grayscale data can be written to the sub-pixel not to be driven (S72 and S73). When the black grayscale voltage is applied to the driving transistor, since no current for driving the light-emitting element is generated from the driving transistor, the sub-pixel not to be driven is turned off and not driven.

[0131] In step S73, the pixel data of the input image is transmitted to the data driver 110 to be converted into a data voltage, and the data voltage is supplied to the sub-pixels to be driven via the data lines. The timing controller 130 may add black grayscale data to be written to the non-driven sub-pixels to the input image data and transmit it to the data driver 110. The black grayscale data may be stored in the internal memory of the timing controller 130 independently of the pixel data of the input image. The black grayscale data is transmitted to the data driver 110 and converted into a black grayscale voltage, which is fed to the sub-pixels to be driven via the data lines.

[0132] refer to Figures 3A to 5D as well as Figure 8 , the cycle of alternate driving of the sub-pixels of the same color arranged in one pixel 101 can be determined before shipping the product (S81). For example, the main sub-pixels S1, S2, and S3 and the redundant sub-pixels S4, S5, and S6 can be alternately driven with a cycle of 1 frame period (where 1 is a natural number).

[0133] When input image data is input to the timing controller 130, the timing controller 130 can control the data driver 110 and the gate driver 120 to alternately write the pixel data of the input image into the main sub-pixels S1, S2, and S3 and the redundant sub-pixels S4, S5, and S6, so that the main sub-pixels S1, S2, and S3 and the redundant sub-pixels S4, S5, and S6 can be alternately driven (S82 and S83). For example, pixel data can be written into the main sub-pixels S1, S2, and S3 during a one-frame period, and then pixel data can be written into the redundant sub-pixels S4, S5, and S6 during the next one-frame period.

[0134] The following is a detailed description of the alternate driving method of sub-pixels.

[0135] for Figures 3B to 3D 、 Figures 4B to 4D and Figures 5B to 5DIn the pixel 101 shown, in the nth horizontal period of the first frame period, the pulse of the scan signal SCAN can be applied to the main sub-pixels S1, S2, and S3 through the gate lines of the first group of gate lines 1031, 1032, and 1033, and the data voltage Vdata1 of the red data synchronized with the pulse of the scan signal SCAN can be applied to the first first sub-pixel S1 through the first data line 1021. Subsequently, in the (n+1)th horizontal period of the first frame period, the pulse of the scan signal SCAN can be applied to the redundant sub-pixels S4, S5, and S6 through the gate lines of the second group of gate lines 1034, 1035, and 1036, and the black grayscale voltage synchronized with the pulse of the scan signal SCAN can be applied to the first second sub-pixel S4. As a result, in the first frame period, the first first sub-pixel S1 of the red sub-pixel SP_R and the first second sub-pixel S4 can be driven to emit light at the target brightness of the red data.

[0136] Subsequently, in the nth horizontal period of the second frame period, a pulse of the scan signal SCAN may be applied to the main sub-pixels S1, S2, and S3 through the gate lines of the first group of gate lines 1031, 1032, and 1033, and a black grayscale voltage synchronized with the pulse of the scan signal SCAN may be applied to the first first sub-pixel S1 through the first data line 1021. Subsequently, in the (n+1)th horizontal period of the second frame period, a pulse of the scan signal SCAN may be applied to the redundant sub-pixels S4, S5, and S6 through the gate lines of the second group of gate lines 1034, 1035, and 1036, and a data voltage Vdata2 of red data synchronized with the pulse of the scan signal SCAN may be applied to the first second sub-pixel S4. As a result, in the second frame period, the first first sub-pixel S1 and the first second sub-pixel S4 of the red sub-pixel SP_R may be driven to emit light at a target brightness of the red data.

[0137] Figure 9 is shown for driving Figures 5A to 5D An example flow chart of a sub-pixel method is shown in FIG.

[0138] Reference 5A to 5D as well as Figure 9 , the timing controller 130 may analyze the pixel data of the input image to determine the grayscale value of the pixel data (S91). When the red data is low grayscale data, the timing controller 130 may write the pixel data to the first second sub-pixel S4 having a smaller driving transistor among the first sub-pixel S1 and the first second sub-pixel S4, thereby driving the first second sub-pixel S4 (S92 and S93). Figure 5AFor the pixel shown, the data driver 110 can output a black grayscale voltage to the first data line 1021 when data is written to the sub-pixels S1, S2, and S3 of the n-th pixel row L(n) under the control of the timing controller 130, and then output a data voltage Vdata1 of red data to the first data line 1021 when data is written to the sub-pixels S4, S5, and S6 of the (n+1)-th pixel row L(n+1). Figures 5B to 5D For the pixels shown, the data driver 110 can output a black grayscale voltage to the first data line 1021 when data is written to the sub-pixels S1, S2 and S3 of the n-th pixel row L(n) under the control of the timing controller 130, and then output a data voltage Vdata1 of red data to the second data line 1022 when data is written to the sub-pixels S4, S5 and S6 of the (n+1) pixel row L(n+1).

[0139] When the red data is not low grayscale data, for example, when the red data is medium-high grayscale data, the timing controller 130 may write the pixel data into the first first subpixel S1 having a larger driving transistor among the first first subpixel S1 and the first second subpixel S4 to drive the first first subpixel S1. Figure 5A For the pixel shown in FIG. 1 , the data driver 110 may output a data voltage Vdata1 of red data to the first data line 1021 when data is written to the sub-pixels S1, S2, and S3 of the n-th pixel row L(n) under the control of the timing controller 130, and then output a black grayscale voltage to the first data line 1021 when data is written to the sub-pixels S4, S5, and S6 of the (n+1)-th pixel row L(n+1). Figures 5B to 5D For the pixels shown, the data driver 110 can output the data voltage Vdata1 of red data to the first data line 1021 when data is written to the sub-pixels S1, S2 and S3 of the n-th pixel row L(n) under the control of the timing controller 130, and then output the black grayscale voltage to the second data line 1022 when data is written to the sub-pixels S4, S5 and S6 of the (n+1)-th pixel row L(n+1).

[0140] In another embodiment, when the red data is not low grayscale data, the timing controller 130 may alternately drive the first sub-pixel S1 and the first second sub-pixel S4 with a cycle of a predetermined frame period (e.g., 1 frame period (where 1 is a natural number)) (S94). An example of alternately driving the first sub-pixel S1 and the first second sub-pixel S4 is as follows.

[0141] for Figure 5AFor the pixels shown, the data driver 110 may output a data voltage Vdata1 of red data to the first data line 1021 when data is written to the sub-pixels S1, S2, and S3 of the n-th pixel row L(n) during the n-th frame period under the control of the timing controller 130, and then output a black grayscale voltage to the first data line 1021 when data is written to the sub-pixels S4, S5, and S6 of the (n+1)-th pixel row L(n+1). Subsequently, the data driver 110 may output a black grayscale voltage to the first data line 1021 when data is written to the sub-pixels S1, S2, and S3 of the n-th pixel row L(n) during the (n+1)-th frame period, and then output a data voltage Vdata1 of red data to the first data line 1021 when data is written to the sub-pixels S4, S5, and S6 of the (n+1)-th pixel row L(n+1).

[0142] for Figures 5B to 5D For the pixels shown, the data driver 110 may output a data voltage Vdata1 of red data to the first data line 1021 when data is written to the sub-pixels S1, S2, and S3 of the n-th pixel row L(n) during the n-th frame period under the control of the timing controller 130, and then output a black grayscale voltage to the second data line 1022 when data is written to the sub-pixels S4, S5, and S6 of the (n+1)-th pixel row L(n+1). Subsequently, the data driver 110 may output a black grayscale voltage to the first data line 1021 when data is written to the sub-pixels S1, S2, and S3 of the n-th pixel row L(n) during the (n+1)-th frame period, and then output a data voltage Vdata1 of red data to the first data line 1021 when data is written to the sub-pixels S4, S5, and S6 of the (n+1)-th pixel row L(n+1).

[0143] Figure 10 is a graph showing the difference in luminous efficiency of light-emitting devices for each color.

[0144] Reference Figure 10 The red light emitting element, the green light emitting element and the blue light emitting element can be 2 ) and have different luminous efficiencies (cd / A). For example, the luminous efficiency of the red light-emitting element ER can be driven to maximum luminous efficiency at a higher current density than the green and blue light-emitting elements. In contrast, the luminous efficiency of the green light-emitting element EG and the blue light-emitting element EB can emit light at maximum luminous efficiency at a relatively low current density. The current density of the light-emitting element is determined by the amount of current, which depends on the gate-source voltage of the drive transistor. The gate-source voltage of the drive transistor can be controlled by the data voltage applied to the gate of the drive transistor.

[0145] from Figure 10It can be seen that since the luminous efficiency can vary depending on the current density of each color of the light-emitting element, it is necessary to optimize the driving conditions of the sub-pixels of each color so that the light-emitting element of each color can be driven with the best luminous efficiency. The present disclosure can set the data voltage and luminous time of the light-emitting element independently for each color, so that the light-emitting element of each color can be driven with the best luminous efficiency. In order to improve the luminous efficiency of each of the red light-emitting element, the green light-emitting element and the blue light-emitting element, the data voltage can be set independently for each color, such as Figure 11 shown.

[0146] The color-specific luminous efficiency characteristics of the light-emitting element are not limited to Figure 10 For example, the color-specific luminous efficiency characteristics of a light-emitting element may vary depending on the manufacturer or material characteristics of the light-emitting element. In the present disclosure, each of the light-emitting elements is driven at maximum luminous efficiency for the color-specific luminous efficiency characteristics of the light-emitting element, but by using EM signals differentiated for each color, degradation of image quality caused by driving to maximum luminous efficiency can be minimized.

[0147] Figure 11 is a diagram showing an example of color-specific data voltages.

[0148] refer to Figure 11 The data voltages output from the data driver 110 may include at least a red data voltage Vdata(R), a green data voltage Vdata(G), and a blue data voltage Vdata(B). The red data voltage Vdata(R) may be applied to a red sub-pixel. The green data voltage Vdata(G) may be applied to a green sub-pixel. The blue data voltage Vdata(B) may be applied to a blue sub-pixel.

[0149] The maximum voltage Vmax of the red data voltage Vdata(R) may be set to a voltage higher than the maximum voltage Vmax of the green data voltage Vdata(G) and the blue data voltage Vdata(B). The minimum voltage Vmin of the red data voltage Vdata(R) may be set to a voltage equal to or higher than the minimum voltage Vmin of the green data voltage Vdata(G) and the blue data voltage Vdata(B). The dynamic range DYR of the red data voltage Vdata(R) (i.e., the voltage range between the minimum voltage Vmin and the maximum voltage Vmax) may be greater than the dynamic range DYG of the green data voltage Vdata(G) and the dynamic range DYB of the blue data voltage Vdata(B). The dynamic range of the data voltages DYR, DYG, and DYB is the voltage range between the minimum voltage Vmin and the maximum voltage Vmax.

[0150] The maximum voltage Vmax of the blue data voltage Vdata(B) may be set to a voltage equal to or higher than the maximum voltage Vmax of the green data voltage Vdata(G). The minimum voltage Vmin of the blue data voltage Vdata(B) may be set to a voltage equal to or higher than the minimum voltage Vmin of the green data voltage Vdata(G).

[0151] When each of the red, green, and blue light-emitting elements is driven in the maximum luminous efficiency region, over-brightness may occur in a specific color, which may cause the color coordinates and white balance to deviate from the target values. The present disclosure can optimize the color coordinates and white balance and the luminous efficiency by controlling the ratio of the lighting intervals of the red, green, and blue light-emitting elements by using the duty cycle of the EM signal set independently for each color to achieve low-power driving.

[0152] Figure 12A and Figure 12B is a diagram showing one example of a wiring structure for applying color-specific EM signals to sub-pixels. Figure 13 It shows Figure 12A and Figure 12B An example waveform diagram of a color-specific EM signal is shown in FIG.

[0153] refer to Figure 12A and Figure 13 , the gate driver 120 may include a first EM driver 120R that outputs a first EM signal EM_R and a second EM driver 120GB that outputs a second EM signal EM_G / B.

[0154] The first EM driver 120R may output a first EM signal EM_R to a first EM line GL_R connected to the red subpixel SP_R while shifting the pulse of the first EM signal EM_R. Each of the first EM lines GL_R may be provided for each of the pixel rows L1 to L(n), or may be connected to two or more pixel rows via a common wiring. The second EM driver 120GB may output a second EM signal EM_G / B to a second EM line GL_G / B connected to the green subpixel SP_G and the blue subpixel SP_B, while shifting the pulse of the second EM signal EM_G / B. Each of the second EM lines GL_G may be provided for each of the pixel rows L1 to L(N), or may be connected to two or more pixel rows via a common wiring.

[0155] The on-duty ratio of the first EM signal EM_R can be smaller than the on-duty ratio of the second EM signal EM_G / B. The on-duty ratio is the ratio of the on-intervals (ON) of the EM signals EM_R and EM_G / B within one pulse period (1T). The on-interval (ON) of the EM signals EM_R and EM_G / B can be the interval of gate-on voltage VEL, and the off-interval (OFF) of the EM signals EM_R and EM_G / B can be the interval of gate-off voltage VEH. When the on-duty ratio of the EM signals EM_R and EM_G / B is small, the on-interval of the light-emitting element is reduced, thereby controlling the brightness of the corresponding subpixel to be low. By reducing the on-interval of the red light-emitting element using the first EM signal EM_R with a relatively small on-duty ratio, overbrightness caused by increasing the data voltage of the red data to improve the driving efficiency of the red light-emitting element is reduced. Since the EM signals EM_R and EM_G / B are independent for each color, the on-duty ratio of the light-emitting element can be freely controlled for each color.

[0156] The color specific EM signals EM_R and EM_G / B can be Figure 12B The output from the level shifter 150 is shown, rather than being applied to the sub-pixels via the gate driver.

[0157] refer to Figure 12B and Figure 13 , the level shifter 150 may receive the strobe timing signal from the timing controller 130 and output color-specific EM signals EM_R( 1 ) to ( 3 ) and EM_G / B( 1 ) to ( 3 ).

[0158] First color-specific EM signals EM_R(1) and EM_G / B(1) may be applied to subpixels of a first group of pixel rows, for example, subpixels of a first pixel row L1 and a fourth pixel row L4, respectively, via EM lines GL_R(1) and GL_G / B(1) commonly connected to the subpixels. The first EM row GL_R(1) to which the first EM signal EM_R(1) is applied may be connected to the red subpixel SP_R. The second EM row GL_G / B(1) to which the second EM signal EM_G / B(1) is applied may be connected to the green subpixel SP_G and the blue subpixel SP_B.

[0159] Second color-specific EM signals EM_R(2) and EM_G / B(2) can be applied to subpixels of a second group of pixel rows, for example, subpixels of the second pixel row L2 and the fifth pixel row L5, respectively, through EM lines GL_R(2) and GL_G / B(2) commonly connected to the subpixels. A first EM line GL_R(2) to which the first EM signal EM_R(2) is applied can be connected to the red subpixel SP_R. A second EM line GL_G / B(2) to which the second EM signal EM_G / B(2) is applied can be connected to the green subpixel SP_G and the blue subpixel SP_B.

[0160] Third color-specific EM signals EM_R(3) and EM_G / B(3) can be applied to subpixels of a third group of pixel rows, for example, subpixels of the third pixel row L3 and the sixth pixel row L6, respectively, through EM lines GL_R(3) and GL_G / B(3) commonly connected to the subpixels. A first EM line GL_R(3) to which the first EM signal EM_R(3) is applied can be connected to the red subpixel SP_R. A second EM line GL_G / B(3) to which the second EM signal EM_G / B(3) is applied can be connected to the green subpixel SP_G and the blue subpixel SP_B.

[0161] Figure 14A and Figure 14B is a diagram showing another example of a wiring structure for applying color-specific EM signals to sub-pixels. Figure 15 It shows Figure 14A and Figure 14B The waveform diagrams of examples of color-specific EM signals are shown.

[0162] refer to Figure 14A and Figure 15 , the gate driver 120 may include a first EM driver 120R outputting a first EM signal EM_R, a second EM driver 120G outputting a second EM signal EM_G, and a third EM driver 120B outputting a third EM signal EM_B.

[0163] The first EM driver 120R may output a first EM signal EM_R to a first EM line GL_R connected to the red subpixel SP_R while shifting the pulse of the first EM signal EM_R. Each of the first EM lines GL_R may be provided for each pixel row L1 to L(N), or may be connected to two or more pixel rows via a common wiring. The second EM driver 120G may output a second EM signal EM_G to a second EM line GL_G connected to the green subpixel SP_G while shifting the pulse of the second EM signal EM_G. Each of the second EM lines GL_G may be provided for each pixel row L1 to L(N), or may be connected to two or more pixel rows via a common wiring. The third EM driver 120B may output a third EM signal EM_B to a third EM line GL_B connected to the blue subpixel SP_B while shifting the pulse of the third EM signal EM_B. Each of the third EM lines GL_B may be provided for each pixel row L1 to L(N), or may be connected to two or more pixel rows via a common wiring.

[0164] The first EM signal EM_R may have a lower on-duty cycle than the second and third EM signals EM_G and EM_B. Since the EM signals EM_R, EM_G, and EM_B are independent for each color, the on-duty cycle of the light-emitting element can be freely controlled for each color. For example, the on-duty cycle of the third EM signal EM_B may be controlled to be greater than the on-duty cycle of the first EM signal EM_R and less than the on-duty cycle of the second EM signal EM_G.

[0165] The color specific EM signals EM_R, EM_G and EM_B can be Figure 14B The output from the level shifter 150 is shown, rather than being applied to the sub-pixels via the gate driver.

[0166] refer to Figure 14B and Figure 15 , the level shifter 150 may receive the strobe timing signal from the timing controller 130 and output color-specific EM signals EM_R( 1 ) to ( 3 ), EM_G( 1 ) to ( 3 ), and EM_B( 1 ) to ( 3 ).

[0167] First color-specific EM signals EM_R(1), EM_G(1), and EM_B(1) can be applied to subpixels of a first group of pixel rows, for example, subpixels of a first pixel row L1 and a fourth pixel row L4, respectively, through EM lines GL_R(1), GL_G(1), and GL_B(1) commonly connected to the subpixels. The first EM line GL_R(1) to which the first EM signal EM_R(1) is applied can be connected to a red subpixel SP_R. The second EM line GL_G(1) to which the second EM signal EM_G(1) is applied can be connected to a green subpixel SP_G. The third EM line GL_B(1) to which the third EM signal EM_B(1) is applied can be connected to a blue subpixel SP_B.

[0168] The second color-specific EM signals EM_R(2), EM_G(2), and EM_B(2) can be applied to the subpixels of the second group of pixel rows, for example, the subpixels of the second pixel row L2 and the fifth pixel row L5, respectively, through the EM lines GL_R(2), GL_G(2), and GL_B(2) commonly connected to the subpixels. The first EM line GL_R(2) to which the first EM signal EM_R(2) is applied can be connected to the red subpixel SP_R. The second EM line GL_G(2) to which the second EM signal EM_G(2) is applied can be connected to the green subpixel SP_G. The third EM line GL_B(2) to which the third EM signal EM_B(2) is applied can be connected to the blue subpixel SP_B.

[0169] The third color-specific EM signals EM_R(3), EM_G(3), and EM_B(3) can be applied to the subpixels of the third group of pixel rows, for example, the subpixels of the third pixel row L3 and the sixth pixel row L6, respectively, through the EM lines GL_R(3), GL_G(3), and GL_B(3) commonly connected to the subpixels. The first EM line GL_R(3) to which the first EM signal EM_R(3) is applied can be connected to the red subpixel SP_R. The second EM line GL_G(3) to which the second EM signal EM_G(3) is applied can be connected to the green subpixel SP_G. The third EM line GL_B(3) to which the third EM signal EM_B(3) is applied can be connected to the blue subpixel SP_B.

[0170] Figure 16 is a circuit diagram illustrating a pixel circuit according to one embodiment of the present disclosure.

[0171] Reference Figure 16 The pixel circuit includes a light emitting element LD, a driving transistor DR, switching transistors M1 and M2, and a compensation circuit 300. The driving transistor DR and the switching transistor M1 may be implemented as, but not limited to, p-channel transistors.

[0172] The light-emitting element LD may include an anode, a cathode, and a light-emitting layer. A pixel drive voltage EVDD may be applied to the anode of the light-emitting element LD. The cathode of the light-emitting element LD may be connected to the drive transistor DR. The light-emitting element LD may be, but is not limited to, a light-emitting element such as an OLED, a mini-LED, or a micro-LED. The mini-LED or micro-LED may have a vertical structure in which electrodes are arranged above and below a semiconductor chip in which the light-emitting element LD is integrated. The semiconductor chip in which the light-emitting element LD is integrated may be implemented in a lateral structure or a flip-chip structure.

[0173] The light emitting element LD, the driving transistor DR, and the switching transistor M1 may be connected in series between a pixel driving voltage EVDD and a ground voltage EVSS.

[0174] The drive transistor DR regulates the current flowing through the drain-source channel according to its gate-source voltage. The gate-source voltage of the drive transistor DR varies with the data voltage Vdata of the pixel data applied to the gate of the drive transistor DR. Therefore, the current flowing through the drive transistor DR varies with the data voltage Vdata. The light-emitting element LD can be driven by the current from the drive transistor DR to emit light.

[0175] The driving transistor DR may be connected between the light emitting element LD and the first switching transistor M1. The driving transistor DR includes a gate to which a data voltage Vdata is applied, a first electrode connected to the cathode of the light emitting element LD, and a second electrode connected to the first electrode of the first switching transistor M1.

[0176] The first switching transistor M1 can be connected between the drive transistor DR and the ground voltage EVSS to switch the current path between the pixel drive voltage EVDD and the ground voltage EVSS. The first switching transistor M1 can be turned on in response to the gate-on voltage of the EM signal EM_R / G / B of a specific domain color, and turned off in response to the gate-off voltage. When the first switching transistor M1 is turned on, the drive transistor DR and the light-emitting element LD can be electrically connected, thereby supplying current to the light-emitting element LD. When the first switching transistor M1 is turned off, the current path between the pixel drive voltage EVDD and the ground voltage EVSS is blocked, so that no current is supplied to the light-emitting element LD.

[0177] The pixel circuit may further include a second switching transistor M2. The second switching transistor M2 is connected between the cathode and anode of the light-emitting element LD and can be turned on in response to the gate-on voltage of the first scan signal SCAN1 and turned off in response to the gate-off voltage. When the second switching transistor M2 is turned on, the cathode and anode of the light-emitting element LD are short-circuited, causing the light-emitting element LD to not emit light. When the second switching transistor M2 is turned off, current can flow to the light-emitting element LD. The second switching transistor M2 can prevent the light-emitting element LD from emitting light when the pixel circuit is initialized and when the threshold voltage of the drive transistor DR is sampled.

[0178] The compensation circuit 300 can be connected to a data line to which a data voltage Vdata is applied, a gate line to which select signals SCAN1, SCAN2, and EM_R / G / B are applied, the gate of the drive transistor DR, and the gates of the switching transistors M1 and M2. The compensation circuit 300 may include multiple transistors and one or more capacitors. The compensation circuit 300 transmits the data voltage Vdata to the gate of the drive transistor DR. The compensation circuit 500 samples the threshold voltage of the drive transistor DR into the capacitor to compensate the gate voltage of the drive transistor DR by the amount of the threshold voltage of the drive transistor DR. The compensation circuit 300 can perform compensation by sampling the threshold voltage of the drive transistor DR using a source follower or a diode connection circuit.

[0179] Figure 17 It is shown that it is applicable to Figure 16 A circuit diagram of an example of a pixel circuit is shown.

[0180] Reference Figure 17 The pixel circuit includes a driving transistor DR that drives the light-emitting element LD, a plurality of switching transistors M1 to M6, and a first capacitor Cst. The pixel circuit may also include a second capacitor C2 and a third capacitor C3. The transistors DR and M1 to M6 in the pixel circuit may be p-channel transistors, but are not limited thereto.

[0181] A pixel drive voltage EVDD, a ground voltage EVSS, and a reference voltage Vref may be applied to the pixel circuit. The pixel drive voltage EVDD may be a constant voltage selected between 8 V and 13 V, and the ground voltage EVSS and the reference voltage Vref may be constant voltages selected between -2 V and 1 V. The reference voltage Vref may be, but is not limited to, a constant voltage equal to or higher than the ground voltage EVSS.

[0182] Data voltage Vdata and strobe signals SCAN1, SCAN2, and EM_R / G / B can be input to the pixel circuit. Data voltage Vdata can be, but is not limited to, a dynamic range voltage between 0V and SVDD. SVDD is the data drive voltage used to drive the output buffers in data driver 110. Data drive voltage SVDD can be, but is not limited to, a constant voltage selected between 12V and 18V. High gate voltages VGH and VEH of strobe signals SCAN1, SCAN2, and EM_R / G / B can be, but are not limited to, constant voltages selected between 10V and 13V, and low gate voltages VGL and VEL can be, but are not limited to, constant voltages selected between -13V and -10V. High gate voltage VEH of the color-specific EM signals EM_R / G / B can be set to be equal to or different from high gate voltage VGH of scan signals SCAN1 and SCAN2. Low gate voltage VEL of the color-specific EM signals EM_R / G / B can be set to be equal to or different from low gate voltage VGL of scan signals SCAN1 and SCAN2. Hereinafter, the gate low voltage VGL, VEL is referred to as a gate-on voltage, and the gate high voltage VGH is referred to as a gate-off voltage.

[0183] An anode of the light emitting element LD may be connected to a first power line PL1 to which a pixel driving voltage EVDD is applied, and a cathode of the light emitting element LD may be connected to a first node n1.

[0184] The driving transistor DR may include a first electrode connected to the first node n1, a gate connected to the second node n2, and a second electrode connected to the third node n3. The first capacitor C1 may be connected between the second node n2 and a fourth node n4.

[0185] The first switching transistor M1 is turned on in response to a gate-on voltage VEL of the color-specific EM signal EM_R / G / B, and is turned off in response to a gate-off voltage VEH of the color-specific EM signal EM_R / G / B. The first switching transistor M1 includes a first electrode connected to a third node n3, a gate connected to a third gate line GL3 to which the color-specific EM signal EM_R / G / B is applied, and a second electrode connected to a second power line PL2.

[0186] The second switching transistor M2 is turned on in response to a gate-on voltage VGL of the first scan signal SCAN1 and is turned off in response to a gate-off voltage VGH of the first scan signal SCAN1. When the second switching transistor M2 is turned on, the first power line PL1, to which the pixel drive voltage EVDD is applied, can be electrically connected to the first node n1. The second switching transistor M2 includes a first electrode connected to the first power line PL1, a gate connected to the first gate line GL1, to which the first scan signal SCAN1 is applied, and a second electrode connected to the first node n1.

[0187] The third switching transistor M3 is turned on in response to a gate-on voltage VEL of the color-specific EM signal EM_R / G / B, and is turned off in response to a gate-off voltage VEH of the color-specific EM signal EM_R / G / B. When the third switching transistor M3 is turned on, the fourth node n4 can be electrically coupled to the third power line PL3 to which the reference voltage Vref is applied. The third switching transistor M3 includes a first electrode coupled to the fourth node n4, a gate coupled to the third gate line GL3, and a second electrode coupled to the third power line PL3.

[0188] The fourth switching transistor M4 is turned on in response to the gate-on voltage VGL of the second scan signal SCAN2 and is turned off in response to the gate-off voltage VGH of the second scan signal SCAN2. When the fourth switching transistor M4 is turned on, the third node n3 can be electrically connected to the third power line PL3 to which the reference voltage Vref is applied. The fourth switching transistor M4 includes a first electrode connected to the third power line PL3, a gate connected to the second gate line GL2 to which the second scan signal SCAN2 is applied, and a second electrode connected to the third node n3.

[0189] The fifth switching transistor M5 is turned on in response to the gate-on voltage VGL of the first scan signal SCAN1 and is turned off in response to the gate-off voltage VGH of the first scan signal SCAN1. When the fifth switching transistor M5 is turned on, the data line DL to which the data voltage Vdata is applied can be electrically connected to the fourth node n4. The fifth switching transistor M5 includes a first electrode connected to the data line DL, a gate connected to the first gate line GL1 to which the first scan signal SCAN1 is applied, and a second electrode connected to the fourth node n4.

[0190] The sixth switching transistor M6 is turned on in response to the gate-on voltage VGL of the first scan signal SCAN1 and is turned off in response to the gate-off voltage VGH of the first scan signal SCAN1. When the sixth switching transistor M6 is turned on, the second node n2 can be electrically coupled to the third node n3. The sixth switching transistor M6 includes a first electrode coupled to the second node n2, a gate coupled to the first gate line GL1, and a second electrode coupled to the third node n3.

[0191] The second capacitor C2 may be connected between the first power line PL1 and the first node n1. The third capacitor C3 may be connected between the first node n1 and the second node n2.

[0192] Figure 17 The pixel circuit shown can be driven by an initialization step, a sampling step, a holding step, and a light emitting step in one frame period. The initialization step can be divided into a first initialization step and a second initialization step, such as Figures 18A to 19B As shown. Figures 18A to 22B In the table, "1H" means a horizontal period. Figures 18A to 22B The operation of the pixel circuit is described assuming that sub-pixels are arranged in an n-th pixel row.

[0193] Figure 18A and Figure 18B It shows Figure 16 A diagram of the first initialization step of the pixel circuit is shown.

[0194] refer to Figure 18A and Figure 18B During the first period Pi1, the first initialization step is performed. During the first period Pi1, the voltage of the second scan signal SCAN2 can be the gate-on voltage VGL, and the voltages of the first scan signal SCAN1 and the color-specific EM signal EM_R / G / B can be the gate-off voltage VEH. Therefore, during the first period Pi1, the fourth switching transistor M4 is turned on, while the other switching transistors M1, M2, M3, M5, and M6 are turned off. During the first period Pi1, the drive transistor DR is turned off.

[0195] During the first period Pi1, the voltage of the third node n3 is initialized to the reference voltage Vref. During the first period Pi1, the other nodes n1, n2 and n4 float. During the first period Pi1, the voltages of the first node n1 and the second node n2 can be maintained at the voltages charged in the previous frame period. The voltage of the fourth node n4 can be maintained at the reference voltage Vref charged during the light-emitting step of the previous frame. During the first period Pi1, the data voltage Vdata(n-1) of the previous pixel row (for example, the (n-1)th pixel row) can be applied to the data line DL.

[0196] Figure 19A and Figure 19B It shows Figure 16 FIG. 1 is a diagram of the second initialization step of the pixel circuit shown.

[0197] refer to Figure 19A and Figure 19B, a second initialization step is performed during the second period Pi2. During the second period Pi2, the voltages of the first scan signal SCAN1 and the second scan signal SCAN2 may be the gate-on voltage VGL, and the voltage of the color-specific EM signal EM_R / G / B may be the gate-off voltage VEH. Therefore, during the second period Pi2, the second switching transistor M2, the fifth switching transistor M5, and the sixth switching transistor M6 are turned on, and the fourth switching transistor M4 is in an on state. On the other hand, during the second period Pi2, the first switching transistor M1 and the third switching transistor M3 are in an off state. During the second period Pi2, the voltage of the first node n1 rises, turning on the drive transistor DR.

[0198] During the second period Pi2, the data voltage Vdata(n) is applied to the data line DL. This data voltage Vdata(n) is applied to the fourth node n4 via the fifth switching transistor M5. During the second period Pi2, the reference voltage Vref is applied to the second node n2 and the third node n3 via the fourth switching transistor M4 and the sixth switching transistor M6. Accordingly, during the second period Pi2, the voltage of the second node n2 is initialized to the reference voltage Vref, and the voltage of the fourth node n4 is the data voltage Vdata(n).

[0199] Figure 20A and Figure 20B It shows Figure 16 Diagram of the sampling steps of the pixel circuit shown.

[0200] refer to Figure 20A and Figure 20B During the third period Ps, a sampling step is performed. During the third period Ps, the voltage of the first scan signal SCAN1 may be the gate-on voltage VGL, and the voltages of the second scan signal SCAN2 and the color-specific EM signals EM_R / G / B may be the gate-off voltages VGH and VEH. Therefore, during the third period Ps, the second switching transistor M2, the fifth switching transistor M5, and the sixth switching transistor M6 are in the on state, and the fourth switching transistor M4 is in the off state. During the third period Ps, the first switching transistor M1 and the third switching transistor M3 are in the off state. During the third period Ps, the voltage at the first node n1 is the voltage EVDD, and the voltage at the second node n2 is the voltage EVDD + Vth. The drive transistor DR is turned on upon entering the third period Ps and is turned off when the turn-off condition (Vs - Vg) + Vth < 0 is met. Here, (Vs - Vg) is the gate-source voltage of the drive transistor DR, i.e., the difference between the voltage Vs at the second node n2 and the voltage at the first node n1 (Vn2 = Vg).

[0201] When the driving transistor DR is turned off, the threshold voltage Vth of the driving transistor DR can be sampled and stored in the first capacitor Cst. During the third period Ps, the voltage of the fourth node n4 is the data voltage Vdata. The first capacitor Cst is charged by the difference voltage between the voltage of the fourth node n4 and the voltage of the second node n2.

[0202] In the case of a non-driven sub-pixel, a black grayscale voltage is applied to the fourth node n04 through the data line DL and the fifth switching transistor M5 during the sampling step.

[0203] Figure 21A and Figure 21B It shows Figure 16 A diagram of the holding step of the pixel circuit shown.

[0204] refer to Figure 21A and Figure 21B The maintaining step is performed during the fourth period Ph. During the fourth period Ph, the voltages of the first scan signal SCAN1, the second scan signal SCAN2, and the color-specific EM signal EM_R / G / B may be the gate-off voltages VGH and VEH. Therefore, during the fourth period Ph, since the first to sixth switching transistors M1 to M6 are in the off state, the second to fourth nodes n2, n3, and n4 float, and thus the voltage of the first capacitor Cst is maintained at its previous state.

[0205] Figure 22A and Figure 22B It shows Figure 16 A diagram showing the light-emitting steps of the pixel circuit.

[0206] refer to Figure 22A and Figure 22B , the light emitting step is performed during the fifth period Pem. During the fifth period Pem, the voltage of the color-specific EM signal EM_R / G / B may be the gate-on voltage VEL, and the voltage of the first scan signal SCAN1 and the second scan signal SCAN2 may be the gate-off voltage VGH. Therefore, during the fifth period Pem, the first switching transistor M1 and the third switching transistor M3 are turned on, while the other switching transistors M2, M4, M5, and M6 are in the off state. During the fifth period Pem, the drive transistor DR generates a current according to the gate-source voltage Vgs to drive the light emitting element LD. The light emitting element LD emits light during the fifth period Pem by the DR current ILD from the drive transistor. The current ILD flowing through the light emitting element LD is as follows:

[0207]

[0208]

[0209] Here, Vs denotes a source voltage of the driving transistor DR or a voltage of the first node n1 , and Vg denotes a gate voltage of the driving transistor DR or a voltage of the second node n2 . represents a constant value determined by the mobility μ, channel capacity Cox, channel width W, channel length L, etc. of the drive transistor DR. Vth represents the threshold voltage of the drive transistor DR.

[0210] As can be seen from the above, by compensating the threshold voltage Vth of the driving transistor DR in the light emitting step, the light emitting element LD can be driven without being affected by the RC delay or IR drop of the pixel driving voltage EVDD and without being affected by changes in the threshold voltage Vth.

[0211] Figure 23 2 is a circuit diagram showing a pixel circuit according to another embodiment of the present disclosure. In this embodiment, redundant descriptions of the previous embodiment are omitted.

[0212] Reference Figure 23 The pixel circuit includes a light emitting element LD, a driving transistor DR, a switching transistor M01, and a compensation circuit 500. The driving transistor DR and the switching transistor M01 can be implemented as, but not limited to, p-channel transistors.

[0213] The anode of the light emitting element LD can be connected to the second electrode of the switching transistor M01, and the ground voltage EVSS can be applied to the cathode of the light emitting element. The driving transistor DR, the switching transistor M01 and the light emitting element LD can be connected in series between the pixel driving voltage EVDD and the ground voltage EVSS.

[0214] The switching transistor M01 is connected between the driving transistor DR and the light-emitting element LD to switch the current path between the pixel driving voltage EVDD and the light-emitting element LD. The switching transistor M01 can be turned on in response to a gate-on voltage of the color-specific EM signal EM_R / G / B and turned off in response to a gate-off voltage of the color-specific EM signal EM_R / G / B.

[0215] The compensation circuit 500 can be connected to a data line to which a data voltage Vdata is applied, a gate line to which select signals SCAN1, SCAN2, and EM_R / G / B are applied, a gate of the drive transistor DR, and a gate of the switching transistor M1. The compensation circuit 500 may include a plurality of transistors and one or more capacitors. The compensation circuit 500 transmits the data voltage Vdata to the gate of the drive transistor DR. The compensation circuit 500 samples the threshold voltage of the drive transistor DR into the capacitor to compensate the gate voltage of the drive transistor DR by the amount of the threshold voltage of the drive transistor DR. The compensation circuit 500 can perform compensation by sampling the threshold voltage of the drive transistor DR using a source follower or a diode connection circuit.

[0216] Figure 24 It is shown that it is applicable to Figure 23 A circuit diagram of an example of a pixel circuit is shown.

[0217] Reference Figure 24 The pixel circuit includes a driving transistor DR that drives the light-emitting element LD, a plurality of switching transistors M01 to M06, and a first capacitor Cst. The pixel circuit may also include a second capacitor C02 and a third capacitor C03. Transistors DR and M01 to M06 in the pixel circuit may be p-channel transistors, but are not limited thereto.

[0218] An anode of the light emitting element LD may be connected to the fourth node n04, and a cathode of the light emitting element LD may be connected to the second power line PL2 to which the ground voltage EVSS is applied.

[0219] The driving transistor DR may include a first electrode connected to a first node n01, a gate connected to a second node n02, and a second electrode connected to a third node n03. A first power line PL1 to which a pixel driving voltage EVDD is applied may be connected to the first node n01. A first capacitor C1 may be connected between the second node n02 and a fifth node n05.

[0220] Each of the first switching transistor M01 and the second switching transistor M02 is turned on in response to a gate-on voltage VEL of the color-specific EM signal EM_R / G / B, and is turned off in response to a gate-off voltage VEH of the color-specific EM signal EM_R / G / B. When the first switching transistor M01 is turned on, the third node n03 can be electrically connected to the fourth node n04. When the second switching transistor M02 is turned on, the fifth node n05 can be electrically connected to the third power line PL3 to which the reference voltage Vref is applied.

[0221] The first switching transistor M01 includes a first electrode connected to the third node n03, a gate connected to the third gate line GL3 to which the color-specific EM signal EM_R / G / B is applied, and a second electrode connected to the fourth node n04. The second switching transistor M02 includes a first electrode connected to the fifth node n05, a gate connected to the third gate line GL3, and a second electrode connected to the third power line PL3.

[0222] Each of the third switching transistor M03 and the sixth switching transistor M06 is turned on in response to the gate-on voltage VGL of the second scan signal SCAN2, and is turned off in response to the gate-off voltage VGH of the second scan signal SCAN2. When the third switching transistor M03 is turned on, the second node n02 can be electrically connected to the third power line PL3 to which the reference voltage Vref is applied. When the sixth switching transistor M06 is turned on, the data line DL to which the data voltage Vdata is applied can be electrically connected to the fifth node n05.

[0223] The third switching transistor M03 includes a first electrode connected to the second node n02, a gate connected to the second gate line GL2 to which the second scan signal SCAN2 is applied, and a second electrode connected to the third power line PL3. The sixth switching transistor M06 includes a first electrode connected to the data line DL, a gate connected to the second gate line GL2, and a second electrode connected to the fifth node n05.

[0224] Each of the fourth switching transistor M04 and the fifth switching transistor M05 is turned on in response to the gate-on voltage VGL of the first scan signal SCAN1, and is turned off in response to the gate-off voltage VGH of the first scan signal SCAN1. When the fourth switching transistor M04 is turned on, the data line DL, to which the data voltage Vdata is applied, can be electrically coupled to the fifth node n05. When the fifth switching transistor M05 is turned on, the second node n02 can be electrically coupled to the third node n03.

[0225] The fourth switching transistor M04 includes a first electrode connected to the data line DL, a gate connected to the first gate line GL1 to which the first scan signal SCAN1 is applied, and a second electrode connected to the fifth node n05. The fifth switching transistor M05 includes a first electrode connected to the second node n02, a gate connected to the first gate line GL1, and a second electrode connected to the third node n03.

[0226] The second capacitor C02 may be connected between the first power line PL1 and the second node n02. The third capacitor C03 may be connected between the fourth node n04 and the second power line PL2.

[0227] Figure 24The pixel circuit shown can be driven in the initialization step, the first holding step, the sampling step, the second holding step and the light emitting step. Figures 25A to 29B The operation of the pixel circuit is described assuming that the sub-pixels are arranged in the nth pixel row. Figures 25A to 29B In the chart, “1H” represents one horizontal period.

[0228] Figure 25A and Figure 25B It shows Figure 24 A diagram showing the initialization steps of the pixel circuit is shown.

[0229] refer to Figure 25A and Figure 25B During the first period Pi, the initialization step is performed. During the first period Pi, the voltage of the second scan signal SCAN2 can be the gate-on voltage VGL, and the voltages of the first scan signal SCAN1 and the color-specific EM signals EM_R / G / B can be the gate-off voltages VGH and VEH. Therefore, during the first period Pi, the third switching transistor M03 and the sixth switching transistor M06 are turned on, while the other switching transistors M01, M02, M04, and M05 are turned off. During the first period Pi, the drive transistor DR is turned off.

[0230] During the first period Pi, the voltage of the second node n02 is initialized to the reference voltage Vref, and the voltage of the fifth node n05 is initialized to the data voltage Vdata(n-1) of the previous pixel row.

[0231] Figure 26A and Figure 26B It shows Figure 24 FIG. 1 is a diagram of the first hold step of the pixel circuit shown.

[0232] refer to Figure 26A and Figure 26B , a first holding step is performed during the second period Ph1. During the second period Ph1, the voltages of the first scan signal SCAN1, the second scan signal SCAN2, and the color-specific EM signal EM_R / G / B may be the gate-off voltages VGH and VEH. Therefore, during the second period Ph1, since the first to sixth switching transistors M01 to M6 are in the off state, the second to fifth nodes n02 to n05 float, and thus the voltage of the first capacitor Cst is maintained at its previous state. The drive transistor DR is in the off state during the second period Ph1.

[0233] Figure 27A and Figure 27B It shows Figure 24 Diagram of the sampling steps of the pixel circuit shown.

[0234] refer to Figure 27A and Figure 27B , a sampling step is performed during the third period Ps. During the third period Ps, the voltage of the first scan signal SCAN1 may be the gate-on voltage VGL, and the voltages of the second scan signal SCAN2 and the color-specific EM signals EM_R / G / B may be the gate-off voltages VGH and VEH. Therefore, during the third period Ps, the fourth switching transistor M04 and the fifth switching transistor M05 may be turned on. During the third period Ps, the first switching transistor M01, the second switching transistor M02, the third switching transistor M03, and the sixth switching transistor M06 are in an off state. During the third period Ps, the data voltage Vdata(n) is applied to the fifth node n05, and the voltage of the second node n02 rises to EVDD+Vth. Here, "Vth" represents the threshold voltage of the drive transistor DR. The difference between the voltage at the fifth node n05 and the voltage at the second node n02 is used to charge the first capacitor Cst.

[0235] In the case of a non-driven sub-pixel, during the sampling step, the black grayscale voltage is applied to the fifth node n05 through the data line DL and the fourth switching transistor M04.

[0236] Figure 28A and Figure 28B It shows Figure 24 FIG. 1 is a diagram of the second holding step of the pixel circuit shown.

[0237] refer to Figure 28A and Figure 28B , a second holding step is performed during the fourth period Ph2. During the fourth period Ph2, the voltages of the first scan signal SCAN1, the second scan signal SCAN2, and the color-specific EM signal EM_R / G / B may be the gate-off voltages VGH and VEH. Therefore, during the fourth period Ph2, since the first to sixth switching transistors M01 to M6 are in the off state, the second to fifth nodes n02 to n05 float, and thus the voltage of the first capacitor Cst is maintained at its previous state. The drive transistor DR is in the off state during the fourth period Ph2.

[0238] Figure 29A and Figure 29B It shows Figure 24 A diagram showing the light-emitting steps of the pixel circuit.

[0239] refer to Figure 29A and Figure 29BDuring the fifth period Pem, the light emitting step is performed. During the fifth period Pem, the voltage of the color-specific EM signal EM_R / G / B may be the gate-on voltage VEL, and the voltage of the first scan signal SCAN1 and the second scan signal SCAN2 may be the gate-off voltage VGH. During the fifth period Pem, the first switching transistor M01 and the second switching transistor M02 are turned on, while the other switching transistors M03, M04, M05, and M06 are in the off state.

[0240] During the fifth period Pem, the reference voltage Vref is applied to the fifth node n05. During the fifth period Pem, the drive transistor DR generates a current based on the gate-source voltage Vgs to drive the light-emitting element LD. The light-emitting element LD emits light during the fifth period Pem by the current ILD from the drive transistor DR. By compensating the threshold voltage Vth of the drive transistor DR during the light-emitting step, the light-emitting element LD can be driven without being affected by changes in the threshold voltage Vth and without being affected by the RC delay or IR drop of the pixel drive voltage EVDD.

[0241] Figure 30 is a waveform diagram illustrating an example of alternately driving the main sub-pixel and the redundant sub-pixel in cycles of a predetermined time period. Figure 31 Is shown by Figure 30 The diagram shows an example of an alternating driving method in which all pixels emit light simultaneously.

[0242] refer to Figure 30 and Figure 31 The main sub-pixels S1, S2, and S3 and the redundant sub-pixels S4, S5, and S6 may be alternately driven in a predetermined period (e.g., one frame period (where I is a natural number)). The description will be made assuming that the predetermined period is one frame period.

[0243] During the n-th frame period FR_n, scan signals SCAN1 and SCAN2 and the data voltage of the n-th frame image A are applied to the main sub-pixels S1, S2, and S3, and color-specific EM signals EM_R and EM_G / B are applied to the redundant sub-pixels S4, S5, and S6. At this time, the main sub-pixels S1, S2, and S3 may perform an initialization step and a sampling step to charge the data voltage of the n-th frame image A, and the light-emitting elements of the redundant sub-pixels S4, S5, and S6 may emit light at the data voltage charged in the previous frame period, the (n-1)-th frame period, to display the previous frame image.

[0244] During the (n+1)th frame period FR_n+1, the color-specific EM signals EM_R and EM_G / B are applied to the primary sub-pixels S1, S2, and S3, while the scan signals SCAN1 and SCAN2 and the data voltage of the (n+1)th frame image B are applied to the redundant sub-pixels S4, S5, and S6. At this time, the redundant sub-pixels S4, S5, and S6 can perform an initialization step and a sampling step to charge the data voltage of the (n+1)th frame image B, and the light-emitting elements of the primary sub-pixels S1, S2, and S3 can emit light with the data voltage of the nth frame image A to display the nth frame image A.

[0245] During the (n+2)th frame period FR_n+2, scan signals SCAN1 and SCAN2 and the data voltage of the (n+2)th frame image C are applied to the main sub-pixels S1, S2, and S3, and color-specific EM signals EM_R and EM_G / B are applied to the redundant sub-pixels S4, S5, and S6. At this time, the main sub-pixels S1, S2, and S3 can perform initialization steps and sampling steps to charge the data voltage of the (n+2)th frame image C, and the light-emitting elements of the redundant sub-pixels S4, S5, and S6 can emit light at the data voltage charged in the (n+1)th frame image B to display the (n+1)th frame image B.

[0246] During the (n+3)th frame period FR_n+3, the color-specific EM signals EM_R and EM_G / B are applied to the primary sub-pixels S1, S2, and S3, while the scan signals SCAN1 and SCAN2 and the data voltage of the (n+3)th frame image D are applied to the redundant sub-pixels S4, S5, and S6. At this time, the redundant sub-pixels S4, S5, and S6 can perform an initialization step and a sampling step to charge the data voltage of the (n+3)th frame image D, and the light-emitting elements of the primary sub-pixels S1, S2, and S3 can emit light with the data voltage of the (n+2)th frame image C to display the (n+2)th frame image C.

[0247] like Figure 30 As shown, the color-specific EM signals EM_R and EM_G / B can be applied to the redundant sub-pixels S4, S5, and S6 throughout the entire one-frame period without being restricted by the time required for the initialization, hold, and sampling steps. Therefore, the degree of freedom in designing the duty ratios of the color-specific EM signals EM_R and EM_G / B can be improved.

[0248] In such Figure 2In the case of the spliced display (TD) shown, when the pulse of the scan signal is shifted sequentially in units of pixel rows in the display panel, data sampling or addressing of the sub-pixels can be performed. If the display panels of the spliced display (TD) have different data sampling timings, when reproducing the image, the positions of the pixel rows displaying the data of the previous frame image in the display panel may be different from each other, and the positions of the pixel rows displaying the data of the current frame image may be different from each other. In this case, the boundaries between adjacent display panels in the spliced display may be visible in the moving object image.

[0249] when Figure 30 and Figure 31 When the alternating drive shown is applied to a tiled display, all pixels in the display panel can emit light in each frame period, thereby preventing object tearing or the appearance of boundaries within objects in the image.

[0250] According to one or more embodiments of the present disclosure, the display device can be applied to mobile devices, video phones, smart watches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, bending devices, sliding devices, variable devices, electronic organizers, e-books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop PCs, laptop PCs, netbook computers, workstations, navigation, vehicle navigation, vehicle display devices, vehicle devices, theater devices, theater display devices, televisions, wallpaper devices, signage devices, gaming devices, laptop computers, monitors, cameras, camcorders, and home appliances, etc. In addition, the display device according to one or more embodiments of the present disclosure can be applied to organic light-emitting lighting devices or inorganic light-emitting lighting devices.

[0251] The objects to be achieved by the present disclosure, means for achieving the objects, and effects of the present disclosure described above do not specify essential features of the claims, and therefore, the scope of the claims is not limited to the disclosure of the present disclosure.

[0252] Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be embodied in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are illustrative in all aspects and do not limit the present disclosure.

[0253] CROSS-REFERENCE TO RELATED APPLICATIONS

[0254] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0018631, filed on February 7, 2024, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A display panel, comprising: Multiple data lines; a plurality of gate lines crossing the data lines; Multiple power cords; as well as a plurality of pixels connected to their corresponding data lines, their corresponding gate lines and the power line, Each of the pixels comprises: sub-pixels of a first color, the sub-pixels of the first color including a first sub-pixel and a first second sub-pixel; sub-pixels of a second color, the sub-pixels of the second color including a second-first sub-pixel and a second-second sub-pixel; and a sub-pixel of a third color, wherein the sub-pixel of the third color includes a third first sub-pixel and a third second sub-pixel, Wherein, the gate line includes: a first light-emitting line connected to a sub-pixel of the first color and applied with a first light-emitting signal; and The second light-emitting line is connected to the sub-pixels of the second color and is applied with a second light-emitting signal.

2. The display panel according to claim 1, wherein: The light emission signal has a duty ratio independently set for each color of the sub-pixel.

3. The display panel according to claim 1, wherein: The second light emitting line is connected to the sub-pixel of the second color and the sub-pixel of the third color.

4. The display panel according to claim 1, wherein: The gate line also includes: A third light-emitting line is connected to the sub-pixels of the third color and is applied with a third light-emitting signal.

5. The display panel according to claim 3, wherein: The first sub-pixel and the first second sub-pixel are connected to a common data line, or are connected to different data lines. The second first sub-pixel and the second second sub-pixel are connected to a common data line, or are connected to different data lines, and The third first sub-pixel and the third second sub-pixel are connected to a common data line or to different data lines. The display panel according to claim 5 , wherein: The gate line also includes: A scan line is connected to the first first sub-pixel, the first second sub-pixel, the second first sub-pixel, the second second sub-pixel, the third first sub-pixel, and the third second sub-pixel, and a scan signal is applied to the scan line.

7. The display panel according to claim 6, wherein: The scan line includes: a first scan line configured to apply a first scan signal to the first first subpixel, the first second subpixel, the second first subpixel, the second second subpixel, the third first subpixel, and the third second subpixel; and A second scan line is configured to apply a second scan signal to the first first sub-pixel, the first second sub-pixel, the second first sub-pixel, the second second sub-pixel, the third first sub-pixel, and the third second sub-pixel.

8. The display panel according to claim 5, wherein: The gate line includes: a first group of gate lines connected to the first first sub-pixel, the second first sub-pixel, and the third first sub-pixel; and a second group of gate lines connected to the first second sub-pixel, the second second sub-pixel, and the third second sub-pixel, and The first group of gate lines includes scan lines configured to apply scan signals to the first first sub-pixel, the second first sub-pixel, and the third first sub-pixel, and The second group of gate lines includes scan lines configured to apply scan signals to the first second sub-pixel, the second second sub-pixel, and the third second sub-pixel.

9. The display panel according to claim 8, wherein: The first group of gate lines includes: a first scan line configured to apply a first scan signal to the first first sub-pixel, the second first sub-pixel, and the third first sub-pixel; and a second scan line configured to apply a second scan signal to the first first sub-pixel, the second first sub-pixel, and the third first sub-pixel, and Wherein, the second group of gate lines includes: a first scan line configured to apply a first scan signal to the first second sub-pixel, the second second sub-pixel, and the third second sub-pixel; and A second scan line configured to apply a second scan signal to the first second sub-pixel, the second second sub-pixel, and the third second sub-pixel.

10. The display panel according to claim 1, wherein Each of the first first sub-pixel and the first second sub-pixel includes: a light-emitting element; and a driving transistor configured to drive the light emitting element, and The channel ratio of the driving transistor provided in the first second sub-pixel is smaller than the channel ratio of the driving transistor provided in the first first sub-pixel.

11. A display device, comprising: a display panel, wherein a plurality of data lines, a plurality of gate lines, a plurality of power lines and a plurality of pixels are arranged in the display panel; a data driver configured to output a data voltage to the data line; as well as a gate driver configured to output a gate signal to the gate line, Each of the pixels comprises: sub-pixels of a first color, the sub-pixels of the first color including a first sub-pixel and a first second sub-pixel; sub-pixels of a second color, the sub-pixels of the second color including a second-first sub-pixel and a second-second sub-pixel; and a sub-pixel of a third color, the sub-pixel of the third color including a third first sub-pixel and a third second sub-pixel, and Wherein, the gate line includes: a first light-emitting line connected to a sub-pixel of the first color and applied with a first light-emitting signal; and The second light-emitting line is connected to the sub-pixels of the second color and is applied with a second light-emitting signal.

12. The display device according to claim 11, wherein The second light emitting line is connected to the sub-pixel of the second color and the sub-pixel of the third color.

13. The display device according to claim 11, wherein The gate line also includes: A third light-emitting line is connected to the sub-pixels of the third color and is applied with a third light-emitting signal.

14. The display device according to claim 11, wherein driving only one of the first first sub-pixel and the first second sub-pixel, The first sub-pixel and the first second sub-pixel are alternately driven in a cycle of a predetermined time period, or The first first sub-pixel and the first second sub-pixel are driven simultaneously.

15. The display device according to claim 14, wherein When only one of the first first subpixel and the first second subpixel is driven, pixel data of an input image is written to one of the first first subpixel and the first second subpixel, and black grayscale data is written to the other subpixel.

16. The display device according to claim 11, wherein During the n-th frame period, pixel data of the n-th frame image is written into the first first sub-pixel, the second first sub-pixel, and the third first sub-pixel, the first light-emitting signal is applied to the first second sub-pixel, and the second light-emitting signal is applied to the second second sub-pixel and the third second sub-pixel, so that the first second sub-pixel, the second second sub-pixel, and the third second sub-pixel emit light, and During the (n+1)th frame period, pixel data of the (n+1)th frame image is written into the first-second sub-pixel, the second-second sub-pixel, and the third-second sub-pixel, the first light-emitting signal is applied to the first-first sub-pixel, and the second light-emitting signal is applied to the second-first sub-pixel and the third-first sub-pixel, so that the first-first sub-pixel, the second-first sub-pixel, and the third-first sub-pixel emit light, Wherein, n is a natural number.

17. The display device according to claim 16, wherein: A duty cycle of the first light emitting signal is different from a duty cycle of the second light emitting signal.

18. The display device according to claim 11, wherein Each of the sub-pixels comprises: a light-emitting element including an anode to which a pixel driving voltage is applied; a switching transistor to which a ground voltage is applied; and A driving transistor is connected between the cathode of the light emitting element and the switching transistor.

19. The display device according to claim 11, wherein Each of the sub-pixels comprises: a light-emitting element including a cathode to which a ground voltage is applied; a driving transistor to which a pixel driving voltage is applied; and A switching transistor is connected between the driving transistor and the anode of the light emitting element.

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