Display panel

Abstract

The embodiment of the invention provides a display panel. According to the display panel, in a gate drive circuit on at least one side of a pixel, in a first direction, a second output unit of a first-type gate circuit and a second output unit of a second-type gate circuit are located between a first output unit of the first-type gate circuit and a first output unit of the second-type gate circuit; the distance between the second output unit of the first-type gate circuit and the second output unit of the second-type gate circuit is shortened, so that when the second output unit of the first-type gate circuit and the second output unit of the second-type gate circuit are formed, the process consistency of the first-type gate circuit and the second output unit of the second-type gate circuit is good, the electrical difference of the first-type gate circuit and the second-type gate circuit is small or even no difference exists, and the reliability of the device is improved. Therefore, the difference between the signals output to the switch transistors of the two adjacent rows of pixel driving circuits by the first type of grid circuits and the second type of grid circuits is small or even no difference, the difference between the data signals written by the two adjacent rows of pixels is small or even no difference, and display abnormity is avoided.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel. Background Art

[0002] With the development of display technology, existing display devices have higher and higher requirements for display effects. In order to improve the display effect, existing display devices will adopt LTPO (Low Temperature Polysilicon Oxide, low temperature polycrystalline silicon oxide) pixel circuits, but the LTPO pixel driving circuit requires more GOA (Gate On Array, gate driving circuit arranged on the array substrate) circuits to output signals, which will lead to an increase in the power consumption of the display device. In order to reduce the power consumption of the display device, CMOS (Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductor) GOA circuits will be used to reduce the number of GOA circuits. Specifically, two GOA units in a first-level CMOS GOA circuit will be used to output signals for odd and even rows respectively, but in actual use, it was found that there was a difference in the writing of data signals of pixels in odd and even rows, resulting in a difference in the brightness of pixels in odd and even rows, resulting in display abnormalities.

[0003] Therefore, in existing display devices, there is a technical problem that the data signals written into pixels in odd-numbered rows and even-numbered rows are different, resulting in abnormal display. Summary of the Invention

[0004] An embodiment of the present application provides a display panel for alleviating the technical problem of display abnormality caused by differences in data signals written into pixels in odd and even rows in existing display devices.

[0005] In order to achieve the above-mentioned objective, according to a first aspect of the present application, a display panel is provided, comprising:

[0006] A plurality of rows of pixels, each pixel comprising a light-emitting device and a pixel driving circuit, wherein the pixel driving circuit comprises a switching transistor, a compensation transistor, and a first initialization transistor;

[0007] a multi-stage gate driving circuit, arranged on at least one side of the pixel along a first direction, each stage of the gate driving circuit comprising a first type of gate circuit and a second type of gate circuit arranged along the first direction, the first type of gate circuit and the second type of gate circuit each comprising a first output unit, a second output unit, a first signal output terminal, and a second signal output terminal, the first output unit being electrically connected to the first signal output terminal, the second output unit being electrically connected to the second signal output terminal, the first signal output terminal and the second signal output terminal of the first type of gate circuit at this stage being respectively connected to the gates of the compensation transistors of two adjacent stages and the gates of the switching transistors of the pixel driving circuit in this row, and the first signal output terminal and the second signal output terminal of the second type of gate circuit at this stage being respectively connected to the gates of the first initialization transistors of two adjacent stages and the gates of the switching transistors of the pixel driving circuit in the next row;

[0008] In the gate driving circuit on at least one side of the pixel, in the first direction, the second output unit of the first type gate circuit and the second output unit of the second type gate circuit are located between the first output unit of the first type gate circuit and the first output unit of the second type gate circuit.

[0009] An embodiment of the present application provides a display panel; in the gate driving circuit on at least one side of the pixel, the display panel shortens the distance between the second output unit of the first type gate circuit and the second output unit of the second type gate circuit by making the second output unit of the first type gate circuit and the second output unit of the second type gate circuit located between the first output unit of the first type gate circuit and the first output unit of the second type gate circuit in the first direction. When the second output unit of the first type gate circuit and the second output unit of the second type gate circuit are formed, the process consistency between the two is good, so that the electrical difference between the two is small or even no difference. Then, the difference between the signals output by the first type gate circuit and the second type gate circuit to the switching transistors of the pixel driving circuits of two adjacent rows is small or even no difference, and the difference between the data signals written by the pixels in two adjacent rows is small or even no difference, thereby avoiding display abnormalities.

[0010] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] To more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. Those skilled in the art can also derive other drawings based on these drawings without inventive effort.

[0012] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same drawing numbers represent the same parts in the following description.

[0013] Figure 1 A schematic plan view of a display panel provided in an embodiment of the present application.

[0014] Figure 2 A schematic cross-sectional view of a display panel provided in an embodiment of the present application.

[0015] Figure 3 A circuit diagram of a pixel driving circuit of a display panel provided in an embodiment of the present application.

[0016] Figure 4 Circuit diagram of the first type of gate circuit and the second type of gate circuit of the gate drive circuit provided in the embodiment of the present application.

[0017] Figure 5 This is a first stacking diagram of the film layers of the display panel provided in an embodiment of the present application.

[0018] Figure 6 This is a second stacking diagram of the film layers of the display panel provided in an embodiment of the present application.

[0019] Figure 7 for Figure 6 A stacking diagram of the film layers in the area corresponding to the first type of gate circuit of the display panel.

[0020] Figure 8 for Figure 7 An exploded view of the active layer of a display panel.

[0021] Figure 9 for Figure 7 An exploded view of the first gate layer of the display panel.

[0022] Figure 10 for Figure 7 An exploded view of the second gate layer of the display panel.

[0023] Figure 11 for Figure 7 An exploded view of the semiconductor layers of a display panel.

[0024] Figure 12 for Figure 7 An exploded view of the third gate layer of the display panel in FIG.

[0025] Figure 13 for Figure 7 Exploded view of the first source and drain layer of the display panel.

[0026] Figure 14 for Figure 7An exploded view of the second source and drain layer of the display panel.

[0027] Figure 15 for Figure 7 An exploded view of the third source and drain layer of the display panel.

[0028] Figure 16 for Figure 7 Exploded view of the first via hole of the display panel.

[0029] Figure 17 for Figure 7 Exploded view of the second via hole of the display panel.

[0030] Figure 18 for Figure 7 Exploded view of the third via hole of the display panel.

[0031] Figure 19 for Figure 7 Exploded view of the fourth via hole of the display panel.

[0032] Figure 20 for Figure 7 A stacking diagram of the active layer and the first gate layer of the display panel.

[0033] Figure 21 for Figure 7 A stacked diagram of the active layer, the first gate layer, and the second gate layer of the display panel.

[0034] Figure 22 for Figure 7 A stacking diagram of the active layer, the first gate layer, the second gate layer and the first via hole of the display panel.

[0035] Figure 23 for Figure 7 A stacked diagram of the active layer, first gate layer, second gate layer, first via hole and semiconductor layer of the display panel.

[0036] Figure 24 for Figure 7 A stacked diagram of the active layer, first gate layer, second gate layer, first via hole, semiconductor layer and third gate layer of the display panel.

[0037] Figure 25 for Figure 7 A stacking diagram of the active layer, first gate layer, second gate layer, first via, semiconductor layer, third gate layer and second via of the display panel.

[0038] Figure 26 for Figure 7 A stacked diagram of the active layer, first gate layer, second gate layer, first via, semiconductor layer, third gate layer, second via and first source and drain layer of the display panel.

[0039] Figure 27 for Figure 7 A stacking diagram of the active layer, first gate layer, second gate layer, first via, semiconductor layer, third gate layer, second via, first source and drain layer, and third via of the display panel.

[0040] Figure 28 for Figure 7 A stacked diagram of the active layer, first gate layer, second gate layer, first via, semiconductor layer, third gate layer, second via, first source and drain electrode layer, third via and second source and drain electrode layer of the display panel.

[0041] Figure 29 for Figure 7 A stacking diagram of the active layer, first gate layer, second gate layer, first via, semiconductor layer, third gate layer, second via, first source and drain layer, third via, second source and drain layer and fourth via of the display panel.

[0042] Figure 30 for Figure 7 A stacked diagram of the active layer, first gate layer, second gate layer, first via, semiconductor layer, third gate layer, second via, first source and drain layer, third via, second source and drain layer, fourth via and third source and drain layer of the display panel. DETAILED DESCRIPTION

[0043] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0044] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," "connected," "electrically connected," and "electrically connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections, electrical connections, or mutual communication; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal communication between two components or the interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0045] In order to illustrate the principle of the technical problem of the present application, some comparative display devices are provided. It should be understood that these comparative display devices cannot be used as the prior art in the embodiments of the present application. To reduce power consumption, existing display devices employ CMOS GOA circuits to reduce the number of GOA circuits. Specifically, two CMOS GOA circuits are provided in a first-level GOA circuit on one side of a comparative display device. One CMOS GOA circuit outputs scan signals for the compensation transistors of two rows of pixels and scan signals for the switching transistors of the pixels in the current row. The other CMOS GOA circuit outputs scan signals for the initialization transistors of two rows of pixels and scan signals for the switching transistors of the next row of pixels. The two CMOS GOA circuits are arranged in a similar repeating unit configuration, i.e., the arrangement direction and order of the units in one CMOS GOA circuit are identical to those in the other CMOS GOA circuit. This results in a large distance between the output units that output the scan signals for the switching transistors in the two CMOS GOA circuits. During the fabrication of the GOA circuits, the process uniformity of the output units in the two CMOS GOA circuits is poor, resulting in significant differences in the electrical properties of the output units in the two CMOS GOA circuits. This results in differences in the rise and fall times of the scan signals received by the switching transistors of the two rows of pixels, leading to differences in data signal writing. This, in turn, leads to differences in the brightness of pixels in odd and even rows, resulting in display anomalies. Therefore, in existing display devices, there is a technical problem that the data signals written into pixels in odd-numbered rows and even-numbered rows are different, resulting in abnormal display.

[0046] In order to solve the above technical problems, the embodiments of the present application provide a display panel to alleviate the above technical problems.

[0047] like Figure 2 As shown, an embodiment of the present application provides a display panel 1, which includes a display area 101 and a non-display area 102. A plurality of rows of pixels 13 are provided in the display area 101. The pixels 13 include a light-emitting device LED and a pixel driving circuit 11 for driving the light-emitting device LED. A multi-stage gate driving circuit 12 is provided in the non-display area 102. The multi-stage gate driving circuit 12 can be arranged along the second direction Y. The gate driving circuit 12 is used to output a scanning signal to the pixel driving circuit 11.

[0048] Specifically, in the embodiment of the present application, the pixel 13 can be at least one of a red sub-pixel, a green sub-pixel, and a blue sub-pixel, and the red sub-pixel, the green sub-pixel, and the blue sub-pixel emit red, green, and blue, respectively. It is understood that each sub-pixel has a light-emitting device LED and a pixel driving circuit 11 that drives the light-emitting device LED.

[0049] Specifically, such as Figure 1As shown, the non-display area 102 can be arranged around the display area 101, but the embodiment of the present application is not limited thereto. The non-display area 102 can be arranged on one side, two sides, or three sides of the display area 101, and the non-display area 102 can be bent to the back of the display area 101. The non-display area 102 can include an upper frame area, a lower frame area, a left frame area, and a right frame area. The gate driving circuit 12 can be arranged in the left frame area and / or the right frame area. The gate driving circuit 12 can be arranged on one side of the display area 101 or on both sides of the display area 101 along the first direction X.

[0050] like Figure 2 As shown, as a specific structure of a display panel 1 in an embodiment of the present application, the display panel 1 includes a substrate 201, a light-shielding layer 202, a buffer layer 203, a blocking layer 204, an active layer 205, a first gate insulating layer 206, a first gate layer 207, a second gate insulating layer 208, a second gate layer 209, a first interlayer insulating layer 210, a semiconductor layer 211, a third gate insulating layer 212, a third gate layer 213, a second interlayer insulating layer 214, a first source-drain layer 215, a first planarization layer 216, a second source-drain layer 217, a second planarization layer 218, a third source-drain layer 219 and a light-emitting functional layer, which are arranged in sequence.

[0051] Specifically, the light-emitting functional layer may include a pixel electrode layer, a pixel definition layer, a light-emitting material layer and a common electrode layer.

[0052] Specifically, the material of the semiconductor layer 211 includes an oxide semiconductor, specifically a metal oxide, more specifically indium gallium zinc oxide.

[0053] Specifically, the material of the active layer 205 includes silicon semiconductor material, specifically low-temperature polysilicon.

[0054] Specifically, such as Figure 2 As shown, Figure 2 It is shown that the display panel 1 includes a first source-drain layer, a second source-drain layer, and a third source-drain layer. This is because the embodiment of the present application is described by taking the design of a display panel that reduces the impedance of the signal line as an example, but the embodiment of the present application is not limited to this. The display panel 1 may include only one or two of the first source-drain layer, the second source-drain layer, and the third source-drain layer.

[0055] Specifically, such as Figure 2 As shown, Figure 2 The buffer layer, barrier layer and light shielding layer are shown in FIG, but the embodiments of the present application are not limited thereto, and one or more layers of these film layers may be removed.

[0056] like Figure 3As shown, the pixel driving circuit 11 includes: a driving transistor T31, a switching transistor T32, a compensation transistor T33, a first initialization transistor T34, a first light emitting transistor T35, a second light emitting transistor T36, a second initialization transistor T37 and a third initialization transistor T38.

[0057] Specifically, such as Figure 3 As shown, the gate of the switching transistor T32 is connected to the second scan line Pscan1, the first electrode of the switching transistor T32 is connected to the data signal line Data, the second electrode of the switching transistor T32 is connected to the first electrode of the driving transistor T31, the gate of the compensation transistor T33 is connected to the first scan line Nscan1, the second electrode of the compensation transistor T33 is connected to the second electrode of the first initialization transistor T34, the first electrode of the compensation transistor T33 is connected to the second electrode of the driving transistor T31, the gate of the first initialization transistor T34 is connected to the third scan line Nscan2, the first electrode of the first initialization transistor T34 is connected to the first initialization line Vi1, the gate of the first light-emitting transistor T35 is connected to the light-emitting control line EM, the first electrode of the first light-emitting transistor T35 is connected to the power high potential signal line VDD, and the first The second electrode of the light-emitting transistor T35 is connected to the first electrode of the driving transistor T31, the gate of the second light-emitting transistor T36 is connected to the light-emitting control line EM, the first electrode of the second light-emitting transistor T36 is connected to the second electrode of the driving transistor T31, the second electrode of the second light-emitting transistor T36 is connected to the light-emitting device LED, the gate of the second initialization transistor T37 is connected to the fourth scan line Pscan2, the first electrode of the second initialization transistor T37 is connected to the second initialization line Vi2, the second electrode of the second initialization transistor T37 is connected to the light-emitting device LED, the gate of the third initialization transistor T38 is connected to the fourth scan line Pscan2, the first electrode of the third initialization transistor T38 is connected to the third initialization line Vi3, and the second electrode of the third initialization transistor T38 is connected to the first electrode of the driving transistor T31.

[0058] Specifically, such as Figure 3 As shown, the light-emitting device LED is connected to the low-potential signal line VSS of the power supply, and the pixel driving circuit further includes a storage capacitor Cst and a boost capacitor Cboost. One end of the storage capacitor Cst is connected to the high-potential signal line VDD of the power supply, and the other end of the storage capacitor Cst is connected to the gate of the driving transistor T31; one end of the boost capacitor Cboost is connected to the gate of the switching transistor T32, and the other end of the boost capacitor Cboost is connected to the gate of the driving transistor T31.

[0059] Specifically, such as Figure 4As shown, the gate drive circuit 12 includes a first type gate circuit 121 and a second type gate circuit 122, the second signal output terminal Pout(n) of the first type gate circuit 121 is connected to the gate of the switching transistor T32 of the pixel in this row, the second signal output terminal Pout(n+1) of the second type gate circuit 122 is connected to the gate of the switching transistor T32 of the pixel in the next row, the first signal output terminal Nout1(n) of the first type gate circuit 121 is electrically connected to the gate of the compensation transistor T33, and the first signal output terminal Nout2(n) of the second type gate circuit 122 is electrically connected to the gate of the first initialization transistor T34.

[0060] Specifically, the gate driving circuit further includes a gate circuit for outputting a signal of the light emitting control line EM and a gate circuit for outputting a signal of the fourth scan line Pscan2.

[0061] Specifically, the driving transistor T31 , the switching transistor T32 , the first light emitting transistor T35 , the second light emitting transistor T36 , the second initialization transistor T37 and the third initialization transistor T38 are silicon semiconductor transistors, and the compensation transistor T33 and the first initialization transistor T34 are oxide semiconductor transistors.

[0062] Specifically, the driving transistor T31 , the switching transistor T32 , the first light emitting transistor T35 , the second light emitting transistor T36 , the second initialization transistor T37 and the third initialization transistor T38 are P-type transistors, and the compensation transistor T33 and the first initialization transistor T34 are N-type transistors.

[0063] Specifically, the oxide semiconductor transistor may be a metal oxide transistor, and the silicon semiconductor transistor may be a low-temperature polysilicon transistor.

[0064] like Figures 1 to 30As shown, an embodiment of the present application provides a display panel, which includes a plurality of rows of pixels 13 and a multi-stage gate driving circuit 12; the pixel 13 includes a light-emitting device LED and a pixel driving circuit 11, and the pixel driving circuit 11 includes a switching transistor T32, a compensation transistor T33 and a first initialization transistor T34; the multi-stage gate driving circuit 12 is arranged on at least one side of the pixel 13 along a first direction X, and each stage of the gate driving circuit 12 includes a first type of gate circuit 121 and a second type of gate circuit 122 arranged along the first direction X, and the first type of gate circuit 121 and the second type of gate circuit 122 each include a first output unit 30, a second output unit 40, a first signal output terminal and a second output terminal. Signal output end, the first output unit 30 is electrically connected to the first signal output end, the second output unit 40 is electrically connected to the second signal output end, the first signal output end Nout1(n) and the second signal output end Pout(n) of the first type gate circuit 121 of this level are respectively connected to the gates of the compensation transistors T33 of the two adjacent levels and the gate of the switching transistor T32 of the pixel driving circuit 11 of this row, the first signal output end Nout2(n) and the second signal output end Pout(n+1) of the second type gate circuit 122 of this level are respectively connected to the gates of the first initialization transistors T34 of the two adjacent levels and the gate of the switching transistor T32 of the pixel driving circuit 11 of the next row.

[0065] In some embodiments, in the gate driving circuit 12 on at least one side of the pixel 13, in the first direction X, the second output unit 40 of the first type gate circuit 121 and the second output unit 40 of the second type gate circuit 122 are located between the first output unit 30 of the first type gate circuit 121 and the first output unit 30 of the second type gate circuit 122.

[0066] An embodiment of the present application provides a display panel; in the display panel, in the gate driving circuit 12 on at least one side of the pixel 13, in the first direction X, the second output unit 40 of the first type gate circuit 121 and the second output unit 40 of the second type gate circuit 122 are located between the first output unit 30 of the first type gate circuit 121 and the first output unit 30 of the second type gate circuit 122, thereby shortening the distance between the second output unit 40 of the first type gate circuit 121 and the second output unit 40 of the second type gate circuit 122. When the second output unit 40 of the first type gate circuit 121 and the second output unit 40 of the second type gate circuit 122 are formed, the process consistency between the two is good, so that the electrical difference between the two is small or even no difference. Therefore, the difference between the signals output by the first type gate circuit 121 and the second type gate circuit 122 to the switching transistors T32 of the pixel driving circuit 11 of the two adjacent rows is small or even no difference, and the difference between the data signals written to the pixels in the two adjacent rows is small or even no difference, thereby avoiding display abnormalities.

[0067] In some embodiments, as Figure 1 、 Figure 4 、 Figure 5 As shown, in the gate driving circuit 12 on at least one side of the pixel 13, in the first direction X, the second output unit 40 of the first type gate circuit 121 and the second output unit 40 of the second type gate circuit 122 are symmetrically arranged about a symmetry axis.

[0068] Specifically, by arranging the second output unit 40 of the first type gate circuit 121 and the second output unit 40 of the second type gate circuit 122 symmetrically about a symmetry axis, the distance between the second output unit 40 of the first type gate circuit 121 and the second output unit 40 of the second type gate circuit 122 can be shortened. Then, when forming the second output unit 40 of the first type gate circuit 121 and the second output unit 40 of the second type gate circuit 122, the process consistency between the two is good, so that the electrical difference between the two is small or even no difference. Then, the difference between the signals output by the first type gate circuit 121 and the second type gate circuit 122 to the switching transistors T32 of the two adjacent rows of pixel driving circuits 11 is small or even no difference, and the difference between the data signals written into the two adjacent rows of pixels is small or even no difference, thereby avoiding display abnormalities.

[0069] In some embodiments, as Figures 4 to 6As shown, the first type gate circuit 121 and the second type gate circuit 122 both include a first control unit 10, a second control unit 20, a third control unit 801, a fourth control unit 802, an output control unit 60, a frequency division unit 50, a reset unit 70, and a switch unit 90 that are electrically connected; the first control unit 10, the second control unit 20, the third control unit 801, the fourth control unit 802, the output control unit 60, the frequency division unit 50, the reset unit 70, and the switch unit 90 in the first type gate circuit 121 are respectively symmetrically arranged with the first control unit 10, the second control unit 20, the third control unit 801, the fourth control unit 802, the output control unit 60, the frequency division unit 50, the reset unit 70, and the switch unit 90 in the second type gate circuit 122 about the symmetry axis.

[0070] Specifically, by symmetrically arranging the units in the first type of gate circuit 121 and the corresponding units in the second type of gate circuit 122, the electrical properties of the first type of gate circuit are similar to or even the same as those of the second type of gate circuit. Then, the difference between the signals output by the first type of gate circuit and the second type of gate circuit is small or even no difference, thereby avoiding display abnormalities.

[0071] In some embodiments, as Figure 4 、 Figure 5 As shown, the display panel 1 also includes a first type of clock signal line CK and a second type of clock signal line XCK, the first type of clock signal line CK and the second type of clock signal line XCK are electrically connected to the first type of gate circuit 121, and the first type of clock signal line CK and the second type of clock signal line XCK are electrically connected to the second type of gate circuit 122; wherein, in the gate driving circuit 12 on at least one side of the pixel, in the first direction X, the first type of clock signal line CK and the second type of clock signal line XCK are provided between the second output unit 40 of the first type of gate circuit 121 and the second output unit 40 of the second type of gate circuit 122.

[0072] Specifically, such as Figure 5As shown, compared with the comparative display device in which the second output unit 40 of the first type gate circuit 121 is far away from the second output unit 40 of the second type gate circuit 122, the embodiment of the present application provides the first type clock signal line CK and the second type clock signal line XCK between the second output unit 40 of the first type gate circuit 121 and the second type gate circuit 122, so that the distance between the second output unit 40 of the first type gate circuit 121 and the second type gate circuit 122 is closer, thereby avoiding display abnormalities, and no modification or only simple modification of the design in the first type gate circuit is required, and the design in the second type gate circuit can be symmetrically arranged with the design in the first type gate circuit, reducing the process difficulty and complexity.

[0073] Specifically, such as Figure 5 As shown, the display panel 1 also includes a plurality of first-type high-potential signal lines PVGH, a plurality of second-type high-potential signal lines NVGH, a plurality of first-type low-potential signal lines PVGL, a plurality of second-type low-potential signal lines NVGL, a first control signal line Control1, a second control signal line Control2, a plurality of first frequency-dividing signal lines PLF, a plurality of second frequency-dividing signal lines NLF, a first start signal line STV1, a second start signal line STV2, a first-type clock signal line CK, and a second-type clock signal line XCK, which are electrically connected to the gate drive circuit 12.

[0074] Specifically, the first-type clock signal line CK includes a first clock signal line PCK1, a second clock signal line PCK2, a third clock signal line PCK3, and a fourth clock signal line PCK4; the second-type clock signal line XCK includes a fifth clock signal line ECK1, a sixth clock signal line ECK2, a seventh clock signal line ECK3, and an eighth clock signal line ECK4; the first clock signal line PCK1 and the third clock signal line PCK3 are electrically connected to two adjacent stages of the first-type gate circuit 121, respectively; the second clock signal line PCK2 and the fourth clock signal line PCK4 are electrically connected to two adjacent stages of the second-type gate circuit 122, respectively; the fifth clock signal line ECK1 and the sixth clock signal line ECK2 are electrically connected to two adjacent stages of the first-type gate circuit 121, respectively; the seventh clock signal line ECK3 and the eighth clock signal line ECK4 are electrically connected to two adjacent stages of the second-type gate circuit 122, respectively;

[0075] In some embodiments, in the setting area of the first type gate circuit 121, in the first direction X, the second type high potential signal line NVGH, the second type low potential signal line NVGL, the second frequency-dividing signal line NLF, the first control signal line Control1, a first type high potential signal line PVGH, the first low potential signal line PVGL, the first frequency-dividing signal line PLF, another first type high potential signal line PVGH, the fifth clock signal line ECK1, the sixth clock signal line ECK2, the first clock signal line PCK1, and the third clock signal line PCK3 are arranged in sequence; in the setting area of the second type gate circuit 122, in the opposite direction of the first direction X, the second type high potential signal line NVGH, the second type low potential signal line NVGL, the second frequency-dividing signal line NLF, the second control signal line Control2, a first type high potential signal line PVGH, the first low potential signal line PVGL, the first frequency-dividing signal line PLF, another first type high potential signal line PVGH, the seventh clock signal line ECK3, the eighth clock signal line ECK4, the second clock signal line PCK2, and the fourth clock signal line PCK4 are arranged in sequence.

[0076] Specifically, the embodiment of the present application adjusts the setting position of the signal line, thereby shortening the distance between the second output unit 40 of the first type gate circuit 121 and the second output unit 40 of the second type gate circuit 122, so that the spacing between the transistors in each unit and the corresponding signal lines is smaller, which is convenient for connection, occupies less space, and has smaller parasitic capacitance.

[0077] Specifically, it is understandable that Figure 4 The first-class clock signal line CK is used to mark it. In the actual connection process, one-level first-class gate circuit 121 in two adjacent gate drive circuits is electrically connected to the first clock signal line PCK1, and the other-level first-class gate circuit 121 is electrically connected to the third clock signal line PCK3. One-level second-class gate circuit 122 in two adjacent gate drive circuits is electrically connected to the second clock signal line PCK2, and the other-level second-class gate circuit 122 is electrically connected to the fourth clock signal line PCK4.

[0078] Specifically, the timings of the first clock signal line PCK1 , the second clock signal line PCK2 , the third clock signal line PCK3 and the fourth clock signal line PCK4 are different.

[0079] Specifically, it is understandable that Figure 4The second-class clock signal line XCK is used to mark it. In the actual connection process, the first-class gate circuit 121 of one of the two adjacent gate drive circuits is electrically connected to the fifth clock signal line ECK1, and the first-class gate circuit 121 of the other level is electrically connected to the sixth clock signal line ECK2. The second-class gate circuit 122 of one of the two adjacent gate drive circuits is electrically connected to the seventh clock signal line ECK3, and the second-class gate circuit 122 of the other level is electrically connected to the eighth clock signal line ECK4.

[0080] Specifically, the timing of the fifth clock signal line ECK1 may be the same as or different from the timing of the seventh clock signal line ECK3, and the timing of the sixth clock signal line ECK2 may be the same as or different from the timing of the eighth clock signal line ECK4.

[0081] Specifically, the fifth clock signal line ECK1 and the sixth clock signal line ECK2 may have different timings, and the seventh clock signal line ECK3 and the eighth clock signal line ECK4 may have different timings.

[0082] Specifically, it is understandable that Figure 4 In the embodiment, the first type gate circuit 121 in the first-level gate driving circuit is electrically connected to the first starting signal line STV1, the first type gate circuit 121 in other levels of gate driving circuits is electrically connected to the internal node P(n-1) of the first type gate circuit 121 in the previous level gate driving circuit, the second type gate circuit 122 in the first level gate driving circuit is electrically connected to the second starting signal line STV2, and the second type gate circuit 122 in other levels of gate driving circuits is electrically connected to the internal node P(n-1) of the second type gate circuit 122 in the previous level gate driving circuit.

[0083] Specifically, the timings of the first start signal line STV1 and the second start signal line STV2 are different.

[0084] Specifically, it is understandable that Figure 4 In the embodiment, the first type gate circuit 121 is electrically connected to the first control signal line Control1, and the second type gate circuit 122 is electrically connected to the second control signal line Control2. The timings of the first control signal line Control1 and the second control signal line Control2 can be the same or different.

[0085] In some embodiments, as Figure 4 、 Figure 6As shown, in the gate driving circuit 12 on at least one side of the pixel 13, in the first direction X, the second output unit 40 of the first type gate circuit 121 and the second output unit 40 of the second type gate circuit 122 are arranged adjacent to each other, and no signal line is provided between the second output unit 40 of the first type gate circuit 121 and the second output unit 40 of the second type gate circuit 122.

[0086] Specifically, such as Figure 6 As shown, by arranging the second output unit 40 of the first type gate circuit 121 adjacent to the second output unit 40 of the second type gate circuit 122, and no signal line is provided between the second output unit 40 of the first type gate circuit 121 and the second output unit 40 of the second type gate circuit 122, the distance between the second output unit 40 of the first type gate circuit 121 and the second type gate circuit 122 can be further shortened, and the process difference between the second output unit 40 of the first type gate circuit 121 and the second type gate circuit 122 can be further reduced, so that the difference between the signals output by the first type gate circuit 121 and the second type gate circuit 122 to the switching transistors T32 of the two adjacent rows of pixel driving circuits 11 is small or even no difference, and the difference between the data signals written into the two adjacent rows of pixels is small or even no difference, thereby avoiding display abnormalities.

[0087] In some embodiments, as Figure 6 As shown, the display panel 1 also includes a plurality of first high potential signal lines PVGH1, a plurality of second high potential signal lines PVGH2, a plurality of third high potential signal lines NVGH1, a plurality of fourth high potential signal lines NVGH2, a plurality of first low potential signal lines PVGL, a plurality of second low potential signal lines NVGL1, a plurality of third low potential signal lines NVGL2, a first control signal line Control1, a second control signal line Control2, a plurality of first frequency division signal lines PLF, a plurality of second frequency division signal lines NLF, a first start signal line STV1, a second start signal line STV2, a first type of clock signal line CK and a second type of clock signal line XCK, which are electrically connected to the gate drive circuit 12.

[0088] Specifically, the first type of clock signal line CK includes a first clock signal line PCK1, a second clock signal line PCK2, a third clock signal line PCK3 and a fourth clock signal line PCK4, and the second type of clock signal line XCK includes a fifth clock signal line ECK1, a sixth clock signal line ECK2, a seventh clock signal line ECK3 and an eighth clock signal line ECK4. The first clock signal line PCK1 and the third clock signal line PCK3 are electrically connected to the first type gate circuit 121 of two adjacent levels, respectively, the second clock signal line PCK2 and the fourth clock signal line PCK4 are electrically connected to the second type gate circuit 122 of two adjacent levels, respectively, the fifth clock signal line ECK1 and the sixth clock signal line ECK2 are electrically connected to the first type gate circuit 121 of two adjacent levels, respectively, and the seventh clock signal line ECK3 and the eighth clock signal line ECK4 are electrically connected to the second type gate circuit 122 of two adjacent levels, respectively.

[0089] In some embodiments, within the setting area of the first type gate circuit 121, in the first direction X, the third high potential signal line NVGH1, the fourth high potential signal line NVGH2, the second low potential signal line NVGL1, the third low potential signal line NVGL2, the first high potential signal line PVGH1, the first control signal line Control1, the second high potential signal line PVGH2, the second frequency-dividing signal line NLF, the first low potential signal line PVGL, the first frequency-dividing signal line PLF, the fifth clock signal line ECK1, the sixth clock signal line ECK2, the first clock signal line PCK1, the third clock signal line PCK3, the first start signal line STV1 and another first high potential signal line PVGH1 are set in sequence.

[0090] In some embodiments, within the setting area of the second type gate circuit 122, in the opposite direction of the first direction X, the third high potential signal line NVGH1, the fourth high potential signal line NVGH2, the second low potential signal line NVGL1, the third low potential signal line NVGL2, the first high potential signal line PVGH1, the second control signal line Control2, the second high potential signal line PVGH2, the second frequency division signal line NLF, the first low potential signal line PVGL, the first frequency division signal line PLF, the seventh clock signal line ECK3, the eighth clock signal line ECK4, the second clock signal line PCK2, the fourth clock signal line PCK4, the second start signal line STV2 and another first high potential signal line PVGH1 are set in sequence.

[0091] Specifically, the embodiment of the present application adjusts the setting position of the signal line, thereby shortening the distance between the second output unit 40 of the first type gate circuit 121 and the second output unit 40 of the second type gate circuit 122, so that the spacing between the transistors in each unit and the corresponding signal lines is smaller, which is convenient for connection, occupies less space, and has smaller parasitic capacitance.

[0092] Specifically, the output voltages of the first high potential signal line PVGH1 and the second high potential signal line PVGH2 can be the same, the difference being that the first high potential signal line PVGH1 and the second high potential signal line PVGH2 are connected to two adjacent gate drive circuits, respectively. It is understandable that when the display panel includes the first high potential signal line PVGH1 and the second high potential signal line PVGH2, Figure 4 The first type of high potential signal line PVGH in the PVGH refers to the first high potential signal line PVGH1 or the second high potential signal line PVGH2.

[0093] Specifically, the output voltages of the third high potential signal line NVGH1 and the fourth high potential signal line NVGH2 can be the same, the difference being that the third high potential signal line NVGH1 and the fourth high potential signal line NVGH2 are connected to two adjacent gate drive circuits, respectively. It is understandable that when the display panel includes the third high potential signal line NVGH1 and the fourth high potential signal line NVGH2, Figure 4 The second type of high potential signal line NVGH in the NVGH refers to the third high potential signal line NVGH1 or the fourth high potential signal line NVGH2.

[0094] Specifically, the output voltages of the second low potential signal line NVGL1 and the third low potential signal line NVGL2 can be the same, the difference being that the second low potential signal line NVGL1 and the third low potential signal line NVGL2 are connected to two adjacent gate drive circuits, respectively. It is understandable that when the display panel includes the second low potential signal line NVGL1 and the third low potential signal line NVGL2, Figure 4 The second type of low potential signal line NVGL in the NVGL structure refers to the second low potential signal line NVGL1 or the third low potential signal line NVGL2.

[0095] Specifically, Figure 6 In the description, the display panel includes the first high potential signal line PVGH1 and the second high potential signal line PVGH2 as an example, but the embodiment of the present application is not limited thereto. The display panel may include only the first type of high potential signal line PVGH.

[0096] Specifically, Figure 6 In the description, the display panel includes the third high potential signal line NVGH1 and the fourth high potential signal line NVGH2 as an example, but the embodiment of the present application is not limited thereto. The display panel may include only the second type high potential signal line NVGH.

[0097] Specifically, Figure 6 In the description, the display panel includes the second low potential signal line NVGL1 and the third low potential signal line NVGL2 as an example, but the embodiments of the present application are not limited thereto. The display panel may include only the second type of low potential signal line NVGL.

[0098] Specifically, in Figure 5 The first start signal line STV1 and the second start signal line STV2 are not shown in FIG. Figure 5 A first start signal line STV1 and a second start signal line STV2 may also be provided.

[0099] In some embodiments, as Figure 6 As shown, the first clock signal line PCK1, the third clock signal line PCK3, the fifth clock signal line ECK1 and the sixth clock signal line ECK2 are arranged between the first control unit 10 of the first type gate circuit 121 and the second output unit 40 of the first type gate circuit 121; the second clock signal line PCK2, the fourth clock signal line PCK4, the seventh clock signal line ECK3 and the eighth clock signal line ECK4 are arranged between the first control unit 10 of the second type gate circuit 122 and the second output unit 40 of the second type gate circuit 122.

[0100] Specifically, such as Figure 6 As shown, by arranging the first clock signal line PCK1, the third clock signal line PCK3, the fifth clock signal line ECK1 and the sixth clock signal line ECK2 between the first control unit 10 of the first type gate circuit 121 and the second output unit 40 of the first type gate circuit 121, the distance between the second output unit 40 of the first type gate circuit 121 and the second output unit 40 of the second type gate circuit 122 is small, and the distance between each signal line and the unit that needs to be electrically connected is small.

[0101] Specifically, such as Figure 6 As shown, by arranging the second clock signal line PCK2, the fourth clock signal line PCK4, the seventh clock signal line ECK3 and the eighth clock signal line ECK4 between the first control unit 10 of the second type gate circuit 122 and the second output unit 40 of the second type gate circuit 122, the distance between the second output unit 40 of the first type gate circuit 121 and the second output unit 40 of the second type gate circuit 122 is small, and the distance between each signal line and the unit that needs to be electrically connected is small.

[0102] In some embodiments, as Figure 6As shown, the orthographic projection of the first high-potential signal line PVGH1 overlaps with the orthographic projection of the second output unit 40 of the first type gate circuit 121, and the orthographic projection of the first start signal line STV1 overlaps with the orthographic projection of the second output unit 40 of the first type gate circuit 121.

[0103] In some embodiments, as Figure 6 As shown, the orthographic projection of the first high-potential signal line PVGH1 overlaps with the orthographic projection of the second output unit 40 of the second type gate circuit 122, and the orthographic projection of the second start signal line STV2 overlaps with the orthographic projection of the second output unit 40 of the second type gate circuit 122.

[0104] Specifically, such as Figure 6 As shown, by making the orthographic projection of a first high-potential signal line PVGH1 overlap with the orthographic projection of the second output unit 40 of the first type gate circuit 121, and the orthographic projection of the first start signal line STV1 overlap with the orthographic projection of the second output unit 40 of the first type gate circuit 121, the distance between the second output unit 40 of the first type gate circuit 121 and the second output unit 40 of the second type gate circuit 122 is small, and the distance between each signal line and the unit that needs to be electrically connected is small.

[0105] Specifically, such as Figure 6 As shown, by making the orthographic projection of a first high-potential signal line PVGH1 overlap with the orthographic projection of the second output unit 40 of the second type gate circuit 122, and the orthographic projection of the second start signal line STV2 overlap with the orthographic projection of the second output unit 40 of the second type gate circuit 122, the distance between the second output unit 40 of the first type gate circuit 121 and the second output unit 40 of the second type gate circuit 122 is small, and the distance between each signal line and the unit that needs to be electrically connected is small.

[0106] In some embodiments, as Figure 5 、 Figure 6 As shown, in the gate driving circuit 12 on at least one side of the pixel 13, the first output unit 30 of the first-type gate circuit 121 and the first output unit 30 of the second-type gate circuit 122 are symmetrically arranged about the symmetry axis in the first direction X. By symmetrically arranging the first output unit 30 of the first-type gate circuit 121 and the first output unit 30 of the second-type gate circuit 122 about the symmetry axis, the electrical properties of the first-type gate circuit are similar to or even identical to those of the second-type gate circuit. As a result, the difference between the signals output by the first-type gate circuit and the second-type gate circuit is small or even non-existent, thereby avoiding display abnormalities.

[0107] In some embodiments, as Figure 5 、 Figure 6 As shown, the display panel 1 also includes signal lines (for example, first frequency-dividing signal lines PLF), and the signal lines (for example, first frequency-dividing signal lines PLF) electrically connected to the first type of gate circuit 121 and the corresponding signal lines (for example, first frequency-dividing signal lines PLF) electrically connected to the second type of gate circuit 122 are symmetrically arranged about the symmetry axis; so that the spacing between each signal line and the corresponding transistor in the first type of gate circuit is close to or even equal to the spacing between each signal line and the corresponding transistor in the second type of gate circuit, and the electrical properties of the first type of gate circuit are close to or even the same as the electrical properties of the second type of gate circuit, then the difference between the signals output by the first type of gate circuit and the second type of gate circuit is small or even no difference, thereby avoiding display abnormalities.

[0108] Specifically, the corresponding signal lines electrically connected to the second type of gate circuit are explained as follows: for example, the first type of gate circuit 121 is electrically connected to the first control signal line Control1, and the second type of gate circuit 122 is electrically connected to the second control signal line Control2. The first control signal line Control1 and the second control signal line Control2 are both signal lines for input control signals. Therefore, the signal line corresponding to the first control signal line Control1 electrically connected to the first type of gate circuit 121 is the second control signal line Control2 electrically connected to the second type of gate circuit; similarly, the first clock signal line PCK1 corresponds to the second clock signal line PCK2, the third clock signal line PCK3 corresponds to the fourth clock signal line PCK4, the fifth clock signal line ECK1 corresponds to the seventh clock signal line ECK3, and the sixth clock signal line ECK2 corresponds to the eighth clock signal line ECK4.

[0109] At the same time, in order to illustrate the connection relationship between each transistor in the first type gate circuit 121 and the second type gate circuit 122 in the embodiment of the present application and the connection relationship between each transistor and the wiring, the embodiment of the present application provides Figure 4 For illustration purposes only.

[0110] like Figure 4As shown, the first type gate circuit 121 and the second type gate circuit 122 both include a first control unit 10, and the first control unit includes a first control transistor T13 and a second control transistor T12. In the first type gate circuit 121, the gate of the first control transistor T13 and the gate of the second control transistor T12 are connected to the first initial signal line STV1 or the internal node P(n-1) of the first type gate circuit 121 in the previous level gate drive circuit. In the second type gate circuit 122, the gate of the first control transistor T13 and the gate of the second control transistor T12 are connected to the second initial signal line STV2 or the internal node P(n-1) of the second type gate circuit 122 in the previous level gate drive circuit. The first electrode of the first control transistor T13 and the first electrode of the second control transistor T12 are electrically connected to the first node K, the second electrode of the first control transistor T13 is connected to the first low potential signal line PVGL, and the second electrode of the second control transistor T12 is connected to the first type high potential signal line PVGH.

[0111] Specifically, such as Figure 4 As shown, the first control unit 10 also includes a ninth control transistor T2, the gate of the ninth control transistor T2 is connected to the second-type clock signal line XCK, the first electrode of the ninth control transistor T2 is connected to the first node K, the second electrode of the ninth control transistor T2, the first electrode of the first control transistor T13 and the first electrode of the second control transistor T12 are connected to the second node O.

[0112] Specifically, such as Figure 4 As shown, the first type gate circuit 121 and the second type gate circuit 122 both include a second control unit 20, and the second control unit 20 includes a third control transistor T1 and a fourth control transistor T3, the gate of the third control transistor T1 and the gate of the fourth control transistor T3 are connected to the first node K, the first electrode of the third control transistor T1 and the first electrode of the fourth control transistor T3 are connected to the internal node P(n) of the first type gate circuit or the second type gate circuit of the gate drive circuit at this level, the second electrode of the third control transistor T1 is connected to the first low potential signal line PVGL, and the second electrode of the fourth control transistor T3 is connected to the first type high potential signal line PVGH.

[0113] Specifically, such as Figure 4As shown, the first type gate circuit 121 and the second type gate circuit 122 both include a first output unit 30, and the first output unit 30 includes a first output transistor T10 and a second output transistor T9. The gate of the first output transistor T10 is connected to the first node K, and the gate of the second output transistor T9 is electrically connected to the first node K. In the first type gate circuit 121, the first electrode of the first output transistor T10 and the first electrode of the second output transistor T9 are connected to the first signal output terminal Nout1(n) of the first type gate circuit 121. In the second type gate circuit 122, the first electrode of the first output transistor T10 and the first electrode of the second output transistor T9 are connected to the first signal output terminal Nout2(n) of the second type gate circuit 122. The second electrode of the first output transistor T10 is connected to the second type low potential signal line NVGL, and the second electrode of the second output transistor T9 is connected to the second type high potential signal line NVGH.

[0114] Specifically, such as Figure 4 As shown, both the first type gate circuit 121 and the second type gate circuit 122 include a second output unit 40, the second output unit 40 includes a third output transistor T6, a fourth output transistor T7 and a first capacitor C1, the gate of the third output transistor T6 is connected to the third node Q, the first electrode of the third output transistor T6 is connected to the first electrode of the fourth output transistor T7, in the first type gate circuit 121, the first electrode of the third output transistor T6 is connected to the second signal output terminal Pout1(n) of the first type gate circuit 121, and in the second type gate circuit 122, the first electrode of the third output transistor T6 is connected to the second signal output terminal Pout1(n+1) of the second type gate circuit 122. The second electrode of the third output transistor T6 is connected to the first-type clock signal line CK, the gate of the fourth output transistor T7 is connected to the internal node P(n) of the first-type gate circuit or the second-type gate circuit of the gate drive circuit at this level, the second electrode of the fourth output transistor T7 is connected to the first-type high-potential signal line PVGH, the first plate of the first capacitor C1 is connected to the gate of the third output transistor T6, in the first-type gate circuit 121, the second plate of the first capacitor C1 is connected to the second signal output end Pout1(n) of the first-type gate circuit 121, and in the second-type gate circuit 122, the second plate of the first capacitor C1 is connected to the second signal output end Pout1(n+1) of the second-type gate circuit 122.

[0115] Specifically, such as Figure 4As shown, the first type gate circuit 121 and the second type gate circuit 122 both include a frequency dividing unit 50, the frequency dividing unit 50 includes a first frequency dividing unit 501 and a second frequency dividing unit 502, the first frequency dividing unit includes a first frequency dividing transistor T16, a second frequency dividing transistor T11 and a second capacitor C2, the gate of the first frequency dividing transistor T16 is connected to the internal node P(n) of the first type gate circuit or the second type gate circuit of the gate driving circuit of this stage, the first electrode of the first frequency dividing transistor T16, the first plate of the second capacitor C2 and the gate of the second frequency dividing transistor T11 are connected, the second electrode of the first frequency dividing transistor T16 is connected to the second frequency dividing signal line NLF, and the first electrode of the second frequency dividing transistor T11 is connected to the second plate of the second capacitor C2. The fourth node W, the second electrode of the second frequency-dividing transistor T11 is connected to the first node K; the second frequency-dividing unit 502 includes a third frequency-dividing transistor T20, a fourth frequency-dividing transistor T19 and a third capacitor C3, the gate of the third frequency-dividing transistor T20 is connected to the internal node P(n) of the first type gate circuit or the second type gate circuit of the gate driving circuit of this level, the first electrode of the third frequency-dividing transistor T20, the first plate of the third capacitor C3 and the gate of the fourth frequency-dividing transistor T19 are connected, the second electrode of the third frequency-dividing transistor T20 is connected to the first frequency-dividing signal line PLF, the first electrode of the fourth frequency-dividing transistor T19 and the second plate of the third capacitor C3 are connected to the fifth node M, and the second electrode of the fourth frequency-dividing transistor T19 is connected to the first node K.

[0116] Specifically, such as Figure 4 As shown, the first type gate circuit 121 and the second type gate circuit 122 both include an output control unit 60, and the output control unit 60 includes a first switching transistor T4, a second switching transistor T5 and a third switching transistor T14, the gate of the first switching transistor T4 is connected to the second type clock signal line XCK, the first electrode of the first switching transistor T4 is connected to the first electrode of the second switching transistor T5, the second electrode of the first switching transistor T4 is connected to the first node K, the gate of the second switching transistor T5 and the gate of the third switching transistor T14 are connected to the first electrode of the third control transistor T1, the second electrode of the second switching transistor T5 is connected to the first type high potential signal line PVGH, the first electrode of the third switching transistor T14 is connected to the first node K, and the second electrode of the third switching transistor T14 is connected to the second type low potential signal line NVGL.

[0117] Specifically, such as Figure 4As shown, both the first type gate circuit 121 and the second type gate circuit 122 include a reset unit 70, and the reset unit 70 includes a reset transistor T15. In the first type gate circuit 121, the gate of the reset transistor T15 is connected to the first control signal line Control1. In the second type gate circuit 122, the gate of the reset transistor T15 is connected to the second control signal line Control2. The first electrode of the reset transistor T15 is connected to the first node K, and the second electrode of the reset transistor T15 is connected to the first type high potential signal line PVGH.

[0118] Specifically, such as Figure 4 As shown, the first type gate circuit 121 and the second type gate circuit 122 both include a third control unit 801, and the third control unit 801 includes a fifth control transistor T17 and a sixth control transistor T18, the gate of the fifth control transistor T17 is connected to the second type clock signal line XCK, the first electrode of the fifth control transistor T17 is connected to the first electrode of the sixth control transistor T18, the second electrode of the fifth control transistor T17 is electrically connected to the first node K, the gate of the sixth control transistor T18 is connected to the gate of the third switch transistor T14, and the second electrode of the sixth control transistor T18 is connected to the first type high potential signal line PVGH.

[0119] Specifically, such as Figure 4 As shown, both the first type gate circuit 121 and the second type gate circuit 122 include a fourth control unit 802, and the fourth control unit 802 includes a seventh control transistor T21 and an eighth control transistor T22, the gate of the seventh control transistor T21 is connected to the second type clock signal line XCK, the first electrode of the seventh control transistor T21 is connected to the first electrode of the eighth control transistor T22, the second electrode of the seventh control transistor T21 is electrically connected to the first node K, the gate of the eighth control transistor T22 is connected to the gate of the third switch transistor T14, and the second electrode of the eighth control transistor T22 is connected to the first type high potential signal line PVGH.

[0120] Specifically, such as Figure 4 As shown, both the first type gate circuit 121 and the second type gate circuit 122 include a switching unit 90, the switching unit 90 includes a fourth switching transistor T8, the gate of the fourth switching transistor T8 is connected to the switching signal line SC, the switching signal line SC is connected to the internal node P(n-2) of the upper two levels of the first type gate circuit 121 or the upper two levels of the second type gate circuit 122, the first electrode of the fourth switching transistor T8 is connected to the third node Q, and the second electrode of the fourth switching transistor T8 is connected to the fifth node M.

[0121] Specifically, the first control transistor T13 , the third control transistor T1 , the fifth control transistor T17 , the seventh control transistor T21 , the first switch transistor T4 , the third switch transistor T14 , and the first output transistor T10 may be oxide semiconductor transistors.

[0122] Specifically, the first control transistor T13 , the third control transistor T1 , the fifth control transistor T17 , the seventh control transistor T21 , the first switch transistor T4 , the third switch transistor T14 , and the first output transistor T10 may be N-type transistors.

[0123] Specifically, the second control transistor T12, the fourth control transistor T3, the sixth control transistor T18, the eighth control transistor T22, the ninth control transistor T2, the second switch transistor T5, the second output transistor T9, the third output transistor T6, the fourth output transistor T7, the first frequency-dividing transistor T16, the second frequency-dividing transistor T11, the third frequency-dividing transistor T20, the fourth frequency-dividing transistor T19, the reset transistor T15, and the fourth switch transistor T8 can be silicon semiconductor transistors.

[0124] Specifically, the second control transistor T12, the fourth control transistor T3, the sixth control transistor T18, the eighth control transistor T22, the ninth control transistor T2, the second switch transistor T5, the second output transistor T9, the third output transistor T6, the fourth output transistor T7, the first frequency-dividing transistor T16, the second frequency-dividing transistor T11, the third frequency-dividing transistor T20, the fourth frequency-dividing transistor T19, the reset transistor T15, and the fourth switch transistor T8 can be P-type transistors.

[0125] Specifically, the first control transistor T13, the third control transistor T1, the fifth control transistor T17, the seventh control transistor T21, the first switch transistor T4, the third switch transistor T14, and the first output transistor T10 are dual-gate transistors, but the embodiments of the present application are not limited thereto, and they can be single-gate transistors.

[0126] Specifically, the first electrode of the transistor in the above embodiment is a source electrode, and the second electrode is a drain electrode; or the first electrode of the transistor in the above embodiment is a drain electrode, and the second electrode is a source electrode.

[0127] Specifically, in order to illustrate the design of the first type gate circuit 121 and the second type gate circuit 122, it is provided Figure 5 and Figure 6 For the sake of explanation, Figure 6 The first type of gate circuit and the signal line connected thereto form Figure 7 , and based on Figure 7The design of the first type gate circuit 121 is described below. The design of the second type gate circuit 122 can refer to the description of the first type gate circuit 121 .

[0128] In some embodiments, as Figure 7 、 Figure 8 As shown, the active layer 205 includes an active pattern T2A of a ninth control transistor T2, an active pattern T3A of a fourth control transistor T3, an active pattern T5A of a second switching transistor T5, an active pattern T6A of a third output transistor T6, an active pattern T7A of a fourth output transistor T7, an active pattern T8A of a fourth switching transistor T8, an active pattern T9A of a second output transistor T9, an active pattern T11A of a second frequency-dividing transistor T11, an active pattern T12A of a second control transistor T12, an active pattern T15A of a reset transistor T15, an active pattern T16A of a first frequency-dividing transistor T16, an active pattern T18A of a sixth control transistor T18, an active pattern T19A of a fourth frequency-dividing transistor T19, an active pattern T20A of a third frequency-dividing transistor T20, and an active pattern T22A of an eighth control transistor T22.

[0129] In some embodiments, as Figure 7 、 Figure 9 As shown, the first gate layer 207 includes the gate T2G of the ninth control transistor T2, the gate T3G of the fourth control transistor T3, the gate T5G of the second switch transistor T5, the gate T6G of the third output transistor T6, the gate T7G of the fourth output transistor T7, the gate T8G of the fourth switch transistor T8, the gate T9G of the second output transistor T9, the gate T11G of the second frequency-dividing transistor T11, the gate T12G of the second control transistor T12, the gate T15G of the reset transistor T15, the gate T16G of the first frequency-dividing transistor T16, the gate T18G of the sixth control transistor T18, the gate T19G of the fourth frequency-dividing transistor T19, the gate T20G of the third frequency-dividing transistor T20, the gate T22G of the eighth control transistor T22, the first plate C1a of the first capacitor C1, the first plate C2a of the second capacitor C2, the first plate C3a of the third capacitor C3, the first gate connecting line G1L1, and the second gate connecting line G1L2.

[0130] Specifically, such as Figure 9 As shown, it can be seen that the lengths of the gate T2G of the ninth control transistor T2 in the first type gate circuit 121 in the two adjacent gate driving circuits are different. This is because the gate T2G of the ninth control transistor T2 in the first type gate circuit 121 in the two adjacent gate driving circuits are respectively connected to the fifth clock signal line ECK1 and the sixth clock signal line ECK2.

[0131] In some embodiments, as Figure 7 、 Figure 10 As shown, the second gate layer 209 includes a first gate T1Ga of the third control transistor T1, a first gate T4Ga of the first switching transistor T4, a first gate T10Ga of the first output transistor T10, a first gate T13Ga of the first control transistor T13, a first gate T4Ga of the third switching transistor T14, a first gate T17Ga of the fifth control transistor T17, a first gate T21Ga of the seventh control transistor T21, a second plate C1b of the first capacitor C1, a second plate C2b of the second capacitor C2, a second plate C3b of the third capacitor C3, a third gate transfer line Emout, a fourth gate transfer line P2out and a first signal output terminal Nout1(n) of the first type gate circuit 121.

[0132] In some embodiments, as Figure 7 、 Figure 11 As shown, the semiconductor layer 211 includes an active pattern T1A of the third control transistor T1, an active pattern T4A of the first switching transistor T4, an active pattern T10A of the first output transistor T10, an active pattern T13A of the first control transistor T13, an active pattern T14A of the third switching transistor T14, an active pattern T17A of the fifth control transistor T17, and an active pattern T21A of the seventh control transistor T21.

[0133] In some embodiments, as Figure 7 、 Figure 12 As shown, the third gate layer 213 includes the second gate T1Gb of the third control transistor T1, the second gate T4Gb of the first switch transistor T4, the second gate T10Gb of the first output transistor T10, the second gate T13Gb of the first control transistor T13, the second gate T14Gb of the third switch transistor T14, the second gate T17Gb of the fifth control transistor T17, the second gate T21Gb of the seventh control transistor T21, the internal node P(n) of the first type of gate circuit of the current stage gate drive circuit, the internal node P(n-2) of the first type of gate circuit of the upper two stages gate drive circuit, and the second signal output terminal Pout1(n) of the first type gate circuit 121.

[0134] In some embodiments, as Figure 7 、 Figure 13As shown, the first source-drain layer 215 includes a first electrode T2D and a second electrode T2S of the ninth control transistor T2, a first electrode T3D and a second electrode T3S of the fourth control transistor T3, a first electrode T5D and a second electrode T5S of the second switch transistor T5, a first electrode T6D and a second electrode T6S of the third output transistor T6, a first electrode T7D and a second electrode T7S of the fourth output transistor T7, a first electrode T8D and a second electrode T8S of the fourth switch transistor T8, a first electrode T9D and a second electrode T9S of the second output transistor T9, and a first electrode T9D and a second electrode T9S of the second output transistor T9. a first electrode T11D and a second electrode T11S of the frequency dividing transistor T11, a first electrode T12D and a second electrode T12S of the second control transistor T12, a first electrode T15D and a second electrode T15S of the reset transistor T15, a first electrode T16D and a second electrode T16S of the first frequency dividing transistor T16, a first electrode T18D and a second electrode T18S of the sixth control transistor T18, a first electrode T19D and a second electrode T19S of the fourth frequency dividing transistor T19, a first electrode T20D and a second electrode T20S of the third frequency dividing transistor T20, a first electrode T22D and a second electrode T22S of the eighth control transistor T22, a first electrode T1D and a second electrode T1S of the third control transistor T1, a first electrode T4D and a second electrode T4S of the first switch transistor T4, a first electrode T10D and a second electrode T10S of the first output transistor T10, a first electrode T13D and a second electrode T13S of the first control transistor T13, a first electrode T14D and a second electrode T14S of the third switch transistor T14, a first electrode T17D and a second electrode T17S of the fifth control transistor T17, and a first electrode T17D and a second electrode T17S of the seventh control transistor T17. The first electrode T21D and the second electrode T21S of the control transistor T21, the first part ECK1-1 of the fifth clock signal line ECK1, the first part ECK1-1 of the sixth clock signal line ECK2, the first part PCK1-1 of the first clock signal line PCK1, the first part PCK3-1 of the third clock signal line PCK3, the first source transfer line SL1, the second source transfer line SL2, the third source transfer line SL3, the fourth source transfer line SL4, the fifth source transfer line SL5, the sixth source transfer line SL6, the seventh source transfer line SL7, and the eighth source transfer line SL8.

[0135] In some embodiments, as Figure 7 、 Figure 14As shown, the second source and drain layer 217 includes a first part NVGH1-1 of the third high potential signal line NVGH1, a first part NVGH2-1 of the fourth high potential signal line NVGH2, a first part NVGL1-1 of the second low potential signal line NVGL2, a first part NVGL2-1 of the third low potential signal line NVGL1, a first high potential signal line PVGH1, a first control signal line Control1, a second high potential signal line PVGH2, a second frequency-dividing signal line NLF, a first low potential signal line PVGL, a first frequency-dividing signal line PLF, a second part ECK1-2 of the fifth clock signal line ECK1, a first part ECK1-2 of the sixth clock signal line ECK2, a second part PCK1-2 of the first clock signal line PCK1, a second part PCK3-2 of the third clock signal line PCK3, a first start signal line STV1, and a first part PVGH1-1 of another first high potential signal line PVGH1.

[0136] In some embodiments, as Figure 7 、 Figure 15 As shown, the third source and drain layer 219 includes the second part NVGH1-2 of the third high potential signal line NVGH1, the second part NVGH2-2 of the fourth high potential signal line NVGH2, the second part NVGL1-2 of the second low potential signal line NVGL1, the second part NVGL2-2 of the third low potential signal line NVGL2, the third part ECK1-3 of the fifth clock signal line ECK1, the third part ECK1-3 of the sixth clock signal line ECK2, the third part PCK1-3 of the first clock signal line PCK1, the third part PCK3-3 of the third clock signal line PCK3, and the second part PVGH1-2 of the first high potential signal line PVGH1.

[0137] Specifically, such as Figures 7 to 15 As shown, the second part NVGH1-2 of the third high potential signal line NVGH1, the second part NVGH2-2 of the fourth high potential signal line NVGH2, the second part NVGL1-2 of the second low potential signal line NVGL1, and the second part NVGL2-2 of the third low potential signal line NVGL2 are respectively connected to the first part NVGH1-1 of the third high potential signal line NVGH1, the first part NVGH2-1 of the fourth high potential signal line NVGH2, the first part NVGL1-1 of the second low potential signal line NVGL1, and the first part NVGL2-1 of the third low potential signal line NVGL2.

[0138] Specifically, such as Figures 7 to 15As shown, the third part ECK1-3 of the fifth clock signal line ECK1, the third part ECK1-3 of the sixth clock signal line ECK2, the third part PCK1-3 of the first clock signal line PCK1, and the third part PCK3-3 of the third clock signal line PCK3 are connected to the second part ECK1-2 of the fifth clock signal line ECK1, the first part ECK1-2 of the sixth clock signal line ECK2, the second part PCK1-2 of the first clock signal line PCK1, and the second part PCK3-2 of the third clock signal line PCK3, respectively. Then, the second part ECK1-2 of the fifth clock signal line ECK1, the first part ECK1-2 of the sixth clock signal line ECK2, the second part PCK1-2 of the first clock signal line PCK1, and the second part PCK3-2 of the third clock signal line PCK3 are respectively connected to the first part ECK1-1 of the fifth clock signal line ECK1, the first part ECK1-1 of the sixth clock signal line ECK2, the first part PCK1-1 of the first clock signal line PCK1, and the first part PCK3-1 of the third clock signal line PCK3.

[0139] Specifically, such as Figures 7 to 15 As shown, the second portion PVGH1 - 2 of the first high potential signal line PVGH1 is connected to the first portion PVGH1 - 1 of the first high potential signal line PVGH1 .

[0140] Specifically, such as Figures 7 to 15 As shown, the first source transfer line SL1 is connected to the gate T12G of the second control transistor T12 and the gate of the first control transistor T13; the second source transfer line SL2 is connected to the gate T15G of the reset transistor T15 and the first control signal line Control1; the third source transfer line SL3 is connected to two sections of the third gate transfer line Emout; the fourth source transfer line SL4 is connected to two sections of the fourth gate transfer line P2out; the fifth source transfer line SL5 is connected to the first signal output terminal Nout1(n) of the two sections of the first type gate circuit 121, the sixth transfer line SL6 is connected to the third gate transfer line Emout, the seventh transfer line SL7 is connected to the two sections of the fourth gate transfer line P2out, and the eighth source transfer line SL8 is connected to the gate of the third switching transistor T14 and the second type clock signal line.

[0141] Specifically, it can be understood that the gate drive circuit 12 also includes a gate circuit that outputs the signal of the light-emitting control line EM and the signal of the fourth scan line Pscan2, the third gate transfer line Emout is connected to the gate circuit that outputs the signal of the light-emitting control line EM and the light-emitting control line EM, and the fourth gate transfer line P2out is connected to the gate circuit that outputs the signal of the fourth scan line Pscan2 and the fourth scan line Pscan2.

[0142] Specifically, such as Figures 7 to 15As shown, it can be seen that in the first-class gate circuit 121 in the two adjacent gate drive circuits, the eighth source transfer line SL8 in one-class first gate circuit 121 is directly connected to the fifth clock signal line ECK1, and the eighth source transfer line SL8 in the other-class first gate circuit 121 is connected to the sixth clock signal line ECK2 through the second gate transfer line G1L2. This is because the gates of the third switching transistors T14 in the two adjacent first-class gate circuits 121 are respectively connected to the fifth clock signal line ECK1 and the sixth clock signal line ECK2.

[0143] Specifically, such as Figures 7 to 15 As shown, it can be seen that in the first-class gate circuits 121 in the two adjacent stages of the gate driving circuit, the second electrode T6S of the third output transistor T6 in one stage of the first-class gate circuit 121 is connected to the first clock signal line PCK1 through the first gate switching line G1L1, and the second electrode T6S of the third output transistor T6 in the other stage of the first-class gate circuit 121 is directly connected to the third clock signal line PCK3.

[0144] Specifically, for Figure 5 The designs of the first and second type gate circuits can refer to the above description; Figure 5 The first start signal line, the second start signal line and the third source and drain layer are omitted, but Figure 5 A first starting signal line, a second starting signal line and a third source-drain layer may also be provided, and may be designed with reference to the above embodiment.

[0145] At the same time, in order to illustrate the location of the vias passing through different film layers, Figures 16 to 19 .

[0146] like Figure 16 As shown, Figure 16 The arrangement position of the first via hole 311 is shown. The first via hole 311 refers to a via hole etched from the first source and drain electrode layer to the active layer, the first gate layer and the second gate layer.

[0147] like Figure 17 As shown, Figure 17 The second via hole 312 is shown. The second via hole 312 refers to a via hole etched from the first source and drain electrode layer to the semiconductor layer and the third gate layer.

[0148] like Figure 18 As shown, Figure 18 The configuration position of the third via hole 313 is shown. The third via hole 313 refers to a via hole etched from the second source and drain electrode layer to the first source and drain electrode layer, specifically, a via hole in the first planarization layer.

[0149] like Figure 19 As shown, Figure 19The fourth via hole 314 is shown as being located at a position where it is etched from the third source / drain electrode layer to the second source / drain electrode layer, specifically a via hole in the second planarization layer.

[0150] Further, in order to illustrate the relative position relationship of each film layer, a Figures 20 to 30 .

[0151] Specifically, such as Figure 20 As shown in FIG, the relative positions of the various structures when the active layer and the first gate layer are stacked can be seen. Figure 21 As shown in FIG, the relative positions of the various structures when the active layer, the first gate layer and the second gate layer are stacked can be seen. Figure 22 As shown in FIG, the relative positions of the active layer, the first gate layer, the second gate layer and the first via stack are shown. Figure 23 As shown in FIG, the relative positions of the active layer, the first gate layer, the second gate layer, the first via hole and the semiconductor layer are stacked. Figure 24 As shown in FIG, the relative positions of the various structures when the active layer, the first gate layer, the second gate layer, the first via hole, the semiconductor layer and the third gate layer are stacked can be seen. Figure 25 As shown in FIG, the relative positions of the various structures when the active layer, the first gate layer, the second gate layer, the first via, the semiconductor layer, the third gate layer and the second via are stacked can be seen. Figure 26 As shown in FIG, the relative positions of the various structures when the active layer, the first gate layer, the second gate layer, the first via hole, the semiconductor layer, the third gate layer, the second via hole and the first source and drain layer are stacked can be seen. Figure 27 As shown in FIG, the relative positions of the various structures when the active layer, the first gate layer, the second gate layer, the first via, the semiconductor layer, the third gate layer, the second via, the first source and drain layer, and the third via are stacked can be seen. Figure 28 As shown in FIG, the relative positions of the various structures when the active layer, the first gate layer, the second gate layer, the first via, the semiconductor layer, the third gate layer, the second via, the first source and drain layer, the third via, and the second source and drain layer are stacked can be seen. Figure 29 As shown in FIG, the relative positions of the various structures when the active layer, the first gate layer, the second gate layer, the first via, the semiconductor layer, the third gate layer, the second via, the first source-drain layer, the third via, the second source-drain layer and the fourth via are stacked can be seen. Figure 30 As shown, the relative positions of the various structures when the active layer, the first gate layer, the second gate layer, the first via, the semiconductor layer, the third gate layer, the second via, the first source-drain layer, the third via, the second source-drain layer, the fourth via and the third source-drain layer are stacked can be seen.

[0152] Specifically, in the embodiments of the present application, since some thin-film transistors adopt a dual-gate design, when the first gate and the second gate of the thin-film transistor are not clearly distinguished, the gate of the thin-film transistor refers to the two gates of the thin-film transistor. For example, in some embodiments of the embodiments of the present application, the gate of the first control transistor T13 includes a first gate T13Ga and a second gate T13Gb. When it is described that the gate of the first control transistor is connected to the gate of other transistors, it means that the first gate and the second gate of the first control transistor are both connected to the gate of the other transistors. Similarly, when other thin-film transistors also include dual gates, please refer to the above description and will not be repeated here.

[0153] Specifically, in the circuit diagrams of the embodiments of the present application, to illustrate the connection relationship between the transistors, each transistor has a gate, a first electrode, and a second electrode. However, in actual design, to reduce the space occupied by the transistors, the electrodes of some transistors may be formed using the same structure. It is understandable that this structure can be regarded as the electrodes of two transistors. Similarly, the structures of the electrodes of other transistors can be determined.

[0154] Specifically, the drawings in the embodiments of the present application show the design of the first type of gate circuit and the second type of gate circuit in the gate driving circuit on one side of the display panel, and specifically the design of the first type of gate circuit and the second type of gate circuit in the gate driving circuit on the left side of the display panel. It can be understood that when gate driving circuits are provided on both sides of the display panel, the gate driving circuit on the other side of the display panel can be symmetrical or identical to the design of the gate driving circuit on this side.

[0155] Specifically, the above embodiments respectively describe the display panel from the perspectives of each circuit, each film layer, each structure and their combination. It can be understood that when there is no conflict between the embodiments, the embodiments can be combined. For example, the material of the active layer 205 includes silicon semiconductor material, and the material of the semiconductor layer 211 includes oxide semiconductor.

[0156] At the same time, an embodiment of the present application provides a display device, which includes the display panel as described in any of the above embodiments.

[0157] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0158] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0159] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0160] The above are merely preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A display panel, characterized in that: include: A plurality of rows of pixels, each pixel comprising a light-emitting device and a pixel driving circuit, wherein the pixel driving circuit comprises a switching transistor, a compensation transistor, and a first initialization transistor; a multi-stage gate driving circuit, arranged on at least one side of the pixel along a first direction, each stage of the gate driving circuit comprising a first type of gate circuit and a second type of gate circuit arranged along the first direction, the first type of gate circuit and the second type of gate circuit each comprising a first output unit, a second output unit, a first signal output terminal, and a second signal output terminal, the first output unit being electrically connected to the first signal output terminal, the second output unit being electrically connected to the second signal output terminal, the first signal output terminal and the second signal output terminal of the first type of gate circuit at this stage being respectively connected to the gates of the compensation transistors of two adjacent stages and the gates of the switching transistors of the pixel driving circuit in this row, and the first signal output terminal and the second signal output terminal of the second type of gate circuit at this stage being respectively connected to the gates of the first initialization transistors of two adjacent stages and the gates of the switching transistors of the pixel driving circuit in the next row; In the gate driving circuit on at least one side of the pixel, in the first direction, the second output unit of the first type gate circuit and the second output unit of the second type gate circuit are located between the first output unit of the first type gate circuit and the first output unit of the second type gate circuit.

2. The display panel according to claim 1, wherein: In the gate driving circuit on at least one side of the pixel, in the first direction, the second output unit of the first-type gate circuit and the second output unit of the second-type gate circuit are symmetrically arranged about a symmetry axis.

3. The display panel according to claim 2, wherein: The first type gate circuit and the second type gate circuit both include a first control unit, a second control unit, a third control unit, a fourth control unit, an output control unit, a frequency dividing unit, a reset unit, and a switch unit that are electrically connected; The first control unit, second control unit, third control unit, fourth control unit, output control unit, frequency division unit, reset unit and switch unit in the first type of gate circuit are respectively symmetrically arranged with the first control unit, second control unit, third control unit, fourth control unit, output control unit, frequency division unit, reset unit and switch unit in the second type of gate circuit about the symmetry axis.

4. The display panel according to claim 3, wherein: In the gate driving circuit on at least one side of the pixel, in the first direction, the second output unit of the first type of gate circuit is adjacent to the second output unit of the second type of gate circuit, and no signal line is provided between the second output unit of the first type of gate circuit and the second output unit of the second type of gate circuit.

5. The display panel according to claim 4, wherein: The display panel further includes a plurality of first high-potential signal lines, a plurality of second high-potential signal lines, a plurality of third high-potential signal lines, a plurality of fourth high-potential signal lines, a plurality of first low-potential signal lines, a plurality of second low-potential signal lines, a plurality of third low-potential signal lines, a first control signal line, a second control signal line, a plurality of first frequency-divided signal lines, a plurality of second frequency-divided signal lines, a first start signal line, a second start signal line, a first type of clock signal line, and a second type of clock signal line, all electrically connected to the gate drive circuit; The first type of clock signal lines include a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line; the second type of clock signal lines include a fifth clock signal line, a sixth clock signal line, a seventh clock signal line, and an eighth clock signal line; the first clock signal line and the third clock signal line are electrically connected to two adjacent stages of the first type of gate circuits, respectively; the second clock signal line and the fourth clock signal line are electrically connected to two adjacent stages of the second type of gate circuits, respectively; the fifth clock signal line and the sixth clock signal line are electrically connected to two adjacent stages of the first type of gate circuits, respectively; and the seventh clock signal line and the eighth clock signal line are electrically connected to two adjacent stages of the second type of gate circuits, respectively; Wherein, within the arrangement area of the first type of gate circuit, in the first direction, the third high potential signal line, the fourth high potential signal line, the second low potential signal line, the third low potential signal line, the first high potential signal line, the first control signal line, the second high potential signal line, the second frequency-divided signal line, the first low potential signal line, the first frequency-divided signal line, the fifth clock signal line, the sixth clock signal line, the first clock signal line, the third clock signal line, the first start signal line and another first high potential signal line are arranged in sequence; In the setting area of the second type of gate circuit, in the opposite direction of the first direction, the third high potential signal line, the fourth high potential signal line, the second low potential signal line, the third low potential signal line, the first high potential signal line, the second control signal line, the second high potential signal line, the second frequency division signal line, the first low potential signal line, the first frequency division signal line, the seventh clock signal line, the eighth clock signal line, the second clock signal line and the fourth clock signal line, the second start signal line and another first high potential signal line are arranged in sequence.

6. The display panel according to claim 5, wherein: The first clock signal line, the third clock signal line, the fifth clock signal line and the sixth clock signal line are provided between the first control unit of the first type gate circuit and the second output unit of the first type gate circuit; The second clock signal line, the fourth clock signal line, the seventh clock signal line and the eighth clock signal line are provided between the first control unit of the second type gate circuit and the second output unit of the second type gate circuit.

7. The display panel according to claim 5, wherein: - an orthographic projection of the first high-potential signal line overlaps with an orthographic projection of the second output unit of the first type gate circuit, and an orthographic projection of the first start signal line overlaps with an orthographic projection of the second output unit of the first type gate circuit; The orthographic projection of the first high-potential signal line overlaps with the orthographic projection of the second output unit of the second-type gate circuit, and the orthographic projection of the second start signal line overlaps with the orthographic projection of the second output unit of the second-type gate circuit.

8. The display panel according to claim 3, wherein: The display panel further includes a first type of clock signal line and a second type of clock signal line, wherein the first type of clock signal line and the second type of clock signal line are electrically connected to the first type of gate circuit, and the first type of clock signal line and the second type of clock signal line are electrically connected to the second type of gate circuit; In the gate driving circuit of at least one side of the pixel, in the first direction, the first type of clock signal line and the second type of clock signal line are provided between the second output unit of the first type of gate circuit and the second output unit of the second type of gate circuit.

9. The display panel according to claim 2, wherein: In the gate driving circuit on at least one side of the pixel, in the first direction, the first output unit of the first type gate circuit and the first output unit of the second type gate circuit are symmetrically arranged about the symmetry axis.

10. The display panel according to claim 2, wherein: The display panel further includes signal lines, and the signal lines electrically connected to the first-type gate circuits and the corresponding signal lines electrically connected to the second-type gate circuits are symmetrically arranged about the symmetry axis.

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