Display panel and display device

Abstract

The invention relates to the technical field of display, and discloses a display panel and a display device.The display panel comprises a substrate and a driving layer located on one side of the substrate; the driving layer comprises a pixel circuit and a shift register, and the shift register comprises a plurality of cascaded shift register units; the shift register unit is located in a display area of the display panel; the display panel at least comprises a first area, a second area and a third area along the direction from one edge of the display panel to the other opposite edge, and the second area is located between the first area and the third area; the pixel circuit comprises a first pixel circuit and a second pixel circuit, the first pixel circuit is located in the first area, the shift register is located in the second area, and the second pixel circuit is located in the third area. The display device comprises the display panel. According to the invention, the circuit reliability and the display quality can be improved while frameless display is realized.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Light-emitting diode (LED) display technology is attracting significant attention as a next-generation display technology. Made of inorganic materials, LEDs offer excellent reliability, resulting in longer lifespans than liquid crystal displays (LCDs) or organic light-emitting diodes (OLEDs). Furthermore, LEDs offer fast lighting, high luminous efficiency, and strong impact resistance, enabling them to display high-brightness and stable images.

[0003] With the recent advancement of display technology, consumers have placed higher demands on display panels. High resolution, high refresh rate, and high screen-to-body ratio have become the mainstream development direction of display panels. However, the edge packaging of existing borderless display devices is prone to problems due to low packaging reliability, which affects the display quality of the entire device.

[0004] Therefore, how to achieve borderless display while improving display quality is a technical problem that needs to be solved urgently by those skilled in the art. Summary of the Invention

[0005] In order to solve the above technical problems, the present disclosure provides a display panel and a display device to solve the problem in the prior art that the display quality of borderless display devices cannot be effectively guaranteed and improved.

[0006] The present disclosure provides a display panel, comprising a substrate, a driving layer located on one side of the substrate;

[0007] The driving layer includes a pixel circuit and a shift register, and the shift register includes a plurality of cascaded shift register units; the shift register unit is located in the display area of the display panel;

[0008] Along a direction from one edge of the display panel to another edge opposite thereto, the display panel comprises at least a first area, a second area, and a third area, and the second area is located between the first area and the third area;

[0009] The pixel circuit includes a first pixel circuit and a second pixel circuit. The first pixel circuit is located in the first area, the shift register is located in the second area, and the second pixel circuit is located in the third area.

[0010] Based on the same inventive concept, the present disclosure also provides a display device, which includes the above-mentioned display panel.

[0011] The technical solution provided by the embodiments of the present disclosure has the following advantages over the prior art:

[0012] The shift register unit included in the shift register of the display panel provided by the present disclosure is located in the display area, which can avoid occupying too much space when the shift register is set in the border area of the display panel, which is beneficial to greatly reducing the border space of the display panel, achieving an ultra-narrow border or even a borderless display effect. The present disclosure sets a first pixel circuit in a first area of the display panel, a second pixel circuit in a third area, and a shift register in a second area between the first area and the third area. The shift register is away from the edge (cutting edge) of the display panel. There is at least a first area between the second area where the shift register is located and the edge of the display panel. The first pixel circuit is set in the first area. By further retracting the shift register into the second area further away from the edge of the display panel, even if the edge of the display panel causes packaging failure due to cutting or other reasons and water and oxygen intrusion, the circuit structure of the shift register located in the second area will not be damaged, thereby ensuring the driving performance of the shift register for the pixel circuits in the entire display panel, which is beneficial to ensuring the display quality of the display panel. Furthermore, the first pixel circuit is located in the first area. Even if the edge of the display panel experiences packaging failure due to cutting or other reasons, resulting in water and oxygen intrusion, the driving performance of a small number of first pixel circuits will only be affected at the smaller packaging failure site. This failure can be repaired appropriately later, without significantly impacting the display of the entire display panel. Therefore, the present disclosure arranges the first pixel circuit in the first area, the second pixel circuit in the third area, and the shift register in the second area between the first and third areas. This achieves a borderless display effect while ensuring the driving performance of the shift register in the second area, thereby improving the overall display quality of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0014] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0015] Figure 1 is a schematic diagram of a planar structure of a display panel provided by an embodiment of the present disclosure;

[0016] Figure 2 yes Figure 1 A schematic diagram of a cross-sectional structure along the A-A' direction;

[0017] Figure 3 yes Figure 1 A schematic diagram of a cross-sectional structure along the B-B' direction;

[0018] Figure 4 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present disclosure;

[0019] Figure 5 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present disclosure;

[0020] Figure 6 yes Figure 5 A schematic cross-sectional structure diagram of a local area of the first zone, the second zone and the first transition zone;

[0021] Figure 7 yes Figure 1 A schematic diagram of a local enlarged structure of the first zone in the middle;

[0022] Figure 8 yes Figure 1 A schematic diagram of a partially enlarged structure of the third zone in the middle;

[0023] Figure 9 yes Figure 1 Another schematic diagram of the partially enlarged structure of the first zone in the middle;

[0024] Figure 10 yes Figure 1 Another partial enlarged structural diagram of the middle third area;

[0025] Figure 11 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present disclosure;

[0026] Figure 12 yes Figure 11 A schematic diagram of the partially enlarged structure of the second area adjacent to the first area, and the second area adjacent to the third area;

[0027] Figure 13 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present disclosure;

[0028] Figure 14 yes Figure 13 A schematic diagram of the partially enlarged structure of the second area adjacent to the first area, and the second area adjacent to the third area;

[0029] Figure 15 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present disclosure;

[0030] Figure 16 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present disclosure;

[0031] Figure 17 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present disclosure;

[0032] Figure 18 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present disclosure;

[0033] Figure 19 yes Figure 18 A schematic diagram of a cross-sectional structure in the C-C' direction;

[0034] Figure 20 yes Figure 18 A schematic diagram of a cross-sectional structure in the D-D' direction;

[0035] Figure 21 yes Figure 18 Schematic diagram of another cross-sectional structure in the C-C' direction;

[0036] Figure 22 yes Figure 18 Another cross-sectional structure schematic diagram in the D-D' direction;

[0037] Figure 23 yes Figure 18 Schematic diagram of another cross-sectional structure in the C-C' direction;

[0038] Figure 24 yes Figure 18 Another cross-sectional structure schematic diagram in the D-D' direction;

[0039] Figure 25 yes Figure 18 Another cross-sectional structure schematic diagram in the D-D' direction;

[0040] Figure 26 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present disclosure;

[0041] Figure 27 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present disclosure;

[0042] Figure 28 yes Figure 27 A schematic diagram of a planar arrangement structure of a transmission area in a display panel;

[0043] Figure 29 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present disclosure;

[0044] Figure 30 yes Figure 29 A schematic diagram of a planar arrangement structure of a transmission area in a display panel;

[0045] Figure 31 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present disclosure;

[0046] Figure 32 yes Figure 31 A schematic diagram of a planar arrangement structure of a transmission area in a display panel;

[0047] Figure 33 Schematic diagram of a planar arrangement structure of a transmission area in a display panel provided by an embodiment of the present disclosure;

[0048] Figure 34 It is a schematic diagram of a planar structure of a display device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0049] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features therein can be combined with each other in the absence of conflict.

[0050] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0051] Please refer to Figure 1-Figure 3 , Figure 1 is a schematic diagram of a planar structure of a display panel provided by an embodiment of the present disclosure, Figure 2 yes Figure 1 A schematic diagram of a cross-sectional structure along the A-A' direction, Figure 3 yes Figure 1 A schematic cross-sectional structure diagram along the BB' direction (it can be understood that in order to clearly illustrate the structure of this embodiment, Figure 1 The display panel 000 provided in this embodiment includes a substrate 10 and a driving layer 20 located on one side of the substrate 10;

[0052] The driving layer 20 includes a pixel circuit 201 and a shift register 202. The shift register 202 includes a plurality of cascaded shift register units 2020. The shift register units 2020 are located in the display area of the display panel 000.

[0053] Along a direction X from one edge 000L1 of the display panel 000 to another edge 000L2 opposite thereto, the display panel 000 includes at least a first area J1, a second area J2, and a third area J3, wherein the second area J2 is located between the first area J1 and the third area J3;

[0054] The pixel circuit 201 includes a first pixel circuit 201A and a second pixel circuit 201B. The first pixel circuit 201A is located in the first area J1 , the shift register 202 is located in the second area J2 , and the second pixel circuit 201B is located in the third area J3 .

[0055] Specifically, the display panel 000 provided in this embodiment can be a micro light-emitting diode (micro LED) display panel or a sub-millimeter light-emitting diode (mini LED) display panel. The film structure of the display panel 000 includes a substrate 10. The substrate 10 can be used as a carrier substrate of the display panel 000 and is used to manufacture and set the remaining structures of the display panel 000 on the substrate 10. For example, in this embodiment, the substrate 10 is used to manufacture a driving layer 20 located on one side of the substrate 10 and various insulating layers and other film structures. The driving layer 20 of this embodiment is generally used to set a thin film transistor 20T that drives the light-emitting element and realizes the light-emitting element to emit light, a capacitor structure, and a signal line structure. For example, the driving layer 20 can be used to manufacture a pixel circuit 201 that drives the light-emitting element to emit light, as well as a shift register 202 that is electrically connected to the pixel circuit 201 and provides a driving signal to the pixel circuit 201. The shift register 202 of this embodiment may include a plurality of cascaded shift register units 2020 , which can provide driving signals (such as scanning driving signals and light-emitting control signals) to pixel circuits 201 in different rows.

[0056] It can be understood that the figure of this embodiment uses block diagrams to represent the pixel circuit 201 and the shift register unit 2020 included in the shift register 202, and the pixel circuit 201 and the shift register unit 2020 are distinguished by different filling patterns. The figure does not illustrate the specific circuit structure of the pixel circuit 201 and the specific circuit structure of the shift register unit 2020. During specific implementation, it can be understood based on the electrical connection structure of the pixel circuit 201 and the shift register 202 included in the display panel in the relevant technology. For example, the pixel circuit 201 may include multiple electrically connected thin film transistors and capacitors, and the shift register 202 may also include multiple electrically connected thin film transistors and capacitors, etc. This embodiment does not limit this.

[0057] Optional, such as Figure 2As shown, the display panel 000 of this embodiment may further include an electrode layer 30 and a plurality of light-emitting elements 40. The electrode layer 30 is located on the side of the driving layer 20 away from the substrate 10. The electrode layer 30 may include a plurality of electrode groups 301. The light-emitting element 40 is bound and bonded to the electrode group 301 of the electrode layer 30. The area where the light-emitting element 40 is located can be understood as the display area of the display panel 000, or as the light-emitting area. The source or drain of the thin film transistor 20T of the driving layer 20 can be electrically connected to the light-emitting element 40 through the electrode group 301 to achieve a driving light-emitting effect after the light-emitting element 40 is bonded to the electrode group 301. Further optionally, the driving layer 20 may further include a plurality of conductive signal lines (such as scan signal lines, data signal lines, power signal lines, etc.) to transmit the driving signal provided by the shift register 202 or the driving signal provided by the subsequently bound driver chip to each light-emitting element 40, thereby achieving a normal light-emitting display effect of the light-emitting element 40.

[0058] It can be understood that this embodiment is illustrated by taking the packaging form of the light-emitting element 40 as a horizontal light-emitting chip. At this time, the number of electrodes in each electrode group 301 set in the electrode layer 30 can be a pair, that is, an electrode group 301 can include two electrodes, and the two electrodes are respectively bound and bonded to the anode and cathode of the light-emitting element 40.

[0059] The driving layer 20 of this embodiment can be a combination of multiple conductive film layers and multiple inorganic layers, or a combination of multiple conductive film layers and multiple inorganic layers or organic layers. This embodiment does not limit this. During specific implementation, the film layer of the driving layer 20 can be set according to the actual design requirements of the panel. Figure 2 The driving layer 20 shown in the example may include a gate metal layer 20A where the gate of the thin film transistor 20T is located, a source and drain metal layer 20B where the source and drain of the thin film transistor 20T are located, a capacitor metal layer 20C where the capacitor plate is located, a semiconductor layer 20P where the active part of the thin film transistor 20T is located, and a first conductive layer 20D for making driving signal lines such as power signal lines, and other conductive film layers in the direction Z perpendicular to the plane where the substrate 10 is located. The first conductive layer 20D can be understood as a conductive film layer in the driving layer 20 that is closest to the electrode layer 30, and may also include inorganic layers or organic layers between adjacent conductive film layers. Optionally, the thin film transistor 20T provided in the driving layer 20 may be a dual-gate transistor, the top gate of which may be made of a gate metal layer 20A, and the bottom gate of which may be located on the side of the semiconductor layer 20P facing the substrate 10. At the same time, the metal layer where the bottom gate is located may be used as a light-shielding metal layer to shield the channel region of the thin film transistor 20T from light, thereby preventing light from shining on the channel region of the thin film transistor 20T to generate carriers and affect the performance of the thin film transistor 20T. Figure 2 This is only an example. In specific implementations, the film structure of the driving layer 20 includes but is not limited to this.

[0060] Optionally, in the film structure of the display panel 000 of this embodiment, the surface of the driving layer 20 away from the substrate 10 can be flattened by providing a flattening layer of organic material to ensure the flatness of the subsequently manufactured electrode layer 30, thereby facilitating the subsequent bonding of the light-emitting element to the electrode group 301 of the electrode layer 30. A protective layer of inorganic material can also be provided on the side of the electrode layer 30 away from the substrate 10 to protect the surface of the array substrate and isolate it from water and oxygen corrosion. The protective layer of inorganic material can have through holes to expose part of the electrode group 301, thereby facilitating the bonding of the exposed part of the electrode group 301 area to the light-emitting element. The electrode layer 30 in this embodiment can be made of a metal material or a transparent conductive material, which is not limited in this embodiment, and only requires that the electrode layer 30 has conductive properties.

[0061] In conventional display panels with borders, a shift register is typically positioned within the border area of the display panel. The shift register units of the shift register are electrically connected to the pixel circuits in the display area via scan signal lines. A single scan signal line typically provides a scan drive signal for a row of pixel circuits. Multiple cascaded shift register units drive multiple pixel circuit rows row by row, enabling the display of multiple pixel rows row by row. Specifically, conventional shift registers are typically positioned within the border area of the pixel circuits, near the edge of the display panel. This design requires a significant amount of space within the border area of the display panel to accommodate the shift register, hindering the realization of ultra-narrow borders or even borderless displays.

[0062] In this embodiment, the shift register 202 of the display panel 000 includes a shift register unit 2020 located in the display area, which can avoid occupying too much space when the shift register 202 is set in the border area of the display panel 000, and is beneficial to greatly reducing the border space of the display panel 000, thereby reducing the border to achieve an ultra-narrow border or even a borderless display effect.

[0063] In addition, during the production of display panels, multiple display panels of the required size are usually formed on a mother substrate, and then individual display panels are cut from the mother substrate to reduce production time and cost. Therefore, when producing the display panels, it is necessary to cut the completed large-sized mother substrate to form a single display panel of the required size. However, the packaging performance of the edge of the display panel is relatively weak after cutting, which can easily cause water and oxygen to invade the film structure of the display area of the display panel from the edge of the display panel, resulting in display failure and display abnormality. Especially for borderless display panels, although the shift register is placed on the lower side of the light-emitting element, the shift register is still relatively close to the edge of the display panel. Therefore, once the packaging fails at the edge of the display panel and water and oxygen invade, the circuit structure of the shift register near the edge of the display panel will be damaged, thereby affecting the shift register's driving performance of the pixel circuit in the entire display panel, and the overall display reliability of the display panel cannot be effectively guaranteed.

[0064] In order to solve the above problem, this embodiment sets a direction X along one edge 000L1 of the display panel 000 pointing to the other edge 000L2 opposite thereto. The display panel 000 includes at least a first area J1, a second area J2 and a third area J3. The second area J2 is located between the first area J1 and the third area J3. The first area J1 can be understood as the area closest to the edge of the display panel 000. Along the directions successively away from the edge of the display panel 000, the second area J2 and the third area J3 are respectively, that is, in the first area J1, the second area J2 and the third area J3, in the direction X from one edge 000L1 of the display panel 000 to the other edge 000L2 opposite thereto, the third area J3 is the area farthest from the edge of the display panel 000, the first area J1 is the area closest to the edge of the display panel 000, the edge of the first area J1 away from the third area J3 is the edge of the display panel 000, and the second area J2 is located between the first area J1 and the third area J3.

[0065] In the display panel 000 of this embodiment, the pixel circuit 201 provided in the driving layer 20 includes a first pixel circuit 201A and a second pixel circuit 201B. The first pixel circuit 201A is located in the first region J1, the shift register 202 is located in the second region J2, and the second pixel circuit 201B is located in the third region J3. It should be understood that in this embodiment, the pixel circuit in the first region J1 is named the first pixel circuit 201A, and the pixel circuit in the third region J3 is named the second pixel circuit 201B, merely to distinguish pixel circuits 201 in different regions. This does not mean that the first pixel circuit 201A and the second pixel circuit 201B have different structures. In a specific implementation, the electrical connection structure of the first pixel circuit 201A and the second pixel circuit 201B can be the same; they are only provided in different regions. In the direction X from one edge 000L1 of the display panel 000 to the opposite edge 000L2, the first pixel circuit 201A is closer to the edge of the display panel 000 than the second pixel circuit 201B.

[0066] It should be noted that, in this embodiment, one edge 000L1 of the display panel 000 is used as Figure 1 The left edge of the display panel 000 and the other edge 000L2 are Figure 1 Taking the right edge of the display panel 000 as an example, the direction X from one edge 000L1 of the display panel 000 to the other edge 000L2 opposite thereto is Figure 1 In the direction from the left side to the right side of the display panel 000, in a specific implementation, an edge 000L1 of the display panel 000 may also be Figure 1 The right edge of the display panel 000 and the other edge 000L2 are Figure 1 The left edge of the display panel 000 is shown in FIG. 1 , and the direction X from one edge 000L1 of the display panel 000 to the other edge 000L2 opposite thereto is Figure 1 The direction from the right to the left in the first zone J1 can be understood as Figure 1 The left edge area of the display panel 000, the first area J1 can also be understood as Figure 1 The right edge area of the display panel 000 is not limited in this embodiment.

[0067] It needs to be further explained that Figure 1 In the example, the display panel 000 includes a first area J1 and a second area J2, and the shift register 202 of the second area J2 drives the first pixel circuit 201A of the first area J1 and the second pixel circuit 201B of the third area J3. In the specific implementation, Figure 4 As shown, Figure 4is another schematic diagram of the planar structure of the display panel provided in the embodiment of the present disclosure (it can be understood that in order to clearly illustrate the structure of this embodiment, Figure 4 Transparency filling is performed), the display panel 000 may include two first areas J1 and two second areas J2, along a direction X from one edge of the display panel 000 to the other edge opposite thereto, namely, one first area J1, one second area J2, one third area J3, another second area J2, and another first area J1, thereby also achieving an effect that the shift register 202 of the second area J2 drives the first pixel circuit 201A of the first area J1 and the second pixel circuit 201B of the third area J3. During specific implementation, it can be set according to actual needs.

[0068] In this embodiment, the first pixel circuit 201A is located in the first area J1, the second pixel circuit 201B is located in the third area J3, and the shift register 202 is located in the second area J2 between the first area J1 and the third area J3. That is, although the shift register 202 is also arranged in the display area of the display panel 000, it can achieve a borderless display effect of the display panel 000, but the shift register 202 is far away from the edge (cutting edge) of the display panel 000. There is at least a first area J1 between the second area J2 where the shift register 202 is located and the edge of the display panel 000. The first pixel circuit 201A is arranged in the first area J1. By further retracting the shift register 202 into the second area J2, which is further away from the edge of the display panel 000, even if the packaging fails at the edge of the display panel due to cutting or other reasons, resulting in water and oxygen intrusion, the circuit structure of the shift register 202 located in the second area J2 will not be damaged. Therefore, the driving performance of the shift register 202 for the pixel circuits in the entire display panel can be guaranteed, which is conducive to ensuring the display quality of the display panel 000.

[0069] In this embodiment, the first pixel circuit 201A is disposed in the first region J1 of the display panel 000. Even if the edge of the display panel experiences packaging failure due to cutting or other reasons, resulting in water and oxygen intrusion, the driving performance of only a few first pixel circuits 201A at the smaller location will be affected. This failure can be repaired appropriately later, without significantly impacting the display of the entire display panel 000. Therefore, in this embodiment, the first pixel circuit 201A is disposed in the first region J1, the second pixel circuit 201B is disposed in the third region J3, and the shift register 202 is disposed in the second region J2 between the first region J1 and the third region J3. This achieves a borderless display effect while ensuring the driving performance of the shift register 202 in the second region J2, thereby improving the overall display quality of the display panel.

[0070] It should be noted that the figure of this embodiment only illustrates the structure of the display panel. In specific implementation, the structure of the display panel includes but is not limited to this, and may also include other structures that can realize the display function. For specific understanding, please refer to the structure of the mini LED or micro LED display panel in the relevant technology. This embodiment will not be described in detail here.

[0071] Optionally, in this embodiment, the shift register unit 2020 included in the shift register 202 is located in the display area of the display panel 000. Then, in the display area of the display panel 000, along the direction Z perpendicular to the plane where the substrate 10 is located, the shift register unit 2020 of the driving layer 20 may partially overlap with at least one electrode group 301 of the electrode layer 30; or along the direction Z perpendicular to the plane where the substrate 10 is located, the signal trace (such as a clock signal line, etc.) connected to the shift register unit 2020 of the driving layer 20 may partially overlap with at least one electrode group 301 of the electrode layer 30; or along the direction Z perpendicular to the plane where the substrate 10 is located, the driving layer 2 0, the signal lines (such as clock signal lines, etc.) connected to the shift register unit 2020, the shift register unit 2020 and the electrode group 301 of the electrode layer 30 do not overlap or overlap, or other settings can be used. During specific implementation, the setting can be selected according to actual needs, and it is only necessary to satisfy that the shift register unit 2020 is located in the display area of the display panel 000. The figures of this embodiment and subsequent embodiments only take the display area of the display panel 000, along the direction Z perpendicular to the plane of the substrate 10, the shift register unit 2020 of the driving layer 20 and at least one electrode group 301 of the electrode layer 30 partially overlap as an example for illustration.

[0072] In some optional embodiments, please refer to Figure 5 and Figure 6 , Figure 5 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present disclosure, Figure 6 yes Figure 5 A schematic cross-sectional structure diagram of a partial area of the first zone, the second zone and the first transition zone in FIG. 1 (It can be understood that in order to clearly illustrate the structure of this embodiment, Figure 5 Transparency filling is performed), in this embodiment, the display panel 000 further includes a first transition area JL1 and a second transition area JL2; the first transition area JL1 is located between the first area J1 and the second area J2, and the second transition area JL2 is located between the second area J2 and the third area J3;

[0073] The driving layer 20 of the first transition region JL1 is provided with a first connecting driving line LX1, and the shift register 202 is electrically connected to the first pixel circuit 201A via the first connecting driving line LX1;

[0074] The driving layer 20 of the second transition region JL2 is provided with a second connecting driving line LX2 , and the shift register 202 is electrically connected to the second pixel circuit 201B via the second connecting driving line LX2 .

[0075] This embodiment explains that in the display panel 000, a direction X along one edge 000L1 of the display panel 000 pointing to another edge 000L2 opposite thereto may also include a first transition region JL1 and a second transition region JL2, wherein the first transition region JL1 is located between the first region J1 and the second region J2, and the second transition region JL2 is located between the second region J2 and the third region J3. When the driving layer 20 of the second area J2 is set with the circuit structure of the shift register 202, the second area J2 where the shift register 202 is located is still normally equipped with the light-emitting element 40 bonded to the electrode group 301, and the shift register 202 of the second area J2 needs to provide a driving signal to the first pixel circuit 201A of the first area J1, and also needs to provide a driving signal to the second pixel circuit 201B of the third area J3, so that the first pixel circuit 201A of the first area J1 and the second pixel circuit 201B of the third area J3 can both be driven normally by the shift register 202 of the second area J2. Therefore, the output ends of each shift register unit 2020 of the shift register 202 of the second area J2 need to lead out signal lines to the first pixel circuit 201A of the first area J1 and the second pixel circuit 201B of the third area J3 respectively. And because the second area J2 is still equipped with a light-emitting element 40, but the second area J2 does not have a pixel circuit 201, the space for arranging the pixel circuit in the driving layer 20 below the light-emitting element 40 of the second area J2 is used to set up the shift register 202. Therefore, the electrode group 301 bonded to the light-emitting element 40 of the second area J2 needs to lead out wires to the pixel circuits in other areas to achieve the driving and luminous effect of the pixel circuits in other areas on the light-emitting element 40 in the second area J2. Therefore, the second area J2 needs to lead out a large number of signal lines (for the signal output of the shift register 202 of the second area J2, and for introducing the driving signal of the pixel circuit for the light-emitting element 40 in the second area J2).In this embodiment, a direction X is set along one edge 000L1 of the display panel 000 pointing to another edge 000L2 opposite thereto. The display panel 000 further includes a first transition region JL1 located between the first region J1 and the second region J2, and a second transition region JL2 located between the second region J2 and the third region J3. The driving layer 20 of the first transition region JL1 is used to set a first connecting driving trace LX1. Optionally, the first connecting driving trace LX1 can be located in at least one conductive film layer of the driving layer 20, or the first connecting driving trace LX1 can also be located in multiple conductive film layers of the driving layer 20. It is only necessary that the driving layer 20 of the first transition region JL1 has sufficient space to arrange the first connecting driving trace LX1. , the shift register 202 of the second area J2 and the first pixel circuit 201A of the first area J1 are electrically connected through the first connecting driving trace LX1; similarly, the driving layer 20 of the second transition area JL2 is used to set the second connecting driving trace LX2. Optionally, the second connecting driving trace LX2 can be located in at least one conductive film layer of the driving layer 20, or the second connecting driving trace LX2 can also be located in multiple conductive film layers of the driving layer 20. It is only necessary to meet the requirement that the driving layer 20 of the second transition area JL2 has sufficient space for arranging the second connecting driving trace LX2, and the shift register 202 of the second area J2 and the second pixel circuit 201B of the third area J3 are electrically connected through the second connecting driving trace LX2.

[0076] Optionally, since the second region J2 is still provided with the light emitting element 40, but the second region J2 is not provided with the pixel circuit 201, the space for providing the pixel circuit in the driving layer 20 below the light emitting element 40 of the second region J2 is used to provide the shift register 202. Figure 6 As shown, the electrode group 301 bonded to the light-emitting element 40 in the second region J2 can also lead an anode connection line LY to the first pixel circuit 201 in the first region J1, thereby enabling the first pixel circuit 201 in the first region J1 to drive the light-emitting element 40 in the second region J2 to emit light. The anode connection line LY can be disposed in the electrode layer 30 of the first transition region JL1. That is, in addition to the electrode group 301, the electrode layer 30 can also be provided with an anode connection line LY to electrically connect the first pixel circuit 201 in the first region J1 to the light-emitting element 40 in the second region J2, ensuring that the light-emitting element 40 in the second region J2 is driven to emit light by the first pixel circuit 201A. Alternatively, when there is insufficient space in the electrode layer 30, the anode connection line LY can be disposed in the surplus driving layer 20 in the first transition region JL1. This embodiment does not limit the film layer for disposing the anode connection line LY. During implementation, the design can be based on the actual film layer space of the display panel.

[0077] It can be understood that when the direction X along one edge 000L1 of the display panel 000 points to the other edge 000L2 opposite thereto, the display panel 000 also includes a first transition region JL1 located between the first area J1 and the second area J2, and also includes a second transition region JL2 located between the second area J2 and the third area J3. The first transition region JL1 and the second transition region JL2 are still provided with light-emitting elements 40. Therefore, the light-emitting elements 40 in the first transition region JL1 and the second transition region JL2 can be driven by the first pixel circuit 201A of the first area J1, or the light-emitting elements 40 in the first transition region JL1 and the second transition region JL2 can also be driven by the second pixel circuit 201B of the third area J3. For example, cross-area connecting wires are set in the driving layer 20 to realize electrical connection between pixel circuits and light-emitting elements in different areas (not shown in the figure). This embodiment will not be elaborated on.

[0078] It can be understood that in some other optional embodiments, the first transition zone JL1 and the second transition zone JL2 may also be provided with some pixel circuits for driving the light-emitting elements 40 in their own areas, that is, the light-emitting elements 40 included in the first transition zone JL1 and the second transition zone JL2 can be driven to emit light by pixel circuits set in other areas, or can be driven to emit light by also setting pixel circuits in the first transition zone JL1 and the second transition zone JL2. This embodiment does not limit this. During specific implementation, it can be reasonably arranged according to the actual space of the panel film layer.

[0079] In some optional embodiments, please refer to Figures 1-6 、 Figure 7 and Figure 8 , Figure 7 yes Figure 1 A schematic diagram of a local enlarged structure of the first zone in the figure. Figure 8 yes Figure 1 A partially enlarged structural diagram of the third area in FIG. 1 (It can be understood that in order to clearly illustrate the structure of this embodiment, Figure 7 and Figure 8 Transparency is filled). In this embodiment, in the first area J1, along a first direction X, three adjacent first pixel circuits 201A form a first pixel circuit group 201AZ, and the first pixel circuit group 201AZ drives three adjacent electrode groups 301. The first direction X is the direction from the first area J1 to the second area J2. The first direction X can also be understood as the direction X from one edge 000L1 of the display panel 000 to the other opposite edge 000L2 (all numbers are marked with X in this embodiment and subsequent embodiments).

[0080] In the third region J3 , along the first direction X, three adjacent second pixel circuits 201B form a second pixel circuit group 201BZ, and the second pixel circuit group 201B drives three adjacent electrode groups 301 ;

[0081] Along the first direction X, a maximum width W1 of the first pixel circuit group 201AZ is smaller than a maximum width W2 of the second pixel circuit group 201BZ.

[0082] This embodiment explains that the shift register 202 is set in the driving layer 20 of the second area J2 of the display panel 000. The second area J2 where the shift register 202 is located is still normally provided with an electrode group 301 for bonding the light-emitting element 40, but the second area J2 is not provided with a pixel circuit 201. The space originally used for arranging the pixel circuit in the driving layer 20 below the light-emitting element 40 in the second area J2 is used to set the shift register 202. Therefore, the electrode group 301 bonded to the light-emitting element 40 in the second area J2 needs to lead out wires to the pixel circuits in other areas to achieve the light-emitting effect of the pixel circuits in other areas driving the light-emitting element 40 in the second area J2. In this embodiment, the second region J2 is still configured as normal with an electrode group 301 for bonding the light-emitting element 40, just like other regions. The electrode group 301 in the second region J2 is driven by the first pixel circuit 201A in the first region J1. That is, each electrode group 301 in the first region J1 and the second region J2 is electrically connected and driven by the first pixel circuit 201A provided in the first region J1, and each electrode group 301 in the third region J3 is electrically connected and driven by the second pixel circuit 201B included in the third region J3 itself. Optionally, one electrode group 301 in the third region J3 can be bonded to one light-emitting element 40, and one electrode group 301 can be electrically connected and driven by one second pixel circuit 201B.

[0083] Because the first pixel circuits 201A provided in the driving layer 20 of the first region J1 need to be electrically connected to the electrode group 301 that drives the first region J1 itself, and also need to be electrically connected to the electrode group 301 of the second region J2, this embodiment compresses the spacing between the first pixel circuits 201A in the first region J1. Specifically, in the first region J1, along the first direction X, three adjacent first pixel circuits 201A form a first pixel circuit group 201AZ, which drives three adjacent electrode groups 301. In the third region J3, along the first direction X, three adjacent second pixel circuits 201B form a second pixel circuit group 201BZ, which drives three adjacent electrode groups 301. Optionally, the three electrode groups 301 driven by the first pixel circuit group 201AZ are electrically connected to three light-emitting elements 40 of different colors, and the three electrode groups 301 driven by the second pixel circuit group 201BZ are electrically connected to three light-emitting elements 40 of different colors. The three adjacent electrode groups 301 driven by the first pixel circuit group 201AZ can be used to bind and bond the three light-emitting elements 40 of different colors, that is, the three light-emitting elements 40 driven by the first pixel circuit group 201AZ can be understood as a pixel unit including three primary colors RGB light-emitting elements, and the three adjacent electrode groups 301 driven by the second pixel circuit group 201BZ can be used to bind and bond the three light-emitting elements 40 of different colors, that is, the three light-emitting elements 40 driven by the second pixel circuit group 201BZ can be understood as a pixel unit including three primary colors RGB light-emitting elements.

[0084] In this embodiment, along the first direction X, the maximum width W1 of the first pixel circuit group 201AZ is smaller than the maximum width W2 of the second pixel circuit group 201BZ. By compressing the distance between two adjacent first pixel circuits 201A in the first area J1 in the first direction X, that is, along the first direction X, the distance between the two adjacent first pixel circuits 201A is D11, and the distance between the two adjacent second pixel circuits 201B is D22; wherein D11<D22, the two adjacent first pixel circuits 201A in a first pixel circuit group 201AZ in the first area J1 in the first direction The maximum spacing D11 on X is smaller than the maximum spacing D22 in the first direction X between two adjacent second pixel circuits 201B in a second pixel circuit group 201BZ in the third area J3, so that the layout density of the multiple first pixel circuits 201A in the first area J1 is greater than the layout density of the multiple second pixel circuits 201B in the third area J3. More first pixel circuits 201A can be set in the first area J1 to drive the light-emitting element 40 of the first area J1 and the light-emitting element 40 of the second area J2 where the shift register 202 is located, thereby ensuring the borderless display effect of the display panel 000.

[0085] It can be understood that the pixel circuit 201 is represented by a block diagram in the figure of this embodiment. In a specific implementation, the pixel circuit 201 is an electrically connected structure including multiple thin-film transistors and capacitors. Therefore, the outer edge of the orthographic projection of the pixel circuit 201 on the plane where the substrate 10 is located will not be a regular shape. Therefore, in this embodiment, along the first direction X, the maximum width W1 of the first pixel circuit group 201AZ can be understood as the width between the two outermost edges of the first pixel circuit group 201AZ in the orthographic projection graphic of the substrate 10 in the first direction X, and the maximum width W2 of the second pixel circuit group 201BZ can be understood as the width between the two outermost edges of the second pixel circuit group 201BZ in the orthographic projection graphic of the substrate 10 in the first direction X. Optionally, along the first direction X, the maximum width dimension of the first pixel circuit group 201AZ can be 118um, and the maximum width dimension of the second pixel circuit group 201BZ can be 250.13um, so that by compressing the distance between two adjacent first pixel circuits 201A in the first area J1 in the first direction X, the maximum width W1 of the first pixel circuit group 201AZ in the first direction X is smaller, so as to achieve the purpose of setting more first pixel circuits 201A in the first area J1.

[0086] In some optional embodiments, please refer to Figures 1-6 、 Figure 9 and Figure 10 , Figure 9 yes Figure 1 Another partial enlarged structural diagram of the first zone in the middle, Figure 10 yes Figure 1 Another partially enlarged structural diagram of the third area in FIG. 1 (It can be understood that in order to clearly illustrate the structure of this embodiment, Figure 9 and Figure 10 Transparency is filled). In this embodiment, in the first area J1, along the first direction X, three adjacent first pixel circuits 201A form a first pixel circuit group 201AZ, and the first pixel circuit group 201AZ drives three adjacent electrode groups 301. The first direction X is the direction from the first area J1 to the second area J2. The first direction X can also be understood as the direction X from one edge 000L1 of the display panel 000 to the other opposite edge 000L2.

[0087] In the third region J3 , along the first direction X, three adjacent second pixel circuits 201B form a second pixel circuit group 201BZ, and the second pixel circuit group 201B drives three adjacent electrode groups 301 ;

[0088] The layout density of the first pixel circuit group 201AZ in the first area J1 is greater than the layout density of the second pixel circuit group 201BZ in the third area J3;

[0089] Along the first direction X, the distance between two adjacent first pixel circuit groups 201AZ is D1, and the distance between two adjacent second pixel circuit groups 201BZ is D2; wherein D1<D2.

[0090] This embodiment explains that the shift register 202 is set in the driving layer 20 of the second area J2 of the display panel 000. The second area J2 where the shift register 202 is located is still normally provided with an electrode group 301 for bonding the light-emitting element 40, but the second area J2 is not provided with a pixel circuit 201. The space originally used for arranging the pixel circuit in the driving layer 20 below the light-emitting element 40 in the second area J2 is used to set the shift register 202. Therefore, the electrode group 301 bonded to the light-emitting element 40 in the second area J2 needs to lead out wires to the pixel circuits in other areas to achieve the light-emitting effect of the pixel circuits in other areas driving the light-emitting element 40 in the second area J2. In this embodiment, the second region J2 is still configured as normal with an electrode group 301 for bonding the light-emitting element 40, just like other regions. The electrode group 301 in the second region J2 is driven by the first pixel circuit 201A in the first region J1. That is, each electrode group 301 in the first region J1 and the second region J2 is electrically connected and driven by the first pixel circuit 201A provided in the first region J1, and each electrode group 301 in the third region J3 is electrically connected and driven by the second pixel circuit 201B included in the third region J3 itself. Optionally, one electrode group 301 in the third region J3 can be bonded to one light-emitting element 40, and one electrode group 301 can be electrically connected and driven by one second pixel circuit 201B.

[0091] Since the first pixel circuit 201A provided in the driving layer 20 of the first region J1 needs to be electrically connected to the electrode group 301 that drives the first region J1 itself, and also needs to be electrically connected to the electrode group 301 of the second region J2, this embodiment therefore compresses the distance between two adjacent first pixel circuit groups 201AZ in the first region J1. Specifically, in the first region J1, along the first direction X, three adjacent first pixel circuits 201A form a first pixel circuit group 201AZ, which drives three adjacent electrode groups 301. In the third region J3, along the first direction X, three adjacent second pixel circuits 201B form a second pixel circuit group 201BZ, which drives three adjacent electrode groups 301. The three electrode groups 301 driven by the first pixel circuit group 201AZ are electrically connected to three light-emitting elements 40 of different colors, and the three electrode groups 301 driven by the second pixel circuit group 201BZ are electrically connected to three light-emitting elements 40 of different colors. The three adjacent electrode groups 301 driven by the first pixel circuit group 201AZ can be used to bind and bond the light-emitting elements 40 of three different colors, that is, the three light-emitting elements 40 driven by the first pixel circuit group 201AZ can be understood as a pixel unit including three primary colors RGB light-emitting elements, and the three adjacent electrode groups 301 driven by the second pixel circuit group 201BZ can be used to bind and bond the light-emitting elements 40 of three different colors, that is, the three light-emitting elements 40 driven by the second pixel circuit group 201BZ can be understood as a pixel unit including three primary colors RGB light-emitting elements.

[0092] In this embodiment, the spacing D1 between two adjacent first pixel circuit groups 201AZ is set to be smaller than the spacing D2 between two adjacent second pixel circuit groups 201BZ. By compressing the spacing D1 between two adjacent first pixel circuit groups 201AZ in the first area J1 in the first direction X, the layout density of the multiple first pixel circuit groups 201AZ in the first area J1 is made greater than the layout density of the multiple second pixel circuit groups 201BZ in the third area J3. More first pixel circuit groups 201AZ can be set in the first area J1 to drive the light-emitting elements 40 of the first area J1 and the light-emitting elements 40 of the second area J2 where the shift register 202 is located, thereby ensuring the borderless display effect of the display panel 000.

[0093] Optional, such as Figures 1-6 、 Figure 7-10 As shown, along the second direction Y, the maximum height of the first pixel circuit group 201AZ is H1, and the maximum height of the second pixel circuit group 201BZ is H2; wherein, H1=H2, and in a direction parallel to the plane where the substrate 10 is located, the second direction Y intersects with the first direction XA. It can be understood that, in this embodiment, the first direction X and the second direction Y are perpendicular to each other in a direction parallel to the plane where the substrate 10 is located.

[0094] This embodiment explains that the arrangement density of the first pixel circuit group 201AZ in the first area J1 and the second pixel circuit group 201BZ in the third area J3 is different. The arrangement density can be changed by changing the width of the first pixel circuit group 201AZ and the width of the second pixel circuit group 201BZ in the first direction X, or by changing the spacing between two adjacent first pixel circuit groups 201AZ and the spacing between two adjacent second pixel circuit groups 201BZ in the first direction X, or by changing the spacing between two adjacent first pixel circuits 201A and the spacing between two adjacent second pixel circuit groups 201B in the first direction X. However, the first pixel circuit group 201AZ in the second direction X is different from the first pixel circuit group 201AZ in the second direction X. The maximum height H1 in the direction Y needs to be kept consistent with the maximum height H2 of the second pixel circuit group 201BZ in the second direction Y as much as possible, so as to ensure that the pixel circuits 201 in the first area J1 and the third area J3 can have sufficient space to arrange the transistors, capacitors and other structures they include, and avoid the compression of the spacing between the first pixel circuit 201A or the first pixel circuit group 201AZ in the first area J1, which affects the driving performance of the first pixel circuit 201A for the light-emitting element 40 and the driving performance of the second pixel circuit 201B for the light-emitting element 40. This can improve the overall light uniformity of the display panel 000 and ensure the display quality.

[0095] Optional, please continue to combine reference Figure 7-10 In this embodiment, the shape of the orthographic projection of the first pixel circuit 201A on the substrate 10 is consistent with the shape of the orthographic projection of the second pixel circuit 201B on the substrate 10 .

[0096] This embodiment explains that the pixel circuit 201 is represented by a block diagram in the figure. However, in actual implementation, since the pixel circuit 201 includes an electrical connection structure of multiple thin film transistors and capacitors, the outer edge of the orthographic projection of the pixel circuit 201 on the plane where the substrate 10 is located will not be a regular shape. However, regardless of whether the orthographic projection shape of the pixel circuit 201 on the plane where the substrate 10 is located is a regular or irregular shape, the shape of the orthographic projection of the first pixel circuit 201A on the substrate 10 and the shape of the orthographic projection of the second pixel circuit 201B on the substrate 10 need to be set to be as consistent as possible. That is, the wiring layout, placement of thin-film transistors and capacitors of the first pixel circuit 201A in the first area J1 and the wiring layout, placement of thin-film transistors and capacitors of the second pixel circuit 201B in the third area J3 must be the same or as similar as possible, so as to ensure that the resistance and parasitic capacitance of each node in the pixel circuit 201 of the first area J1 and the third area J3 are the same. Therefore, when displaying, it can be ensured that the display uniformity of the first area J1 and the third area J3 will not be different due to the difference in resistance and parasitic capacitance, which is conducive to improving display uniformity and enhancing display effect.

[0097] In some optional embodiments, please refer to Figure 11 and Figure 12 , Figure 11 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present disclosure, Figure 12 yes Figure 11 A partial enlarged structural diagram of the second area adjacent to the first area and the second area adjacent to the third area (it can be understood that in order to clearly illustrate the structure of this embodiment, Figure 11 and Figure 12 Transparency filling is performed), in this embodiment, the multiple shift registers 202 include a first shift register 202A and a second shift register 202B, the first shift register 202A includes a plurality of cascaded first shift register units 202A0, and the second shift register 202B includes a plurality of cascaded second shift register units 202B0;

[0098] The first shift register unit 202A0 includes two light emitting control signal output terminals EM OUT , two luminous control signal output terminals EM OUT are electrically connected to the first pixel circuit 201A of the first region J1 and the second pixel circuit 201B of the third region J3 respectively;

[0099] The second shift register unit 202B0 includes two scan control signal output terminals SCAN OUT , two scan control signal output terminals SCAN OUT The first pixel circuit 201A in the first region J1 and the second pixel circuit 201B in the third region J3 are electrically connected respectively.

[0100] This embodiment explains that the display panel 000 sets the shift register 202 in the second area J2, that is, when it is further away from the edge of the display panel 000, multiple shift registers 202 include a first shift register 202A and a second shift register 202B, the first shift register 202A includes a plurality of cascaded first shift register units 202A0, and the second shift register 202B includes a plurality of cascaded second shift register units 202B0. The first shift register 202A can be used to provide a light-emitting control signal for each pixel circuit in the display panel 000. The first shift register 202A includes a plurality of cascaded first shift register units 202A0. The first shift register unit 202A0 can be used to provide a light-emitting control signal for the pixel circuit 201 of at least one pixel circuit row, such as the light-emitting control signal required by the gate of the light-emitting control transistor included in the pixel circuit 201. The light-emitting control signal can be used to control the conduction and cutoff of the light-emitting control transistor in the pixel circuit 201. The second shift register 202B can be used to provide a scan control signal for each pixel circuit in the display panel 000. The second shift register 202B includes multiple cascaded second shift register units 202B0. The second shift register unit 202B0 can be used to provide a scan control signal for the pixel circuit 201 of at least one pixel circuit row, such as the scan control signal required for the gate of other transistors included in the pixel circuit 201 except the light-emitting control transistor. The conduction and cutoff of other transistors in the pixel circuit 201 except the light-emitting control transistor can be controlled by the scan control signal.

[0101] Each first shift register unit 202A0 of this embodiment includes two light emitting control signal output terminals EM OUT , two luminous control signal output terminals EM OUT The first pixel circuit 201A of the first area J1 and the second pixel circuit 201B of the third area J3 are electrically connected to each other. Figure 11 and Figure 12 As shown, the two light emitting control signal output terminals EM of the first shift register unit 202A0 are OUT In the example, a light control signal output terminal EM OUT The leftward pulling line is electrically connected to the first pixel circuit 201A of the first region J1, such as the gate of the light emitting control transistor included in the first pixel circuit 201A of the first region J1, and another light emitting control signal output terminal EM OUT The wire is pulled to the right and electrically connected to the second pixel circuit 201B of the third area J3, such as electrically connected to the gate of the light-emitting control transistor included in the second pixel circuit 201B of the third area J3, so that the first shift register 202A of the second area J2 provides a light-emitting control signal to the pixel circuits 201 of the first area J1 and the third area J3 on both sides thereof, thereby realizing a light-emitting control driving effect for all pixel circuits 201 in the display panel 000.

[0102] Each second shift register unit 202B0 includes two scan control signal output terminals SCAN OUT , two scan control signal output terminals SCAN OUT The first pixel circuit 201A of the first area J1 and the second pixel circuit 201B of the third area J3 are electrically connected to each other. Figure 11 and Figure 12 As shown, the two scan control signal output terminals SCAN of the second shift register unit 202B0 OUT In the example, a scan control signal output terminal SCAN OUT The leftward pull line is electrically connected to the first pixel circuit 201A of the first area J1, such as being electrically connected to the gate of any transistor other than the light emitting control transistor included in the first pixel circuit 201A of the first area J1, and another scan control signal output terminal SCAN OUT The wire is pulled to the right and electrically connected to the second pixel circuit 201B of the third area J3, such as electrically connected to the gate of any transistor other than the light-emitting control transistor included in the second pixel circuit 201B of the third area J3, so that the second shift register 202B of the second area J2 provides a scanning control signal to the pixel circuits 201 of the first area J1 and the third area J3 on both sides thereof, thereby realizing a scanning control driving effect on all pixel circuits 201 in the display panel 000, and further realizing normal driving of the pixel circuit 201 by the shift register 202 in the display panel 000.

[0103] In some optional embodiments, please refer to Figure 13 and Figure 14 , Figure 13 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present disclosure, Figure 14 yes Figure 13 A partial enlarged structural diagram of the second area adjacent to the first area and the second area adjacent to the third area (it can be understood that in order to clearly illustrate the structure of this embodiment, Figure 13 and Figure 14Transparency filling is performed). In this embodiment, along the first direction X, the maximum width of the first shift register unit 202A0 is W11, and along the second direction Y, the maximum height of the first shift register unit 202A0 is H11; wherein, W11<H11, the first direction X is the direction from the first area J1 to the second area J2, and the first direction X can also be understood as the direction X from one edge 000L1 of the display panel 000 to the other edge 000L2 opposite thereto (this embodiment and subsequent embodiments are all labeled X); in a direction parallel to the plane of the substrate 10, the second direction Y intersects the first direction X. It can be understood that in this embodiment, the first direction X and the second direction Y are perpendicular to each other in a direction parallel to the plane of the substrate 10.

[0104] This embodiment explains that the display panel 000 sets the shift register 202 in the second area J2, that is, when it is further away from the edge of the display panel 000, the multiple shift registers 202 include a first shift register 202A, the first shift register 202A includes a plurality of cascaded first shift register units 202A0, and the first shift register 202A can be used to provide a light-emitting control signal for each pixel circuit in the display panel 000. The first shift register 202A includes a plurality of cascaded first shift register units 202A0, and the first shift register unit 202A0 can be used to provide a light-emitting control signal for the pixel circuits 201 of at least one pixel circuit row, such as the light-emitting control signal required by the gate of the light-emitting control transistor included in the pixel circuit 201. The light-emitting control signal can be used to control the conduction and cutoff of the light-emitting control transistor in the pixel circuit 201. The first shift register unit 202A0 outputs a light-emitting control signal through a light-emitting control signal output terminal EM. OUT The first shift register unit 202A0 is electrically connected to a row of first pixel circuits 201A, and provides a light emitting control signal to the row of first pixel circuits 201A. The first shift register unit 202A0 outputs a light emitting control signal through another light emitting control signal output terminal EM. OUTThe first shift register unit 202A0 is electrically connected to a row of second pixel circuits 201B and provides light-emitting control signals to the row of second pixel circuits 201B. In this embodiment, the maximum width W11 of the first shift register unit 202A0 in the first direction X is smaller than the maximum height H11 of the first shift register unit 202A0 in the second direction Y. That is, the orthographic projection of the first shift register unit 202A0 on the substrate 10 is narrower in the first direction X and wider in the second direction Y. This facilitates one first shift register unit 202A0 driving at least two rows of pixel circuits. Since the first shift register unit 202A0 is used to provide a light-emitting control signal for the pixel circuit, the first shift register unit 202A0 providing the light-emitting control signal has less influence on the operation of the pixel circuit 201 than the second shift register unit 202B0. Therefore, the shape of the orthographic projection of the first shift register unit 202A0 on the substrate 10 can be arranged to be narrow in the first direction X and wide in the second direction Y, which facilitates the use of a one-drive-two driving method, that is, one first shift register unit 202A0 jointly drives two rows of pixel circuits 201, which helps to save the layout space of the shift register 202 in the first area J1.

[0105] In some optional embodiments, please continue to refer to Figure 13 and Figure 14 In this embodiment, along the first direction X, the maximum width of the second shift register unit 202B0 is W21, and along the second direction Y, the maximum height of the second shift register unit 202B0 is H21; wherein W21>H21.

[0106] This embodiment explains that when the display panel 000 sets the shift register 202 in the second area J2, that is, further away from the edge of the display panel 000, the multiple shift registers 202 include a second shift register 202B, and the second shift register 202B can be used to provide a scan control signal for each pixel circuit in the display panel 000. The second shift register 202B includes a plurality of cascaded second shift register units 202B0. The second shift register unit 202B0 can be used to provide a scan control signal for the pixel circuit 201 of a pixel circuit row, such as the scan control signal required for the gate of other transistors included in the pixel circuit 201 except the light-emitting control transistor. The conduction and cutoff of other transistors in the pixel circuit 201 except the light-emitting control transistor can be controlled by the scan control signal.

[0107] The second shift register unit 202B0 outputs a scan control signal through a scan control signal output terminal SCAN OUT The second shift register unit 202B0 is electrically connected to a row of first pixel circuits 201A and provides a scan control signal to the row of first pixel circuits 201A. The second shift register unit 202B0 outputs a scan control signal through another scan control signal output terminal SCAN. OUTThe second shift register unit 202B0 is electrically connected to a row of second pixel circuits 201B and provides a scan control signal to the row of second pixel circuits 201B. In this embodiment, the maximum width of the second shift register unit 202B0 in the first direction X is W21, which is greater than the maximum height of the second shift register unit 202B0 in the second direction Y is H21. That is, the orthographic projection of the second shift register unit 202B0 on the substrate 10 is wider in the first direction X and narrower in the second direction Y. This facilitates one second shift register unit 202B0 to drive only one row of pixel circuits. Since the second shift register unit 202B0 is used to provide a scan control signal for the pixel circuit, the second shift register unit 202B0 that provides the scan control signal has a greater impact on the operation of the pixel circuit 201 than the first shift register unit 202A0. Therefore, the shape of the second shift register unit 202B0's positive projection on the substrate 10 can be arranged to be wider in the first direction X and narrower in the second direction Y, so that a one-drive-one driving method is adopted, that is, one second shift register unit 202B0 only drives one row of pixel circuits 201, which can ensure the normal driving effect of the pixel circuit 201 and realize that multiple rows of pixel circuits can display and drive each row of light-emitting elements one by one.

[0108] It should be noted that, in the figure of this embodiment, the first shift register unit 202A0 and the second shift register unit 202B0 of the shift register 202 are represented by a block diagram. In a specific implementation, the first shift register unit 202A0 and the second shift register unit 202B0 are circuit structures including a plurality of thin film transistors and a plurality of capacitors, etc., respectively. Therefore, the outer edges of the orthographic projections of the first shift register unit 202A0 and the second shift register unit 202B0 on the plane where the substrate 10 is located will not be regular shapes. Therefore, in this embodiment, the maximum width W11 of the first shift register unit 202A0 in the first direction X can be understood as the outermost edges of the first shift register unit 202A0 in the orthographic projection of the substrate 10 in the first direction X. the width between the two places; the maximum height H11 of the first shift register unit 202A0 in the second direction Y can be understood as the height between the two outermost edges of the first shift register unit 202A0 in the second direction Y in the orthographic projection pattern of the substrate 10; similarly, the maximum width W21 of the second shift register unit 202B0 in the first direction X can be understood as the width between the two outermost edges of the second shift register unit 202B0 in the first direction X in the orthographic projection pattern of the substrate 10; the maximum height H21 of the second shift register unit 202B0 in the second direction Y can be understood as the height between the two outermost edges of the second shift register unit 202B0 in the second direction Y in the orthographic projection pattern of the substrate 10.

[0109] In some optional embodiments, please refer to Figure 15 , Figure 15is another schematic diagram of the planar structure of the display panel provided in the embodiment of the present disclosure (it can be understood that in order to clearly illustrate the structure of this embodiment, Figure 15 Transparency filling is performed), in this embodiment, the display panel 000 includes a plurality of transmission areas TA, and the plurality of transmission areas TA include a first transmission area TA1, a second transmission area TA2, and a third transmission area TA3;

[0110] The first transmission area TA1 is located in the first area J1, the second transmission area TA2 is located in the second area J2, and the third transmission area TA3 is located in the third area J3;

[0111] The area of the first transmission area TA1 is smaller than that of the third transmission area TA3 .

[0112] This embodiment illustrates that the display panel 000 may further include multiple transmission areas TA. The transmission areas TA can be understood as regions with a light transmittance greater than that of the light-emitting area where the light-emitting element 40 is located, thereby achieving a transparent display effect in the display panel 000. In specific implementations, light-shielding structures such as metal can be positioned away from the transmission areas TA, or low-transmittance film layers within the transmission areas TA can be hollowed out to increase the light transmittance of the transmission areas TA. For more details, reference can be made to the film layer configuration methods for transmission areas in related transparent display technologies.

[0113] The display panel 000 of this embodiment disposes the shift register 202 in the second area J2, that is, further away from the edge of the display panel 000. This ensures a borderless display effect while also guaranteeing the electrical drive performance of the shift register 202. Furthermore, a certain area of transparent area (the transparent area TA can be understood as an area where the shift register unit, pixel circuit, and other circuits are not disposed) is reserved between adjacent electrode groups 301 in the second direction Y, so that the display panel has a certain transmittance, thereby achieving a transparent display effect for a borderless display.

[0114] The display panel 000 of this embodiment is provided with multiple transmission areas TA including a first transmission area TA1, a second transmission area TA2, and a third transmission area TA3; wherein the first transmission area TA1 is located in the first area J1, the second transmission area TA2 is located in the second area J2, and the third transmission area TA3 is located in the third area J3; that is, the first area J1 close to the edge of the display panel 000 also includes multiple first transmission areas TA1, so that the display panel 000 can be used for transparent display while achieving a borderless display and a display effect with high edge transparency.

[0115] Since the first area J1 needs to be provided with a large number of first pixel circuits 201A to respectively drive the light emitting elements 40 bonded to the electrode group 301 within the first area J1 and the light emitting elements 40 bonded to the electrode group 301 within the third area J3, it may be necessary to pull wires to drive to other areas (such as Figure 5and Figure 6 In the embodiment, the display panel 000 includes light-emitting elements 40 in both the first transition region JL1 and the second transition region JL2. Therefore, the first pixel circuits 201A in the first region J1 are arranged at a relatively high density. As described in the above embodiment, the width of the first pixel circuit groups 201AZ and the spacing between adjacent first pixel circuit groups 201AZ are both relatively small. Therefore, if a first transparent area TA1 is provided in the first region J1, the area of the first transparent area TA1 must be smaller than the area of the third transparent area TA3 in the third region J3 to prevent interference between the first transparent area TA1 and the first pixel circuits 201A. Despite the small area of the first transparent area TA1, an edge-transparent display effect can still be achieved.

[0116] It can be understood that, in this embodiment, the area of the first transmission area TA1 and the area of the third transmission area TA3 both represent the area of a plane figure of the orthographic projection of the first transmission area TA1 on the plane where the substrate 10 is located.

[0117] It should be noted that, in this embodiment Figure 15 The shapes of the first transmission area TA1 in the first region J1, the second transmission area TA2 in the second region J2, and the third transmission area TA3 in the third region J3 are merely illustrative. In specific implementations, the shapes of the transmission areas TA in different regions of the display panel 000 can be configured based on the actual layout space of each region. For example, signal traces in the display panel 000 can be bent to avoid routing as compactly as possible, leaving more space for the transmission areas TA. This can also ensure a smoother and more uniform light emission effect from the light-emitting element 40 in areas outside the non-transmission area. It should be understood that the shape of the transmission area TA in this embodiment refers to the planar shape of the orthographic projection of the transmission area TA onto the plane of the substrate 10.

[0118] Optional, please continue to refer to Figure 15 In this embodiment, the shape of the second transmission area TA2 is different from that of the first transmission area TA1 , and the shape of the second transmission area TA2 is different from that of the third transmission area TA3 .

[0119] This embodiment explains that since the first pixel circuit 201A needs to be set in the first area J1 and the second pixel circuit 201B needs to be set in the third area J3, in order to ensure that the resistance and parasitic capacitance of each node in the pixel circuit 201 of the first area J1 and the third area J3 are the same, thereby avoiding the first area J1 and the third area J3 from having different display uniformity due to different resistance and parasitic capacitance during display, so as to improve display uniformity and enhance display effect, it is necessary to set the shape of the orthographic projection of the first pixel circuit 201A on the substrate 10 and the shape of the orthographic projection of the second pixel circuit 201B on the substrate 10 to be the same as the shape of the orthographic projection of the second pixel circuit 201B on the substrate 10. The shape of the orthographic projection of 10 needs to be set to be as consistent as possible, that is, the wiring layout, placement of thin film transistors and capacitors of the first pixel circuit 201A in the first area J1 and the wiring layout, placement of thin film transistors and capacitors of the second pixel circuit 201B in the third area J3 need to be the same or as consistent as possible. Therefore, the shape of the first transmission area TA1 in the first area J1 and the shape of the third transmission area TA3 in the third area J3 can be the same or substantially the same. For example, the general shape of the first transmission area TA1 and the general shape of the third transmission area TA3 can both be rounded ellipses or circles, and the third transmission area TA3 can be substantially the same. The pixel circuit 201 is not provided in the second area J2, and the driving layer 20 is provided with a shift register 202. The circuit structure of each shift register unit 2020 in the shift register 202 is different from the circuit structure of the pixel circuit 201. Therefore, the overall circuit layout shape of each shift register unit 2020 in the second area J2 is also different. Moreover, the shift registers 202 in the second area J2 are only arranged in a cascade pattern in the second direction Y. In the first direction X, because there is only one group (the first shift register unit 202A0 and the second shift register unit 202B0) on a single side, it is The second transmission area TA2 is irregular, so the place where there is surplus space in the second area J2 except the shift register 202 can be set, so the shape of the transmission area in the first area J1 and the third area J3 can be different, that is, the shape of the second transmission area TA2 is different from the shape of the first transmission area TA1, and the shape of the second transmission area TA2 is different from the shape of the third transmission area TA3, so that the shapes of the transmission areas TA in different areas of the display panel 000 can be reasonably arranged to further increase the area ratio of the transmission area TA in the display panel 000 and improve the transparent display effect.

[0120] Optional, please continue to refer to Figure 15 In this embodiment, the shapes of the plurality of first transmission areas TA1 in the first region J1 are the same, and the shapes of the plurality of third transmission areas TA3 in the third region J3 are the same;

[0121] At least two second transmission areas TA2 of the second region J2 have different shapes.

[0122] In the display panel 000 of this embodiment, since the shape of the orthographic projection of the first pixel circuit 201A on the substrate 10 needs to be set to be as consistent as possible, the wiring layout, placement of thin film transistors and capacitors of the first pixel circuit 201A in the first area J1 and the wiring layout, placement of thin film transistors and capacitors of the second pixel circuit 201B in the third area J3 need to be the same or as consistent as possible. Therefore, the shape of the first transparent area TA1 in the first area J1 and the shape of the third transparent area TA3 in the third area J3 can be the same or basically the same. However, since the first shift register unit 202A0 in the second area J2 is used to provide a light-emitting control signal for the pixel circuit, the first shift register unit 202A0 that provides the light-emitting control signal has a smaller influence on the operation of the pixel circuit 201 than the second shift register unit 202B0, so the shape of the orthographic projection of the first shift register unit 202A0 on the substrate 10 can be arranged as a shape that is narrower in the first direction X and wider in the second direction Y, which is convenient for driving in a one-drive-two manner; and the second shift register unit 202B0 is used to provide a scan control signal for the pixel circuit, and the second shift register unit 202B0 that provides the scan control signal has a greater influence on the operation of the pixel circuit 201 than the first shift register unit 202A0, so the shape of the orthographic projection of the second shift register unit 202B0 on the substrate 10 can be arranged as a shape that is wider in the first direction X and wider in the second direction Y. The narrow shape in the two directions Y enables a one-drive-one driving method, that is, the shape of the first shift register unit 202A0 projected on the substrate 10 is narrow in the first direction X and wide in the second direction Y, and the shape of the second shift register unit 202B0 projected on the substrate 10 is wide in the first direction X and narrow in the second direction Y. Therefore, among the multiple second transmission areas TA2 provided in the second region J2 outside the shift register 202, at least two second transmission areas TA2 have different shapes. For example, the multiple second transmission areas TA2 can have a circular shape, a rectangular shape, a square shape, etc. Second transmission areas TA2 of different shapes can be provided in any spare space in the second region J2 other than the shift register 202, thereby fully utilizing the spare space in the second region J2 to improve the transparent display effect.

[0123] Optionally, in this embodiment, the shape of the second transparent area TA2 included in the second zone J2 can also be that the edge of the second transparent area TA2 includes at least one straight edge and at least one arc edge (not shown in the figure), so that the signal line electrically connected to the shift register unit 2020 along the second direction Y can be as close to the straight edge of the second transparent area TA2 as possible to increase the transmittance as much as possible, and the arc edge of the second transparent area TA2 can better match the shape of the third transparent area TA3 of the third zone J3, and the arc edge of the second transparent area TA2 can also better match the shape of the first transparent area TA1 of the first zone J1, which is beneficial to reduce diffraction, avoid display halo, and improve display quality.

[0124] In some optional embodiments, please refer to Figure 16 , Figure 16 is another schematic diagram of the planar structure of the display panel provided in the embodiment of the present disclosure (it can be understood that in order to clearly illustrate the structure of this embodiment, Figure 16 Transparency filling is performed), in this embodiment, the display panel 000 further includes a first transition area JL1 and a second transition area JL2; the first transition area JL1 is located between the first area J1 and the second area J2, and the second transition area JL2 is located between the second area J2 and the third area J3;

[0125] The driving layer 20 of the first transition region JL1 is provided with a first connecting driving line LX1, and the shift register 202 is electrically connected to the first pixel circuit 201A via the first connecting driving line LX1;

[0126] The driving layer 20 of the second transition region JL2 is provided with a second connecting driving line LX2 , and the shift register 202 is electrically connected to the second pixel circuit 201B via the second connecting driving line LX2 .

[0127] The first transition area JL1 includes a plurality of fourth transmission areas TA4, and the second transition area JL2 includes a plurality of fifth transmission areas TA5;

[0128] An edge of the fourth transmission area TA4 facing the second area J2 is a straight line edge, and an edge of the fifth transmission area TA5 facing the second area J2 is a straight line edge.

[0129] Optionally, the area of the fourth transmission area TA4 is smaller than that of the first transmission area TA1 , and the area of the fifth transmission area TA5 is smaller than that of the third transmission area TA3 .

[0130] This embodiment explains that the display panel 000 may further include a first transition region JL1 and a second transition region JL2 along the first direction X, wherein the first transition region JL1 is located between the first region J1 and the second region J2 , and the second transition region JL2 is located between the second region J2 and the third region J3 . When the driving layer 20 of the second area J2 is set with the circuit structure of the shift register 202, the second area J2 where the shift register 202 is located is still normally equipped with the light-emitting element 40 bonded to the electrode group 301, and the shift register 202 of the second area J2 needs to provide a driving signal to the first pixel circuit 201A of the first area J1, and also needs to provide a driving signal to the second pixel circuit 201B of the third area J3, so that the first pixel circuit 201A of the first area J1 and the second pixel circuit 201B of the third area J3 can both be driven normally by the shift register 202 of the second area J2. Therefore, the output ends of each shift register unit 2020 of the shift register 202 of the second area J2 need to lead out signal lines to the first pixel circuit 201A of the first area J1 and the second pixel circuit 201B of the third area J3 respectively. And because the second area J2 is still equipped with a light-emitting element 40, but the second area J2 does not have a pixel circuit 201, the space for arranging the pixel circuit in the driving layer 20 below the light-emitting element 40 of the second area J2 is used to set up the shift register 202. Therefore, the electrode group 301 bonded to the light-emitting element 40 of the second area J2 needs to lead out wires to the pixel circuits in other areas to achieve the driving and luminous effect of the pixel circuits in other areas on the light-emitting element 40 in the second area J2. Therefore, the second area J2 needs to lead out a large number of signal lines (for the signal output of the shift register 202 of the second area J2, and for introducing the driving signal of the pixel circuit for the light-emitting element 40 in the second area J2).In this embodiment, a direction X is set along one edge 000L1 of the display panel 000 pointing to another edge 000L2 opposite thereto. The display panel 000 further includes a first transition region JL1 located between the first region J1 and the second region J2, and a second transition region JL2 located between the second region J2 and the third region J3. The driving layer 20 of the first transition region JL1 is used to set a first connecting driving trace LX1. The first connecting driving trace LX1 can be located in at least one conductive film layer of the driving layer 20, or the first connecting driving trace LX1 can also be located in multiple conductive film layers of the driving layer 20. It is only necessary that the driving layer 20 of the first transition region JL1 has sufficient space to arrange the first connecting driving trace LX1. , the shift register 202 of the second area J2 and the first pixel circuit 201A of the first area J1 can be electrically connected through the first connecting driving trace LX1; similarly, the driving layer 20 of the second transition area JL2 is used to set the second connecting driving trace LX2, and the second connecting driving trace LX2 can be located in at least one conductive film layer of the driving layer 20, or the second connecting driving trace LX2 can also be located in multiple conductive film layers of the driving layer 20. It is only necessary to meet the requirement that the driving layer 20 of the second transition area JL2 has sufficient space for arranging the second connecting driving trace LX2, and the shift register 202 of the second area J2 and the second pixel circuit 201B of the third area J3 can be electrically connected through the second connecting driving trace LX2.

[0131] When the display panel 000 is used for transparent display, that is, the display panel 000 includes multiple transmission areas TA, the first transition area JL1 includes multiple fourth transmission areas TA4, and the second transition area JL2 includes multiple fifth transmission areas TA5; optionally, the area of the fourth transmission area TA4 is smaller than the area of the first transmission area TA1, and the area of the fifth transmission area TA5 is smaller than the area of the third transmission area TA3. This allows the first transition area JL1 and the second transition area JL2 to have more space for arranging signal lines connecting the second area J2 and the third area J3, and connecting the second area J2 and the third area J3 (as described above). Figure 5 and Figure 6 The embodiment of the connection driving wiring and the anode connection line) is conducive to achieving a transparent display effect in the first transition area JL1 and the second transition area JL2, while also ensuring the driving between the shift register 202 of the second area J2 and the first pixel circuit 201A of the first area J1 and the second pixel circuit 201B of the third area J3, as well as the driving of the light-emitting element 40 by all pixel circuits 201, thereby improving the rationality of the wiring layout in the panel.

[0132] In this embodiment, the fourth transmission area TA4 is further configured to have a straight edge on one side facing the second area J2, and the fifth transmission area TA5 is further configured to have a straight edge on one side facing the second area J2. Since the shift register 202 in the second area J2 includes a plurality of first shift register units 202A0 in a cascade structure and a plurality of second shift register units 202B0 in a cascade structure, and the shift register units 2020 in the cascade structure need to be electrically connected in cascade via wiring extending along the second direction Y, the fourth transmission area TA4 in the first transition area JL1 is further configured to have a straight edge on one side facing the second area J2 to avoid the longitudinal direction of the second area J2. To the wiring, the edge of the fifth transparent area TA5 set in the second transition area JL2 toward the second area J2 is set as a straight edge to avoid the longitudinal wiring of the second area J2 (such as the clock signal line, power signal line, reset signal line, etc. required for the electrical connection between the multiple cascaded first shift register units 202A0 of the shift register 202 in the second area J2, and the electrical connection between the multiple cascaded second shift register units 202B0, which are not described in detail in this embodiment. For details, please refer to the electrical connection structure of the shift register in the relevant technology for understanding), thereby simplifying the wiring layout of the second area J2, which is beneficial to improving process efficiency.

[0133] Optionally, in this embodiment, the first transition region JL1 includes a plurality of fourth transmission regions TA4, and the second transition region JL2 includes a plurality of fifth transmission regions TA5. The edges of the fourth transmission regions TA4 may include at least one straight edge and at least one curved edge. This allows the signal traces electrically connected to the shift register unit 2020 along the second direction Y to fit as closely as possible to the straight edges of the fourth transmission regions TA4, thereby maximizing transmittance. Furthermore, the curved edges of the fourth transmission regions TA4 may better match the shapes of the transmission regions in other regions, thereby facilitating reduced diffraction, avoiding display haloing, and improving display quality. Similarly, the edges of the fifth transmission regions TA5 may include at least one straight edge and at least one curved edge. This allows the signal traces electrically connected to the shift register unit 2020 along the second direction Y to fit as closely as possible to the straight edges of the fifth transmission regions TA5, thereby maximizing transmittance. Furthermore, the curved edges of the fifth transmission regions TA5 may better match the shapes of the transmission regions in other regions, thereby facilitating reduced diffraction, avoiding display haloing, and improving display quality.

[0134] In some optional embodiments, please refer to Figure 17 , Figure 17 is another schematic diagram of the planar structure of the display panel provided in the embodiment of the present disclosure (it can be understood that in order to clearly illustrate the structure of this embodiment, Figure 17Transparency filling is performed). In this embodiment, in the first area J1, along the first direction X, three adjacent first pixel circuits 201A form a first pixel circuit group 201AZ, and the first pixel circuit group 201AZ drives three adjacent electrode groups 301; wherein the first direction X is the direction from the first area J1 to the second area J2;

[0135] In the first region J1, along a first direction X, a plurality of first pixel circuit groups 201AZ form a first pixel circuit group row 201AZH, and a plurality of first transmission areas TA1 form a first transmission area row TA1H. Along a second direction Y, the first pixel circuit group row 201AZH is located between two adjacent first transmission area rows TA1H. The second direction Y intersects the first direction X in a direction parallel to the plane of the substrate 10.

[0136] This embodiment explains that in the first area J1, along the first direction X, three adjacent first pixel circuits 201A form a first pixel circuit group 201AZ, and the first pixel circuit group 201AZ drives three adjacent electrode groups 301; the three electrode groups 301 driven by the first pixel circuit group 201AZ are electrically connected to three light-emitting elements 40 of different colors, and the three adjacent electrode groups 301 driven by the first pixel circuit group 201AZ can be used to bind and bond three light-emitting elements 40 of different colors, that is, the three light-emitting elements 40 driven by the first pixel circuit group 201AZ can be understood as a pixel unit including three primary color RGB light-emitting elements.

[0137] When the first area J1 of the display panel 000 of this embodiment includes a plurality of first transmission areas TA1, a plurality of first pixel circuit groups 201AZ along the first direction X in the first area J1 may be arranged to form a first pixel circuit group row 201AZH. The plurality of first pixel circuit group rows 201AZH are arranged along the second direction Y. A plurality of first transmission areas TA1 along the first direction X form a first transmission area row TA1H. The plurality of first transmission area rows TA1H are arranged along the second direction Y. Then, along the second direction Y, the first pixel circuit group row 201AZH is arranged between two adjacent first transmission area rows T. A1H, so that the layout of the first pixel circuit 201A in the first area J1 can be more compact, that is, the layout of the first pixel circuit group 201AZ can be more compact, and the first area J1 can be provided with more first pixel circuits 201A to drive the light-emitting elements of the first area J1 itself and drive the light-emitting elements 40 of the second area J2, so as to ensure the transparent display effect of the first area J1 while maximizing the layout number of the first pixel circuits 201A in the first area J1, thereby realizing the driving and luminous performance of the overall light-emitting elements of the display panel 000.

[0138] Optional, such as Figure 17As shown, in the third area J3, along the first direction X, three adjacent second pixel circuits 201B form a second pixel circuit group 201BZ, and the second pixel circuit group 201BZ drives three adjacent electrode groups 301;

[0139] The four third transmission areas TA3 of the third region J3 are arranged around one second pixel circuit group 201BZ.

[0140] This embodiment explains that the layout density of the second pixel circuit 201B in the third area J3 of the display panel 000 can be relatively small, and one electrode group 301 in the third area J3 can be bonded to one light-emitting element 40, and one electrode group 301 can be electrically connected and driven through one second pixel circuit 201B. Therefore, the positional relationship between the third transparent area TA3 and the second pixel circuit 201B in the third area J3 can be that in the third area J3, along the first direction X, three adjacent second pixel circuits 201B form a second pixel circuit group 201BZ, and the second pixel circuit group 201BZ drives three adjacent electrode groups 301; in the third area J3, along the first direction X, three adjacent second pixel circuits 201B form a second pixel circuit group 201BZ, and the second pixel circuit group 201B drives three adjacent electrode groups 301. The three electrode groups 301 driven by the second pixel circuit group 201BZ are electrically connected to three light-emitting elements 40 of different colors. The three adjacent electrode groups 301 driven by the second pixel circuit group 201BZ can be used to bind and bond the three light-emitting elements 40 of different colors, that is, the three light-emitting elements 40 driven by the second pixel circuit group 201BZ can be understood as a pixel unit including three primary color RGB light-emitting elements. The four third transmission areas TA3 of the third area J3 are arranged around a second pixel circuit group 201BZ. A second pixel circuit group 201BZ of the third area J3 can be arranged in the middle area surrounded by the four third transmission areas TA3, so that the transmission area of the third area J3 can be large enough, and there is more space to set the third transmission area TA3, which is conducive to better improving the transparent display effect.

[0141] Optionally, in this embodiment, the signal lines of the third zone J3 are bent and avoided. For example, the connection lines between the shift register 202 and the second pixel circuit 201B can be bent and avoided outside the third transparent area TA3, so that the layout of the lines is as compact as possible, leaving more space for setting up the third transparent area TA3, which is conducive to increasing the layout area of the third transparent area TA3 of the third zone J3 and improving the transparent display effect.

[0142] In some optional embodiments, please refer to Figures 18-20 , Figure 18 is another schematic diagram of the planar structure of the display panel provided in the embodiment of the present disclosure (it can be understood that for the sake of distinction, Figure 18Different filling patterns are used to represent the edge transmission area TAA and the non-edge transmission area TAB, in order to clearly illustrate the structure of this embodiment. Figure 18 Transparency filled), Figure 19 yes Figure 18 A schematic diagram of a cross-sectional structure in the C-C' direction, Figure 20 yes Figure 18 A schematic cross-sectional structure diagram taken along the D-D' line in the middle shows that in the display panel 000 of this embodiment, the multiple transmission areas TA include multiple edge transmission areas TAA and multiple non-edge transmission areas TAB. The non-edge transmission areas TAB are not included between the edge transmission areas TAA and the edge 000L of the display panel 000. The non-edge transmission areas TAB are located on the side of the edge transmission areas TAA away from the edge 000L of the display panel 000.

[0143] The display panel 000 includes a plurality of organic layers 001 and a plurality of inorganic layers 002 located on one side of a substrate 10. Optionally, the organic layers 001 may be made of a material selected from photosensitive polyimide (PSPI) and acrylic resin, and the inorganic layers 002 may be made of a material selected from silicon nitride (SiN) and silicon oxide (SiO).

[0144] In the edge transmission area TAA, the display panel 000 does not include the organic layer 001 , and the display panel 000 includes at least one inorganic layer 002 ;

[0145] In the non-edge transmission area TAB, the display panel 000 does not include the organic layer 001 and the inorganic layer 002 .

[0146] This embodiment illustrates that when a display panel 000 is used for a transparent display, the display panel 000 includes multiple transmission areas TA. The transmission areas TA have a higher transmittance of heat-generating light than other areas, thereby achieving a transparent display effect. The multiple transmission areas TA may include multiple edge transmission areas TAA and multiple non-edge transmission areas TAB. The edge transmission area TAA refers to the transmission area at the edge 000L of the display panel 000. The non-edge transmission area TAB is located on the side of the edge transmission area TAA away from the edge 000L of the display panel 000. The non-edge transmission area TAB is not located between the edge transmission area TAA and the edge 000L of the display panel 000.

[0147] like Figure 19 As shown, the film structure of the display panel 000 of this embodiment can be a combination of multiple conductive film layers and multiple inorganic layers and organic layers. The display panel 000 includes multiple organic layers 001 and multiple inorganic layers 002 located on one side of the substrate 10, wherein, as shown in FIG. Figure 19The driving layer 20 shown in the example may include a gate metal layer 20A where the gate of the thin film transistor 20T is located, a source and drain metal layer 20B where the source and drain of the thin film transistor 20T are located, a capacitor metal layer 20C where the capacitor plate is located, a semiconductor layer 20P where the active part of the thin film transistor 20T is located, and a first conductive layer 20D for making driving signal lines such as power signal lines, and other conductive film layers in the direction Z perpendicular to the plane where the substrate 10 is located. The first conductive layer 20D can be understood as a conductive film layer in the driving layer 20 that is closest to the electrode layer 30, and may also include an inorganic layer 002 or an organic layer 001 between adjacent conductive film layers. Optionally, the thin film transistor 20T provided in the driving layer 20 may be a dual-gate transistor, the top gate of which may be made of a gate metal layer 20A, and the bottom gate of which may be located on the side of the semiconductor layer 20P facing the substrate 10. At the same time, the metal layer where the bottom gate is located may be used as a light-shielding metal layer to shield the channel region of the thin film transistor 20T from light, thereby preventing light from shining on the channel region of the thin film transistor 20T to generate carriers and affect the performance of the thin film transistor 20T. Figure 19 This is only an example. In specific implementations, the film structure of the driving layer 20 includes but is not limited to this.

[0148] In this embodiment, the insulating layers between the semiconductor layer 20P and the gate metal layer 20A, between the gate metal layer 20A and the capacitor metal layer 20C, between the capacitor metal layer 20C and the source and drain metal layer 20B, and on the side of the electrode layer 30 away from the substrate 10 can be inorganic layers 002, which can play the role of insulation protection and isolation of water and oxygen intrusion. The insulating layers between the source and drain metal layer 20B and the first conductive layer 20D, and between the first conductive layer 20D and the electrode layer 30 can be organic layers 002, which are relatively thick and can play an insulating role as well as a flattening role.

[0149] When the display panel 000 of this embodiment is used for transparent display, in order to improve the transmittance, part of the film layer with low transmittance in the transmittance area TA is generally etched away to ensure that the transmittance of the transmittance area TA is effectively improved.

[0150] In this embodiment, the edge transmission area TAA and the non-edge transmission area TAB have different film layer structures, which can also be understood as the edge transmission area TAA and the non-edge transmission area TAB having different film layers etched for improving transmittance. Specifically, in the edge transmission area TAA, the display panel 000 does not include the organic layer 001, and the light transmittance of the organic layer 001 is poor. Etching away all the organic layer 001 in the edge transmission area TAA can ensure the high transmittance of the edge transmission area TAA, but the display panel 000 includes at least one inorganic layer 002 in the edge transmission area TAA, that is, at least one inorganic layer 002 is retained in the edge transmission area TA, such as at least retaining the insulating layer between the semiconductor layer 20P and the gate metal layer 20A in the edge transmission area TA, or retaining at least the insulating layer between the gate metal layer 20A and the capacitor metal layer 20C in the edge transmission area TA, or retaining the insulating layer between the gate metal layer 20A and the capacitor metal layer 20C in the edge transmission area T A at least retains the insulating layer between the capacitor metal layer 20C and the source / drain metal layer 20B, or at least retains the insulating layer on the side of the electrode layer 30 away from the substrate 10 in the edge transmission area TA (not shown in the figure), or preferably retains all the above-mentioned inorganic layers 002 in the edge transmission area TA, and only etches away the insulating layer between the source / drain metal layer 20B and the first conductive layer 20D and the insulating layer between the first conductive layer 20D and the electrode layer 30, so that the inorganic layer 002 retained in the edge transmission area TAA near the edge 000L of the display panel 000 can cover the organic layer 001 around the edge transmission area TAA, and the relatively dense structure of the inorganic layer 002 effectively blocks the intrusion of water vapor, reduces the probability of water absorption of the organic layer 001 around the edge transmission area TAA, thereby ensuring the display quality and service life of the display panel 000, and improving the product yield and product reliability. In the non-edge transparent area TAB, the display panel 000 does not include the organic layer 001 and the inorganic layer 002, that is, the organic layer 001 and the inorganic layer 002 in the film layer of the non-edge transparent area TAB of the display panel 000 are all etched away, which can effectively improve the transmittance. Moreover, since the non-edge transparent area TAB is far away from the edge 000L of the display panel 000, even if the organic layer 001 and the inorganic layer 002 are all etched away, the probability of water and oxygen intrusion is small, and the impact on the display performance is small.

[0151] Optional, such as Figure 18 、 Figure 21 and Figure 22 As shown, Figure 21 yes Figure 18 Another cross-sectional structure diagram in the C-C' direction, Figure 22 yes Figure 18Another cross-sectional structural diagram along the D-D' line is shown. When the display panel 000 of this embodiment is used for a transparent display, to improve transmittance, portions of the film layers with low transmittance in the transmittance area TA are generally etched away to ensure that transmittance in the transmittance area TA is effectively improved. Furthermore, when both the organic layer 001 and the inorganic layer 002 in the non-edge transmittance area TAB are hollowed out and etched, and the organic layer 001 in the edge transmittance area TAA is hollowed out and etched, leaving only at least one inorganic layer 002, the hollowed-out area formed on one side of the substrate 10 can be filled with the subsequent encapsulation structure 003 to ensure surface flatness of the display panel 000 after the manufacturing process is completed.

[0152] It can be understood that the packaging structure 003 can be a packaging film layer with good light transmittance. The specific process technology and structure of the packaging structure 003 are not described in detail in this embodiment. For details, please refer to the packaging process of micro LED display panels or miniLED display panels in related technologies for understanding.

[0153] In some optional embodiments, please refer to Figure 18 、 Figure 23 and Figure 24 , Figure 23 yes Figure 18 Another cross-sectional structure diagram in the C-C' direction, Figure 24 yes Figure 18 Another cross-sectional structural diagram along the D-D' direction, in the film layer structure of the display panel 000 provided in this embodiment, the multiple organic layers 001 include a first planarization layer 001A and a second planarization layer 001B, and the multiple inorganic layers 002 include multiple interlayer insulating layers 002A, a first passivation layer 002B, and a second passivation layer 002C;

[0154] The display panel 000 includes a non-transmitting area NTA except for the transmissive area TA. In the non-transmitting area NTA, along a direction Z perpendicular to the plane of the substrate 10, the display panel 000 includes a substrate 10, a plurality of interlayer insulating layers 002A, a first passivation layer 002B, a first planarization layer 001A, a second planarization layer 001B, and a second passivation layer 002C.

[0155] In the edge transmission area TAA, along a direction Z perpendicular to the plane of the substrate 10, the display panel 000 includes a substrate 10, and a plurality of interlayer insulating layers 002A, a first passivation layer 002B, and a second passivation layer 002C sequentially stacked on the substrate 10;

[0156] In the non-edge transparent area TAB, along the direction Z perpendicular to the plane of the substrate 10, the display panel 000 includes a hollow portion LK, which penetrates multiple interlayer insulating layers 002A, the first passivation layer 002B, the first planarization layer 001A, the second planarization layer 001B, and the second passivation layer 002C on one side of the substrate 10.

[0157] This embodiment explains that the film structure of the display panel 000 can be a combination of multiple conductive film layers and multiple inorganic layers and organic layers. For example, the multiple conductive film layers of the display panel 000 include a semiconductor layer 20P, a gate metal layer 20A, a capacitor metal layer 20C, a source and drain metal layer 20B, a first conductive layer 20D, an electrode layer 30 and other conductive film layers located on one side of the substrate 10; the multiple inorganic layers 002 include multiple interlayer insulating layers 002A, a first passivation layer 002B, and a second passivation layer 002C, and also include multiple interlayer insulating layers 002A, such as the first interlayer insulating layer 002A1, the gate metal layer 002B, and the second passivation layer 002C located between the semiconductor layer 20P and the gate metal layer 20A. A second interlayer insulating layer 002A2 is provided between the source metal layer 20A and the capacitor metal layer 20C, a third interlayer insulating layer 002A3 is provided between the capacitor metal layer 20C and the source / drain metal layer 20B, the first passivation layer 002B is provided between the source / drain metal layer 20B and the first planarizing layer 001A, and the second passivation layer 002C is provided on the side of the electrode layer 30 away from the substrate 10; the multiple organic layers 001 include a first planarizing layer 001A and a second planarizing layer 001B, the first planarizing layer 001A is provided between the first passivation layer 002B and the first conductive layer 20D, and the second planarizing layer 001B is provided between the first conductive layer 20D and the electrode layer 30.

[0158] In this embodiment, the area other than the transmission area TA in the display panel 000 is set as a non-transmission area NTA. The non-transmission area NTA can be understood as the area where the pixel circuit 201, the shift register 202, the light-emitting element 40, the electrode group 301, etc. are arranged. In the non-transmission area NTA, along the direction Z perpendicular to the plane of the substrate 10, the film structure of the display panel 000 can sequentially include the substrate 10, the channel region light-shielding metal layer, the buffer layer, the semiconductor layer 20P, the first interlayer insulating layer 002A1, the gate metal layer 20A, the second interlayer insulating layer 002A2, the capacitor metal layer 20C, the third interlayer insulating layer 002A3, the source and drain metal layer 20B, the first passivation layer 002B, the first planarization layer 001A, the first conductive layer 20D, the second planarization layer 001B, the electrode layer 30, and the second passivation layer 002C.

[0159] In the edge transmission area TAA of the transmission area TA, along the direction Z perpendicular to the plane where the substrate 10 is located, the display panel 000 includes a substrate 10, and a plurality of interlayer insulating layers 002A, a first passivation layer 002B, and a second passivation layer 002C stacked in sequence on the substrate 10. In the prior art, if the shift register is set in the area near the edge of the display panel during the borderless display design, the circuit will fail due to the intrusion of water vapor. Therefore, in this embodiment, the shift register 202 is further retracted to the second area J2, further away from the edge 000L of the display panel 000. After the shift register 202 is further retracted, only the organic layer 001 that affects the light transmittance is removed from the edge transmission area TAA near the edge 000L of the display panel 000, and the inorganic layer 002 is retained. In this way, the side wall of the non-transmission area NTA adjacent to the edge transmission area TAA in the display panel 000 can be covered with the side wall of the organic layer 001 by the inorganic layer 002 (such as the structure of Figure 23 As shown), the dense protection performance of the inorganic layer 002 prevents water vapor from intruding, further blocks and isolates the path of water vapor intrusion, which is conducive to better ensuring circuit reliability.

[0160] In the non-edge transmission area TAB, along the direction Z perpendicular to the plane of the substrate 10, the display panel 000 includes a hollow portion LK. The hollow portion LK penetrates multiple interlayer insulating layers 002A, the first passivation layer 002B, the first planarization layer 001A, the second planarization layer 001B, and the second passivation layer 002C on one side of the substrate 10. That is, the inorganic layer 002 and the organic layer 001 of the non-edge transmission area TAB are all dug out. While removing the organic layer 001 that affects the light transmittance, the inorganic layer 002 is also removed, which can further improve the transmittance and enhance the transparent display effect.

[0161] In some optional embodiments, please continue to refer to Figure 18 and Figure 24 In this embodiment, in the non-edge-transmitting area TAB, the first passivation layer 002B includes a first opening 002BK, which penetrates the thickness of the first passivation layer 002B; the first planarization layer 001A includes a second opening 001AK, which penetrates the thickness of the first planarization layer 001A; the second planarization layer 001B includes a third opening 001BK, which penetrates the thickness of the second planarization layer 001B; the interlayer insulating layer 002A includes a fourth opening 002AK, which penetrates the thickness of the interlayer insulating layer 002A;

[0162] The orthographic projection of the third opening 001BK on the substrate 10 covers the orthographic projection of the second opening 001AK on the substrate 10, the orthographic projection of the second opening 001AK on the substrate 10 covers the orthographic projection of the first opening 002BK on the substrate 10, and the orthographic projection of the first opening 002BK on the substrate 10 covers the orthographic projection of the fourth opening 002AK on the substrate 10; the orthographic projection area of the third opening 001BK on the substrate 10 is larger than the orthographic projection area of the second opening 001AK on the substrate 10, the orthographic projection area of the second opening 001AK on the substrate 10 is larger than the orthographic projection area of the first opening 002BK on the substrate 10, and the orthographic projection area of the first opening 002BK on the substrate 10 is larger than the orthographic projection area of the fourth opening 002AK on the substrate 10;

[0163] Outside the non-edge transparent area TAB, that is, in the non-transparent area NTA, at least part of the second passivation layer 002C covers the side walls of the third opening 001BK of the second planarization layer 001B, and covers the side walls of the second opening 001AK of the first planarization layer 001A, and covers the side walls of the first opening 002BK of the first passivation layer 002B, and covers the side walls of the fourth opening 002AK of the interlayer insulating layer 002A, and at least part of the second passivation layer 002C is in direct contact with the substrate 10.

[0164] This embodiment explains that the non-edge transparent area TAB formation method in the display panel 000 can be that after the first passivation layer 002B and the film layer below it are formed on the substrate 10, the non-edge transparent area TAB is exposed and etched to form a fourth opening 002AK of the interlayer insulating layer 002A, the fourth opening 002AK penetrates the thickness of the interlayer insulating layer 002A, and the first opening 002BK of the first passivation layer 002B is formed, the first opening 002BK penetrates the thickness of the first passivation layer 002B, and then the first passivation layer 002B is further formed away from the substrate 10. After the first planarization layer 001A is formed, the first planarization layer 001A is etched. Exposure and etching are performed to form a second opening 001AK in the first planarization layer 001A. The second opening 001AK penetrates the thickness of the first planarization layer 001A, and the orthographic projection of the second opening 001AK on the substrate 10 covers the orthographic projection of the first opening 002BK on the substrate 10. The orthographic projection of the first opening 002BK on the substrate 10 covers the orthographic projection of the fourth opening 002AK on the substrate 10. The orthographic projection area of the second opening 001AK on the substrate 10 is larger than the orthographic projection area of the first opening 002BK on the substrate 10. The orthographic projection area of the first opening 002BK on the substrate 10 is larger than the orthographic projection area of the fourth opening 002AK on the substrate 10.Then, the first planarization layer 001A is continuously formed on the side away from the substrate 10 until the second planarization layer 001B is formed. The second planarization layer 001B is exposed and etched to form a third opening 001BK in the second planarization layer 001B. The third opening 001BK penetrates the thickness of the second planarization layer 001B, and the orthographic projection of the third opening 001BK on the substrate 10 covers the orthographic projection of the second opening 001AK on the substrate 10. The orthographic projection area of the third opening 001BK on the substrate 10 is larger than the orthographic projection area of the second opening 001AK on the substrate 10. Shadow area, finally, the second passivation layer 002C is formed and etched after the electrode layer 30 is made and patterned, forming the fifth opening 002CK of the second passivation layer 002C and other through holes exposing part of the electrode group 301, the fifth opening 002CK penetrates the thickness of the second passivation layer 002C, and the orthographic projection of the fifth opening 002CK on the substrate 10 is located within the orthographic projection range of the fourth opening 002AK on the substrate 10, and the orthographic projection area of the fifth opening 002CK on the substrate 10 is smaller than the orthographic projection area of the fourth opening 002AK on the substrate 10, so that The second passivation layer 002C can cover the sidewalls of the openings in the non-transparent area NTA along the sidewalls of the third opening 001BK of the second planarization layer 001B, the sidewalls of the second opening 001AK of the first planarization layer 001A, the sidewalls of the first opening 002BK of the first passivation layer 002B, and the sidewalls of the fourth opening 002AK of the interlayer insulating layer 002A, in sequence. Only a portion of the second passivation layer 002C is in direct contact with the substrate 10. The third opening 001BK, the second opening 001AK, and the first opening 002 BK, the fourth opening 002AK, and the fifth opening 002CK together form a hollow portion LK, that is, the hollow portion LK penetrates multiple interlayer insulating layers 002A, the first passivation layer 002B, the first planarization layer 001A, the second planarization layer 001B, and the second passivation layer 002C on one side of the substrate 10, so that the inorganic layer 002 and the organic layer 001 of the non-edge transparent area TAB are all dug out. While removing the organic layer 001 that affects the transmittance, the inorganic layer 002 is also removed, which can further improve the transmittance and help to better enhance the transparent display effect.

[0165] In some optional embodiments, please refer to Figure 18 and Figure 25 , Figure 25 yes Figure 18Another cross-sectional structural diagram along the D-D' direction. In this embodiment, in the non-edge transparent area TAB, the first passivation layer 002B includes a first opening 002BK, and the first opening 002BK penetrates the thickness of the first passivation layer 002B; the first planarization layer 001A includes a second opening 001AK, and the second opening 001AK penetrates the thickness of the first planarization layer 001A; the second planarization layer 001B includes a third opening 001BK, and the third opening 001BK penetrates the thickness of the second planarization layer 001B;

[0166] The orthographic projection of the third opening 001BK on the substrate 10 covers the orthographic projection of the second opening 001AK on the substrate 10, and the orthographic projection of the second opening 001AK on the substrate 10 covers the orthographic projection of the first opening 002BK on the substrate 10. The orthographic projection area of the third opening 001BK on the substrate 10 is larger than the orthographic projection area of the second opening 001AK on the substrate 10, and the orthographic projection area of the second opening 001AK on the substrate 10 is larger than the orthographic projection area of the first opening 002BK on the substrate 10.

[0167] Outside the non-edge transparent area TAB, that is, in the non-transparent area NTA, at least a portion of the second passivation layer 002C covers the side walls of the third opening 001BK of the second planarization layer 001B, and covers the side walls of the second opening 001AK of the first planarization layer 001A, and at least a portion of the second passivation layer 002C is in direct contact with the surface of the first passivation layer 002B away from the substrate 10.

[0168] This embodiment explains that the non-edge transparent area TAB in the display panel 000 is formed by exposing and etching the non-edge transparent area TAB after the first passivation layer 002B and the film layer thereunder are formed on the substrate 10 to form a fourth opening 002AK in the interlayer insulating layer 002A, where the fourth opening 002AK penetrates the thickness of the interlayer insulating layer 002A, and forming a first opening 002BK in the first passivation layer 002B, where the first opening 002BK penetrates the thickness of the first passivation layer 002B, where the orthographic projection of the first opening 002BK on the substrate 10 covers the orthographic projection of the fourth opening 002AK on the substrate 10, and where the orthographic projection area of the first opening 002BK on the substrate 10 is larger than the orthographic projection area of the fourth opening 002AK on the substrate 10.

[0169] Then, the first passivation layer 002B continues to be formed on the side away from the substrate 10 until the first planarization layer 001A is formed. The first planarization layer 001A is exposed and etched to form a second opening 001AK in the first planarization layer 001A. The second opening 001AK penetrates the thickness of the first planarization layer 001A, and the orthographic projection of the second opening 001AK on the substrate 10 covers the orthographic projection of the first opening 002BK on the substrate 10. The orthographic projection area of the second opening 001AK on the substrate 10 is larger than the orthographic projection area of the first opening 002BK on the substrate 10. At this time, since the orthographic projection area of the second opening 001AK on the substrate 10 is larger than the orthographic projection area of the first opening 002BK on the substrate 10, in the non-transparent area NTA, after the second opening 001AK is opened, at least a portion of the surface of the first passivation layer 002B on the side away from the substrate 10 is exposed.

[0170] Next, film formation continues on the side of the first planarization layer 001A facing away from the substrate 10 until the second planarization layer 001B is formed. The second planarization layer 001B is then exposed and etched to form a third opening 001BK in the second planarization layer 001B. The third opening 001BK penetrates the thickness of the second planarization layer 001B, and the orthographic projection of the third opening 001BK on the substrate 10 overlaps the orthographic projection of the second opening 001AK on the substrate 10. The orthographic projection area of the third opening 001BK on the substrate 10 is larger than the orthographic projection area of the second opening 001AK on the substrate 10. Because the orthographic projection area of the third opening 001BK on the substrate 10 is larger than the orthographic projection area of the second opening 001AK on the substrate 10, a portion of the surface of the first passivation layer 002B facing away from the substrate 10 is still exposed in the non-transparent area NTA after the third opening 001BK is formed.

[0171] Finally, the second passivation layer 002C is formed and etched after the electrode layer 30 is formed and patterned, forming the fifth opening 002CK of the second passivation layer 002C and other through holes exposing part of the electrode group 301. The fifth opening 002CK penetrates the thickness of the second passivation layer 002C, and the orthographic projection of the fifth opening 002CK on the substrate 10 is located within the orthographic projection range of the second opening 001AK on the substrate 10. The orthographic projection area of the fifth opening 002CK on the substrate 10 is smaller than the orthographic projection area of the second opening 001AK on the substrate 10, and the orthographic projection of the fifth opening 002CK on the substrate 10 covers The orthographic projection area of the first opening 002BK on the substrate 10 and the orthographic projection area of the fifth opening 002CK on the substrate 10 are larger than the orthographic projection area of the first opening 002BK on the substrate 10, so that the second passivation layer 002C can be arranged in the non-transparent area NTA along the sidewalls of the third opening 001BK of the second planarization layer 001B and the sidewalls of the second opening 001AK of the first planarization layer 001A, and only covers the sidewalls of the opening of the organic layer 001 thereunder. At least a portion of the second passivation layer 002C is in direct contact with the surface of the first passivation layer 002B exposed away from the substrate 10 (e.g., Figure 25 The process is relatively simple (as shown in the dotted box JK). The step difference can be reduced when forming the second passivation layer 002C, avoiding thin film formation on both sides of the TAB in the non-edge transparent area, which may cause over-etching risks. This is beneficial to simplifying the process while improving the process yield and ensuring product performance.

[0172] In some alternative embodiments, please refer to Figure 19-Figure 25 、 Figure 26 , Figure 26 is another schematic diagram of the planar structure of the display panel provided in the embodiment of the present disclosure (it can be understood that for the sake of distinction, Figure 26 Different filling patterns are used to represent the edge transmission area TAA and the non-edge transmission area TAB, in order to clearly illustrate the structure of this embodiment. Figure 26 Transparency filling is performed), in this embodiment, in the first area J1, the plurality of first transmission areas TA1 include edge transmission areas TAA and non-edge transmission areas TAB;

[0173] In the second region J2, the plurality of second transmission areas TA2 include edge transmission areas TAA and non-edge transmission areas TAB;

[0174] In the third region J3, the plurality of third transmission areas TA3 include edge transmission areas TAA and non-edge transmission areas TAB;

[0175] Along a direction from one edge 000L of the display panel 000 to the other edge 000L opposite thereto, only one edge transmission area TAA is included between the edge 000L of the display panel 000 and the non-edge transmission area TAB.

[0176] This embodiment explains that the display panel 000 includes a first area J1, a second area J2, and a third area J3. When the shift register 202 is located in the second area J2, the transmission area TA provided in each of the first area J1, the second area J2, and the third area J3 includes an edge transmission area TAA and a non-edge transmission area TAB; and along a direction from one edge 000L of the display panel 000 to another edge 000L opposite thereto, taking the display panel 000 as a square with four edges, namely, a first edge 000L1, a second edge 000L2, a third edge 000L3, and a fourth edge 000L4 as an example, if along a direction (a first direction X) from the first edge 000L1 of the display panel 000 to the second edge 000L2 opposite thereto, there is only one edge transmission area TAA between the first edge 000L1 of the display panel 000 and the non-edge transmission area TAB, the display panel 000 There is only one edge transmission area TAA between the second edge 000L2 and the non-edge transmission area TAB; along the direction (second direction Y) from the third edge 000L3 of the display panel 000 to the fourth edge 000L4 opposite thereto, there is only one edge transmission area TAA between the third edge 000L3 of the display panel 000 and the non-edge transmission area TAB, and there is only one edge transmission area TAA between the fourth edge 000L4 of the display panel 000 and the non-edge transmission area TAB, that is, only one row of transmission areas TA or one column of transmission areas TA close to the edge 000L of the display panel 000 is the edge transmission area TAA, and the rest are non-edge transmission areas TAB. Although the organic layer 001 of only one row of transmission areas TA or one column of transmission areas TA close to the edge 000L of the display panel 000 is hollowed out in order to improve the edge transmittance, at least one inorganic layer 002 is retained (as mentioned above Figure 19 、 Figure 21 、 Figure 23 As shown in the embodiment, the denser structure of the inorganic layer 002 effectively blocks the intrusion of water vapor, thereby reducing the probability of water absorption by the organic layer 001 around a row of transmission areas TA or a column of transmission areas TA near the edge 000L of the display panel 000, thereby ensuring the display quality and service life of the display panel 000 and improving product yield and product reliability.

[0177] Optional, such as Figure 27 As shown, Figure 27 is another schematic diagram of the planar structure of the display panel provided in the embodiment of the present disclosure (it can be understood that for the sake of distinction, Figure 27 Different filling patterns are used to represent the edge transmission area TAA and the non-edge transmission area TAB, in order to clearly illustrate the structure of this embodiment. Figure 27Transparency filling is performed), in some other optional embodiments, along the direction (first direction X) from the first edge 000L1 of the display panel 000 to the second edge 000L2 opposite thereto, at least two edge transmission areas TAA may be included between the first edge 000L1 of the display panel 000 and the non-edge transmission area TAB, and at least two edge transmission areas TAA may be included between the second edge 000L2 of the display panel 000 and the non-edge transmission area TAB; along the direction (second direction Y) from the third edge 000L3 of the display panel 000 to the fourth edge 000L4 opposite thereto, the third edge 000L 3 and the non-edge transmission area TAB may include at least two edge transmission areas TAA, and the fourth edge 000L4 of the display panel 000 may include at least two edge transmission areas TAA between the non-edge transmission area TAB, that is, at least two rows of transmission areas TA or at least two columns of transmission areas TA near the edge 000L of the display panel 000 are edge transmission areas TAA, and the rest are non-edge transmission areas TAB. Although in order to improve the edge transmittance, at least two rows of transmission areas TA or at least two columns of transmission areas TA near the edge 000L of the display panel 000 are provided to hollow out the organic layer 001, at least one inorganic layer 002 is retained (as described above). Figure 19 、 Figure 21 、 Figure 23 As shown in the embodiment, there are more areas and a greater number of edge transmission areas TAA near the edge 000L of the display panel 000, retaining at least one inorganic layer. The denser structure of the inorganic layer 002 effectively blocks the intrusion of water vapor, and reduces the probability of water absorption by the organic layer 001 around at least two rows of transmission areas TA or at least two columns of transmission areas TA near the edge 000L of the display panel 000. This can further ensure the display quality and service life of the display panel 000, and is conducive to better improving product yield and product reliability.

[0178] It is understandable that if Figure 28 As shown, Figure 28 yes Figure 27 A schematic diagram of a planar arrangement structure of a transmission area in a display panel (it can be understood that, in order to facilitate distinction, Figure 28 In the figure, different filling patterns are used to represent the edge transmission area TAA and the non-edge transmission area TAB. In order to clearly illustrate the layout structure of the edge transmission area TAA and the non-edge transmission area TAB of this embodiment, Figure 28 Will Figure 27The structure of the display panel is simplified. The display panel 000 may include a first area J1, a first transition area JL1, a second area J2, a second transition area JL2, a third area J3, another second transition area JL2, another second area J2, another first transition area JL1, and another first area J1. As for the transmission area TA included in the entire display panel 000, at least two rows of transmission areas TA or at least two columns of transmission areas TA near the edge 000L of the display panel 000 are edge transmission areas TAA, and the rest are non-edge transmission areas TAB. By setting the transmission areas TA near the edge 000L of the display panel 000 L's at least two rows of transmission areas TA or at least two columns of transmission areas TA hollow out the organic layer 001, but retain at least one inorganic layer 002, so that there are more areas and a greater number of edge transmission areas TAA near the edge 000L of the display panel 000 to retain at least one inorganic layer. The relatively dense structure of the inorganic layer 002 effectively blocks the intrusion of water vapor, and reduces the probability of water absorption by the organic layer 001 around the at least two rows of transmission areas TA or at least two columns of transmission areas TA near the edge 000L of the display panel 000, which can further ensure the display quality and service life of the display panel 000, and is conducive to better improving product yield and product reliability.

[0179] In some alternative embodiments, please refer to Figure 19-Figure 25 、 Figure 29 and Figure 30 , Figure 29 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present disclosure, Figure 30 yes Figure 29 A schematic diagram of a planar arrangement structure of a transmission area in a display panel (it can be understood that, in order to facilitate distinction, Figure 29 and Figure 30 Different filling patterns are used to represent the edge transmission area TAA and the non-edge transmission area TAB, in order to clearly illustrate the structure of this embodiment. Figure 29 Transparency filling is performed), in this embodiment, the plurality of first transmission areas TA1 of the first area J1 are all edge transmission areas TAA;

[0180] In the second region J2, the plurality of second transmission areas TA2 include edge transmission areas TAA and non-edge transmission areas TAB;

[0181] In the third region J3, the plurality of third transmission areas TA3 include edge transmission areas TAA and non-edge transmission areas TAB;

[0182] In the second region J2 and the third region J3 , only one edge transmission region TAA is included between the edge 000L of the display panel 000 and the non-edge transmission region TAB.

[0183] This embodiment explains that the display panel 000 includes a first area J1, a second area J2, and a third area J3. When the shift register 202 is located in the second area J2, the transmission areas TA set in the first area J1 are all edge transmission areas TAA, and the transmission areas TA set in the second area J2 and the third area J3 respectively include edge transmission areas TAA and non-edge transmission areas TAB; and along the direction (second direction Y) pointing from the third edge 000L3 of the display panel 000 to the fourth edge 000L4 opposite thereto, there is only one edge transmission area TAA between the third edge 000L3 of the display panel 000 and the non-edge transmission area TAB, and there is only one edge transmission area TAA between the fourth edge 000L4 of the display panel 000 and the non-edge transmission area TAB, that is, the second area of the display panel 000 Only a row of transmission areas TA near the edge 000L in J2 and the third area J3 is an edge transmission area TAA, and the rest are non-edge transmission areas TAB. Although in order to improve the edge transmittance, the organic layer 001 and the inorganic layer 002 of the non-edge transmission area TAB in the display panel 000 need to be hollowed out, all the transmission areas TA in the first area J1 are set as edge transmission areas TA to retain at least one inorganic layer 002, and a row of transmission areas TA near the third edge 000L3 and the fourth edge 000L4 in the second area J2 and the third area J3 is an edge transmission area TA, and at least one inorganic layer 002 is also retained. This can further improve the reliability of each edge area of the display panel 000, thereby ensuring the display quality and service life of the display panel 000, and improving product yield and product reliability.

[0184] Optional, such as Figure 30 As shown, in order to clearly illustrate the layout structure of the edge transmission area TAA and the non-edge transmission area TAB of this embodiment, Figure 30 Will Figure 29The structure of the display panel is simplified. The display panel 000 may include a first area J1, a first transition area JL1, a second area J2, a second transition area JL2, a third area J3, another second transition area JL2, another second area J2, another first transition area JL1, and another first area J1. As for the transmission area TA included in the entire display panel 000, the transmission area TA of the first area J1 in the display panel 000 is an edge transmission area TAA. In the first transition area JL1, the second area J2, the second transition area JL2, and the third area J3, the direction along the third edge 000L3 of the display panel 000 points to the fourth edge 000L4 opposite thereto (the second direction Y). There is only one edge transmission area TAA between the third edge 000L3 of the display panel 000 and the non-edge transmission area TAB. , only one edge transmission area TAA is included between the fourth edge 000L4 of the display panel 000 and the non-edge transmission area TAB, that is, only a row of transmission areas TA near the edge 000L of the display panel 000 in the first transition area JL1, the second area J2, the second transition area JL2, and the third area J3 is the edge transmission area TAA, and the rest are non-edge transmission areas TAB, so that more areas and a larger number of edge transmission areas TAA near the first edge 000L1 and the second edge 000L2 of the display panel 000 retain at least one inorganic layer. The relatively dense structure of the inorganic layer 002 effectively blocks the intrusion of water vapor and reduces the probability of water absorption by the organic layer 001 around the edge transmission area TAA of the display panel 000, which can further ensure the display quality and service life of the display panel 000, and is conducive to better improving product yield and product reliability.

[0185] In some alternative embodiments, please refer to Figure 19-Figure 25 、 Figure 31 and Figure 32 , Figure 31 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present disclosure, Figure 32 yes Figure 31 A schematic diagram of a planar arrangement structure of a transmission area in a display panel (it can be understood that, in order to facilitate distinction, Figure 31 and Figure 32 Different filling patterns are used to represent the edge transmission area TAA and the non-edge transmission area TAB, in order to clearly illustrate the structure of this embodiment. Figure 31 Transparency filling is performed), in this embodiment, the plurality of first transmission areas TA1 of the first area J1 are all edge transmission areas TAA;

[0186] The plurality of second transmission areas TA2 of the second region J2 are all edge transmission areas TAA;

[0187] In the third region J3, the plurality of third transmission areas TA3 include edge transmission areas TAA and non-edge transmission areas TAB;

[0188] In the third region J3 , only one edge transmission region TAA is included between the edge 000L of the display panel 000 and the non-edge transmission region TAB.

[0189] This embodiment explains that the display panel 000 includes a first area J1, a second area J2, and a third area J3. When the shift register 202 is located in the second area J2, the transmission areas TA provided in the first area J1 and the second area J2 closer to the edges of the display panel 000 are both edge transmission areas TAA, and the transmission area TA provided in the third area J3 includes the edge transmission area TAA and the non-edge transmission area TAB. In addition, along the direction (second direction Y) pointing from the third edge 000L3 of the display panel 000 to the fourth edge 000L4 opposite thereto, there is only one edge transmission area TAA between the third edge 000L3 of the display panel 000 and the non-edge transmission area TAB, and there is only one edge transmission area TAA between the fourth edge 000L4 of the display panel 000 and the non-edge transmission area TAB, that is, only the edge transmission area TAA in the third area J3 of the display panel 000 is closer to the edge 000L3. A row of transmission areas TA in 00L is an edge transmission area TAA, and the rest are non-edge transmission areas TAB. Although in order to improve the edge transmittance, the organic layer 001 and the inorganic layer 002 of the non-edge transmission area TAB in the display panel 000 need to be hollowed out, all the transmission areas TA in the first zone J1 and the second zone J2 that are closer to the two side edges of the display panel 000 (the first edge 000L1 and the second edge 000L2) are set as edge transmission areas TA, and at least one inorganic layer 002 is retained. In the third zone J3, a row of transmission areas TA close to the third edge 000L3 and the fourth edge 000L4 is an edge transmission area TA, and at least one inorganic layer 002 is also retained. This can further improve the reliability of each edge area of the display panel 000, thereby ensuring the display quality and service life of the display panel 000, and improving product yield and product reliability.

[0190] Optional, such as Figure 32 As shown, in order to clearly illustrate the layout structure of the edge transmission area TAA and the non-edge transmission area TAB of this embodiment, Figure 32 Will Figure 31The structure of the display panel is simplified. The display panel 000 may include a first area J1, a first transition area JL1, a second area J2, a second transition area JL2, a third area J3, another second transition area JL2, another second area J2, another first transition area JL1, and another first area J1. As for the transmission area TA included in the entire display panel 000, the transmission areas TA of the first area J1, the first transition area JL1, the second area J2, and the second transition area JL2 in the display panel 000 are all edge transmission areas TAA. In the third area J3, the direction along the third edge 000L3 of the display panel 000 points to the fourth edge 000L4 opposite thereto (the second direction Y). There is only one edge transmission area TAA between the third edge 000L3 of the display panel 000 and the non-edge transmission area TAB. There is only one edge transmission area TAA between the four edges 000L4 and the non-edge transmission area TAB, that is, in the third area J3 of the display panel 000, only a row of transmission areas TA close to its edge 000L is the edge transmission area TAA, and the rest are non-edge transmission areas TAB, so that there are more areas and a larger number of edge transmission areas TAA near the first edge 000L1 and the second edge 000L2 of the display panel 000 to retain at least one inorganic layer, that is, the area retaining the inorganic layer 002 at the edge of the display panel 000 is increased, which can better improve the effect of isolating water vapor intrusion. Through the relatively dense structure of the inorganic layer 002, the intrusion of water vapor can be effectively blocked, and the probability of water absorption of the organic layer 001 around the edge transmission area TAA of the display panel 000 is reduced, which can further ensure the display quality and service life of the display panel 000, and is conducive to better improving product yield and product reliability.

[0191] Optional, such as Figure 33 As shown, Figure 33 is a schematic diagram of a planar arrangement structure of the transmission area in the display panel provided by the embodiment of the present disclosure (it can be understood that, for the sake of convenience, Figure 33 In the figure, different filling patterns are used to represent the edge transmission area TAA and the non-edge transmission area TAB. In order to clearly illustrate the layout structure of the edge transmission area TAA and the non-edge transmission area TAB of this embodiment, Figure 33The structure of the display panel is simplified, and only the transmission area TA of the display panel 000 is illustrated. The display panel 000 may include a first area J1, a first transition area JL1, a second area J2, a second transition area JL2, a third area J3, another second transition area JL2, another second area J2, another first transition area JL1, and another first area J1. As for the transmission area TA included in the entire display panel 000, the transmission areas TA of the first area J1, the first transition area JL1, the second area J2, and the second transition area JL2 in the display panel 000 are all edge transmission areas TAA. In the third area J3, the direction along the third edge 000L3 of the display panel 000 points to the fourth edge 000L4 opposite thereto (the second direction Y). At least two edge transmission areas TAA may be included between the third edge 000L3 of the display panel 000 and the non-edge transmission area TAB. The fourth edge 000L3 of the display panel 000 may be the same as the non-edge transmission area TAB. At least two edge transmission areas TAA may be included between 00L4 and the non-edge transmission area TAB, that is, at least two rows of transmission areas TA near the third edge 000L3 in the third area J3 of the display panel 000 are edge transmission areas TAA, and at least two rows of transmission areas TA near the fourth edge 000L4 in the third area J3 of the display panel 000 are edge transmission areas TAA, and the rest are non-edge transmission areas TAB, so that there are more areas and more numbers of edge transmission areas TAA near the first edge 000L1, the second edge 000L2, the third edge 000L3, and the fourth edge 000L4 of the display panel 000 to retain at least one inorganic layer. The relatively dense structure of the inorganic layer 002 can effectively block the intrusion of water vapor, reduce the probability of water absorption of the organic layer 001 around the edge transmission area TAA of the display panel 000, further improve the display quality of the display panel 000 in the third area J3, and help to better improve product yield and product reliability.

[0192] In some alternative embodiments, please refer to Figure 34 , Figure 34 1 is a schematic diagram of a planar structure of a display device provided in an embodiment of the present disclosure. The display device 111 provided in this embodiment includes the display panel 000 provided in the above embodiment of the present invention. Figure 34 This embodiment uses a mobile phone as an example to illustrate the display device 111. It is understood that the display device 111 provided in the embodiment of the present invention can be a computer, a television, an in-vehicle display device, or other display device 111 having a display function, and the present invention does not impose any specific limitations thereon. The display device 111 provided in the embodiment of the present invention has the beneficial effects of the display panel 000 provided in the embodiment of the present invention. For details, please refer to the detailed description of the display panel 000 in the above embodiments, and this embodiment will not be repeated here.

[0193] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0194] The foregoing description is intended only to provide specific embodiments of the present disclosure, intended to enable those skilled in the art to understand and implement the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the embodiments described herein, but rather to be construed in the broadest manner consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that: It includes a substrate and a driving layer located on one side of the substrate; The driving layer includes a pixel circuit and a shift register, and the shift register includes a plurality of cascaded shift register units; the shift register units are located in the display area of the display panel; Along a direction from one edge of the display panel to another edge opposite thereto, the display panel comprises at least a first area, a second area, and a third area, wherein the second area is located between the first area and the third area; The pixel circuit includes a first pixel circuit and a second pixel circuit, the first pixel circuit is located in the first area, the shift register is located in the second area, and the second pixel circuit is located in the third area.

2. The display panel according to claim 1, wherein: The display panel further includes a first transition area and a second transition area; the first transition area is located between the first area and the second area, and the second transition area is located between the second area and the third area; The driving layer of the first transition region is provided with a first connecting driving wire, and the shift register is electrically connected to the first pixel circuit via the first connecting driving wire; The driving layer in the second transition region is provided with a second connecting driving wire, and the shift register is electrically connected to the second pixel circuit via the second connecting driving wire.

3. The display panel according to claim 1, wherein: The display panel further includes an electrode layer, the electrode layer is located on a side of the driving layer away from the substrate, and the electrode layer includes a plurality of electrode groups; In the first area, along a first direction, three adjacent first pixel circuits form a first pixel circuit group, and the first pixel circuit group drives three adjacent electrode groups; wherein the first direction is the direction from the first area to the second area; In the third area, along the first direction, three adjacent second pixel circuits form a second pixel circuit group, and the second pixel circuit group drives three adjacent electrode groups; Along the first direction, a maximum width of the first pixel circuit group is smaller than a maximum width of the second pixel circuit group.

4. The display panel according to claim 3, wherein: The display panel includes a plurality of light emitting elements; The three electrode groups driven by the first pixel circuit group are electrically connected to the light-emitting elements of three different colors, and the three electrode groups driven by the second pixel circuit group are electrically connected to the light-emitting elements of three different colors.

5. The display panel according to claim 3, wherein: The layout density of the first pixel circuit group in the first area is greater than the layout density of the second pixel circuit group in the third area; Along the first direction, a distance between two adjacent first pixel circuit groups is D1, and a distance between two adjacent second pixel circuit groups is D2; wherein D1<D2.

6. The display panel according to claim 5, wherein: Along the second direction, the maximum height of the first pixel circuit group is H1, and the maximum height of the second pixel circuit group is H2; wherein H1=H2, and in a direction parallel to the plane of the substrate, the second direction intersects the first direction.

7. The display panel according to claim 3, wherein: Along the first direction, a distance between two adjacent first pixel circuits is D11, and a distance between two adjacent second pixel circuits is D22; wherein D11<D22.

8. The display panel according to claim 3, wherein: The shape of the orthographic projection of the first pixel circuit on the substrate is consistent with the shape of the orthographic projection of the second pixel circuit on the substrate.

9. The display panel according to claim 1, wherein: The plurality of shift registers include a first shift register and a second shift register, the first shift register includes a plurality of cascaded first shift register units, and the second shift register includes a plurality of cascaded second shift register units; The first shift register unit includes two light emitting control signal output terminals, and the two light emitting control signal output terminals are electrically connected to the first pixel circuit in the first area and the second pixel circuit in the third area respectively; The second shift register unit includes two scan control signal output terminals, and the two scan control signal output terminals are electrically connected to the first pixel circuit in the first area and the second pixel circuit in the third area, respectively.

10. The display panel according to claim 9, wherein: Along the first direction, the maximum width of the first shift register unit is W11, and along the second direction, the maximum height of the first shift register unit is H11; wherein, W11<H11, the first direction is the direction from the first region to the second region, and in the direction parallel to the plane of the substrate, the second direction intersects with the first direction.

11. The display panel according to claim 10, wherein: Along the first direction, a maximum width of the second shift register unit is W21, and along the second direction, a maximum height of the second shift register unit is H21; wherein W21>H21.

12. The display panel according to claim 1, wherein The display panel includes a plurality of transmission areas, wherein the plurality of transmission areas include a first transmission area, a second transmission area, and a third transmission area; The first transmission area is located in the first area, the second transmission area is located in the second area, and the third transmission area is located in the third area; The area of the first transmission region is smaller than that of the third transmission region.

13. The display panel according to claim 12, wherein: The shape of the second transmission area is different from that of the first transmission area, and the shape of the second transmission area is different from that of the third transmission area.

14. The display panel according to claim 12, wherein: The first transmission areas in the first region have the same shape, and the third transmission areas in the third region have the same shape; At least two of the second transmission areas in the second region have different shapes.

15. The display panel according to claim 12, wherein: The display panel further includes a first transition area and a second transition area; the first transition area is located between the first area and the second area, and the second transition area is located between the second area and the third area; The driving layer of the first transition region is provided with a first connecting driving wire, and the shift register is electrically connected to the first pixel circuit via the first connecting driving wire; The driving layer in the second transition region is provided with a second connecting driving wire, and the shift register is electrically connected to the second pixel circuit via the second connecting driving wire; The first transition zone includes a plurality of fourth transmission zones, and the second transition zone includes a plurality of fifth transmission zones; An edge of the fourth transmission area facing the second area is a straight line, and an edge of the fifth transmission area facing the second area is a straight line.

16. The display panel according to claim 15, wherein: The fourth transmission region has an area smaller than that of the first transmission region, and the fifth transmission region has an area smaller than that of the third transmission region.

17. The display panel according to claim 12, wherein: The display panel further includes an electrode layer, the electrode layer is located on a side of the driving layer away from the substrate, and the electrode layer includes a plurality of electrode groups; In the first area, along a first direction, three adjacent first pixel circuits form a first pixel circuit group, and the first pixel circuit group drives three adjacent electrode groups; wherein the first direction is the direction from the first area to the second area; In the first area, along the first direction, multiple first pixel circuit groups form a first pixel circuit group row, and multiple first transmission areas form a first transmission area row; along the second direction, the first pixel circuit group row is located between two adjacent first transmission area rows; wherein, in a direction parallel to the plane of the substrate, the second direction intersects with the first direction.

18. The display panel according to claim 17, wherein: In the third area, along the first direction, three adjacent second pixel circuits form a second pixel circuit group, and the second pixel circuit group drives three adjacent electrode groups; The four third transmission areas of the third region are arranged around one second pixel circuit group.

19. The display panel according to claim 12, wherein: The plurality of transmission areas include a plurality of edge transmission areas and a plurality of non-edge transmission areas, the non-edge transmission areas are not included between the edge transmission area and the edge of the display panel, and the non-edge transmission area is located on a side of the edge transmission area away from the edge of the display panel; The display panel includes a plurality of organic layers and a plurality of inorganic layers located on one side of the substrate; In the edge transmission area, the display panel does not include the organic layer, and the display panel includes at least one inorganic layer; In the non-edge transmission area, the display panel does not include the organic layer and the inorganic layer.

20. The display panel according to claim 19, wherein The organic layer is made of a material selected from photosensitive polyimide and acrylic resin, and the inorganic layer is made of a material selected from silicon nitride and silicon oxide.

21. The display panel according to claim 19, wherein The plurality of organic layers include a first planarization layer and a second planarization layer, and the plurality of inorganic layers include a plurality of interlayer insulating layers, a first passivation layer, and a second passivation layer; The area of the display panel other than the transmission area is a non-transmission area. In the non-transmission area, along a direction perpendicular to the plane where the substrate is located, the display panel includes the substrate, the plurality of interlayer insulating layers, the first passivation layer, the first planarization layer, the second planarization layer, and the second passivation layer; In the edge transmission area, along a direction perpendicular to the plane where the substrate is located, the display panel includes the substrate, and a plurality of the interlayer insulating layers, the first passivation layer, and the second passivation layer sequentially stacked on the substrate; In the non-edge-transmitting area, along a direction perpendicular to the plane of the substrate, the display panel includes a hollow portion, and the hollow portion penetrates the multiple interlayer insulating layers, the first passivation layer, the first planarization layer, the second planarization layer, and the second passivation layer on one side of the substrate.

22. The display panel according to claim 21, wherein: In the non-edge-transmitting area, the first passivation layer includes a first opening, the first opening penetrates the thickness of the first passivation layer; the first planarization layer includes a second opening, the second opening penetrates the thickness of the first planarization layer; the second planarization layer includes a third opening, the third opening penetrates the thickness of the second planarization layer; The orthographic projection of the third opening on the substrate covers the orthographic projection of the second opening on the substrate, and the orthographic projection of the second opening on the substrate covers the orthographic projection of the first opening on the substrate; The orthographic projection area of the third opening on the substrate is larger than the orthographic projection area of the second opening on the substrate, and the orthographic projection area of the second opening on the substrate is larger than the orthographic projection area of the first opening on the substrate; Outside the non-edge transparent area, at least part of the second passivation layer covers the side walls of the third opening of the second planarization layer and the side walls of the second opening of the first planarization layer, and at least part of the second passivation layer is in direct contact with the surface of the first passivation layer away from the substrate.

23. The display panel according to claim 21, wherein: In the non-edge-transmitting area, the first passivation layer includes a first opening, the first opening extends through the thickness of the first passivation layer; the first planarization layer includes a second opening, the second opening extends through the thickness of the first planarization layer; the second planarization layer includes a third opening, the third opening extends through the thickness of the second planarization layer; the interlayer insulating layer includes a fourth opening, the fourth opening extends through the thickness of the interlayer insulating layer; The orthographic projection of the third opening on the substrate covers the orthographic projection of the second opening on the substrate, the orthographic projection of the second opening on the substrate covers the orthographic projection of the first opening on the substrate, and the orthographic projection of the first opening on the substrate covers the orthographic projection of the fourth opening on the substrate; The orthographic projection area of the third opening on the substrate is larger than the orthographic projection area of the second opening on the substrate, the orthographic projection area of the second opening on the substrate is larger than the orthographic projection area of the first opening on the substrate, and the orthographic projection area of the first opening on the substrate is larger than the orthographic projection area of the fourth opening on the substrate; Outside the non-edge transparent area, at least part of the second passivation layer covers the side walls of the third opening of the second planarization layer, the side walls of the second opening of the first planarization layer, the side walls of the first opening of the first passivation layer, and the side walls of the fourth opening of the interlayer insulating layer, and at least part of the second passivation layer is in direct contact with the substrate.

24. The display panel according to claim 19, wherein: In the first area, the plurality of first transmission areas include the edge transmission area and the non-edge transmission area; In the second area, the plurality of second transmission areas include the edge transmission area and the non-edge transmission area; In the third area, the plurality of third transmission areas include the edge transmission area and the non-edge transmission area; Along a direction from one edge of the display panel to another edge opposite thereto, only one edge transmission area is included between the edge of the display panel and the non-edge transmission area.

25. The display panel according to claim 19, wherein The plurality of first transmission areas in the first region are all edge transmission areas; In the second area, the plurality of second transmission areas include the edge transmission area and the non-edge transmission area; In the third area, the plurality of third transmission areas include the edge transmission area and the non-edge transmission area; In the second area and the third area, only one edge transmission area is included between the edge of the display panel and the non-edge transmission area.

26. The display panel according to claim 19, wherein: The plurality of first transmission areas in the first region are all edge transmission areas; The plurality of second transparent areas in the second region are all the edge transparent areas; In the third area, the plurality of third transmission areas include the edge transmission area and the non-edge transmission area; In the third area, only one edge transmission area is included between the edge of the display panel and the non-edge transmission area.

27. A display device, characterized in that: A display panel comprising any one of claims 1-26.

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