Parallel capacitor type broadband single-pole double-throw switch circuit
By introducing parallel capacitors and distributed transistor layouts in single-pole double-throw switches, the problem of difficult to take into account both insertion loss and isolation in microwave communication systems is solved, and a broadband switching circuit with low loss and high isolation is realized.
Patent Information
- Application Number
- CN202510552205.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-29
- Publication Date
- 2025-08-08
AI Technical Summary
In microwave communication systems, existing single-pole double-throw switches are difficult to achieve low insertion loss and high isolation at the same time. Especially in signal transmission in high frequency bands, the signal loss is high, affecting the performance of the communication system.
The single-pole double-throw switch structure of parallel capacitors is adopted. By connecting capacitors at both ends of series transistors, combining distributed transistor layout and complementary control logic, the isolation and insertion loss of the switch are optimized.
In the 17-40GHz frequency band, the insertion loss is reduced to less than 2dB and the isolation is increased to more than 23dB. It is suitable for high-frequency signal switching in microwave communication systems, with low loss and broadband characteristics.
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Figure CN120454697A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of microwave integrated circuit technology, and specifically relates to a broadband single-pole double-throw switch circuit with a parallel capacitor. Specifically, the circuit utilizes a 100nm GaAs process and employs a series-parallel structure, with capacitors connected in parallel across the series transistors to improve the switch's insertion loss and isolation. Background Art
[0002] The RF single-pole double-throw (SPDT) switch is the core of the T / R assembly. Its isolation, insertion loss, power handling, and other indicators directly impact the performance of the entire transceiver system. With the rapid development of mobile communication technology, the requirements for miniaturization, high power handling, and broadband transmission and reception front-ends are increasing. However, the insertion loss and isolation of the switch are mutually constrained. Furthermore, parasitic parameters introduced by high power handling affect the insertion loss and isolation at the high frequency end. Therefore, achieving both high isolation and low insertion loss in broadband switches is difficult.
[0003] In 2018, Peng-I Mei et al. designed a single-pole, double-throw (SPDT) switch operating in the 15-35 GHz frequency range. This design employed a pure parallel structure and stacked field-effect transistors to improve power handling capability. The switch achieved insertion loss of less than 3 dB, isolation greater than 25 dB, and an input 1dB compression point of 26 dBm. See [P.-I. Mei et al., "Single-Pole Double-Throw Switch Using Stacked-FET Configuration at Millimeter Wave Frequencies," 2018 Asia-Pacific Microwave Conference (APMC), Kyoto, Japan, 2018, pp. 791-793, doi:10.23919 / APMC.2018.8617164.]
[0004] In 2021, Yi-Fan Tsao et al. designed a single-pole, double-throw switch operating in the 8-40 GHz frequency range using a series-parallel topology. The circuit exhibited insertion loss less than 3.2 dB, isolation greater than 27 dB, and an input 1dB compression point of 33 dBm. See [Y.-F. Tsao, Y. Wang, C.-M. Tsao, H.-J. Würfl and H.-T. Hsu, "An X-to Ka-band Single-Pole-Double-Throw Switch with Good Power Handling Capability," 2021 IEEE Asia-Pacific Microwave Conference (APMC), Brisbane, Australia, 2021, pp. 229-231, doi:10.1109 / APMC52720.2021.9661627.]
[0005] As can be seen, within the millimeter-wave frequency range, while wider continuous bandwidth can lead to higher data rates, it inevitably suffers from higher signal loss during propagation. To overcome this issue, phased arrays are currently widely used, integrating numerous transmitter and receiver modules into a single chip. Therefore, a miniaturized single-pole double-throw switch that maintains low insertion loss while improving isolation is needed for application in RF and millimeter-wave communication systems. Summary of the Invention
[0006] Technical problem: In order to solve the above problems, the present invention provides a parallel capacitor single-pole double-throw switch structure. The switch adopts a one-series and three-parallel structure. Specifically, capacitors are connected in parallel at both ends of the series transistor to improve the isolation of the switch while reducing the insertion loss of the switch.
[0007] Technical solution: To solve the above technical problems, the present invention proposes a parallel capacitor single-pole double-throw switch adopting the following technical solution:
[0008] The broadband single-pole double-throw switch circuit has two branches, branch one and branch two, and three ports, namely a first port, a second port, and a third port. The first port is connected to the second port via a first microstrip line and branch one, and the first port is connected to the third port via a first microstrip line and branch two. Branch two has the same structure as branch one.
[0009] The branch circuit is sequentially connected to the second microstrip line, the third microstrip line, the fifth microstrip line, the seventh microstrip line, and the ninth microstrip line; the second microstrip line and the third microstrip line are respectively connected to the drain and the source of the first transistor; one end of the fourth microstrip line is connected between the third microstrip line and the fifth microstrip line, and the other end of the fourth microstrip line is connected to the drain of the second transistor; one end of the sixth microstrip line is connected between the fifth microstrip line and the seventh microstrip line, and the other end of the sixth microstrip line is connected to the drain of the third transistor; one end of the eighth microstrip line is connected between the seventh microstrip line and the ninth microstrip line, and the other end of the eighth microstrip line is connected to the drain of the fourth transistor; one end of the ninth microstrip line is connected to the seventh microstrip line, and the other end is connected to the third port.
[0010] The gate of the first transistor is connected to a first DC bias through a first bias resistor; the gate of the second transistor is connected to a second DC bias through a second bias resistor; the gate of the third transistor is connected to a second DC bias through a third bias resistor; and the gate of the fourth transistor is connected to the second DC bias through a fourth bias resistor.
[0011] A first capacitor is further connected between the source and the drain of the first transistor.
[0012] In the second branch, the gate of the first transistor is connected to the second DC bias via the first bias resistor, the gate of the second transistor is connected to the first DC bias via the second bias resistor, the gate of the third transistor is connected to the first DC bias via the third bias resistor, and the gate of the fourth transistor is connected to the first DC bias via the fourth bias resistor; one end of the ninth microstrip line is connected to the seventh microstrip line, and the other end is connected to the third port.
[0013] Both branch one and branch two are used as conducting branches and isolating branches. When Vg1=0V and Vg2=-5V, branch one is a conducting branch and branch two is an isolating branch; when Vg1=-5V and Vg2=0V, branch one is an isolating branch and branch two is a conducting branch.
[0014] Beneficial effects:
[0015] 1) By introducing a shunt capacitor at the series transistor, the insertion loss of the broadband single-pole double-throw switch is reduced while the isolation of the switch is improved.
[0016] 2) The structure is simple, adopting a one-series and three-parallel structure; the circuit area is small, only 1mm×1mm.
[0017] 3) Suitable for situations where high-frequency signal switching is required in microwave communication systems, such as millimeter-wave phased array front-end applications. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Figure 1 It is a topological diagram of a parallel capacitor type broadband single-pole double-throw switch circuit of the present invention;
[0019] Figure 2 This is a diagram showing the isolation and insertion loss simulation results of a parallel capacitor-type broadband single-pole double-throw switch circuit according to the present invention;
[0020] Figure 3 It is a simulation result diagram of the power capacity of the parallel capacitor type broadband single-pole double-throw switch circuit of the present invention.
[0021] Figure 4 This is a diagram showing the power capacity simulation results of the switching circuit corresponding to these operating frequencies according to the present invention.
[0022] The figure shows: a first port Port1, a second port Port2, a third port Port3, a first microstrip line MLIN1, a second microstrip line MLIN2, a third microstrip line MLIN3, a fourth microstrip line MLIN4, a fifth microstrip line MLIN5, a sixth microstrip line MLIN6, a seventh microstrip line MLIN7, an eighth microstrip line MLIN8, and a ninth microstrip line MLIN9; a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a first DC bias V g1 , the second DC bias V g1 , first capacitor C1, first bias resistor R 1-1 , the second bias resistor R 1-2 , the third bias resistor R 1-3 , the fourth bias resistor R 1-4 . DETAILED DESCRIPTION
[0023] This invention proposes a broadband single-pole, double-throw (SPDT) switch circuit with parallel capacitors, comprising one RF input port and two RF output ports. The circuit consists of two symmetrically spaced branches, each of which includes a multi-stage microstrip line cascade structure and a transistor control unit. The input port is connected to the inputs of the two branches via a main microstrip line, while the outputs of the two branches are connected to the two output ports, respectively.
[0024] Each branch consists of a cascade of multiple transistors, with a DC bias voltage controlling the transistors' on and off states. Specifically, each branch uses four field-effect transistors, with the first-stage transistor connected in series with the main signal path, and the remaining three transistors connected in parallel at different nodes within the branch. The signal path is turned on and off by controlling the DC bias voltage on the gate of the first-stage transistor. The remaining transistors exhibit high impedance when reverse biased, enhancing isolation.
[0025] Connecting capacitors in parallel across the first-stage transistor can reduce the insertion loss of the switch circuit by lowering the on-state resistance of the series transistor when it is turned on, thereby adjusting the problem of the mutual restriction between the insertion loss and isolation of the switch.
[0026] The branches use a symmetrical mirror-image layout, coupled with complementary bias voltage control logic. When the control voltage of the series transistors in branch one is 0V and the control voltage of the series transistors in branch two is -5V, branch one conducts and the branches are isolated; vice versa.
[0027] This invention utilizes a distributed transistor layout and parallel capacitor topology to effectively reduce RF signal insertion loss and broaden the operating bandwidth. This circuit is suitable for microwave communication systems requiring high-frequency signal switching, offering advantages such as low insertion loss, high isolation, and a wide operating bandwidth.
[0028] The present invention will be further described below with reference to the accompanying drawings.
[0029] The figure shows: a first port Port1, a second port Port2, a third port Port3, a first microstrip line MLIN1, a second microstrip line MLIN2, a third microstrip line MLIN3, a fourth microstrip line MLIN4, a fifth microstrip line MLIN5, a sixth microstrip line MLIN6, a seventh microstrip line MLIN7, an eighth microstrip line MLIN8, and a ninth microstrip line MLIN9; a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a first DC bias V g1 , the second DC bias V g1 , first capacitor C1, first bias resistor R 1-1 , the second bias resistor R 1-2 , the third bias resistor R 1-3 , the fourth bias resistor R 1-4 .
[0030] like Figure 1 As shown, a broadband single-pole double-throw switch circuit with low insertion loss includes a first port Port1, a microstrip line MLIN1, a branch 1, a branch 2, a second port Port2 and a third port Port3;
[0031] The single-pole double-throw switch has three ports: a first port Port1, a second port Port2, and a third port Port3. The first port Port1 is connected to the second port Port2 via a first microstrip line MLIN1 and a branch 1. The first port Port1 is connected to the third port Port3 via a first microstrip line MLIN1 and a branch 2.
[0032] The branch 1 includes microstrip lines: a second microstrip line MLIN2, a third microstrip line MLIN3, a fourth microstrip line MLIN4, a fifth microstrip line MLIN5, a sixth microstrip line MLIN6, a seventh microstrip line MLIN7, an eighth microstrip line MLIN8, and a ninth microstrip line MLIN9; a first transistor Q1, a second transistor Q2, a third transistor Q3, and a fourth transistor Q4; a first bias resistor R1-1 , the second bias resistor R 1-2 , the third bias resistor R 1-3 , the fourth bias resistor R 1-4 ; first capacitor C1. Among them, one end of the second microstrip line MLIN2 is connected to the first microstrip line MLIN1, and the other end is connected to the drain of the first transistor Q1; one end of the third microstrip line MLIN3 is connected to the source of the first transistor Q1, and the other end is connected in series with the fifth microstrip line MLIN5, the seventh microstrip line MLIN7, and the ninth microstrip line MLIN9 to the second port Port2. The drain of the first transistor Q1 is connected to the second microstrip line MLIN2, the source is connected to the third microstrip line MLIN3, and the gate is connected to the first bias resistor R 1-1 To the first DC bias V g1 , the first capacitor C1 is connected in parallel to both ends of the first transistor Q1. One end of the fourth microstrip line MLIN4 is connected to the middle of the third microstrip line MLIN3 and the fifth microstrip line MLIN5, and the other end is connected to the drain of the second transistor Q2; the source of the second transistor Q2 is grounded, and the gate is connected to the ground through the second bias resistor R 1-2 After the second DC bias V g2 One end of the sixth microstrip line MLIN6 is connected to the middle of the fifth microstrip line MLIN5 and the seventh microstrip line MLIN7, and the other end is connected to the drain of the third transistor Q3; the source of the third transistor Q3 is grounded, and the gate is connected to the third bias resistor R 1-3 After the second DC bias V g2 One end of the eighth microstrip line MLIN8 is connected to the middle of the seventh microstrip line MLIN7 and the ninth microstrip line MLIN9, and the other end is connected to the drain of the fourth transistor Q4; the source of the fourth transistor Q4 is grounded, and the gate is connected to the fourth bias resistor R 1-4 After the second DC bias V g2 .
[0033] The structure of the branch 2 is the same as that of the branch 1 and is symmetrical with the branch 1 about the first microstrip line MLIN1. The difference is that the first transistor Q1 of the branch 2 is connected to the first bias resistor R 1-1 Connect to the second DC bias V g2 The second transistor Q2 is biased by the second bias resistor R 1-2 Connect to the first DC bias V g1 , the third transistor Q3 is connected to the third bias resistor R 1-3 Connect to the first DC bias V g1 , the fourth transistor Q4 is biased by the fourth bias resistor R 1-4 Connect to the first DC bias V g1 One end of the ninth microstrip line MLIN9 is connected to the seventh microstrip line MLIN7, and one end is connected to the third port Port3.
[0034] The branch 1 and branch 2 can be used as a conducting branch and an isolating branch. g1 =0V, V g2 =-5V, branch 1 is the conducting branch and branch 2 is the isolating branch; when V g1 =-5V, V g2 =0V, branch 1 is an isolation branch and branch 2 is a conducting branch.
[0035] Figure 2 This is the simulation result of the insertion loss and isolation of the switch circuit of the present invention applied in the 17-40GHz frequency band. g1 =0V, V g2 = -5V, branch one conducts and branch two is isolated. By connecting a capacitor in parallel across transistor Q1, the isolation branch is increased. At 17-40GHz, the switch has an insertion loss of less than 2dB and an isolation greater than 23dB. At 17-34GHz, the switch achieves isolation exceeding 30dB.
[0036] Figure 3 This graph shows the measured insertion loss and isolation of the switch circuit of the present invention applied in the 17-40 GHz frequency band. When the control voltages Vg1 = 0V and Vg2 = -5V, branch one conducts and branch two isolates. At 17-40 GHz, the measured insertion loss of the switch is less than 1.8dB, and the isolation is greater than 29.7dB.
[0037] In order to better demonstrate the effect of the ultra-wideband high-power single-pole double-throw switch circuit of the embodiment, this embodiment performs simulations on operating frequencies of 17 GHz, 25 GHz, 32 GHz, and 40 GHz. Figure 4 This is a diagram of the power capacity simulation results of the switching circuit corresponding to these operating frequencies applied in the present invention. It can be seen that at 17 GHz, 25 GHz and 32 GHz, the input 0.1 dB compression point is greater than 25 dBm, and the 0.1 dB compression point at 40 GHz is approximately 22 dBm.
[0038] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as within the scope of protection of the present invention.
Claims
1. A broadband single-pole double-throw switch circuit with parallel capacitors, characterized in that: The broadband single-pole double-throw switch circuit has two branches, branch one and branch two, and three ports, namely a first port (Port1), a second port (Port2), and a third port (Port3). The first port (Port1) is connected to the second port (Port2) via a first microstrip line (MLIN1) and branch one, and the first port (Port1) is connected to the third port (Port3) via a first microstrip line (MLIN1) and branch two. Branch two has the same structure as branch one.
2. The parallel capacitor type broadband single-pole double-throw switch circuit according to claim 1, characterized in that: The branch circuit 1 is sequentially connected to a second microstrip line (MLIN2), a third microstrip line (MLIN3), a fifth microstrip line (MLIN5), a seventh microstrip line (MLIN7), and a ninth microstrip line (MLIN9); the second microstrip line (MLIN2) and the third microstrip line (MLIN3) are respectively connected to the drain and source of the first transistor (Q1); one end of the fourth microstrip line (MLIN4) is connected between the third microstrip line (MLIN3) and the fifth microstrip line (MLIN5), and the other end of the fourth microstrip line (MLIN4) is connected to the drain of the second transistor (Q2); One end of the sixth microstrip line (MLIN6) is connected between the fifth microstrip line (MLIN5) and the seventh microstrip line (MLIN7), and the other end of the sixth microstrip line (MLIN6) is connected to the drain of the third transistor (Q3); one end of the eighth microstrip line (MLIN8) is connected between the seventh microstrip line (MLIN7) and the ninth microstrip line (MLIN9), and the other end of the eighth microstrip line (MLIN8) is connected to the drain of the fourth transistor (Q4); one end of the ninth microstrip line (MLIN9) is connected to the seventh microstrip line (MLIN7), and the other end is connected to the third port (Port3).
3. The parallel capacitor type broadband single-pole double-throw switch circuit according to claim 2, characterized in that: The gate of the first transistor (Q1) is connected to the first bias resistor (R 1-1 ) is connected to the first DC bias (V g1 ); The gate of the second transistor (Q2) is connected to the second bias resistor (R 1-2 ) is connected to the second DC bias (V g2 ); The gate of the third transistor (Q3) is connected to the gate of the third transistor (Q3) through the third bias resistor (R 1-3 ) is connected to the second DC bias (V g2 ); The gate of the fourth transistor (Q1) is connected to the gate of the fourth transistor (Q1) through the fourth bias resistor (R 1-4 ) is connected to the second DC bias (V g2 ).
4. The parallel capacitor type broadband single-pole double-throw switch circuit according to claim 3, characterized in that: A first capacitor (C1) is also connected between the source and the drain of the first transistor (Q1).
5. The parallel capacitor type broadband single-pole double-throw switch circuit according to claim 1, 2, 3 or 4, characterized in that: In the second branch, the gate of the first transistor (Q1) is connected to the first bias resistor (R 1-1 ) is connected to the second DC bias (V g2 ), the gate of the second transistor (Q2) is connected to the second bias resistor (R 1-2 ) is connected to the first DC bias (V g1 ), the gate of the third transistor (Q3) is connected to the third bias resistor (R 1-3 ) is connected to the first DC bias (V g1 ), the gate of the fourth transistor (Q4) is connected to the fourth bias resistor (R 1-4 ) is connected to the first DC bias (V g1 ); one end of the ninth microstrip line (MLIN9) is connected to the seventh microstrip line (MLIN7), and the other end is connected to the third port (Port3).
6. The parallel capacitor type broadband single-pole double-throw switch circuit according to claim 5, characterized in that: Both branch one and branch two are used as conducting branches and isolating branches. When Vg1=0V and Vg2=-5V, branch one is a conducting branch and branch two is an isolating branch; when Vg1=-5V and Vg2=0V, branch one is an isolating branch and branch two is a conducting branch.