Electronic device capable of facilitating transmission of control letter box and method thereof

Abstract

An electronic device and a method thereof capable of facilitating control box transmission are presented. An electronic device includes an interconnect controller including a physical layer circuit for signal transmission, a signal interface, a link controller coupled to the physical layer circuit through the signal interface, and a bypass path coupled to the link controller for controlling frame transmission. The link controller is configured to transmit data to the physical layer circuitry through the signal interface, and to transmit a control frame to the physical layer circuitry through a signal path including the bypass path to bypass at least one circuit stage of the link controller.

Description

Technical Field

[0001] The present disclosure relates to a circuit, a controller, and a method for frame transmission of an electronic device, and more particularly to a circuit, a controller, a method, and an electronic device for facilitating frame transmission of an interconnection protocol. Background Art

[0002] The Mobile Industry Processor Interface (MIPI) Alliance has developed interconnect protocol technologies, such as the MIPI M-PHY specification related to the physical layer and the MIPI UniPro specification related to the Unified Protocol (UniPro), for interconnecting chips from one chip within or affected by a mobile device to another, to achieve higher transmission speeds and low-power operation. On the other hand, the Joint Electron Device Engineering Council (JEDEC) has used the MIPI M-PHY and MIPI UniPro specifications to launch a high-performance non-volatile memory standard called Universal Flash Storage (UFS). The UFS standard achieves gigabit-level high-speed transmission and low-power operation, and provides the required functionality and scalability for advanced mobile systems (e.g., computing devices such as smartphones, tablets, multimedia devices, and wearable devices), promoting rapid industry adoption.

[0003] A system implemented according to the UFS standard or the UniPro specification includes a local host (e.g., a computing device or chip) and a remote device (e.g., a storage device or another chip). A bidirectional link is established between the host and the device, and the link can be configured with one or more lanes in either transmission direction. According to the UniPro specification (e.g., UniPro version 2.0), link-level flow control is adopted in the data link (DL) layer of the stacking protocol of the UniPro specification. Data link layer flow control ensures that the sender knows how much buffer space is available in the data link layer of the receiving end of the link. Using a credit-based flow control mechanism, the receiver transmits credit information (in the form of Acknowledgment and Flow Control (AFC) frames) to update the credit information maintained by the sender.

[0004] According to the UniPro specification, the data link layer's AFC frame acknowledges correctly received data frames and is used to exchange flow control information for the corresponding traffic class. The data link layer's Negative Acknowledgment Control (NAC) frame is transmitted when the receiver detects any errors in a frame, receives a data frame (also known as DL data) with an incorrect frame sequence number, or requires reverse link reinitialization.

[0005] In digital circuits, pipelining involves parallelizing operations to optimize resource utilization, thereby increasing overall throughput. The UniPro layer can be designed to operate efficiently as a pipelined hardware implementation. However, introducing pipelining to increase throughput can inadvertently increase the transmission latency of DL control frames, such as AFC or NAC frames. Given the impact of latency on bandwidth utilization and performance, it is desirable to reduce the latency of DL control frames. Attempting to address pipeline latency by reducing pipeline levels can lead to setup time violations, especially at high clock frequencies. Setup time violations involve a duration during which input data must remain stable before the clock trigger edge, and changes in data within this setup time window can result in data loss and metastability issues. Despite the advantages of pipeline architectures, reducing latency, particularly in terms of clock cycles, has proven to be a challenging task. Summary of the Invention

[0006] In the present disclosure, various techniques for facilitating the transmission of control frames for an interconnect protocol are provided and applicable to an electronic device capable of communicating with another electronic device according to the interconnect protocol.

[0007] Various embodiments of an electronic device configured to facilitate control frame transmission are presented. The electronic device includes an interconnect controller, the interconnect controller comprising: a physical layer circuit for signal transmission, a signal interface, a link controller coupled to the physical layer circuit via the signal interface, and a bypass path coupled to the link controller for control frame transmission. The link controller is configured to transmit data to the physical layer circuit via the signal interface, and to transmit control frames to the physical layer circuit via a signal path including the bypass path to bypass at least one circuit stage of the link controller.

[0008] Several embodiments of a method for facilitating control frame transmission in an electronic device are provided. The method includes the steps of: transmitting data from a link controller of the electronic device to a physical layer circuit of the electronic device via a signal interface; and transmitting a control frame from the link controller to the physical layer circuit via a signal path including a bypass path coupled to the link controller for control frame transmission to bypass at least one circuit stage of the link controller.

[0009] In some embodiments of the method or the electronic device, the link controller is configured to transmit the control frame directly to the physical layer circuit through the bypass path.

[0010] In some embodiments of the method or the electronic device, the link controller is configured to transmit the control frame directly from the pipeline circuit of the link controller to the physical layer circuit through the bypass path.

[0011] In some embodiments of the method or the electronic device, the link controller is configured to transmit the control frame directly from the pipeline circuit of the link controller to the physical layer circuit through the bypass path to bypass at least one circuit stage between the pipeline circuit of the link controller and the physical layer circuit.

[0012] In some embodiments of the method or the electronic device, the link controller is configured to transmit the control frame directly from a data link layer of the link controller to the physical layer circuit through the bypass path.

[0013] In some embodiments of the method or the electronic device, the link controller is configured to transmit the control frame directly to the physical layer circuit through the bypass path to bypass a physical adapter layer of the link controller.

[0014] In some embodiments of the method or the electronic device, the link controller is configured to directly transmit the control frame to the physical layer circuit via the bypass path, and the physical layer circuit is configured to, in response to the control frame, transmit a control information signal based on the control frame and suspend signal transmission based on data received through the signal interface.

[0015] In some embodiments of the method or the electronic device, the physical layer circuit is configured to transmit the control information signal based on the control frame and suspend signal transmission based on data received through the signal interface in response to a control signal associated with the control frame and received through the bypass path.

[0016] In some embodiments of the method or the electronic device, the physical layer circuit is configured to continue transmitting the signal based on data received through the signal interface after transmitting the control information signal based on the control frame.

[0017] In some embodiments of the method or the electronic device, the control information signal includes information based on the control frame and information based on a control symbol of a continuation of preempted frame (COF).

[0018] In some embodiments of the method or the electronic device, the bypass path is coupled between a circuit stage of the link controller and the signal interface.

[0019] In some embodiments of the method or the electronic device, the link controller is configured to transmit the control frame from the pipeline circuit of the link controller to the physical layer circuit through the signal path including the bypass path and the signal interface.

[0020] In some embodiments of the method or the electronic device, the link controller is configured to transmit the control frame from the pipeline circuit of the link controller to the physical layer circuit via the signal path including the bypass path and the signal interface to bypass at least one circuit stage between the pipeline circuit of the link controller and the signal interface.

[0021] In some embodiments of the method or the electronic device, the bypass path is connected between a data link layer of the link controller and an interface module of a physical adapter layer of the link controller, and the interface module is connected to the signal interface.

[0022] In some embodiments of the method or the electronic device, the link controller is configured to transmit the control frame from a data link layer of the link controller to the physical layer circuit through the signal path including the bypass path and the signal interface.

[0023] In some embodiments of the method or the electronic device, the link controller is configured to transmit the control frame to the physical layer circuit through the signal path including the bypass path and the signal interface to bypass a physical adapter layer entity of a physical adapter layer of the link controller.

[0024] In some embodiments of the method or the electronic device, the control frame is an acknowledgment and flow control (AFC) frame or a negative acknowledgment control (NAC) frame based on UniPro.

[0025] Therefore, the above embodiments can facilitate control frame transmission, thereby reducing delay in control frame transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A block diagram illustrating one embodiment of a communication system capable of communicating according to an interconnection protocol.

[0027] Figure 2 A block diagram illustrating one embodiment of a device including an interconnect controller including a link controller and physical layer circuitry is shown.

[0028] Figure 3 A block diagram is shown of another embodiment of a device including an interconnection controller comprising a link controller and a physical layer circuit.

[0029] Figure 4 To display based on Figure 2 Schematic diagram of one embodiment of a pipeline-based architecture of an interconnect controller.

[0030] Figure 5A FIG. 1 is a diagram showing an example of frame transmission using a bypass path for AFC frame transmission.

[0031] Figure 5B FIG. 1 is a diagram showing an example of frame transmission without using a bypass path for AFC frame transmission.

[0032] Figure 6A FIG. 1 is a diagram showing an example of frame transmission using a bypass path for NAC frame transmission.

[0033] Figure 6B FIG. 1 is a diagram showing an example of frame transmission in which a bypass path is not used for NAC frame transmission.

[0034] Figure 7 To illustrate the bypass path between the link controller and the physical layer circuit, Figure 2 A block diagram of an embodiment of a device.

[0035] Figure 8 A flow chart illustrating one embodiment of a method for facilitating transmission of a control frame.

[0036] Figure 9 A flow chart illustrating one embodiment of a method for facilitating transmission of a control frame.

[0037] Figure 10A To show the bypass path involved based on Figure 2 A block diagram of an embodiment of a circuit.

[0038] Figure 10B To illustrate the bypass path between the link controller and the physical layer circuit, Figure 2 A block diagram of an embodiment of a circuit.

[0039] Figure 11A The figure shows the circuit architecture of a storage system for an interconnection protocol according to an embodiment of the present disclosure.

[0040] Figure 11B To illustrate the application of an embodiment of the present disclosure Figure 11A Block diagram of the circuit architecture of the controller for the interconnection protocol in .

[0041] Figure 11C To illustrate the application of an embodiment of the present disclosure Figure 11A Block diagram of the circuit architecture of the controller for the interconnection protocol in .

[0042] Figure 12 yes Figure 11A A schematic diagram of an embodiment of a layered structure of a storage system according to an interconnection protocol.

[0043] Figure 13 FIG. 1 is a schematic diagram of an example of an AFC letterbox structure.

[0044] Figure 14 FIG. 4 is a schematic diagram showing an example of a NAC frame structure.

[0045] Figure 15 is a schematic diagram of an embodiment of a data frame preempted by a control frame via a bypass path.

[0046] Reference numerals

[0047] 10 First Device

[0048] 11 Interconnection Controller

[0049] 11A~11E, 21D interconnection controller

[0050] 20 Second device

[0051] 21 Interconnection Controller

[0052] 101, 201 physical layer circuits

[0053] 101A~101E physical layer circuit

[0054] 101E-01 Data Controller

[0055] 101E-03 Transmission Module

[0056] 101E-05 Control frame receiving unit

[0057] 105, 205 link controller

[0058] 105A~105E link controller

[0059] 110, 210 physical adapter (PA) layer

[0060] 110A~110E physical adapter (PA) layer circuit

[0061] 111B interface (INF) module

[0062] 113B Physical Adapter (PA) layer processing unit

[0063] 120, 220 Data Link (DL) layer

[0064] 120A to 120E data link (DL) layer circuits

[0065] 121E Data Link (DL) Transmitter (TX)

[0066] 123E Data Link (DL) Receiver (RX)

[0067] 125E Control Frame Transmission Unit

[0068] 201D physical layer circuit

[0069] 600 Data Link (DL) Receiver (RX)

[0070] 710 Credit Processing Unit

[0071] 720 Answer and Flow Control (AFC) request timer

[0072] 730 Flow Control (FC) Protection Timer

[0073] 740 Retransmission Timer

[0074] 800 Control Frame Transmission Unit

[0075] 810 Control frame generator

[0076] 910 Data Controller

[0077] 911 control unit

[0078] 913 Data Selector

[0079] 930 Transmission Module

[0080] 950 Control frame receiving unit

[0081] 1000 Storage System

[0082] 1010 host

[0083] 1011 Host Interface

[0084] 1012 Host Controller

[0085] 1013 Hardware Protocol Engine

[0086] 1014 processing units

[0087] 1016 Application Processor

[0088] 1020 Storage Devices

[0089] 1021 device interface

[0090] 1022 Device Controller

[0091] 1023 Hardware Protocol Engine

[0092] 1024 processing units

[0093] 1026 storage modules

[0094] 1110, 1210 physical layer

[0095] 1111, 1211 transmitters

[0096] 1112, 1212 receivers

[0097] 1130, 1230 Unified Protocol (UniPro) layer

[0098] 1131, 1231 physical adapter (PA) layer

[0099] 1132, 1232 data link (DL) layer

[0100] 1133, 1233 network layer

[0101] 1134, 1234 transport layer

[0102] 1135, 1235 Device Management Entity (DME)

[0103] AFC response and flow control frame

[0104] BP1, BP2 bypass paths

[0105] BPA, BPB, BPC, BPE bypass paths

[0106] CN circuit connection

[0107] COF Continuation of Occupied Frame

[0108] CS circuit level

[0109] M1A, M1B circuit modules

[0110] M2A, M2B circuit modules

[0111] NAC negative acknowledgement control frame

[0112] PC1, PC2 protocol controller

[0113] PS Pause signal

[0114] REG register

[0115] RX1 Local Receiver (RX)

[0116] RX2 Remote Receiver (RX)

[0117] Steps S10 to S20

[0118] Steps S210 to S260

[0119] SF1, SF2 signal interface

[0120] SL1, SL2 data paths

[0121] TA, TB, TE bus

[0122] TX1 Local Transmitter (TX)

[0123] TX2 Remote Transmitter (TX)

[0124] RST reset line

[0125] CLK clock line

[0126] Din data cable

[0127] Dout data cable DETAILED DESCRIPTION

[0128] In order to fully understand the purpose, features and effects of the present disclosure, the present disclosure is described in detail with reference to the following specific embodiments and the accompanying drawings.

[0129] The present disclosure provides various techniques for facilitating control frame transmission, applicable to an electronic device capable of communicating with another electronic device according to an interconnect protocol. An embodiment of a method for facilitating control frame transmission is provided. This technique enables more efficient and effective control frame transmission by utilizing a signal path to bypass at least one circuit stage of a link controller, thereby reducing control frame transmission latency and enhancing performance.

[0130] Figure 1 Schematic diagram showing an embodiment of a communication system capable of communicating according to an interconnection protocol. Where appropriate, the interconnection protocol may be based on the UniPro specification, the UFS system, or other related communication protocols or specifications. For example, the communication system includes a first device 10 and a second device 20, which may be a local host and a remote device, respectively, or vice versa. Figure 1 In the embodiment, first device 10 includes physical layer circuitry 101 for signal transmission and a link controller 105, which can be implemented as interconnection controller 11. Similarly, second device 20 includes physical layer circuitry 201 for signal transmission and a link controller 205, which can be implemented as interconnection controller 21. Link controller 105 of first device 10, for example, implements the protocol layer (or "link layer," for example, in relation to the physical layer of M-PHY) of an interconnection protocol, such as a modified UniPro layer including a physical adapter (PA) layer 110 and a data link layer (DL) 120. Similarly, link controller 205 of second device 20, for example, also implements the protocol layer (or "link layer"), such as a modified UniPro layer including a physical adapter (PA) layer 210 and a data link layer (DL) 220. First device 10 can communicate with second device 20 via a link according to the interconnection protocol. The link includes at least one bidirectional data channel SL1 and at least one bidirectional data channel SL2. For example, the interconnect protocol is applicable to a variety of devices (e.g., with respect to the first device or the second device), such as application processors, coprocessors, modems, storage subsystems including non-volatile memory modules, displays, camera sensors, 3D graphics and multimedia accelerators, chips, etc. It is also applicable to different types of data traffic, such as control information, bulk data transmission, and packetized streams. Where appropriate, other relevant MIPI Alliance specifications or other relevant specifications can also be used for physical layer or application layer implementation.

[0131] like Figure 1As shown, the first device 10 (or second device 20) also includes a signal interface SF1 (or SF2) and a bypass path BP1 (or BP2). The link controller 105 (or 205) is coupled to the physical layer circuit 101 (or 201) via the signal interface SF1 (or SF2). The bypass path BP1 (or BP2) is coupled to the link controller 105 (or 205) for controlling frame transmission. The link controller 105 (or 205) is configured to transmit data such as PA frames to the physical layer circuit 101 (or 201) via the signal interface SF1 (or SF2), and to transmit control frames (or 201) to the physical layer circuit 101 (or 201) via a signal path including the bypass path BP1 (or BP2). Transmitting the control frame from the DL layer 120 (or 220) to the physical layer circuit 101 (or 201) via the signal path including the bypass path BP1 (or BP2) can bypass one or more circuit stages of the link controller 105 (or 205), such as the circuit stage of the PA layer 110 (or 210), thereby speeding up the control frame transmission speed and reducing the control frame transmission delay. In addition, as Figure 1 The circuit architecture or related adjustments of the interconnect controller with bypass paths shown can be referred to as a "cross layer" architecture.

[0132] For example, the signal interface SF1 (or SF2) can be implemented as an interface module and interface bus based on the reference M-PHY module interface (RMMI) of the M-PHY specification (e.g., version 5.0) or other interfaces, as long as the PA layer 110 (or 210) and the physical layer circuit 101 (or 201) both adopt this interface and communicate consistently through this interface.

[0133] For example, the bypass path BP1 (or BP2) can be implemented as a circuit module and a bus, as long as the PA layer 110 (or 210) and the physical layer circuit 101 (or 201) consistently adopt such a path for control frame transmission.

[0134] In some embodiments, the control frame can be an Acknowledgement and Flow Control (AFC) frame or a Negative Acknowledgement Control (NAC) frame based on the Unified Protocol (UniPro) (eg, version 2.0).

[0135] Based on Figure 1In some embodiments, the interconnect controller 11 (or 21) of the first device 10 (or the second device 20) can be configured to activate (enable) or deactivate (disable) the bypass path. When the bypass path is activated, the link controller 105 (or 205) can transmit a control frame from its data link layer 120 (or 220) to its physical layer circuit 101 (or 201) via a signal path including the bypass path BP1 (or BP2). When the bypass path is deactivated, the link controller 105 (or 205) can transmit a control frame to the physical layer circuit 101 (or 201) via the PA layer 110 (or 210) and the signal interface SF1 (or SF2).

[0136] Various embodiments for facilitating control frame transmission in an interconnect protocol are provided below, which speed up control frame transmission through a bypass path.

[0137] Figure 2 A block diagram showing one embodiment of a device including an interconnect controller including a link controller and a physical layer circuit is shown. Figure 2 In FIG. 1 , an interconnection controller 11A with a bypass path BPA is shown, providing an architecture of a hardware implementation of the interconnection controller, which can be viewed as Figure 1 An embodiment of the interconnection controller 11 in FIG. 2 may be applied to implement the interconnection controller 21. The interconnection controller 11A includes a link controller 105A for implementing the protocol layer (or "link layer") and a physical layer circuit 101A for signal transmission. The link controller 105A includes, for example, a physical adapter (PA) layer circuit 110A and a data link (DL) layer circuit 120A. In particular, a bypass path BPA is connected between the circuit level of the link controller 105A and the physical layer circuit 101A. For example, the bypass path BPA includes a circuit module M1A in the DL layer circuit 120A, a bus TA including one or more lines or traces, and a circuit module M2A in the physical layer circuit 101A. The circuit module M1A is used to transmit control frames to the circuit module M2A in the physical layer circuit 101A.

[0138] By using Figure 2 In the illustrated architecture, the link controller 105A can be configured to transmit control frames directly from the data link layer circuit 120A of the link controller 105A to the physical layer circuit 101A using the bypass path BPA as a signal path to bypass at least one circuit stage of the link controller 105A.

[0139] exist Figure 2 In FIG. 1 , the link controller 105A is configured to transmit the control frame directly to the physical layer circuit 101A via the bypass path BPA to bypass the physical adapter layer circuit 110A of the link controller 105A.

[0140] Based on Figure 2 In some embodiments, the link controller 105A is configured to transmit a control frame directly to the physical layer circuit 101A through the bypass path BPA, and the physical layer circuit 101A is configured to respond to the control frame by transmitting a control information signal based on the control frame and suspending signal transmission based on data received through the signal interface SF1.

[0141] Based on Figure 2 In some embodiments, the physical layer circuit 101A can be configured to transmit a control information signal based on the control frame and suspend transmission of a signal based on data received via the signal interface SF1 in response to a control signal associated with the control frame received via the bypass path BPA. For example, the circuit module M1A transmits a control signal associated with the control frame to the circuit module M2A. In response to the control signal and the control frame, the circuit module M2A transmits a signal requesting the physical layer circuit 101A to transmit a control information signal based on the control frame and suspend transmission of a signal based on data received via the signal interface SF1.

[0142] Based on Figure 2 In some embodiments, the physical layer circuit 101A is configured to continue transmitting a signal based on data received through the signal interface SF1 after transmitting the control information signal based on the control frame.

[0143] Based on Figure 2 In some embodiments, the control information signal includes information based on a control frame and information based on a continuation of preempted frame (COF) control symbol. For example, the COF control symbol can be a control symbol indicating a continuation of a preempted frame (e.g., a DL layer data frame) according to the UniPro specification (e.g., version 2.0). Figure 2In the example, the circuit module M1A transmits a control frame (e.g., an AFC or NAC frame) and a COF control symbol to the circuit module M2A. In response to the control frame and the COF control symbol, the circuit module M2A transmits a signal to request the physical layer circuit 101A to transmit a control information signal containing information based on the control frame and information based on the COF control symbol. Compared to the preemption of DL layer data frames and the transmission of associated data and control symbols to the PA layer as described in the conventional UniPro specification (e.g., version 2.0) performed in the DL layer, this embodiment accelerates the transmission of control frames by transmitting the control frames and COF control symbols through a bypass path BPA to bypass the PA layer circuit 110A, and suspending the signal transmission of the data received by the physical layer circuit 101A from the PA layer circuit 110A in the physical layer circuit 101A. In the embodiment based on Figure 2 In another example, the circuit module M1A transmits a control frame (e.g., an AFC or NAC frame) and the circuit module M2A can be configured to receive the control frame and generate a COF control symbol, and then output the control frame and the COF control symbol to the circuit level of the physical layer circuit 101A for signal transmission.

[0144] Figure 3 A block diagram showing another embodiment of a device including an interconnection controller comprising a link controller and a physical layer circuit. Figure 3 In FIG. 1 , the interconnection controller 11B is shown as having a bypass path BPB, which provides another architecture for the hardware implementation of the interconnection controller, which can be regarded as Figure 1 The embodiment of the interconnection controller 11 in the embodiment may be applied to realize Figure 1 The interconnection controller 21 in FIG. The interconnection controller 11B includes a link controller 105B for implementing the protocol layer (or "link layer") and a physical layer circuit 101B for signal transmission. Link controller 105B includes, for example, a physical adapter (PA) layer circuit 110B and a data link (DL) layer circuit 120B. In particular, a bypass path BPB is coupled between the circuit level of link controller 105B and signal interface SF1. For example, bypass path BPB includes circuit module M1B in DL layer circuit 120B, a bus TB comprising one or more lines or traces, and circuit module M2B in PA layer circuit 110B. Circuit module M1B is used to transmit control frames to circuit module M2B in PA layer circuit 110B.

[0145] Based on Figure 3 In some embodiments, the link controller 105B is configured to transmit the control frame from the DL layer circuit 120B (eg, the pipeline circuit of the link controller 105B) to the physical layer circuit 101B via a signal path including a bypass path BPB and a signal interface SF1.

[0146] Based on Figure 3 In some embodiments, the link controller 105B is configured to transmit a control frame from the DL layer circuit 120B (e.g., the pipeline circuit of the link controller 105B) to the physical layer circuit 101B via a signal path including a bypass path BPB and the signal interface SF1 to bypass one or more circuit stages between the DL layer circuit 120B (e.g., the pipeline circuit of the link controller 105B) and the signal interface SF1.

[0147] In some based Figure 3 In the embodiment of the present invention, the bypass path BPB is connected between the data link layer circuit 120B of the link controller 105B and the interface (INF) module 111B of the physical adapter layer 110B of the link controller 105B. The interface module 111B is connected to the signal interface SF1 and provides signals in accordance with the signal interface SF1 to output data connected to the physical adapter (PA) layer processing unit 113B of the interface (INF) module 111B.

[0148] Based on Figure 3 In some embodiments, the link controller 105B is configured to transmit the control frame from the data link layer circuit 120B of the link controller 105B to the physical layer circuit 101B via a signal path including a bypass path BPB and a signal interface SF1.

[0149] Based on Figure 3 In some embodiments, the link controller 105B is configured to transmit a control frame to the physical layer circuit 101B via a signal path including a bypass path BPB and a signal interface SF1, thereby bypassing the physical adapter layer processing unit 113B of the adapter layer circuit 110B of the link controller 105B. The physical adapter layer processing unit 113B is configured to receive input data (e.g., DL frames) from the DL layer circuit 120B and output output data (e.g., PA frames) to the physical layer circuit 101B based on the input data.

[0150] Based on Figure 3In some embodiments, the PA layer circuit 110B can be configured to, in response to a control signal associated with a control frame received via the bypass path BPB, first transmit the control frame received from the bypass path BPB to the physical layer circuit 101B and suspend the transmission of other data received from the DL layer circuit 120B via a circuit connection (e.g., represented by CN, such as a register or buffer connection between two pipeline circuits). For example, circuit module M1B transmits a control signal associated with the control frame to circuit module M2B. In response to the control signal and the control frame, circuit module M2B transmits a signal requesting interface module 111B of the PA layer circuit 110B to transmit the control frame received from the bypass path BPB to the physical layer circuit 101B via signal interface SF1. In response, interface module 111B transmits the control frame and suspends data transmission based on data received via the circuit connection CN between the PA layer circuit 110B and the DL layer circuit 120B.

[0151] Based on Figure 3 In some embodiments, the PA layer circuit 110B can be configured to continue data transmission based on data received through the circuit connection CN after transmitting the control frame to the physical layer circuit 101B.

[0152] Based on Figure 3 In some embodiments, the control frame and an associated control symbol of a continuation of a preempted frame (COF) are transmitted to a physical layer circuit.

[0153] Figure 4 To display based on Figure 2 A schematic diagram of an embodiment of a pipeline architecture of an interconnected controller. Figure 4 As shown, the display is based on Figure 2 The interconnection controller 11C has a bypass path BPC, thereby providing a hardware-implemented pipeline-based architecture of the interconnection controller, which can be viewed as Figure 1 An embodiment of the interconnection controller 11 in, or can be applied to Figure 1 The interconnection controller 21 in FIG. The interconnection controller 11C includes a link controller 105C for implementing the protocol layer (or "link layer") and a physical layer circuit 101C for signal transmission. The link controller 105C includes, for example, a physical adapter (PA) layer circuit 110C and a data link (DL) layer circuit 120C. Specifically, the link controller 105C is configured to transmit control frames directly from the DL layer circuit 120C of the link controller 105C to the physical layer circuit 101C via a bypass path (BPC). Figure 4The physical layer circuit 101C, the physical adapter (PA) layer circuit 110C, and the data link (DL) layer circuit 120C are each pipeline-based circuits. Each pipeline-based circuit includes a plurality of circuit stages (CS) and a plurality of registers (REGs) involved in processing of each layer (e.g., the physical layer, the PA layer, or the DL layer). In particular, Figure 4 In the embodiment, the link controller 105C is configured to transmit control frames such as AFC or NAC frames directly from the DL layer circuit 120C to the physical layer circuit 101C through the bypass path BPC to bypass multiple circuit stages between the DL layer circuit 120C and the physical layer circuit 101C (including the registers between the circuit stages). Specifically, for example, whenever a control frame such as an AFC or NAC frame is generated, the DL layer circuit 120C can immediately transmit the AFC or NAC frame together with the COF control symbol to a circuit module of the physical layer circuit 101C, such as a circuit module configured to receive the frame control and coupled between the encoder and the register of the physical layer circuit 101C. In this way, pipeline delays of several clocks can be saved for the control frame, and the control frame (whenever generated) can be transmitted to the physical layer circuit for signal transmission faster and earlier. Figure 4 Compared to the embodiments of the present invention, the method of reducing pipeline delay by reducing pipeline stages or increasing clock frequency may cause setup time violations and is difficult to implement.

[0154] In addition, based on Figure 3 Embodiments of the pipeline architecture of the interconnect controller can be derived to bypass at least one or more circuit stages of the PA layer circuit 110C.

[0155] According to the UniPro specification (e.g., version 2.0), some AFC frame transmission conditions are used below as examples of triggering the transmission of an AFC frame with the Credit Transmission Request (CReq) bit set to "0", where the AFC frame can be generated for a specific traffic class (e.g., Traffic Class 0 (TC0) or Traffic Class 1 (TC1)). When one of the above conditions is met, the DL layer transmits the AFC frame. The AFC frame transmission will inevitably affect the following: Figure 1 The overall performance of the communication system is shown.

[0156] In one example of the AFC frame transmission condition, the AFC frame is transmitted after the NAC frame is received.

[0157] In one example of an AFC frame transmission condition, before transmitting the NAC frame, if the NAC frame is not triggered by the expiration of the flow control protection timer for traffic class x (e.g., FCx_PROTECTION_TIMER in the UniPro specification) or the retransmission timer for traffic class x (e.g., TCx_REPLAY_TIMER in the UniPro specification), then the AFC frame is transmitted. In this example, the DL layer needs to be able to receive the AFC frame before the NAC frame.

[0158] In one example of the AFC frame transmission condition, the AFC frame is transmitted after the TCx_REPLAY_TIMER expires.

[0159] In one example of an AFC frame transmission condition, the AFC frame is transmitted after the AFC request timer for traffic class x (denoted as AFCx_REQUEST_TIMER in the UniPro specification) expires.

[0160] In one example of the AFC frame transmission condition, when the difference between the currently received frame sequence number requiring an acknowledgement (currentTCxFrSeqNum) and the last acknowledged frame sequence number (lastAFCxFrSeqNum) exceeds the DL_TCxOutAckThreshold, the AFC frame is transmitted.

[0161] In one example of the AFC frame transmission condition, after receiving a retransmitted data frame, the AFC frame is transmitted when the frame sequence number of the retransmitted data frame is equal to the frame sequence number of the last acknowledged frame.

[0162] In one example of an AFC frame transmission condition, the AFC frame is transmitted when the difference between available credit (A credit accumulator) and transmitted credit (S credit register) exceeds a DL_AFCxCreditThreshold threshold.

[0163] In one example of an AFC frame transmission condition, the AFC frame is transmitted after receiving an AFCx frame with the CReq bit set to 1. Even when DL_PeerTCxPresent is FALSE, the response to this condition requires the transmission of AFCx with a higher priority.

[0164] In one example of an AFC frame transmission condition, the AFC frame is transmitted after receiving PA_DL_PAUSE.ind while AFCx_REQUEST_TIMER is running. The response to this situation requires the transmission of AFCx with a higher priority.

[0165] in addition, Figure 13 The AFC frame shown includes an AFC control symbol and two data symbols. The AFC control symbol contains the control symbol identifier ESC_DL and its AFC parameters, a traffic class (TC) field, a CReq bit, and reserved bits. A data symbol includes a frame number, reserved bits, and a credit value. The AFC frame ends with a cyclic redundancy check (CRC) field, such as CCITT's CRC-16, where CCITT stands for International Telegraph and Telephone Consultative Committee.

[0166] In addition, according to the UniPro specification (e.g., version 2.0), some NAC frame transmission conditions are used as examples below to trigger the transmission of NAC frames (with the reset link request (RReq) bit set to "1"), where NAC frames can be generated for specific traffic classes (e.g., traffic class 0 (TC0) or traffic class 1 (TC1)). When at least one of the conditions occurs, the DL layer transmits the NAC frame. NAC frame transmission will inevitably affect the following: Figure 1 As shown in the figure, the overall performance of the communication system is improved. Whenever possible, NAC frame transmission needs to be performed as early as possible to request the counterparty to transmit data again.

[0167] In one example of the NAC frame transmission condition, the NAC frame is transmitted when a CRC error occurs in an incoming frame.

[0168] In one example of the NAC frame transmission condition, the NAC frame is transmitted when an RX buffer overflow occurs for any traffic class.

[0169] In one example of a NAC frame transmission condition, the NAC frame is transmitted when a frame with a payload length greater than DL_SYMBOL_MTU symbols in any traffic class is received.

[0170] In one example of the NAC frame transmission condition, the NAC frame is transmitted when a frame sequence number in a received data frame of any traffic class is incorrect.

[0171] In one example of the NAC frame transmission condition, the NAC frame is transmitted when one AFCx symbol is not followed by two data symbols.

[0172] In one example of the NAC frame transmission condition, the NAC frame is transmitted when an AFCx symbol is not followed by a data symbol.

[0173] In one example of the NAC frame transmission condition, the NAC frame is transmitted when there is no data symbol (ie, CRC symbol) following the EOF_EVEN or EOF_ODD symbol.

[0174] In one example of the NAC frame transmission condition, when PA_ERROR.ind is received, the NAC frame is transmitted.

[0175] In one example of the NAC frame transmission condition, when the frame has not yet started, if a COF, EOF_EVEN, or EOF_ODD symbol is received, the NAC frame is transmitted.

[0176] In one example of a NAC frame transmission condition, when a data frame of the same traffic class is already in progress and the data frame is not currently preempted, the NAC frame is transmitted if a SOF symbol is received.

[0177] In one example of the NAC frame transmission condition, when a data frame of TC1 is already in progress, if a SOF symbol with TC=0 is received, the NAC frame is transmitted.

[0178] In one example of the NAC frame transmission condition, during a data frame of the same traffic class, when the data frame is not preempted, if a COF symbol is received, the NAC frame is transmitted.

[0179] In one example of a NAC frame transmission condition, the NAC frame is transmitted when a COF symbol is received that continues a data frame of a different traffic class.

[0180] In one example of the NAC frame transmission condition, the NAC frame is transmitted when an EOF_EVEN, EOF_ODD, or data symbol is received after the CRC of the preempted frame.

[0181] In one example of a NAC frame transmission condition, the NAC frame is transmitted when a defined field of a received DL control symbol has an invalid value (eg, undefined control symbol type or TC).

[0182] In one example of a NAC frame transmission condition, a NAC frame is transmitted when an unexpected framing sequence or data symbols between frames are received.

[0183] in addition, Figure 14 The NAC frame shown includes NAC control symbols and data symbols. The NAC control symbol contains the control symbol identifier ESC_DL and its NAC parameters, a traffic class (TC) field, reserved bits, and RReq bits. The NAC frame also ends with a cyclic redundancy check (CRC) field (e.g., CCITT CRC-16).

[0184] like Figures 5A to 6B The following examples shown show the use of Figure 1 or Figure 2-4The technical effects of the cross-layer architecture of the relevant embodiments and the comparison with the case where the cross-layer architecture is not used. Figures 5A to 6B Before describing the communication system, some assumptions are made. In the communication system, a first device (e.g., a host device) using an interconnection controller 11D and a second device (e.g., a remote device) using an interconnection controller 21D communicate with each other through one channel from the first device to the second device and another channel from the second device to the first device according to an interconnection protocol. Figures 5A to 6B Like a "snapshot", it shows the signal transmission status of the frame between the first device and the second device at a specific time point, wherein the rectangle with the text (such as "AFC", "NAC" or "Data") inside represents the frame being transmitted, the blank rectangle represents the time interval without real data transmission, or the rectangle with the text "Error" represents the error symbol of the frame. In particular, the interconnection controllers 11D and 21D implement the system based on Figures 1 to 4 Or one of the related examples for controlling the bypass path of the frame transmission. The interconnection controllers 11D and 21D can be configured to activate or deactivate the function of the bypass path. For ease of explanation and brevity, Figures 5A to 6B The display interconnect controller has its physical layer circuit. For other implementation details, please refer to Figures 1 to 4 Please refer to one of the related embodiments or examples. Figures 5A to 6B , the physical layer circuit 101D of the interconnection controller 11D has a local transmitter (TX) represented by TX1 and a local receiver (RX) represented by RX1. Similarly, the physical layer circuit 201D of the interconnection controller 21D has a remote transmitter (TX) represented by TX2 and a remote receiver (RX) represented by RX2.

[0185] For data frame transmission, for example, when transmitting a DL data frame to a peer, the interconnection controller (e.g., 11D or 21D) temporarily stores the data in the DL data frame in a buffer in case the DL data frame needs to be retransmitted (or replayed). For example, retransmission is required if the timer associated with the DL data frame expires or an NAC frame is received. If an AFC frame associated with the DL data frame is received before the timer expires or the NAC frame is received, the data in the DL data frame can be released from the buffer; otherwise, the data in the DL data frame remains in the buffer. Similar operations are performed for another DL data frame to be transmitted. For example, if the buffer is full, transmission of the DL frame is suspended until an AFC or NAC frame is received or the timer expires.

[0186] Figure 5A An example of letterframe transmission showing the use of a bypass path for AFC letterframe transmission. Figure 5AIn the example, the interconnection controllers 11D and 21D are configured to activate the bypass path function. In the scenario of this example, the interconnection controller 21D transmits data (e.g., data symbols of a DL layer data frame) to the local RX (RX1) of the interconnection controller 11D via the remote TX (TX2), and the local RX (RX1) of the interconnection controller 11D correctly receives the data. As a result, the DL layer of the interconnection controller 11D transmits the AFC frame associated with the DL layer data frame to the remote RX (RX2) of the interconnection controller 21D via the local TX (TX1). Therefore, Figure 5A As shown in FIG, since the AFC frame transmission of the host device has a shorter delay in the cross-layer architecture, the interconnection controller 21D of the remote device can continuously transmit the DL layer data frame through the remote TX (TX2) without any substantial time gap between them. Figure 5A In this embodiment, after receiving an AFC frame via the remote RX (RX2), the interconnection controller 21D can be notified that the DL layer data frame associated with the AFC frame has been received by its peer (e.g., a host device) shortly after the interconnection controller 21D transmitted the DL layer data frame via the remote TX (TX2). Specifically, the buffer used to store retransmission data in the DL layer of the interconnection controller 21D can be prevented from filling up due to the notification of the receipt of the AFC frame. In this way, the interconnection controller 21D can transmit a series of data via the remote TX (TX2) without time gaps.

[0187] Figure 5B An example of frame transmission without using the bypass path for AFC frame transmission is shown. Interconnection controllers 11D and 21D are configured to disable the bypass path function. In this example scenario, interconnection controller 21D also transmits data (e.g., data symbols of a DL layer data frame) to the local RX (RX1) of interconnection controller 11D via the remote TX (TX2), and the local RX (RX1) of interconnection controller 11D correctly receives the data. Compared to Figure 5A In the case shown, since the bypass path function is disabled or the cross-layer architecture is not used, Figure 5B There is a long delay in the AFC frame being transmitted to the remote device. Figure 5A Compared with the scene, Figure 5B The interconnection controller 21D in the example obtains the AFC frame later, so there is a time gap when the interconnection controller 21D transmits data.

[0188] Figure 6AAn example of frame transmission using a bypass path involving NAC frames is shown. The interconnection controllers 11D and 21D are configured to activate the bypass path function. In the scenario of this example, the interconnection controller 21D transmits data (e.g., data symbols of a DL layer data frame) to the local RX (RX1) of the interconnection controller 11D via the remote TX (TX2), but the local RX (RX1) of the interconnection controller 11D receives some erroneous data. As a result, the DL layer of the interconnection controller 11D transmits the NAC frame associated with the erroneous data to the remote RX (RX2) of the interconnection controller 21D via the local TX (TX1). Therefore, as Figure 6A As shown in FIG, since the NAC frame transmission of the host device has a shorter delay in the cross-layer architecture, the interconnection controller 21D of the remote device can retransmit the DL layer data frame through the remote TX (TX2) with a small time gap. Figure 5A In this embodiment, after receiving the NAC frame via the remote RX (RX2), the interconnection controller 21D can be notified that the DL layer data frame associated with the AFC frame has not been received by its peer (e.g., host device) shortly after the interconnection controller 21D transmitted the DL layer data frame via the remote TX (TX2). In this way, the interconnection controller 21D can quickly retransmit a series of data via the remote TX (TX2) with a small time gap.

[0189] Figure 6B An example of frame transmission without a bypass path involving NAC frames is shown. The interconnection controllers 11D and 21D are configured to disable the bypass path function. In this example scenario, the interconnection controller 21D also transmits data (e.g., data symbols of a DL layer data frame) to the local RX (RX1) of the interconnection controller 11D via the remote TX (TX2), but the interconnection controller 11D at the local RX (RX1) receives some erroneous data. Compared to Figure 6A In the case shown, since the bypass path function has been disabled or the cross-layer architecture is not used, Figure 6B The NAC frame is transmitted to the remote device with a longer delay. Figure 6A Compared with the scene, Figure 6B The interconnection controller 21D in FIG. 1 obtains the NAC frame later, so the interconnection controller 21D retransmits data with a larger time gap.

[0190] Figure 7 To illustrate the bypass path between the link controller and the physical layer circuit, Figure 2 A block diagram of an embodiment of a device. Figure 7 In FIG. 1 , an interconnection controller 11E with a bypass path BPE is shown, providing an architecture for a hardware implementation of an interconnection controller, which can be viewed as Figure 1The implementation example of the interconnection controller 11 in the embodiment may be applied to realize Figure 1 The interconnection controller 21 in FIG. The interconnection controller 11E includes a link controller 105E for implementing the protocol layer (or "link layer") and a physical layer circuit 101E for signal transmission. The link controller 105E includes, for example, a physical adapter (PA) layer circuit 110E and a data link (DL) layer circuit 120E. In particular, a bypass path BPE connects between the circuit level of the link controller 105E and the physical layer circuit 101E. For example, the bypass path BPE includes circuit modules (such as a control frame transmission unit 125E) in the DL layer circuit 120E, a bus TE comprising one or more lines or traces, and circuit modules (such as a control frame reception unit 101E-05) in the physical layer circuit 101E.

[0191] The control frame transmission unit 125E in the DL layer circuit 120E is configured to directly transmit the control frame to the control frame receiving unit 101E-05 in the physical layer circuit 101E through the bus TE.

[0192] In this regard, Figure 7 As shown, the DL layer circuit 120E includes a DL transmitter (TX) 121E, a DL receiver (RX) 123E, and a control frame transmission unit 125E coupled to the DL TX 121E and the DL RX 123E. The DL TX 121E transmits DL layer data frames to the PA layer circuit 110E. For example, control frames such as AFC or NAC frames can be generated by the DL TX 121E or the control frame transmission unit 125E. The DL TX 121E and the DL RX 123E can generate control frame requests, for example, based on the aforementioned examples of AFC frame transmission conditions or NAC frame transmission conditions. In response to the control frame request, the DL layer circuit 120E can generate a control frame. The control frame transmission unit 125E can transmit the control frame directly to the control frame receiving unit 101E-05 in the physical layer circuit 101E via the bus TE, bypassing the PA layer circuit 110E. In addition, when the link controller 105E implements the UniPro specification, the control frame transmission unit 125E can transmit the control frame with the COF control symbol. Alternatively, the COF control symbol can be generated in the control frame receiving unit 101E-05.

[0193] In addition, the control frame transmission unit 125E can transmit a control signal associated with the control frame to the control frame receiving unit 101E-05. In response to the control signal and the control frame, the control frame receiving unit 101E-05 transmits a signal requesting the physical layer circuit 101E to transmit a control information signal based on the control frame and to suspend transmission of a signal based on the PA data received from the PA layer circuit 110E.

[0194] In this regard, Figure 7 As shown, the physical layer circuit 101E includes a data controller 101E-01, a transmission module 101E-03, and a control frame receiving unit 101E-05 coupled to the data controller 101E-01. In response to a control signal and a control frame, the control frame receiving unit 101E-05 transmits a signal (also known as a preemption request) to the data controller 101E-01, requesting the physical layer circuit 101E to transmit signals based on the control frame and to suspend transmission of signals based on received PA data. Upon receiving the preemption request, the data controller 101E-01 transmits a pause signal (e.g., an asserted signal) denoted by PS to the PA layer circuit 110E, requesting the PA layer circuit 110E to suspend data transmission to the physical layer circuit 101E. Meanwhile, data controller 101E-01 receives the control frame and COF control symbol output from control frame receiving unit 101E-05 and transmits them to a subsequent stage, such as transmission module 101E-03, for transmitting a control information signal based on the control frame and COF control symbol. Data controller 101E-01 then triggers PA layer circuit 110E to resume data transmission by deasserting the pause signal.

[0195] Therefore, based on Figure 2 The architecture can transmit control frames directly from the DL layer circuit 120E to the physical layer circuit 101E, bypassing the PA layer circuit 110E. This effectively and efficiently reduces the delay in transmitting control frames from the DL layer circuit 120E to the physical layer circuit 101E. In contrast, in a pipeline-based architecture, if control frames such as AFC or NAC frames are transmitted to the physical layer circuit 101E via the PA layer circuit 110E, when the control frames are generated later than other data link layer data symbols or PA layer control symbols, they need to wait in queue, resulting in longer delays. Specifically, if the link controller 105E is implemented based on the UniPro specification (e.g., version 2.0), the lane allocation, skip symbol insertion, and idle skip symbol insertion performed in the PA layer circuit 110E may result in longer delays.

[0196] Figure 8 FIG1 is a flow chart showing one embodiment of a method for facilitating transmission of a control frame. Figure 8 In the method, the method includes step S10 and step S20.

[0197] In step S10, data is transmitted from the link controller of the electronic device to the physical layer circuit of the electronic device through the signal interface (such as SF1 or SF2). For example, the link controller and the physical layer circuit are based on Figure 1-7 Any one or other of the embodiments or examples.

[0198] In step S20, a control frame (eg, AFC or NAC frame) is transmitted from a link controller to a physical layer circuit to bypass at least one circuit stage of the link controller via a signal path including a bypass path coupled to the link controller for control frame transmission.

[0199] Based on Figure 8 In one embodiment, the control frame is transmitted directly from the link controller to the physical layer circuit via a signal path including a bypass path. For example, the bypass paths such as BP1, BP2, BPA, BPC, and BPE are based on Figure 1 、 Figure 2 、 Figure 4-7 Any one or other of the embodiments or examples.

[0200] In some examples, a control frame (e.g., an AFC or NAC frame) can be transmitted from the link controller to the physical layer circuit via a signal path including a bypass path (e.g., BPB) and a signal interface (e.g., SF1), such as based on Figure 3 shown.

[0201] Based on Figure 8 In one embodiment, the method further includes: in response to the control frame, transmitting, by the physical layer circuit, a control information signal based on the control frame, and suspending signal transmission based on data received through the signal interface.

[0202] Based on Figure 8 In one embodiment, the method further comprises: after transmitting the control information signal based on the control frame, continuing to transmit a signal based on data received through the signal interface.

[0203] Generally speaking, a cross-layer architecture can be implemented through different preemption locations. The preemption location is the location in the interconnection controller's circuitry where the bypass path from the DL layer for controlling frame transmission ends. As described above, the preemption location can be configured at the end of the PA layer (for example, before a signal interface such as the RMMI interface) or within the physical layer (for example, after the RMMI interface). The following embodiments utilize a configuration in which the preemption location is located within the physical layer. When implementing preemption control, additional signals are added to the RMMI interface to implement this functionality.

[0204] Figure 9One embodiment of a method for facilitating transmission of a control frame is shown. Figure 9 As shown, the method includes steps S210-S260. Figure 7 , and the implementation of the method is not limited to the examples.

[0205] In step S210, a control frame request is generated. For example, referring to Figure 7 , the DL TX 121E or the DL RX 123E may send a control frame request to the control frame transmission unit 125E or the DL TX 121E according to the above-mentioned AFC or NAC frame transmission condition.

[0206] In step S220, a control frame is generated. In response to the control frame request, the DL layer circuit 120E can generate the control frame. Figure 7 In one example, the control frame transmission unit 125E generates the control frame. In another example, the DL TX 121E generates a control frame in response to the control frame request and outputs the control frame to the control frame transmission unit 125E.

[0207] In step S230, the control frame and the control signal are transmitted to the physical layer circuit to bypass the PA layer circuit. For example, the control frame transmission unit 125E transmits the control frame (e.g., the AFC or NAC frame) and the control signal associated with the control frame (e.g., the signal set to the active state) to the control frame reception unit 101E-05 in the physical layer 101E to bypass the PA layer circuit 110E.

[0208] In step S240, a signal is generated to suspend data transmission based on the PA data. Figure 7 As described in the above example, in response to the control signal and the control frame, the control frame receiving unit 101E-05 requests the physical layer circuit 101E to transmit a control information signal based on the control frame and to suspend signal transmission based on the received PA data. The data controller 101E-01 transmits a pause signal (PS) (e.g., a signal set to an active state) to the PA layer circuit 110E to request the PA layer circuit 110E to suspend data transmission.

[0209] In step S250 , data transmission based on the PA data is suspended. For example, in response to the suspension signal, the PA layer circuit 110E suspends its data transmission to the physical layer circuit 101E.

[0210] In step S260, the physical layer circuit transmits a control information signal based on the control frame. For example, when the PA layer circuit 110E suspends data transmission, the data controller 101E-01 receives the control frame and COF control symbol output from the control frame receiving unit 101E-05 and transmits them to a subsequent stage, such as the transmission module 101E-03, to transmit a control information signal based on the control frame and COF control symbol.

[0211] Figure 10A Displays the bypass paths involved based on Figure 2 An embodiment of a circuit. Figure 10A In the example, the control frame transmission unit 800 can be considered as a bypass path (e.g., TA, TB, TE or Figure 2 、 Figure 3 、 Figure 7 , etc.) in a circuit module (e.g., M1A, M1B, 125E, or Figure 2 、 Figure 3 、 Figure 7 The control frame transmission unit 800 transmits the control frame and the control signal associated with the control frame through a bus of a bypass path, wherein the bus may have two or more lines or traces. Figure 10A Related and the operations described below can be considered as based on Figure 8 、 Figure 9 or embodiments of steps of the method of the related examples (e.g., S20, S210, S220, S230, etc.), as appropriate.

[0212] The control frame transmission unit 800 includes a control frame generator 810, which is used to respond to the control frame generated by some circuit modules in the DL layer circuit (eg, Figure 2 、 Figure 3 、 Figure 7A control frame, such as an AFC or NAC frame, is generated based on an AFC request or NAC request issued by the data link layer (e.g., 120A, 120B, 120E, or other examples). For example, the credit processing unit 710 for processing credits in the data link layer may issue an AFC request to generate an AFC frame based on at least one of the AFC frame transmission conditions related to credits (mentioned above). For example, the acknowledgment and flow control (AFC) request timer 720 may issue an AFC request to generate an AFC frame based on at least one of the AFC frame transmission conditions related to the AFC request timer (mentioned above). For example, the flow control (FC) protection timer 730 may issue an AFC request to generate an AFC frame based on at least one of the AFC frame transmission conditions related to the flow control (FC) protection timer (mentioned above). For example, the retransmission timer 740 may issue an AFC request to generate an AFC frame based on at least one of the AFC frame transmission conditions related to the retransmission timer (mentioned above). For example, the DL receiver (RX) 600 processing one or more tasks in the data link layer may issue an NAC request to generate an NAC frame based on at least one of the NAC frame transmission conditions (mentioned above).

[0213] Figure 10B Shows the bypass path between the link controller and the physical layer circuit based on Figure 2 An embodiment of a circuit. Figure 10B In the embodiment, the control frame receiving unit 950 (or called preemptive controller) can be used as a bypass path (eg, Figure 2 、 Figure 7 TA, TE or other examples in the example etc.) in the circuit module (e.g. Figure 2 、 Figure 7 The control frame receiving unit 950 receives the control frame and the control signal associated with the control frame via a bus of a bypass path, wherein the bus may have two or more lines or traces. In addition, the data controller 910 includes a control unit 911 and a data selector 913, which can be regarded as Figure 7 The embodiment of the data controller 101E-01 can be implemented in a physical layer circuit (e.g., 101A, 101C, 101E or related examples). In addition, whenever appropriate, Figure 10B Related and the operations described below can be considered as based on Figure 8 、 Figure 9 or embodiments of steps (e.g., S20, S240, S250, S260, etc.) of the method of the related examples.

[0214] In response to the control signal and the control frame (or further coupled with the COF control symbol), the control frame receiving unit 950 transmits a signal (or called a preemptive request) to the control unit 911 of the data controller 910 to request the physical layer circuit (e.g., Figure 1 、 Figure 2 or Figure 7 101A, 101C or 101E shown in FIG, or related examples) based on the control frame to transmit the control information signal (for example, a signal output by the physical layer circuit according to the M-PHY specification (for example, version 5.0)), and pause based on the control frame from the PA layer circuit (for example, Figure 1 、 Figure 2 or Figure 7 110A, 110C, or 110E, or related examples) to receive PA data. Upon receiving the preemption request, the control unit 911 of the data controller 910 transmits a pause signal PS (e.g., an active signal) to the PA layer circuit, requesting the PA layer circuit to pause its data transmission to the physical layer circuit. Simultaneously, the control frame receiving unit 950 outputs the control frame and COF control symbol as preemptive input data to the data selector 913 via the control unit 911 of the data controller 910. In response to the preemption request, the control unit 911 of the data controller 910 transmits a selection signal to control the data selector 913 to select the preemptive input data as the output data of the data selector 913. The data selector 913 outputs the output data to a subsequent stage of the physical layer circuit, such as the transmission module 930 (e.g., a transmitter), to transmit a control information signal based on the control frame and COF control symbol. Afterwards, the control unit 911 of the data controller 910 triggers the PA layer circuit (e.g., 110E) to resume data transmission, for example, by setting the pause signal PS to an inactive state. The control unit 911 can then transmit a signal (also known as a preemption completion signal) to the control frame receiving unit 950 to notify the control frame receiving unit 950 that the preemption request is complete.

[0215] Concerning the preemption of the above control frame, Figure 15 An embodiment showing that a control frame preempts a data frame via a bypass path. Figure 10BFor example, when the PA layer circuit is outputting PA data including data of a DL layer data frame represented by data 1511, the PA layer circuit receives a pause signal (PS) from the data controller 910 and pauses the transmission of its PA data, wherein the data 1511 includes a control symbol identifier ESC_DL and parameters indicating the start of a frame (SOF), a traffic category field, and a reserved bit, and includes multiple data bytes. At the same time, the control frame receiving unit 950 outputs the control frame and the COF control symbol as preemptive input data to the data selector 913. The control frame is based on, for example, an NAC frame, such as Figure 15 As shown in the data 1610; COF control symbol, such as Figure 15 As indicated by the data 1620 in the , it includes the control symbol identifier ESC_DL and its parameters indicating COF, the traffic category field and the reserved bit. In response to the selection signal, the data selector 913 outputs the preempted input data as output data to the subsequent stage of the physical layer circuit (for example, the transmission module 930) to transmit the control information signal. Afterwards, the data controller 910 triggers the PA layer circuit to continue data transmission, for example, by setting the pause signal PS to an inactive state. Afterwards, the PA layer circuit continues to output the remaining part of the preempted DL layer data frame, such as Figure 15 As shown in the data 1512 in , the data 1512 includes the remaining data bytes, the control symbol identifier ESC_DL and its parameter indicating EOF_EVEN, the frame sequence number, and the CCITT CRC-16 data bytes.

[0216] In one embodiment, the control frame receiving unit 950 can be implemented by a logic circuit, for example, including a buffer (such as a latch, etc.) for temporarily storing the control frame and COF control symbol, and a control logic for processing the control signal and interacting with the data controller 910, such as Figure 10B In one embodiment, the control frame receiving unit 950 can be implemented to directly output the control frame and COF control symbol to the data selector 913 through wiring.

[0217] In some embodiments, it is possible to modify Figure 10B circuits to meet the needs of cross-layer architectures with different pre-emptive positions. For example, Figure 10B The circuit can be configured and included in a Figure 3 The PA layer circuit of the embodiment (for example, Figure 3 For example, the data controller 910 can Figure 3The PA layer processing unit 113B receives the PA data and outputs a pause signal (PS) to the PA layer processing unit 113B, wherein the output data of the data selector 913 is output to Figure 3 The interface module 111B is used to achieve the pre-emptive position in the PA layer circuit 110B.

[0218] In addition, when based on Figure 7 When a communication system such as a COM implements an interconnection protocol derived from the UniPro specification, it involves the following control frame (e.g., Figure 15 The COF control symbol (e.g., Figure 15 The traffic category field of the COF control symbol needs to be set to the same traffic category as that in the data 1511 of the DL layer data frame.

[0219] In some embodiments, if based on Figure 7 If a communication system only supports one type of traffic class, such as traffic class 0 (TC0), the traffic class field has a fixed value and the COF control symbol can be set accordingly.

[0220] In some embodiments, if based on Figure 7 If a communication system supports at least two types of traffic categories, such as traffic category 0 (TC0) or traffic category 1 (TC1), the traffic category field of the COF control symbol can be set to a value that matches the same traffic category of the DL layer data frame preempted by the associated control frame by using a traffic category (TC) record unit. For example, the traffic category (TC) record unit is a logic unit or circuit configured in the DL layer circuit 120E for recording traffic categories, including elements such as flags (or registers) and logic circuits. Whenever the DL layer circuit 120E transmits a DL layer data frame, the TC record unit records the traffic category of the transmitted data frame. Thereafter, as Figure 7 The DL layer circuit 120E can generate a control frame with a traffic class value obtained from the TC record unit in response to a control frame request generated by the DL TX 121E or the DL RX 123E. Using the traffic class value obtained from the TC record unit, the COF control symbol used for preemption in the physical layer circuit 101E can be generated by the DL layer circuit 120E (e.g., the control frame transmission unit 125E) or the physical layer circuit 101E (e.g., the control frame reception unit 101E-05).

[0221] Furthermore, since the latency of the PA layer circuit 110E, for example, implemented as a pipeline circuit, is a fixed number of clock cycles (e.g., 2 or 3 clock cycles), the DL layer circuit 120E can be configured to provide a traffic class value that matches the DL layer data frame preempted in the physical layer circuit 101E. Table 1 shows a time-sequential record of traffic class values for DL layer data frames output to the PA layer circuit 110E in an embodiment of a TC recording unit. In Table 1, for ease of explanation, the smaller the number in the time column, the earlier the DL layer data frame was transmitted to the PA layer circuit 110E.

[0222] Table 1

[0223] time 1 2 3 4 5 6 Traffic level TC1 TC1 TC1 TC0 TC0 TC0

[0224] In one example, assume that the PA layer circuit 110E has a latency of two clock cycles and that a bypass path is used to preempt a control frame (or insert a COF control symbol) at time 4. The DL layer circuit 120E can use the record maintained by the TC record unit to trace back to the traffic class value at time 2 (4-2=2), as shown in Table 1, and expects that the physical layer circuit 101E is processing a DL layer data frame of TC1 at time 2. Therefore, the DL layer circuit 120E can determine the traffic class value used for the COF control symbol preempted in the physical layer circuit 101E to represent TC1.

[0225] Furthermore, if the TC record unit traces back the records maintained by the TC record unit and finds that no DL layer data frames are being processed in the DL layer circuit 120E, the COF control symbol may not be generated. Table 2 shows a time-sequential record of traffic class values for DL layer data frames output to the PA layer circuit 110E in another embodiment of the TC record unit, where an "X" indicates that no DL layer data frame is being transmitted.

[0226] Table 2

[0227] time 1 2 3 4 5 6 7 8 9 10 Traffic level TC1 TC1 TC1 TC0 TC0 TC0 X X X X

[0228] In one example, assume that the PA layer circuit 110E has a latency of two clock cycles and that the bypass path is used to preempt a control frame (or insert a COF control symbol) at time 9. The DL layer circuit 120E can trace the traffic class value at time 7 (9-2=7) by using the record maintained by the TC record unit, as shown in Table 2, and expects that the physical layer circuit 101E is not processing a DL layer data frame at time 7. At the same time, if the PA layer circuit 110E is not outputting a PACP frame to the physical layer circuit 101E, the DL layer circuit 120E can transmit a control frame to the physical layer circuit 101E by using the bypass path BPE without using the COF control symbol. If the PA layer circuit 110E is outputting a PACP frame to the physical layer circuit 101E, the DL layer circuit 120E can transmit a control frame to the physical layer circuit 101E by using the bypass path BPE without using the COF control symbol, as long as the PA layer circuit 110E completes transmission of the PACP frame. For example, according to the UniPro specification (e.g., version 2.0), when the PA layer needs to perform an operation that requires link use (e.g., a power consumption mode change or PACP frame transmission), a handshaking procedure is used between the PA layer and the DL layer. The PA layer and the DL layer coordinate link use (e.g., using a control primitive represented by "PA_DL_PAUSE"). By using the handshaking procedure, the DL layer circuit 120E can be informed of whether the PA layer circuit 110E is transmitting a PACP frame, etc. Therefore, the DL layer circuit 120E can be implemented to accordingly determine whether to use the bypass path BPE to transmit a control frame to the physical layer circuit 101E, and whether to use or not use the COF control symbol.

[0229] The following provides various embodiments for facilitating an interconnection protocol and is applicable to an electronic device capable of communicating with another electronic device according to an interconnection protocol. The interconnection protocol can be derived from a UFS standard or a UniPro specification. For example, a conventional UFS system includes a UFS host and a UFS device. The UFS host and the UFS device communicate with each other through their respective UFS interconnect (UniPro Interconnect, UIC) layers, which include UniPro and M-PHY. Therefore, the interconnection protocol can be implemented and derived from the architecture of a conventional UFS system by using an adjusted UFS system, which implements an adjusted version of UniPro and an adjusted version of M-PHY.

[0230] In the following embodiments, UniPro version 2.0 is used as an example, but the implementation of the present disclosure is not limited thereto.

[0231] Various embodiments for implementing the interconnection protocol are provided below.

[0232] Please refer to Figure 11A , which illustrates a circuit architecture diagram according to an embodiment of the present disclosure. Figure 11A As shown, the storage system 1000 includes a host 1010 and a storage device 1020. The host 1010 and the storage device 1020 communicate via an interconnection protocol, so that the host 1010 can perform data access to the storage device 1020. Figure 1-4 、 Figure 7 、 Figures 10A-10B One or more of the embodiments or related examples can be applied to Figure 11A Circuit architecture or its related examples (such as Figure 11B or Figure 11C ).according to Figure 11A The circuit architecture of the present invention relates to a cross-layer architecture, and the above-mentioned technology is applicable to the first device 10 of one or more embodiments described above, which can communicate with the second device 20 of one or more embodiments described above according to the interconnection protocol, wherein the host 1010 and the storage device 1020 can be used to implement the first device 10 and the second device 20, respectively, or vice versa. Figure 11A In the circuit architecture of FIG. 1 , the controller in the host 1010 or the storage device 1020 for implementing the interconnection protocol can be implemented in various configurations. Figure 11A As shown, the controller in the host 1010 (e.g., host controller 1012) for implementing the interconnection protocol or the controller in the storage device 1020 (e.g., device controller 1022) for implementing the interconnection protocol can be implemented as a circuit architecture including a hardware protocol engine and a processing unit, wherein the processing unit of the controller is optional. In another example, as Figure 11B As shown, the controller in the host 1010 for implementing the interconnection protocol is called, for example, the protocol controller PC1, which can be configured to include a host interface 1011 and a hardware protocol engine 1013 and be implemented as a single chip, wherein the processing unit 1014 can be regarded as an external circuit of the protocol controller PC1. In addition, similarly, the controller in the storage device 1020 for implementing the interconnection protocol (or referred to as the protocol controller of the storage device 1020) can be configured to include a device interface 1021 and a hardware protocol engine 1023 and be implemented as a single chip, wherein the processing unit 1024 can be regarded as an external circuit of the protocol controller. For another example, as Figure 11CAs shown, the controller in the host 1010 for implementing the interconnection protocol, for example, the protocol controller PC2, can be configured to include a host interface 1011, a hardware protocol engine 1013, and a processing unit 1014, and is implemented as a single chip. In addition, similarly, the controller in the storage device 1020 for implementing the interconnection protocol (or referred to as the protocol controller of the storage device 1020) can be configured to include a device interface 1021, a hardware protocol engine 1023, and a processing unit 1024, and is implemented as a single chip. Therefore, according to Figure 11A The circuit architecture in the host 1010 or the storage device 1020 for implementing the interconnection protocol can be considered to include or represent a controller based on Figure 11A 、 Figure 11B or Figure 11C Example of . Figure 11A The description of other related examples also applies to Figure 11A 、 Figure 11B or Figure 11C Example of .

[0233] Figure 11A The circuit architecture shown is flexible enough to be effectively configured to meet the requirements of different products, thereby adapting to the diverse designs of manufacturers to better develop products. For example, the host 1010 is a computing device, such as a smart phone, a tablet computer, a multimedia device, or other electronic device. The storage device 1020 is, for example, a storage device inside or outside the computing device, and is a storage device such as a non-volatile memory-based storage device. The storage device 1020 can be written with data or provide the written data to the host 1010 under the control of the host 1010. The storage device 1020 can be implemented as an internal storage device, a memory card, a solid-state drive (SSD), etc.; however, the implementation of the present disclosure is not limited to the above examples.

[0234] The host 1010 includes a host interface 1011 , a host controller 1012 , and an application processor 1016 .

[0235] The host interface 1011 implements the physical layer of the interconnection protocol in order to link to the storage device 1020. For example, the host interface 1011 is based on Figure 1-10B or related instances (where appropriate) to implement an adapted version of the physical (M-PHY) layer.

[0236] The host controller 1012 is coupled between the host interface 1011 and the application processor 1016. When the application processor 1016 needs to access data from the storage device 1020, it transmits the corresponding access operation instruction or write data to the host controller 1012 and communicates with the storage device 1020 via the interconnect protocol, thereby completing the data access to the storage device 1020.

[0237] The host controller 1012 includes, for example, a hardware protocol engine 1013 and a processing unit 1014 , wherein the processing unit 1014 is optional.

[0238] The hardware protocol engine 1013 implements the link layer of the interconnection protocol. The link layer can be implemented according to the modified version of UniPro illustrated above. The hardware protocol engine 1013 communicates with the host interface 1011 and the processing unit 1014 and performs data conversion according to the specifications of the link layer. In addition, the hardware protocol engine 1013 (or the host controller 1012) can be regarded as Figure 1 An embodiment of the link controller 105 of the first device 10 shown, or capable of being based on Figure 1-10B One or more of the embodiments or related examples, as appropriate.

[0239] The processing unit 1014 is coupled to the hardware protocol engine 1013 and communicates with the application processor 1016. The processing unit 1014 is capable of executing one or more firmware programs. For example, access operation commands or write data output by an operating system, driver, or application program executed by the application processor 1016 are converted by the firmware executed by the processing unit 1014 into a format compatible with the link layer of the interconnection protocol. The command or data is then output to the hardware protocol engine 1013 for processing according to the link layer specifications. Alternatively, read data returned by the storage device 1020 in response to a read command from the host 1010 is returned to the hardware protocol engine 1013 according to the link layer specifications of the interconnection protocol. The corresponding firmware executed by the processing unit 1014 converts the data into a format compatible with the operating system, driver, or application program executed by the application processor 1016, and can then be read. The firmware can be stored, for example, in the internal memory of the processing unit 1014 or in the internal memory of the host controller 1012, where the internal memory can include volatile memory and non-volatile memory. The processing unit 1014 is optional, that is, the tasks of the above firmware can be implemented in the hardware protocol engine 1013 through hardware.

[0240] The memory device 1020 includes a device interface 1021 , a device controller 1022 , and a storage module 1026 .

[0241] The device interface 1021 implements the physical layer of the interconnection protocol to link to the host 1010. For example, the device interface 1021 is used to implement an adjusted version of the physical (M-PHY) layer based on Figures 1 to 10B One or more of the embodiments or related examples, as appropriate.

[0242] The device controller 1022 is coupled between the device interface 1021 and the storage module 1026. With respect to the interconnection protocol, the device controller 1022 has functions corresponding to or similar to those of the host controller 1012 described above. When the host 1010 issues and transmits an access operation command or write data to the storage device 1020 via the interconnection protocol, the device controller 1022 converts the received data into the corresponding access operation command or write data via the interconnection protocol, thereby facilitating data access by the storage module 1026. Alternatively, the device controller 1022 transmits read data returned by the storage device 1020 in response to a read command from the host 1010 back to the host 1010 according to the link layer of the interconnection protocol. The storage module 1026 includes, for example, one or more non-volatile memory chips, such as flash memory chips. In one example, the storage device 1020 may further include a flash memory controller. The flash memory controller is coupled between the device controller 1022 and the memory module 1026 and can be configured to control write, read, or erase operations of the memory module 1026 and to exchange data with the memory module 1026 via an address bus or a data bus. In another example, the flash memory controller can be further provided in the device controller 1022.

[0243] The device controller 1022 includes, for example, a hardware protocol engine 1023 and a processing unit 1024 , wherein the processing unit 1024 is optional.

[0244] The hardware protocol engine 1023 implements the link layer of the interconnection protocol. The link layer can be implemented according to a modified version of UniPro as described above. The hardware protocol engine 1023 communicates with the device interface 1021 and the processing unit 1024 and performs data conversion according to the specifications of the link layer. In addition, the hardware protocol engine 1023 (or the device controller 1022) can be regarded as Figure 1 An embodiment of the link controller 205 of the second device 20 shown, or capable of being based on Figure 1-10B One or more of the embodiments or related examples, as appropriate.

[0245] The processing unit 1024 is coupled to the hardware protocol engine 1023 and communicates with the host 1010 via the device interface 1021. The processing unit 1024 is capable of executing one or more firmware programs. For example, the processing unit 1024 executes one or more firmware programs to communicate with the flash memory controller described above, thereby exchanging data between the interconnect protocol and the flash memory controller, such as access operation commands, write data, or read data. The firmware programs can be stored, for example, in the internal memory of the processing unit 1024, the internal memory of the device controller 1022, or a predetermined storage area of the storage module 1026. The internal memory can include both volatile and non-volatile memory.

[0246] like Figure 11A As shown, the host interface 1011 can be coupled to the device interface 1021, for example, via data lines Din and Dout for transmitting or receiving data, a reset line RST for transmitting a hardware reset signal, and a clock line CLK for transmitting a clock signal. The data lines Din and Dout can be implemented as multiple pairs, where a pair of data lines Din or a pair of data lines Dout can be referred to as a channel, for example, for transmitting differential signals. The host interface 1011 can communicate with the device interface 1021 using at least one interface protocol; however, implementations of the present disclosure are not limited to the above examples.

[0247] The interconnection protocol is illustrated using a modified version of the UFS standard. The UFS standard includes the UFS command set (UCS) layer, the UFS transport (UTP) layer, and the UFS interconnect (UIC) layer. The UIC layer includes the link layer and the physical layer. In the interconnection protocol, the link layer of the UIC layer can be implemented according to a modified version of the UniPro specification, and the physical layer of the UIC layer can be implemented according to a modified version of the M-PHY specification.

[0248] Please refer to Figure 12 , which shows the UFS standard Figure 11A Schematic diagram of an embodiment of a layered architecture of a storage system in FIG. Since the UFS standard is based on the MIPI UniPro layer and the MIPI M-PHY layer, Figure 11A The host interface 1011 and the hardware protocol engine 1013 of the host 1010 shown in FIG are used to implement Figure 12 The adjusted physical layer 1110 and the adjusted UniPro layer 1130. In addition, Figure 11A The device interface 1021 and the hardware protocol engine 1023 of the storage device 1020 are used to implement Figure 12The physical layer 1210 and the UniPro layer 1230 in the adjustment. In addition, the cross-layer architecture Figure 1-4 、 Figure 7 、 Figures 10A-10B One or more of the embodiments or related examples can be applied to Figure 12 Layered architecture.

[0249] like Figure 12 As shown, the adjusted UniPro layer 1130 (or 1230) can include an adjusted physical adapter (PA) layer 1131 (or 1231), a data link (DL) layer 1132 (or 1232), a network layer 1133 (or 1233), and a transport layer 1134 (or 1234). The layers in the adjusted UniPro layer 1230 of the storage device 1020 can also operate and be implemented similarly.

[0250] The adapted physical adapter layer (1131 or 1231) couples the adapted physical layer (1110 or 1210) to the data link layer (1132 or 1232). The adapted physical adapter layer (1131 or 1231) can perform bandwidth control and power management between the adapted physical layer (1110 or 1210) and the data link layer (1132 or 1232). In implementation, the adapted physical layer 1110 of the host 1010 includes a transmitter (TX) 1111 and a receiver (RX) 1112, while the adapted physical layer 1210 of the memory device 1020 includes a transmitter (TX) 1211 and a receiver (RX) 1212, thereby establishing data channels SL1 and SL2 for full-duplex communication. The adapted UniPro specification can support multiple data channels for each transmission direction (e.g., forward or reverse) of the link.

[0251] The data link layer (1132 or 1232) can perform flow control for data transmission between the host 1010 and the storage device 1020. According to one or more of the above embodiments, the data link layer can perform error detection and retransmit frames if errors occur.

[0252] The network layer (1133 or 1233) is used to select a routing function for a transmission path of a packet received from the transport layer (1134 or 1234).

[0253] The transport layer (1134 or 1234) can use the command received from the UFS application layer to configure a data segment suitable for the protocol and transmit the data segment to the network layer (1133 or 1233), or can extract the command from the packet received from the network layer (1133 or 1233) and transmit the command to the UFS application layer.

[0254] In addition, the adjusted UniPro layer (1130 or 1230) can further implement a device management entity (DME) (1135 or 1235), which can communicate with the adjusted physical layer (1110 or 1210) and each layer in the adjusted UniPro layer (1130 or 1230), for example, the adjusted physical adapter layer (1131 or 1231), the data link layer (1132 or 1232), the network layer (1133 or 1233) and the transport layer (1134 or 1234), so as to communicate with the UFS application layer, thereby implementing the overall functions of the adjusted unified protocol (UniPro), such as control or configuration functions, including power on, power off, reset and power consumption mode changes.

[0255] Therefore, cross-layer architecture Figure 1-4 、 Figure 7 、 Figures 10A-10B One or more of the embodiments or related examples, when appropriate, can be applied to Figure 11A 、 Figure 11B 、 Figure 11C or Figure 12 to perform the Figure 8 、 Figure 9 The operations of one or more of the embodiments or the operations of one or more of the related embodiments or examples.

[0256] Furthermore, in this disclosure, reference to "asserting" (or alternatives thereof, such as "asserted" or "assertion") a signal means that the signal is set to its active state, which may be an active signal level at a high or low level, or a signal having some associated form. Reference to "de-asserting" (or alternatives thereof, such as "de-asserted" or "de-assertion") a signal means that the signal is set to its inactive state, which may be an inactive signal level at a low or high level, or a signal having another associated form. If a signal has an active-low state, then "asserting" the signal means setting the signal to a low level, and "de-asserting" the signal means setting the signal to a high level. If a signal is active-high, then making the signal "active" means setting the signal to a high level, and making the signal "inactive" means setting the signal to a low level.

[0257] In addition, in the above-mentioned embodiments related to the host and the storage device, the hardware protocol engine in the host controller or device controller can be designed based on a hardware description language (HDL) such as Verilog or any other design method for digital circuits generally known to those skilled in the art of the present disclosure, and can be implemented by one or more circuits based on, for example, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a complex programmable logic device (CPLD), or by a dedicated circuit or module. The host controller or device controller (or the processing unit or hardware protocol engine therein) can also be based on a microcontroller, a processor, or a digital signal processor (DSP).

[0258] As described above, techniques for facilitating control frame transmission are provided and are applicable to an electronic device capable of communicating with another electronic device according to an interconnect protocol. Embodiments of devices and methods for facilitating control frame transmission are also provided. By utilizing these techniques, control frame transmission can be performed more efficiently and effectively, thereby reducing control frame transmission latency and improving performance.

[0259] The present disclosure is described using the above-mentioned multiple embodiments. Those skilled in the art should understand that these embodiments are merely for describing the contents of the present disclosure and should not be construed as limiting the scope of the present disclosure. It should be noted that all equivalent changes, substitutions, and replacements made to the embodiments are within the scope of the present disclosure. Therefore, the scope of protection of the present disclosure should conform to the broadest interpretation of the appended claims.

Claims

1. An electronic device configured to facilitate control frame transmission, the electronic device comprising: Interconnect controller, including: Physical layer circuits, used for signal transmission; and Signal interface; a link controller coupled to the physical layer circuit number via the signal interface; and A bypass path coupled to the link controller for controlling frame transmission, The link controller is configured to transmit data to the physical layer circuit via the signal interface, and transmit a control frame to the physical layer circuit via a signal path including the bypass path to bypass at least one circuit stage of the link controller. 2 . The electronic device according to claim 1 , wherein the bypass path serves as the signal path and is connected between a circuit stage of the link controller and the physical layer circuit.

3. The electronic device of claim 2 , wherein the link controller is configured to transmit the control frame directly from the pipeline circuit of the link controller to the physical layer circuit through the bypass path to bypass at least one circuit stage between the pipeline circuit of the link controller and the physical layer circuit. 4 . The electronic device of claim 2 , wherein the link controller is configured to directly transmit the control frame from a data link layer of the link controller to the physical layer circuit through the bypass path. 5 . The electronic device of claim 2 , wherein the link controller is configured to transmit the control frame directly to the physical layer circuit through the bypass path to bypass a physical adapter layer of the link controller.

6. The electronic device according to claim 2 , wherein the link controller is configured to directly transmit the control frame to the physical layer circuit through the bypass path, and the physical layer circuit is configured to, in response to the control frame, transmit a control information signal based on the control frame and suspend signal transmission based on data received through the signal interface.

7. The electronic device according to claim 6, wherein the physical layer circuit is configured to transmit the control information signal based on the control frame and suspend signal transmission based on data received through the signal interface in response to a control signal associated with the control frame and received through the bypass path. 8 . The electronic device according to claim 6 , wherein the physical layer circuit is configured to continue transmitting the signal based on data received through the signal interface after transmitting the control information signal based on the control frame.

9. The electronic device according to claim 6, wherein the control information signal includes information based on the control frame and information based on a control symbol of a continuation COF of a preempted frame.

10. The electronic device of claim 1, wherein the bypass path is coupled between a circuit stage of the link controller and the signal interface, and the signal path includes the bypass path and the signal interface.

11. The electronic device of claim 10 , wherein the link controller is configured to transmit the control frame from the pipeline circuit of the link controller to the physical layer circuit through the signal path including the bypass path and the signal interface to bypass at least one circuit stage between the pipeline circuit of the link controller and the signal interface. 12 . The electronic device according to claim 10 , wherein the bypass path is connected between a data link layer of the link controller and an interface module of a physical adapter layer of the link controller, and the interface module is connected to the signal interface. 13 . The electronic device according to claim 10 , wherein the link controller is configured to transmit the control frame from a data link layer of the link controller to the physical layer circuit through the signal path including the bypass path and the signal interface.

14. The electronic device according to claim 10, wherein the link controller is configured to transmit the control frame to the physical layer circuit through the signal path including the bypass path and the signal interface to bypass a physical adapter layer entity of a physical adapter layer of the link controller.

15. The electronic device according to claim 1, wherein The control frame is an answer and flow control AFC frame or a negative answer control NAC frame based on the unified protocol UniPro.

16. A method for facilitating control frame transmission for use in an electronic device, the method comprising: Transmitting data from the link controller of the electronic device to the physical layer circuit of the electronic device through a signal interface; as well as A control frame is transmitted from the link controller to the physical layer circuit via a signal path including a bypass path coupled to the link controller for control frame transmission to bypass at least one circuit stage of the link controller.

17. The method of claim 16, wherein the control frame is transmitted from the link controller directly to the physical layer circuit through the bypass path as the signal path to bypass a physical adapter layer of the link controller.

18. The method of claim 16, further comprising: In response to the control frame, the physical layer circuit transmits a control information signal based on the control frame and suspends signal transmission based on data received through the signal interface.

19. The method according to claim 18, wherein The method further comprises: After transmitting the control information signal based on the control frame, the signal transmission based on the data received through the signal interface is continued.

20. The method of claim 16, wherein the control frame is transmitted from the link controller to the physical layer circuit through the signal path including the bypass path and the signal interface to bypass at least one circuit stage between a pipeline circuit of the link controller and the signal interface.

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