Control system suitable for FDD and TDD digital front-end radio frequency transceiver

Abstract

The invention discloses a control system suitable for FDD (Frequency Division Duplexing) and TDD (Time Division Duplexing) digital front-end radio frequency transceiving equipment. The control system comprises an ORAN (Orthogonal Radio Access Network) forward transmission interface module, a downlink module, an uplink module, a TDD system module and a management module, the ORAN fronthaul interface module is located between an O-DU and an O-RU for interconnection, the downlink module comprises a Beamforming Management module, an OFDM module, a Channel Filter module, a DUC Mixer module, a CFR module, a DPD module and a PAP module, and the uplink module comprises a Beamforming module, a frequency compensation module, a temperature compensation module and a PIM Cancellation module. The management module comprises a calibration interface configuration module, a power measurement interface configuration module, a DEF unified peripheral management module and a TA timing management module; and the TDD system module is used for TDD dynamic control to support a 3GPP 5G NR / LTE TDD standard frame structure and customize a non-standard time slot ratio, and configuration parameters comprise a time slot length, a CP type and a special time slot ratio. According to the invention, a unified system test and management scheme can be realized, and radio frequency equipment and digital equipment of different manufacturers can be docked.

Description

Technical Field

[0001] The present invention relates to the technical field of wireless communication equipment, and in particular to a control system suitable for FDD and TDD digital front-end radio frequency transceiver equipment. Background Art

[0002] Currently, TDD (time division duplex) radio frequency systems widely utilize architectures combining FPGAs or ASICs with high-performance radio frequency chips to meet the needs of applications such as 5G base stations, massive MIMO, and millimeter wave communications. These systems suffer from a high degree of integration and customization optimized for specific standards; fixed time slot control and limited flexibility; and limited software updates, making it difficult to adapt to new standard evolutions (such as 6G pre-research). Integrated digital front-end TDD control and configurable data paths can effectively reduce resource utilization. Furthermore, dynamically configurable TDD custom non-standard time slot allocations can dynamically adjust the GP market and improve spectrum utilization.

[0003] Traditional wireless access network equipment uses CPRI and eCPRI interfaces, and the interface protocols are relatively closed. The interface protocols of different manufacturers are different, and the data front-end uplink and downlink processing of each manufacturer has different layered processing, resulting in a large number of interfaces for each module and a lack of uniformity in the data links. As a result, the RF equipment and digital equipment of different manufacturers are incompatible, and the equipment docking and debugging are cumbersome and complicated. There is a lack of unified system testing and equipment management solutions. The open radio access network, referred to as ORAN, uses an independent building block design to allow cellular network equipment developed by different suppliers to interoperate. With the development of technology and the improvement of data processing capabilities, ORU, as a component of ORAN, will have a wider range of applications.

[0004] To address this situation, a FPGA-based TDD digital front-end processing system suitable for ORAN equipment was developed. Summary of the Invention

[0005] The object of the present invention is to provide a control system applicable to FDD and TDD digital front-end radio frequency transceiver equipment to solve the problems raised in the above background technology.

[0006] To achieve the above objectives, the present invention provides the following technical solutions: a control system applicable to FDD and TDD digital front-end radio frequency transceiver equipment, comprising an ORAN fronthaul interface module, a downlink module, an uplink module, a TDD system module, and a management module;

[0007] The ORAN fronthaul interface module is located between the O-DU and O-RU for interconnection. The downlink module includes a beamforming management module, an OFDM module, a channel filter module, a ducator mixer module, a cyclic frame rate (CFR) module, a dynamic detection and detection (DPD) module, and a pulse access point (PAP) module. The uplink module includes a beamforming module, a frequency compensation module, a temperature compensation module, and a PIM cancellation module. The management module includes a calibration interface configuration module, a power measurement interface configuration module, a DEF unified peripheral management module, and a TA timing management module. The TDD system module is used for dynamic TDD control, supports the 3GPP 5G NR / LTE TDD standard frame structure, and customizes non-standard time slot ratios. Configuration parameters include time slot length, CP type, and special time slot ratio.

[0008] Preferably, the ORAN fronthaul interface module includes:

[0009] 25G line rate Fronthaul Interface;

[0010] C-Plane, U-Plane, S-Plane, and M-Plane link data processing;

[0011] Beamforming Management;

[0012] AXI-Lite configuration interface;

[0013] Fronthaul Interface Package filter module processing;

[0014] ORAN router module;

[0015] Supports 1588v2 protocol.

[0016] Preferably, the downlink module is used by the system to obtain beamforming-related information from the ORAN C-Plane section field, and then send it to the beamforming management module, and perform weight processing on all IQ data according to the time information provided by the timing module.

[0017] Preferably, the TDD system module includes module one and module two, module one is responsible for 1588 synchronization and dynamic generation of TDD frame format, and module two generates multiple custom delay inversion signals.

[0018] Preferably, the functional modules of the CFR module include peak detection, peak scaling, distributor, and peak clipping pulse generator;

[0019] Peak detection: The peak detection module first calculates the amplitude and phase of the input signal, and then indicates the amplitude and phase that exceed the threshold;

[0020] Peak scaling: The peak value and phase detected by the peak are used as inputs of this module. This module determines the complex scaling. The scaling amplitude is equal to the difference between the signal peak value and the threshold value. The phase is the phase information of the peak signal.

[0021] Distributor: The distributor includes a peak distributor and a CPG distributor. The peak distributor calculates a peak-scaled indication signal based on the provided peak delay and the set maximum allowable delay. The indication signal corresponds to the scaling factor.

[0022] Peak clipping pulse generator: The peak clipping pulse generator is designed to have the same frequency band as the input signal, and the coefficient of the peak clipping pulse is obtained through filter design method.

[0023] Preferably, the DPD simulation algorithm implementation platform of the DPD module is Matlab, and the entire DPD simulation architecture consists of three modules, including source data reading model, PD model calculation, and PA output calculation.

[0024] Preferably, the PAP module adopts Verilog coding language, and its functional implementation is divided into three major modules: PAP_CTRL module, SRL_DET module, and Data_Ramping module, to realize the common protection of PA.

[0025] Preferably, the source data reading model is used to read forward and feedback data, and obtain data from the mat file collected by Xilinx software. The mat file contains 8192 32-bit read data, of which the first 4096 data are used as tx_data forward data, and the following 4096 data are used as rx_data receiving data. The 32-bit rx_data is converted into 16-bit two-way signed I and Q signals, and the two-way signals are interpolated into one channel of 8192 points;

[0026] PA output calculation: The data rx_data after the PA is filtered and the output is the PA feedback data fb_data. The feedback data is the data after being amplified by the power amplifier (PA). The amplification factor of the feedback data, i.e., the gain, must be eliminated. The gain elimination method is to divide the power of the transmitted signal by the power of the feedback signal to obtain its amplification factor. Then, the feedback signal is divided by the amplification factor to obtain the unamplified feedback data.

[0027] The PD model calculation is used to implement the pre-distortion function. The PD adopts a memory polynomial structure. The PD module first reads the source data, and then performs the dpd_process function to calculate the parameters of the PD module.

[0028] In the dpd_process function, the input signal and feedback signal are first synchronized and power-aligned. Then, according to the power amplifier model, the corresponding PD model is selected. Finally, the parameters of the PD polynomial are calculated based on the forward and feedback data and stored in the corresponding data file for subsequent processing. After the PD parameters are calculated, the parameters are saved, and then the calculation of the PD polynomial needs to be implemented. The memory polynomial structure is usually used to describe the PD model, and the PD coefficient is obtained by reading the parameter data file. If there is no data file, the default output is equal to the input, that is, there is no PD function.

[0029] Compared with the prior art, the present invention has the following beneficial effects:

[0030] System modular design framework;

[0031] Significantly improves the time slot switching speed and accuracy of the TDD system, making it suitable for dynamically changing wireless channel environments;

[0032] Supports flexible and scalable multi-channel synchronous configuration to meet future higher-capacity communication needs;

[0033] The hardware architecture is highly versatile and can be easily integrated into different application scenarios;

[0034] Support seamless connection of equipment from different ORAN manufacturers;

[0035] Signal simulation analysis for in-depth data simulation and analysis at multiple module points on the link. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 This is a system block diagram of the present invention;

[0037] Figure 2 This is a schematic diagram of the ORAN fronthaul interface module of the present invention;

[0038] Figure 3 Schematic diagram of the OFDM module of the present invention;

[0039] Figure 4 Schematic diagram of the TDD system module of the present invention;

[0040] Figure 5 This is a schematic diagram of CLGC of the present invention;

[0041] Figure 6 Schematic diagram of the DPD module of the present invention. DETAILED DESCRIPTION

[0042] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0043] See also Figure 1-6 , the present invention provides a technical solution: a control system suitable for FDD and TDD digital front-end radio frequency transceiver equipment, including an ORAN fronthaul interface module, a downlink module, an uplink module, a TDD system module and a management module;

[0044] The ORAN fronthaul interface module is located between the O-DU and O-RU for interconnection. The downlink module includes a beamforming management module, an OFDM module, a channel filter module, a ducator mixer module, a cyclic frame rate (CFR) module, a dynamic detection and detection (DPD) module, and a pulse access point (PAP) module. The uplink module includes a beamforming module, a frequency compensation module, a temperature compensation module, and a PIM cancellation module. The management module includes a calibration interface configuration module, a power measurement interface configuration module, a DEF unified peripheral management module, and a TA timing management module. The TDD system module is used for dynamic TDD control, supports the 3GPP 5G NR / LTE TDD standard frame structure, and customizes non-standard time slot ratios. Configuration parameters include time slot length, CP type, and special time slot ratio.

[0045] In the present invention, the ORAN fronthaul interface module includes:

[0046] 25G line rate Fronthaul Interface;

[0047] C-Plane, U-Plane, S-Plane, and M-Plane link data processing;

[0048] Beamforming Management;

[0049] AXI-Lite configuration interface;

[0050] Fronthaul Interface Package filter module processing;

[0051] ORAN router module;

[0052] Supports 1588v2 protocol.

[0053] In the present invention, the downlink module is used by the system to obtain beamforming-related information from the ORAN C-Plane section field, and then send it to the beamforming management module, which performs weight processing on all IQ data based on the time information provided by the timing module;

[0054] The ORAN C-Plane section extension 1 applies to sending beamforming weights from the O-DU to the O-RU. When the section extension 1 appears in the section description, the O-RU shall associate the beamforming weight set delivered in the section extension 1 with the beamforming weight set delivered in the section description. In subsequent C-Plane messages, the same beamId can be called without sending the beamforming weights again.

[0055] In the present invention, the TDD system module includes module one and module two, module one is responsible for 1588 synchronization and dynamic generation of TDD frame format, and module two generates multiple custom delay inversion signals.

[0056] In the present invention, the CFR module: Currently, the more advanced wireless communication systems have relatively high peak-to-average ratio signals. To ensure that the signals are not distorted, power amplifier back-off must be performed, which leads to a decrease in power amplifier efficiency. The crest factor reduction (CFR) algorithm clips the peak of the signal before the power amplifier to effectively reduce the peak-to-average ratio of the system signal. By reducing the peak-to-average ratio of the signal, the power amplifier back-off is reduced, thereby improving the efficiency of the power amplifier.

[0057] The basic principle of the PC_CFR algorithm is to subtract the spectral pulse that matches the input signal spectrum from the signal peak that exceeds the threshold, thereby achieving the purpose of reducing the signal peak-to-average ratio. In the process of peak clipping implemented by the PC_CFR algorithm, the peak detection module detects the amplitude of the input signal, provides each peak position indication signal and the amplitude and phase information of the corresponding peak; the peak scaling module generates an amplitude difference based on the peak amplitude and the threshold value, and the amplitude difference is combined with the phase information to generate a complex weighting, which is used to scale the coefficient of the peak clipping pulse. While performing peak scaling, the distributor will assign a peak clipping pulse generator to the detected peak signal for peak clipping. The clipped signal is then multiplied by the coefficient of the scaled peak clipping pulse, and finally the sum is performed to obtain the clipped signal.

[0058] The functional modules of the CFR module include peak detection, peak scaling, distributor, and peak clipping pulse generator;

[0059] Peak detection: The peak detection module first calculates the amplitude and phase of the input signal, and then indicates the amplitude and phase that exceed the threshold;

[0060] Peak scaling: The peak value and phase detected by the peak are used as inputs of this module. This module determines the complex scaling. The scaling amplitude is equal to the difference between the signal peak value and the threshold value. The phase is the phase information of the peak signal.

[0061] Distributor: The distributor includes a peak distributor and a CPG distributor. The peak distributor calculates a peak-scaled indication signal based on the provided peak delay and the set maximum allowable delay. The indication signal corresponds to the scaling factor.

[0062] Peak clipping pulse generator: The peak clipping pulse generator is designed to have the same frequency band as the input signal, and the coefficient of the peak clipping pulse is obtained through filter design method.

[0063] The present invention first designs a prototype filter that matches the single-carrier spectrum. If the input signal is a single carrier, the coefficients of the prototype filter are the coefficients required for peak clipping pulses. For multi-carrier configurations, frequency shifting is performed on the basis of the prototype filter. The replicas of the shifted prototype filter are required to be placed at the center frequency of each carrier. These replicas of the prototype filters are then added together to obtain a composite multi-band filter. The coefficients of the composite multi-band filter are the coefficients required for peak clipping.

[0064] In the present invention, the DPD simulation algorithm implementation platform of the DPD module is Matlab, and the entire DPD simulation architecture consists of three modules, including source data reading model, PD model calculation, and PA output calculation.

[0065] Power amplifiers (PAs) are key components in communication systems, impacting system performance. PAs inherently exhibit nonlinearity. In wireless communications, nonlinear distortion can have two consequences for the entire system: in-band signal distortion, which increases the system's bit error rate and severely impacts signal transmission; and out-of-band spectrum spread, which interferes with the transmission of signals from adjacent channels. To ensure PA linearity and efficiency, various linearization methods are employed, including Cartesian feedback, feedforward linearization, and digital predistortion (DPD). Of these linearization methods, digital predistortion (DPD) offers the most cost-effective solution.

[0066] In PA, its nonlinearity can be described by amplitude modulation (AM) distortion and phase modulation (PM) distortion. Amplitude-amplitude (AM-AM) conversion and amplitude-phase (AM-PM) conversion;

[0067] This is the main consideration for memoryless power amplifiers. The essence of power amplifier linearization is actually to eliminate the impact of the two conversions AM-AM and AM-PM.

[0068] The 1dB compression point is used to determine the division between an amplifier's linear and nonlinear regions (saturation). The 1dB compression point is defined as the input signal position where the actual gain drops 1dB below the ideal gain. When the input signal is small, the amplifier operates in its linear region, with a linear relationship between input and output.

[0069] For systems using non-constant envelope modulation, the input signal is of varying amplitude, resulting in significant spectral growth in the output signal, which can cause intermodulation interference with adjacent channels. ACPR (adjacent channel power rate) primarily reflects the effect of amplifier distortion on adjacent channels.

[0070] The ACPR value is defined as the ratio of adjacent channel power to main channel power. When analyzing the nonlinearity of high-power amplifiers in communication systems, ACPR is arguably the most practical and effective parameter. When testing system specifications, ACPR is often measured to ensure it meets requirements. Given the same system bit error rate, a lower ACPR value indicates higher bandwidth utilization and reduced inter-channel interference. Therefore, using ACPR is a more effective method for analyzing the performance characteristics of power amplifiers operating in the nonlinear region.

[0071] Error vector magnitude (EVM) is one of the important indicators for measuring the performance of the peak clipping CFR algorithm and the DPD algorithm in the system.

[0072] When analyzing the nonlinear characteristics of a power amplifier, it's first necessary to establish a suitable model for the amplifier. This is because different amplifiers have different characteristics, so when analyzing different amplifiers, it's necessary to establish corresponding models to more accurately describe the amplifier's characteristics. Generally, amplifier models can be divided into two categories: memory-only models and memory-only models, depending on whether the amplifier exhibits a memory effect.

[0073] As the signal bandwidth becomes wider, the memory effect becomes more and more significant. The result of the memory effect is that the current output of the amplifier depends not only on the current input signal, but also on the past input. At this time, the memory of the amplifier cannot be ignored. For this kind of amplifier, the memoryless model cannot fully describe its nonlinear characteristics and can only provide very limited linearization capabilities during the pre-distortion process. Therefore, the amplifier model must have memory.

[0074] In the present invention, the PAP module adopts Verilog coding language, and its functions are divided into three major modules: PAP_CTRL module, SRL_DET module, and Data_Ramping module, so as to realize the common protection of PA.

[0075] In the present invention, the source data reading model is used to read forward and feedback data, and obtains data from the mat file collected by Xilinx software. The mat file contains 8192 32-bit read data, of which the first 4096 data are used as tx_data forward data, and the following 4096 data are used as rx_data received data. The 32-bit rx_data is converted into 16-bit two-way signed I and Q signals, and the two-way signals are interpolated into one channel of 8192 points;

[0076] PA output calculation: The data rx_data after the PA is filtered and the output is the PA feedback data fb_data. The feedback data is the data after being amplified by the power amplifier (PA). The amplification factor of the feedback data, i.e., the gain, must be eliminated. The gain elimination method is to divide the power of the transmitted signal by the power of the feedback signal to obtain its amplification factor. Then, the feedback signal is divided by the amplification factor to obtain the unamplified feedback data.

[0077] The PD model calculation is used to implement the pre-distortion function. The PD adopts a memory polynomial structure. The PD module first reads the source data, and then performs the dpd_process function to calculate the parameters of the PD module.

[0078] In the dpd_process function, the input signal and feedback signal are first synchronized and power-aligned. Then, according to the power amplifier model, the corresponding PD model is selected. Finally, the parameters of the PD polynomial are calculated based on the forward and feedback data and stored in the corresponding data file for subsequent processing. After the PD parameters are calculated, the parameters are saved, and then the calculation of the PD polynomial needs to be implemented. The memory polynomial structure is usually used to describe the PD model, and the PD coefficient is obtained by reading the parameter data file. If there is no data file, the default output is equal to the input, that is, there is no PD function.

[0079] The CLGC of the present invention automatically detects transmit power and dynamically adjusts gain (typically digital gain / analog gain) to maintain stable transmit output power; prevents power drift (such as gain changes caused by temperature affecting the PA); meets the strict requirements of communication standards for transmit power error (such as those specified in 5G NR); and protects the RF front end from overdriving or underdriving.

[0080] The system of the present invention includes modules such as processing of C / U / S / M data of the ORAN fronthaul interface, uplink and downlink data downlink beamforming management, OFDM, ChannelFilter, DUC Mixer, CFR, DPD, PAP, uplink beamforming, frequency compensation, temperature compensation, PIM Cancellation, PRACH channel processing, calibration interface configuration, and power measurement. Radio frequency equipment that meets this standard can implement a unified system testing and management solution, as well as achieve the connection between radio frequency equipment and digital equipment from different manufacturers.

[0081] The contents not described in detail in this specification belong to the prior art known to professional and technical personnel in this field. Although the embodiments of the present invention have been shown and described, it is understood by those skilled in the art that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of the present invention. The scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A control system suitable for FDD and TDD digital front-end radio frequency transceiver equipment, characterized by: Includes ORAN fronthaul interface module, downlink module, uplink module, TDD system module and management module; The ORAN fronthaul interface module is located between the O-DU and O-RU for interconnection. The downlink module includes a beamforming management module, an OFDM module, a channel filter module, a ducator mixer module, a cyclic frame rate (CFR) module, a dynamic detection and detection (DPD) module, and a pulse access point (PAP) module. The uplink module includes a beamforming module, a frequency compensation module, a temperature compensation module, and a PIM Cancellation module. The management module includes a calibration interface configuration module, a power measurement interface configuration module, a DEF unified peripheral management module, and a TA timing management module. The TDD system module is used for dynamic TDD control, supports the 3GPP 5GNR / LTE TDD standard frame structure, and customizes non-standard time slot ratios. Configuration parameters include time slot length, CP type, and special time slot ratio.

2. A control system suitable for FDD and TDD digital front-end radio frequency transceiver equipment according to claim 1, characterized in that: The ORAN fronthaul interface module includes: 25G line rate Fronthaul Interface; C-Plane, U-Plane, S-Plane, and M-Plane link data processing; Beamforming Management; AXI-Lite configuration interface; Fronthaul Interface Package filter module processing; ORAN router module; Supports 1588v2 protocol.

3. The control system for FDD and TDD digital front-end radio frequency transceiver equipment according to claim 1, characterized in that: The downlink module is used by the system to obtain beamforming-related information from the ORAN C-Plane section field, and then send it to the beamforming management module, which performs weight processing on all IQ data based on the time information provided by the timing module.

4. The control system for FDD and TDD digital front-end radio frequency transceiver equipment according to claim 1, characterized in that: The TDD system module includes module one and module two. Module one is responsible for 1588 synchronization and dynamic generation of TDD frame format, and module two generates multiple custom delay inversion signals.

5. The control system for FDD and TDD digital front-end radio frequency transceiver equipment according to claim 1, characterized in that: The functional modules of the CFR module include peak detection, peak scaling, distributor, and peak clipping pulse generator; Peak detection: The peak detection module first calculates the amplitude and phase of the input signal, and then indicates the amplitude and phase that exceed the threshold; Peak scaling: The peak value and phase detected by the peak are used as inputs of this module. This module determines the complex scaling. The scaling amplitude is equal to the difference between the signal peak value and the threshold value. The phase is the phase information of the peak signal. Distributor: The distributor includes a peak distributor and a CPG distributor. The peak distributor calculates a peak-scaled indication signal based on the provided peak delay and the set maximum allowable delay. The indication signal corresponds to the scaling factor. Peak clipping pulse generator: The peak clipping pulse generator is designed to have the same frequency band as the input signal, and the coefficient of the peak clipping pulse is obtained through filter design method.

6. The control system applicable to FDD and TDD digital front-end radio frequency transceiver equipment according to claim 1, characterized in that: The DPD simulation algorithm implementation platform of the DPD module is Matlab. The entire DPD simulation architecture consists of three modules, including source data reading model, PD model calculation, and PA output calculation.

7. The control system applicable to FDD and TDD digital front-end radio frequency transceiver equipment according to claim 1, characterized in that: The PAP module adopts Verilog coding language, and its functions are divided into three major modules: PAP_CTRL module, SRL_DET module, and Data_Ramping module to realize the joint protection of PA.

8. The control system applicable to FDD and TDD digital front-end radio frequency transceiver equipment according to claim 6, characterized in that: The source data reading model is used to read forward and feedback data from the mat file collected by Xilinx software. The mat file contains 8192 32-bit read data, of which the first 4096 data are used as tx_data forward data and the following 4096 data are used as rx_data receiving data. The 32-bit rx_data is converted into 16-bit two-way signed I and Q signals, and the two-way signals are interpolated into one channel of 8192 points. PA output calculation: The data rx_data after the PA is filtered and the output is the PA feedback data fb_data. The feedback data is the data after being amplified by the power amplifier (PA). The amplification factor of the feedback data, i.e., the gain, must be eliminated. The gain elimination method is to divide the power of the transmitted signal by the power of the feedback signal to obtain its amplification factor. Then, the feedback signal is divided by the amplification factor to obtain the unamplified feedback data. The PD model calculation is used to implement the pre-distortion function. The PD adopts a memory polynomial structure. The PD module first reads the source data, and then performs the dpd_process function to calculate the parameters of the PD module. In the dpd_process function, the input signal and feedback signal are first synchronized and power-aligned. Then, according to the power amplifier model, the corresponding PD model is selected. Finally, the parameters of the PD polynomial are calculated based on the forward and feedback data and stored in the corresponding data file for subsequent processing. After the PD parameters are calculated, the parameters are saved, and then the calculation of the PD polynomial needs to be implemented. The memory polynomial structure is usually used to describe the PD model, and the PD coefficient is obtained by reading the parameter data file. If there is no data file, the default output is equal to the input, that is, there is no PD function.

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