Encryption and decryption acceleration method and device for SM4-OFB mode

By refinely decomposing and parallelizing the SM4 algorithm in OFB mode, using multiple rounds of parallel optimization and intermediate value feedback methods, the problem of improving the encryption and decryption speed of the SM4 algorithm is solved, achieving an increase of 6.3% of the encryption speed and a 53.1% of the decryption speed.

CN120455113APending Publication Date: 2025-08-08INSTITUTE OF INFORMATION ENGINEERING CHINESE ACADEMY OF SCIENCES
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Patent Information

Application Number
CN202510682896.4
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-05-26
Publication Date
2025-08-08

AI Technical Summary

Technical Problem

The prior art cannot effectively realize the parallel processing of the SM4 algorithm encryption and decryption process in OFB mode, resulting in the inability to improve the encryption and decryption speed.

Method used

Using a method combining multiple rounds of parallel optimization and intermediate value feedback, the SM4 algorithm in the OFB mode is refined and decomposed to accelerate the SM4-OFB encryption and decryption process, and parallel calculation and parameter calibration technology are used.

Benefits of technology

Without increasing computing power, the SM4 encryption speed in OFB mode is improved by about 6.3% and the decryption speed is increased by about 53.1%.

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Abstract

The invention belongs to the technical field of information, and relates to an encryption and decryption acceleration method and device for an SM4-OFB mode. According to the method, any two rounds of SM4-OFB acceleration processes are firstly realized, and then SM4-OFB encryption acceleration and SM4-OFB decryption acceleration are realized based on the acceleration processes. According to the method, the encryption process of the SM4 algorithm in the OFB mode is refined and decomposed, software implementation of the SM4 algorithm in the OFB mode is accelerated in a parameter calibration mode by calculating association between round functions and combining inverse sequence transformation before ciphertext output, and the parallel encryption speed can be effectively increased. On the premise of not additionally increasing the computing power, the SM4 encryption speed in the OFB mode can be averagely improved by about 6.3%, and meanwhile, the decryption speed in the SM4-OFB mode can be improved by about 53.1%.
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Description

Technical Field

[0001] The present invention belongs to the field of information technology, and in particular relates to an encryption and decryption acceleration method and device for an SM4-OFB mode. Background Art

[0002] The SM4 algorithm is a block symmetric cipher designed by the State Cryptography Administration. It performs data encryption and decryption operations to ensure the confidentiality of data and information. OFB mode stands for output-feedback mode. In OFB mode, the output of the cipher algorithm is fed back into the input. Instead of directly encrypting plaintext using the cipher algorithm, OFB mode generates ciphertext blocks by performing an XOR (exclusive OR) operation on the plaintext block and the cipher algorithm output.

[0003] The national encryption SM4 algorithm in OFB mode is a sequential encryption implementation scheme that cannot effectively implement the parallel processing of the encryption process. Therefore, the encryption and decryption process cannot be effectively parallelized and accelerated. Summary of the Invention

[0004] In response to the above problems, the present invention provides an encryption and decryption acceleration method and device for the SM4-OFB mode, which uses a method combining multi-round parallel optimization and intermediate value feedback to improve the encryption and decryption speed of the SM4 algorithm in the OFB mode.

[0005] The technical solution adopted in the present invention is as follows:

[0006] An encryption and decryption acceleration method for an SM4-OFB mode includes two rounds of SM4 iterative acceleration processes under the OFB mode, wherein the two rounds of SM4 iterative acceleration processes under the OFB mode include the following steps:

[0007] 1) In OFB mode, the calculation equation for any two SM4 encryption descriptions is:

[0008]

[0009] Among them, X a,b Indicates the b-th state value of the a-th round of encryption; represents XOR operation; T represents T transformation; rk a Indicates the key state value of the a+1th round; M0 indicates the initial plaintext information; M i Represents the input state value of the i-th round of encryption, M i+1 Represents the output state value of the i-th round of encryption, M0=ICV, ICV represents the initialization vector;

[0010] 2) Generate a random number X′ i,34 ,X′ i,35, and calculate the second encrypted input plaintext (X i+1,0 ,X i+1,1 ,X i+1,2 ,X i+1,3 )=(X′ i,35 ,X′ i,34 ,X i,33 ,X i,32 ), where X a,b Indicates the actual calculated state value, X′ a,b is the guessed state value;

[0011] 3) Parallel computing:

[0012]

[0013] in,

[0014]

[0015] 4) Parallel calculation of variable X i,34 ,X′ i+1,4 ,in

[0016] 5) Assumptions in Among them, σ′0 and σ0 represent the defined state values, T(σ0) represents T transformation, S(σ0) represents S-box transformation, and “<” represents a circular left shift operation;

[0017] 6) Calibrate the output variables of the first round of encryption in the second SM4 iteration:

[0018]

[0019] The first round of calibration parameters are: where X″ i+1,4 represents the defined state value, T(σ′0) represents the T transformation;

[0020] 7) Parallel Computing X i,35 ,X′ i+1,5 :

[0021]

[0022] 8) Assumptions but

[0023]

[0024] Among them, δ0 and δ′0 represent the defined state values, and T(δ0) represents the T transformation.

[0025] Furthermore, the above method implements the SM4-OFB encryption acceleration process using the following steps:

[0026] 1) Input the initialization vector IV and perform the first 32-round SM4 encryption process;

[0027] 2) When the first SM4 encryption process reaches the 30th round, the second SM4 encryption process is started using the method described in claim 1;

[0028] 3) After the second SM4 encryption completes 2 rounds of encryption, the first SM4 completes all 32 rounds of encryption, and the output value is M1;

[0029] 4) Use M1 to correct the state after the second SM4 encryption round 2, so that the state after the second SM4 encryption round 2 is the correct value;

[0030] 5) Continue to perform the second SM4 encryption and jump to step 2);

[0031] 6) When encryption is completed After SM4 encryption, record the output intermediate value M

[0032] 7) Continue to execute all encryption processes until all intermediate values are generated;

[0033] 8) The ciphertext and the intermediate value M Sent to the decryptor.

[0034] Furthermore, the above method implements the SM4-OFB decryption acceleration process using the following steps:

[0035] 1) The decryption party receives the ciphertext data and the intermediate value M Input the initialization vector IV and perform the first 32-round SM4 encryption process;

[0036] 2) When the first SM4 encryption process reaches the 30th round, the second SM4 encryption process is started using the method described in claim 1;

[0037] 3) After the second SM4 encryption completes 2 rounds of encryption, the first SM4 completes all 32 rounds of encryption, and the output value is M1;

[0038] 4) Use M1 to correct the state after the second SM4 encryption round 2, so that the state after the second SM4 encryption round 2 is the correct value;

[0039] 5) Synchronously execute The 32-round encryption process of SM4, refer to steps 2), 3), and 4);

[0040] 6) Continue to execute the second SM4 encryption synchronously and jump to step 2) to execute the Second SM4 encryption and jump to step 2);

[0041] 7) When encryption is completed After the nth SM4 encryption, the nth SM4 encryption is also completed to obtain the final plaintext data.

[0042] An encryption and decryption acceleration device for the SM4-OFB mode, comprising an SM4-OFB encryption acceleration module and / or an SM4-OFB decryption acceleration module; the SM4-OFB encryption acceleration module adopts the above-mentioned method of the present invention to achieve SM4-OFB encryption acceleration; the SM4-OFB decryption acceleration module adopts the above-mentioned method of the present invention to achieve SM4-OFB decryption acceleration.

[0043] The beneficial effects of the present invention are as follows:

[0044] This paper decomposes the encryption process of the SM4 algorithm in OFB mode in detail. By calculating the correlation between round functions and combining it with the reverse transformation before ciphertext output, this method accelerates the software implementation of the SM4 algorithm in OFB mode through parameter calibration, effectively improving the parallel encryption speed. Without increasing computing power, the average encryption speed of SM4 in OFB mode is increased by approximately 6.3%, and the decryption speed in SM4-OFB mode is increased by approximately 53.1%. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 It is the encryption iteration process of any two SM4 in OFB mode. Among them, Round Function represents the round function, PLAINTEXTP i Indicates plain text status, CIPHERTEXTC i Indicates the ciphertext status.

[0046] Figure 2 It is the SM4-OFB encryption process.

[0047] Figure 3 This is the SM4-OFB decryption process. DETAILED DESCRIPTION

[0048] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to specific embodiments and accompanying drawings.

[0049] Technique 1: Any two rounds of SM4-OFB acceleration process

[0050] Figure 1The encryption iteration process of any two SM4 iterations in OFB mode is described. A two-round SM4 iteration acceleration method in OFB mode includes the following steps:

[0051] 1. In OFB mode, any two SM4 encryption description calculation equations:

[0052]

[0053] Where M0=ICV,X i,32 ,X i,33 Known.

[0054] Among them, X a,b Represents the state value of the group, that is, the b-th state value of the a-th round of encryption, such as X i,34 represents the 34th state value of the i-th round of encryption, X i+1,0 Indicates the 0th state value of the i+1th round of encryption; represents XOR operation; T represents T transformation; rk a Indicates the key status value of round a+1, for example, rk 30 represents the 31st round key, rk0 represents the first round key, rk1 represents the second round key; M0 represents the initial plaintext information; ICV represents the initialization vector, M i Represents the input state value of the i-th round of encryption, M i+1 Represents the output state value of the i-th round of encryption.

[0055] 2. Generate a random number X′ i,34 ,X′ i,35 , and calculate the second encrypted input plaintext (X i+1,0 ,X i+1,1 ,X i+1,2 ,X i+1,3 )=(X′ i,35 ,X′ i,34 ,X i,33 ,X i,32 ). Where X a,b Indicates the actual calculated state value, X′ a,b Is the guessed state value, such as X i,34 is the actual calculated state value, X′ i,34 is the guessed state value.

[0056] 3. Parallel computing:

[0057]

[0058] in,

[0059]

[0060] 4. Parallel calculation of variable X i,34 ,X′ i+1,4 ,in

[0061] 5. Assumptions in

[0062] Among them, σ′0 and σ0 represent defined state values and have no actual physical meaning; T(σ0) represents T transformation, S(σ0) represents S-box transformation, <<< represents a circular left shift operation, and 2, 10, 18, and 24 represent the number of bits corresponding to the circular shift.

[0063] 6. Calibrate the output variables of the first round of encryption in the second SM4 iteration,

[0064]

[0065] The first round calibration parameter (i.e., the check value of the second round encryption intermediate state, so that the second round calculation becomes the correct value) is:

[0066]

[0067] Among them, X″ i+1,4 It represents the defined state value and has no actual physical meaning. T(σ′0) represents the T transformation.

[0068] 7. Parallel Computing X i,35 ,X′ i+1,5 :

[0069]

[0070] 8. Assumptions but

[0071]

[0072]

[0073] Among them, δ0 and δ0′ represent defined state values and have no actual physical meaning, and T(δ0) represents T transformation.

[0074] Technology 2: SM4-OFB encryption acceleration method

[0075] The SM4-OFB encryption process is as follows Figure 2 As shown in Figure 1. A complete SM4 encryption process consists of 32 round function iterations. For the plaintext encryption process of n groups, n 32 rounds of SM4 encryption are required to generate n intermediate values Mi. The SM4-OFB encryption process acceleration steps are as follows:

[0076] 1. Input the initialization vector IV and perform the first 32-round SM4 encryption process;

[0077] 2. When the first SM4 encryption reaches the 30th round, the second SM4 encryption process begins using technology 1;

[0078] 3. After the second SM4 encryption completes two rounds of encryption, the first SM4 completes all 32 rounds of encryption, and the output value is M1, which is the status value of the SM4 encryption process;

[0079] 4. Use M1 to correct the state after the second SM4 encryption round 2, so that the state after the second SM4 encryption round 2 is the correct value;

[0080] 5. Continue with the second SM4 encryption and jump to step 2;

[0081] 6. When encryption is complete After SM4 encryption, record the output intermediate value M

[0082] 7. Continue to execute all encryption processes until all intermediate values are generated;

[0083] 8. The ciphertext (ciphertext group 1 to n) and the intermediate value M Sent to the decryptor.

[0084] Technology 3: SM4-OFB decryption acceleration method

[0085] The SM4-OFB decryption process is as follows Figure 3 As shown in Figure 1. A complete SM4 encryption process consists of 32 round function iterations. For the plaintext decryption process of n groups, n 32 rounds of SM4 encryption are required to generate n intermediate values Mi. The SM4-OFB decryption process acceleration steps are as follows:

[0086] 1. The decryption party receives the ciphertext data and the intermediate value M Input the initialization vector IV and perform the first 32-round SM4 encryption process;

[0087] 2. When the first SM4 encryption reaches the 30th round, the second SM4 encryption process begins using technology 1;

[0088] 3. After the second SM4 encryption completes two rounds of encryption, the first SM4 completes all 32 rounds of encryption, and the output value is M1;

[0089] 4. Use M1 to correct the state after the second SM4 encryption round 2, so that the state after the second SM4 encryption round 2 is the correct value;

[0090] 5. Synchronously execute The 32-round encryption process of SM4, refer to steps 2, 3, and 4;

[0091] 6. Continue to execute the second SM4 encryption synchronously and jump to step 2 to execute Second SM4 encryption and jump to step 2;

[0092] 7. When encryption is complete After the nth SM4 encryption, the nth SM4 encryption is also completed to obtain the final plaintext data.

[0093] In summary, the present invention refines and decomposes the encryption process of the SM4 algorithm in the OFB mode, calculates the correlation between the round functions (steps 6 and 8 in technology one), and combines the inverse transformation before the ciphertext output (step 4 in technology two and three), and accelerates the software implementation of the SM4 algorithm in the OFB mode through parameter calibration, which can effectively improve the parallel encryption speed.

[0094] This invention is applicable to applications using SM4-OFB encryption, effectively improving the encryption and decryption speeds in these scenarios. For example, it can be used to encrypt cameras. After a camera captures image or video data, the SM4-OFB encryption method designed using this method can more efficiently and securely send the data to a server, ensuring data security.

[0095] Another embodiment of the present invention provides an encryption and decryption acceleration device for the SM4-OFB mode, including an SM4-OFB encryption acceleration module and / or an SM4-OFB decryption acceleration module; the SM4-OFB encryption acceleration module adopts the above-mentioned method (technology two) of the present invention to realize SM4-OFB encryption acceleration; the SM4-OFB decryption acceleration module adopts the above-mentioned method (technology three) of the present invention to realize SM4-OFB decryption acceleration.

[0096] The division of the above modules is only for illustration purposes. In actual applications, the above functions can be assigned to different functional modules as needed to complete all or part of the functions described in the above method. The specific working process of each module can refer to the corresponding process in the above method embodiment and will not be repeated here.

[0097] Another embodiment of the present invention provides a computer device (computer, server, smart phone, etc.), which includes a memory and a processor, wherein the memory stores a computer program, the computer program is configured to be executed by the processor, and the computer program includes instructions for executing each step in the method of the present invention.

[0098] Another embodiment of the present invention provides a computer-readable storage medium (such as ROM / RAM, magnetic disk, optical disk), wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a computer, the steps of the method of the present invention are implemented.

[0099] The specific embodiments of the present invention disclosed above are intended to facilitate understanding and implementation of the present invention. Those skilled in the art will appreciate that various substitutions, changes, and modifications are possible without departing from the spirit and scope of the present invention. The present invention should not be limited to the embodiments disclosed in this specification; the scope of protection of the present invention shall be determined by the scope defined in the claims.

Claims

1. A method for accelerating encryption and decryption in SM4-OFB mode, characterized in that: The two-round SM4 iterative acceleration process under the OFB mode includes the following steps: 1) In OFB mode, the calculation equation for any two SM4 encryption descriptions is: Among them, X a,b Indicates the b-th state value of the a-th round of encryption; represents XOR operation; T represents T transformation; rk a Indicates the key state value of the a+1th round; M0 indicates the initial plaintext information; M i Represents the input state value of the i-th round of encryption, M i+1 Represents the output state value of the i-th round of encryption, M0=ICV, ICV represents the initialization vector; 2) Generate a random number X′ i,34 ,X′ i,35 , and calculate the second encrypted input plaintext (X i+1,0 ,X i+1,1 ,X i+1,2 ,X i+1,3 )=(X′ i,35 ,X′ i,34 ,X i,33 ,X i,32 ), where X a,b Indicates the actual calculated state value, X′ a,b is the guessed state value; 3) Parallel computing: in, 4) Parallel calculation of variable X i,34 ,X′ i+1,4 ,in 5) Assumptions in Among them, σ0′ and σ0 represent the defined state values, T(σ0) represents T transformation, S(σ0) represents S-box transformation, and <<< represents circular left shift operation; 6) Calibrate the output variables of the first round of encryption in the second SM4 iteration: The first round of calibration parameters are: where X″ i+1,4 represents the defined state value, T(σ′0) represents the T transformation; 7) Parallel Computing X i,35 ,X′ i+1,5 : 8) Assumptions but Among them, δ0 and δ0′ represent the defined state values, and T(δ0) represents the T transformation.

2. The method according to claim 1, characterized in that The following steps are used to implement the SM4-OFB encryption acceleration process: 1) Input the initialization vector IV and perform the first 32-round SM4 encryption process; 2) When the first SM4 encryption process reaches the 30th round, the second SM4 encryption process is started using the method described in claim 1; 3) After the second SM4 encryption completes 2 rounds of encryption, the first SM4 completes all 32 rounds of encryption, and the output value is M1; 4) Use M1 to correct the state after the second SM4 encryption round 2, so that the state after the second SM4 encryption round 2 is the correct value; 5) Continue to perform the second SM4 encryption and jump to step 2); 6) When encryption is completed After the SM4 encryption, record the intermediate value of the output 7) Continue to execute all encryption processes until all intermediate values are generated; 8) The ciphertext and the intermediate value Sent to the decryptor.

3. The method according to claim 1 or 2, characterized in that The following steps are used to implement the SM4-OFB decryption acceleration process: 1) The decryption party receives the ciphertext data and the intermediate value Input the initialization vector IV and perform the first 32-round SM4 encryption process; 2) When the first SM4 encryption process reaches the 30th round, the second SM4 encryption process is started using the method described in claim 1; 3) After the second SM4 encryption completes 2 rounds of encryption, the first SM4 completes all 32 rounds of encryption, and the output value is M1; 4) Use M1 to correct the state after the second SM4 encryption round 2, so that the state after the second SM4 encryption round 2 is the correct value; 5) Synchronously execute The 32-round encryption process of SM4, refer to steps 2), 3), and 4); 6) Continue to execute the second SM4 encryption synchronously and jump to step 2) to execute the Second SM4 encryption and jump to step 2); 7) When encryption is completed After the nth SM4 encryption, the nth SM4 encryption is also completed to obtain the final plaintext data.

4. An encryption and decryption acceleration device for SM4-OFB mode, characterized in that: It includes an SM4-OFB encryption acceleration module and / or an SM4-OFB decryption acceleration module; the SM4-OFB encryption acceleration module adopts the method described in claim 1 or 2 to achieve SM4-OFB encryption acceleration; the SM4-OFB decryption acceleration module adopts the method described in claim 1 or 3 to achieve SM4-OFB decryption acceleration.

5. A computer device, characterized in that: The method comprises a memory and a processor, wherein the memory stores a computer program, the computer program is configured to be executed by the processor, and the computer program comprises instructions for executing the method according to any one of claims 1 to 3.

6. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a computer, the method according to any one of claims 1 to 3 is implemented.