Decoder and carrier rocket

Abstract

The embodiment of the invention provides a decoder and a carrier rocket, and the decoder comprises a jump edge detection module which is used for receiving a voltage signal which is coded by adopting a Manchester II code and is converted by a physical layer transceiver, an integrator which is used for carrying out integration by adopting a positive value when the received RX is at a high level so as to obtain an integral value, when the received RX # is at a high level, a negative value is adopted for integration to obtain an integral value; the synchronous head detection and window comparator is used for pre-judging the synchronous head according to the integral value and the starting time of the jump edge of the RX or the starting time of the jump edge of the RX # by utilizing the symmetry of the synchronous head, determining a code element value corresponding to a data bit according to the occurrence of the integral value in an upper judgment window or a lower judgment window and the jump edge of the RX or the RX # in sequence, and sending the code element value to the synchronous head detection and window comparator; and when the data bits behind the synchronous head are decoded or the decoding is completed, the judgment of the synchronous head is successful. The problem of serious code distortion caused by overlong bus can be solved, and the synchronous head and the data bit can be reliably decoded.

Description

Technical Field

[0001] The present invention relates to the field of decoding, and in particular to a decoder and a carrier rocket. Background Art

[0002] In the current context of commercial aerospace, rocket bodies are becoming longer and longer, and the length of the 1553B bus is almost more than 150 meters. Long-distance bus transmission causes serious code distortion at the receiving end, and the traditional method has a high bit error rate in decoding in complex long-distance environments.

[0003] The closest approach currently is a decoder for Manchester II codes with fixed sync headers that uses an integral principle. However, the 1553B standard uses two sync headers to represent data words and command words, making traditional fixed sync header decoding inadequate. Furthermore, similar methods lack fault detection capabilities.

[0004] In the process of implementing the present invention, the applicant discovered that the prior art has at least the following problems:

[0005] For large launch vehicles, the 1553B bus is too long and the code distortion is serious, resulting in high bit error rate and poor reliability of traditional decoders. Summary of the Invention

[0006] The embodiments of the present invention provide a decoder and a carrier rocket, which can solve the technical problem in the prior art that the traditional decoder has a high bit error rate and poor reliability due to serious code distortion caused by the excessive length of the 1553B bus.

[0007] To achieve the above objectives, on the one hand, an embodiment of the present invention provides a decoder, comprising:

[0008] The transition edge detection module is used to receive a voltage signal encoded using Manchester II code and converted by a physical layer transceiver, wherein the voltage signal includes two digital level signals: RX and RX#; and detect the transition edges of RX and RX# respectively;

[0009] An integrator, configured to integrate a positive value to obtain an integral value when the received RX is at a high level, and to integrate a negative value to obtain an integral value when the received RX# is at a high level;

[0010] The synchronization header detection and window comparator is used to utilize the symmetry of the synchronization header to pre-determine the synchronization header based on the integration value and the starting time of the RX jump edge or the starting time of the RX# jump edge. Then, it appears in the upper decision window or the lower decision window according to the integration value, and determines the code value corresponding to the data bit according to the RX or RX# jump edge. The synchronization header judgment is considered successful when the data bit after the synchronization header is decoded or when the decoding is completed.

[0011] On the other hand, an embodiment of the present invention provides a launch vehicle, comprising the aforementioned decoder, wherein the decoder is connected to a physical layer transceiver, and the physical layer transceiver is connected to a 1553B bus, wherein the decoder is integrated on an FPGA.

[0012] The above technical solution has the following beneficial effects:

[0013] For the two digital level signals RX and RX# to be received, RX is 1 and RX# is 0 when the voltage signal is a positive voltage difference, RX is 0 and RX# is 1 when the voltage signal is a negative voltage difference, and both RX and RX# are 0 when the voltage difference is small. Therefore, when the current RX signal is high, a positive value is used for integration to obtain the integral value, and positive values are integrated upward. Therefore, the code element value of the corresponding synchronization header or data bit can be obtained by decoding the current RX signal. Since the corresponding code element value is obtained by decoding the current RX signal, the code element value corresponding to the current RX# signal can also be obtained.

[0014] Similarly, when the current RX# signal is high, a negative value is used for integration to obtain the integral value, and the negative value is used for downward integration. That is, when the received voltage signal RX is 1, the integrator increments by 1, and when RX# is 1, the integrator decrements by 1; otherwise, the integrator remains constant. Thus, the code element value of the corresponding sync header or data bit can be obtained by decoding the current RX# signal. Since the corresponding code element value is obtained by decoding the current RX# signal, the code element value corresponding to the current RX signal can also be obtained. It is then necessary to determine the start time of the bit corresponding to the current RX or RX# signal. By predetermining the start time of the sync header based on the integrated value and the start time of the RX or RX# transition edge according to the embodiments of the present invention, the end time of the first half of the sync header can be determined. The symmetry of the sync header allows the code element value and corresponding end time of the second half of the sync header to be determined. Subsequently, the code element value corresponding to the data bit and the start and end times of the data bit are determined based on the presence of the integrated value in the upper or lower decision window and the transition edge of RX or RX#. When the data bits following the synchronization header are decoded or the decoding is completed, the synchronization header is deemed to be successfully determined and the synchronization header is locked.

[0015] The technical means of the embodiments of the present invention: integration value, jump edge and decision window can address the technical problems of serious code distortion of the voltage signal and high bit error rate and poor reliability of traditional decoders caused by the long 1553B bus for transmitting the voltage signal encoded by Manchester II code and converted by the physical layer transceiver. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0017] Figure 1 is a structural diagram of a decoder according to an embodiment of the present invention;

[0018] Figure 2 is a circuit block diagram including a decoder according to an embodiment of the present invention;

[0019] Figure 3 is a logic block diagram of a decoder algorithm according to an embodiment of the present invention;

[0020] Figure 4 is a Manchester II biphasic level diagram of an embodiment of the present invention;

[0021] Figure 5 : is a synchronization header waveform of Manchester II type encoding according to an embodiment of the present invention;

[0022] Figure 6 is a decoding state machine diagram of an embodiment of the present invention;

[0023] Figure 7 is a simulation waveform of decoding according to an embodiment of the present invention;

[0024] Figure 8 is the data bit decoding of the simulation of the embodiment of the present invention;

[0025] Figure 9 This is a typical command / status word of an embodiment of the present invention, and its data area is encoded into hexadecimal (A123)H. DETAILED DESCRIPTION

[0026] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0027] The abbreviations used in the embodiments of the present invention are defined as follows:

[0028] Manchester II code: A biphase level code where 1 / -1 represents bit 1 and -1 / 1 represents bit 0.

[0029] Bit time: The time required to transmit a symbol bit as specified in the 1553B standard, also known as a symbol period in the communications field.

[0030] Code element: A symbol that carries information, which can be a set of voltage waveforms with certain characteristic patterns. A single waveform can be a code element.

[0031] bit: a binary digit.

[0032] FPGA: Field Programmable Gate Array, field programmable gate array.

[0033] IP core: Intellectual Property core, short for intellectual property core, is a hardware description language program with specific circuit functions.

[0034] like Figure 1 As shown, in combination with an embodiment of the present invention, a decoder is provided, comprising:

[0035] The transition edge detection module is used to receive a voltage signal encoded using Manchester II code and converted by a physical layer transceiver, wherein the voltage signal includes two digital level signals: RX and RX#; and detect the transition edges of RX and RX# respectively;

[0036] An integrator, configured to integrate a positive value to obtain an integral value when the received RX is at a high level, and to integrate a negative value to obtain an integral value when the received RX# is at a high level;

[0037] The synchronization header detection and window comparator is used to utilize the symmetry of the synchronization header to pre-determine the synchronization header based on the integration value and the starting time of the RX jump edge or the starting time of the RX# jump edge. Then, it appears in the upper decision window or the lower decision window according to the integration value, and determines the code value corresponding to the data bit according to the RX or RX# jump edge. The synchronization header judgment is considered successful when the data bit after the synchronization header is decoded or when the decoding is completed.

[0038] For the two digital level signals RX and RX# to be received, RX is 1 and RX# is 0 when the voltage signal is a positive voltage difference, RX is 0 and RX# is 1 when the voltage signal is a negative voltage difference, and both RX and RX# are 0 when the voltage difference is small. Therefore, when the current RX signal is high, a positive value is used for integration to obtain the integral value, and positive values are integrated upward. Therefore, the code element value of the corresponding synchronization header or data bit can be obtained by decoding the current RX signal. Since the corresponding code element value is obtained by decoding the current RX signal, the code element value corresponding to the current RX# signal can also be obtained.

[0039] Similarly, when the current RX# signal is high, a negative value is used for integration to obtain the integral value, and the negative value is used for downward integration. That is, when the received voltage signal RX is 1, the integrator increments by 1, and when RX# is 1, the integrator decrements by 1; otherwise, the integrator remains constant. Thus, the code element value of the corresponding sync header or data bit can be obtained by decoding the current RX# signal. Since the corresponding code element value is obtained by decoding the current RX# signal, the code element value corresponding to the current RX signal can also be obtained. It is then necessary to determine the start time of the bit corresponding to the current RX or RX# signal. By predetermining the start time of the sync header based on the integrated value and the start time of the RX or RX# transition edge according to the embodiments of the present invention, the end time of the first half of the sync header can be determined. The symmetry of the sync header allows the code element value and corresponding end time of the second half of the sync header to be determined. Subsequently, the code element value corresponding to the data bit and the start and end times of the data bit are determined based on the presence of the integrated value in the upper or lower decision window and the transition edge of RX or RX#. When the data bits following the synchronization header are decoded or the decoding is completed, the synchronization header is deemed to be successfully determined and the synchronization header is locked.

[0040] The technical means of the embodiments of the present invention: integration value, jump edge and decision window can address the technical problems of serious code distortion of the voltage signal and high bit error rate and poor reliability of traditional decoders caused by the long 1553B bus for transmitting the voltage signal encoded by Manchester II code and converted by the physical layer transceiver.

[0041] Preferably, the transition edge refers to a rising edge;

[0042] The synchronization header detection and window comparator includes a synchronization header decision submodule, and the synchronization header decision submodule is used to:

[0043] In the process of waiting for the synchronization header, if the integral value corresponding to RX for the first half of the synchronization header is higher than the synchronization header upper threshold in the upper threshold comparator since the moment when RX# has a rising edge, the command / status word is marked as 1 and the data word is marked as 0, wherein the synchronization header upper threshold is a positive value;

[0044] If, starting from the moment when RX has a rising edge, for the first half of the synchronization header, the integral value corresponding to RX# is lower than the synchronization header lower limit threshold in the lower limit threshold comparator, the instruction / status word is marked as 0, and the data word is marked as 1, wherein the synchronization header lower limit threshold is a negative value.

[0045] Among them, the 1553B bus is half-duplex (data transmission means that data can be transmitted in two directions of a signal carrier, but not at the same time), time division multiplexing transmission mode. Figure 4As shown in the figure, 1553B bus data is transmitted in serial mode in the bus. The physical layer transceiver uses Manchester II type biphase level encoding. 1 / -1 represents bit 1, -1 / 1 represents bit 0, and 0 / 0 represents bus idle. The bit transmission rate is usually 1Mbps. Figure 5 As shown, the word format of the 1553B bus differs from conventional Manchester-coded communication in that its data bit synchronization headers have two types: the instruction / status word and the data word. The instruction / status word consists of a high level at 1.5 bits and a low level at 1.5 bits, while the data word, on the other hand, consists of a low level at 1.5 bits and a high level at 1.5 bits. Therefore, accurate detection of the synchronization header is crucial for correct decoding of the 1553B bus. The instruction / status word is specified in the 1553B standard and represents two meanings of the same synchronization header waveform: the instruction word is sent by the master control (BC), and the status word is returned by the remote terminal (RT). Because the waveforms of the "instruction" and "status word" are identical, in this embodiment of the present invention, the "instruction" and "status word" are treated as the same variable. Figure 5 The first row is the reference code rate clock; the second, third, and fourth rows are the non-return-to-zero code waveforms (binary digital signals (signals before encoding)).

[0046] Due to the Manchester II code's symmetrical bipolar nature, embodiments of the present invention employ an "integrated threshold window comparison method" for decoding. This method employs two window comparators (upper and lower) within the decoder for decoding, as well as two upper and lower threshold comparators for determining the synchronization header. Ideally, the integral value of the symbol waveform within a symbol period is zero. A symbol represents a bit in the 1553B bus standard, and a synchronization header occupies three bits.

[0047] The synchronization header upper threshold and the synchronization header lower threshold are both set to the integral value corresponding to half the synchronization header duration. When the synchronization header upper threshold is a positive value, it is used to determine the synchronization header of the instruction / status word. When the synchronization header lower threshold is a negative value, it is used to determine the synchronization header of the data word.

[0048] The sync header determination submodule uses two threshold comparators: an upper threshold comparator and a lower threshold comparator. To determine the sync header type, when the integrated value exceeds the upper sync header threshold in the upper threshold comparator, the flag_csw register is marked as 1, indicating that the flag_csw register likely contains the instruction / status word, indicating that the instruction / status word is valid. The data word is marked as 0, indicating that the data word is invalid. When the integrated value falls below the lower sync header threshold in the lower threshold comparator, the flag_dw register is marked as 1, indicating that the flag_dw register likely contains the data word, indicating that the data word is valid. The instruction / status word is marked as 0, indicating that the instruction / status word is invalid. During normal operation, the two register values are mutually exclusive (cannot be 0 or 1 at the same time). When the first valid bit (data bit) after the sync header appears or when decoding is complete, the sync header determination is considered successful, and the final sync header status is latched. Simultaneously, the decoding state machine transitions to the decoding state.

[0049] Preferably, the synchronization header detection and window comparator further includes a decision window, and the decision window includes the upper decision window and the lower decision window, wherein:

[0050] The judgment window is used to display the integral value corresponding to the data bit after the synchronization header and make a judgment based on the integral value corresponding to the data bit;

[0051] If the integral value corresponding to the current data bit falls within the upper decision window and RX# has a rising edge within the lower decision window, it indicates that the current data bit is valid and meets the decoding condition for decoding the current data bit into codeword 1, then the current data bit is decoded into a codeword with a codeword value of 1; or

[0052] If the integral value corresponding to the current data bit falls within the lower decision window and RX has a rising edge within the upper decision window, it indicates that the current data bit is valid and meets the decoding conditions for decoding the current data bit into codeword 0, then the current data bit is decoded into a codeword with a codeword value of 0.

[0053] When decoding one of the voltage signals, the decision moment is based on the decision window (upper decision window or lower decision window) where the integral value corresponding to the voltage signal is located, and the transition of the other voltage signal (i.e., the appearance of a rising edge). Because the two level signals are exactly 180 degrees apart, and because each signal is distorted, the transition edges of the two voltage signals that originally overlap at the same time may be misaligned, that is, the impact on each voltage signal causes the signal width to change, resulting in different overlaps between the transition edges of the two voltage signals; when the other voltage signal has a rising edge, the integral value of the voltage signal is already very high, that is, it has entered the corresponding decision window, so it can be very clearly and accurately judged that the voltage signal is valid, indicating that the current data bit is valid and meets the decoding conditions for decoding the current data bit into code element 0 or 1.

[0054] Repeat the above decoding process until all data bits are decoded.

[0055] Preferably, the decoder further comprises:

[0056] a data receiving shift register, configured to, after decoding a current data bit into a symbol with a symbol value of 1, receive the symbol value 1 and latch the symbol value 1; or, after decoding the current data bit into a symbol with a symbol value of 0, receive the symbol value 0 and latch the symbol value 0;

[0057] And after obtaining the next code element value, the previous code element value is shifted by one position in sequence, and then the next code element value is received and latched.

[0058] The decoded code element value is either 1 or 0. The data receiving shift register shifts the status of the received decoded code element in sequence according to the results of the synchronization header detection and the window comparator. Shift reception is to use the serial input and parallel output shift register to receive and store these successfully decoded code words in sequence. The receiving process continues until all 17 bits of data are received.

[0059] Preferably, the upper decision window has a first upper threshold and a first lower threshold, and the position and range of the upper decision window are determined by the first upper threshold and the first lower threshold; the lower decision window has a second upper threshold and a second lower threshold, and the position and range of the lower decision window are determined by the second upper threshold and the second lower threshold;

[0060] The judgment window is specifically used for:

[0061] If the integral value corresponding to the current data bit exceeds the first lower limit threshold of the upper decision window and is less than the first upper limit threshold, it indicates that the integral value corresponding to the current data bit falls within the upper decision window;

[0062] If the integral value corresponding to the current data bit crosses the second upper threshold of the lower decision window and is greater than the second lower threshold, it indicates that the integral value corresponding to the current data bit falls within the lower decision window.

[0063] For decoding of data bits, an upper decision window and a lower decision window are set. Each decision window has an upper threshold and a lower threshold. Reasonable upper threshold and lower threshold are set so that the difference between the upper threshold and the lower threshold of each window can adapt to the decoder's ability to adapt to voltage signals (code types).

[0064] Preferably, the decoder further comprises a state machine, wherein:

[0065] The synchronization header judgment submodule is further configured to deem the synchronization header judgment successful when the first data bit after the synchronization header is decoded to obtain the corresponding code element value, and to determine the second half of the synchronization header by utilizing the symmetry of the synchronization header and latch the synchronization header mark;

[0066] The state machine is used to jump from the current state to the next state according to the state change during the decoding process. Figure 6 As shown, the state machine includes: Waiting for Sync Header, Decoding, Decoding Error, and Idle / Complete. When in the Waiting for Sync Header state, it jumps to Decoding if the sync head is found. When the bus is idle or the sync head condition is not met, it remains in the Waiting for Sync Header state. When decoding is complete, it jumps from the Decoding state to the Idle / Complete state. In the event of a decoding error, it jumps from the Decoding state to the Decoding Error state. It can also jump from the Decoding Error state to the Idle / Complete state. When the number of decoded bits is 17 and the parity bit and the first 16 bits of data are verified, the state machine jumps to the Idle / Complete state. The state machine uses a one-hot encoding, which provides a certain degree of fault tolerance. Of course, other encodings, such as Gray code, can also be used.

[0067] Preferably, the integrator is further configured to correct the integral value corresponding to the current data bit to the integral value corresponding to half the current data bit while decoding the current data bit into a symbol value.

[0068] For decoding of data bits, an upper decision window and a lower decision window are set. Each decision window has an upper threshold and a lower threshold. The difference between the upper threshold and the lower threshold of the window will affect the ability of the decoder to adapt to code distortion. The ideal value of the difference between the center value of the decision window ((upper threshold + lower threshold) / 2, that is, the middle position of the decision window) and the value is the integral value corresponding to the half position. Therefore, the integral value corresponding to the current data bit is corrected to the integral value corresponding to the half position of the current data bit to eliminate the integral error caused by code distortion. Figure 8In the example, an integrator is used to integrate the received RX and RX#, and while decoding the current data bit into a symbol value, the integral value shown in the circle is corrected to the straight line below to eliminate the accumulation of pattern width errors in the integrator caused by signal distortion and data clock jitter on the 1553B bus. Otherwise, the accumulation of such errors will continue to affect the decision of subsequent symbols (because the integral value of the previous symbol will also be used in the integration process of the next symbol). Figure 8 As shown, the first column is the signal name, and the second column is the signal value at the time indicated by the yellow vertical line.

[0069] Preferably, the decoder further includes a decoding error judgment module, wherein the decoding error judgment module is configured to:

[0070] When the synchronization header is severely distorted and a valid synchronization header cannot be determined, the synchronization header decoding error is determined.

[0071] When waiting for the synchronization head state, compare the difference between the integrator rise and fall time to see if it is seriously out of tolerance. If it is out of tolerance, the corresponding error indication position is 1, and it is automatically cleared after it is correctly decoded once.

[0072] If a valid number of code elements cannot be correctly determined within a preset time, the data bit decoding error is determined;

[0073] or,

[0074] If the check bit is wrong, it is determined that the data bit decoding is wrong, wherein the check bit is a check result obtained by performing real-time check on the code element value received in the data receiving shift register by a parity check module;

[0075] or,

[0076] When the width difference between the first 1.5 bit hours and the last 1.5 bit hours of the synchronization header is greater than the preset value, resulting in the integrator output value at the first symbol position after the synchronization header not being within the upper and lower decision windows of the integration, the synchronization header decoding is determined to be an error;

[0077] When more than one bit of the binary state code representing the state machine is 1 or all bits are 0, it is determined that the state machine has an error.

[0078] If the error is out of tolerance, the corresponding error indicator position is 1, and it is automatically cleared after each correct decoding. The decoding error judgment module can identify different errors and mark them with corresponding symbols. Therefore, the rich identification facilitates debugging work under complex working conditions.

[0079] Preferably, the transition edge detection module is specifically used to:

[0080] Receives a voltage signal from the 1553B bus that is encoded using Manchester II code and converted by the physical layer transceiver. Figure 2 This is a partial circuit block diagram of the decoder of an embodiment of the present invention when applied to a specific system, including a decoder, a shared message memory, a 1553BBC controller, a 1553BRT controller, a 1553BMT controller, and a bus interface. The decoder is located and is provided separately for use within the 1553B bus controller. The 1553B bus is a redundant bus, with at least two paths, Bus A (BUSA) and Bus B (BUSB), backing up each other. Decoder A and Decoder B each serve a bus, BUSA, and BUSB. There is a protocol layer behind decoders A and B for processing the 1553B bus protocol (AB bus selection). The protocol layer has the right to decide whether to receive data from Bus A or Bus B.

[0081] Decoder A and Decoder B are connected to 1553B bus physical layer transceivers A and B, respectively. The interfaces of Decoder A and Decoder B are standardized, with inputs of two signals, RX and RX#, facilitating connection to the 1553B bus physical layer transceiver chip. The output is a standard AXI-STREAM interface, facilitating ease of use and integration. AXI-STREAM is a standard CPU bus protocol jointly developed by ARM and other companies. AXI (Advanced Extensible Interface) is commonly referred to in English as Advanced Extensible Interface - Streaming Protocol.

[0082] In summary, if Figure 3 As shown in FIG. 1 , a logic block diagram of a decoder algorithm according to an embodiment of the present invention is shown. The left side shows the input of the 1553B bus signal to be decoded. The signal is two digital level signals coming from the physical layer transceiver channel of the 1553B bus (used for converting binary digital signals to analog waveforms on the bus). The two signals are denoted as RX and RX#. When there is a positive voltage difference on the 1553B bus, RX is 1 and RX# is 0. When there is a negative voltage difference on the bus, RX is 0 and RX# is 1. When the bus voltage difference is small, both RX and RX# are 0.

[0083] 1. The transition edge detection module is used to detect the rising edge and falling edge of the above RX and RX# signals respectively.

[0084] 2. The integrator is used to integrate the RX and RX# signals: when RX is 1, the integrator adds 1; when RX# is 1, the integrator subtracts 1; otherwise, the integrator remains constant. The upper and lower limits of the integrator's integration are limited according to the parameters necessary for the decoder's operation, such as the working master clock frequency, oversampling rate, decision window threshold, etc. The time step of integration is the clock period of the working clock. When the half synchronization header is 1.5 bits, the subsequent data code element is 1 bit. The integrator has a reasonable limit range. The limit range is set according to the communication code element rate and other settings to prevent the integrator from overflowing. The integrator also has the function of correcting the integration error and the ability to self-clear in time according to the idle state of the bus to prevent the accumulation and spread of errors.

[0085] 3. The sync header detector and window comparator are used to determine the status of the sync header and data bits (i.e., symbol value) based on the rising edge time of the RX or RX# signal and the integrated value of the integrator. Simultaneously, the integrated value of the integrator is corrected based on the respective status of the sync header and data bits (i.e., symbol value) to eliminate integration errors caused by pattern distortion.

[0086] 4. The timeout counter and receive counter modules are used to determine the receive decoding timeout. For example, if the judgment condition is still not met after more than 1 bit after the synchronization header is found, the decoding times out. The modules also count the number of correctly received code elements and provide a judgment basis for the error detection logic of the decoding error judgment module.

[0087] 5. The error detection logic of the decoding error judgment module is used to indicate the working status of the decoder. The working status is an indication signal of whether the decoder is working normally or abnormally.

[0088] 6. The parity check module is used to perform real-time verification on the code element value received in the data receiving shift register to obtain the verification result.

[0089] 7. The data receiving shift register is used to sequentially shift the state (symbol value) of the received decoded codeword according to the decoding results of the synchronization header detection and the window comparator.

[0090] 8. The AXI-STREAM interface logic is used to aggregate received data, verification results, and error status to form standard AXI-STREAM bus protocol interface logic.

[0091] like Figure 7 As shown in the figure, it is a simulated voltage signal, decoder_int (decoder_int is a variable name, representing the value of the integrator output) is the integrator output waveform, and this series of waveforms is the sequential transmission of instruction / status words (instruction word, status word respectively). Figure 7In the figure, the bottom two lines are used to pre-judge and mark whether the current data packet is a command word / status word or a data word; flag_csw represents the mark (flag bit) of the command / status word, and flag_dw represents the mark (flag bit) of the data word.

[0092] Figure 9 For a typical command / status word, its data area is encoded into hexadecimal (A123)H. The first column is the signal name, and the second column is the signal value at the time indicated by the yellow vertical line.

[0093] First, the synchronization header, which occupies three bits, is shown. The integrator output waveform (decoder_int) produces a large triangular waveform. When the integrated value exceeds the upper threshold of the lower decision window, flag_csw is set to 1, indicating a possible command / status word. Subsequently, when the integrator output falls within the upper window threshold and the RX# signal (rx_data_n in the figure) experiences a rising edge, the decoding condition for a symbol is met, representing a logic level 1. Similarly, when the integrator output falls within the lower decision window threshold and the RX signal (rx_data in the figure) experiences a rising edge, the decoding condition for a symbol is met, representing a logic level 0. This continues in this manner. After decoding the next 15 symbols, the receive shift register value, the parity check module output, and the error detection logic output of the decoding error determination module are simultaneously latched, forming the final decoder output. This ultimately forms the output timing of the standard interface via the AXI-STREAM interface logic.

[0094] Preferably, the 1553B bus is mostly used in fields such as aerospace and railways. The decoding algorithm for its voltage signal is the core of 1553B bus-related products, so the decoder can be used in any equipment and facilities that require the 1553B bus, such as aviation, aerospace, railways, drilling and exploration. Any equipment and facilities of the 1553B bus include 1553B bus monitoring equipment, 1553B active couplers, 1553B bus controller chip designs, 1553B bus controllers, and all other products that require decoding of 1553B bus signals. For 1553B active couplers, it can be modified to decode and encode at the same time. For example, the encoding work starts immediately after finding the synchronization header, and each decoded code element is pushed into the cache. The encoder continuously reads the data in the cache and re-encodes it to achieve the functional development of a highly reliable 1553B bus signal repeater.

[0095] In combination with an embodiment of the present invention, a launch vehicle is provided, comprising any of the aforementioned decoders, wherein the decoder is connected to a physical layer transceiver, and the physical layer transceiver is connected to a 1553B bus, wherein the decoder is integrated on an FPGA.

[0096] The beneficial effects achieved by the embodiments of the present invention are as follows:

[0097] 1. The embodiment of the present invention adopts the sync header detection based on the integral value and the window comparator in accordance with the 1553B bus standard, and fully realizes the sync header detection, data bit decoding and error indication functions of the 1553B voltage signal. In the test environment of the 1553B bus with the same length as that in the prior art, no bit errors occurred when using this decoder.

[0098] Using an integrated decoder within the FPGA minimizes FPGA resources (approximately 194 LUTs and 160 FFs). This improves decoder reliability, eliminates the need for a dedicated decoder chip, and reduces production and R&D costs, PCB area, and FPGA resources, resulting in a simple and efficient design. The advantages of using FPRGA include flexibility, reconfigurability, strong real-time performance, and compatibility with existing hardware, eliminating the need for additional processor hardware.

[0099] 2. The integration-based sync header detection and window comparator eliminate the need for dedicated sampling clock recovery and provide symbol waveform filtering and de-burring capabilities. This addresses the severe distortion of long 1553B bus lines. Without the need for specialized filter circuits, the integration step size can be flexibly configured to reliably decode both sync headers and data bits. This highly reliable design effectively reduces the bit error rate (BER) even in long 1553B bus lines and complex interference environments. Theoretically, reliable decoding can be achieved even with a 25% symbol waveform skew. This addresses the difficulty of estimating the optimal decision moment in traditional decoders over long distances and complex environments, making decoding susceptible to interference. This addresses the existing problem that "existing decoders often rely on the symbol's own transition edges (rising and falling edges) as the basis for determining the decision moment. This makes them sensitive to severely distorted signals and difficult to accurately estimate the optimal decision moment, resulting in high BER in complex environments. Traditional decoders often use 16x oversampling, which limits their adaptability to the large random waveform width distortion of Manchester II code patterns, making it difficult to accurately select the optimal sampling decision moment."

[0100] 3. It has complete decoding error indication function and error indication identification signal, which is convenient for debugging and fault location and troubleshooting in actual application, and realizes the fault diagnosis function when it is integrated, as well as the system-level bus error diagnosis function of the integrated system.

[0101] 4. A standard AXI-STREAM bus interface is formed, which is convenient for use and integration into specific systems.

[0102] It should be understood that the specific order or hierarchy of steps in the disclosed processes is an example of an exemplary method. Based on design preferences, it should be understood that the specific order or hierarchy of steps in the process can be rearranged without departing from the scope of the present disclosure. The accompanying method claims present elements of the various steps in an exemplary order and are not intended to be limited to the specific order or hierarchy described.

[0103] In the foregoing detailed description, various features are grouped together in a single embodiment to simplify the disclosure. This method of disclosure should not be interpreted as reflecting an intention that embodiments of the claimed subject matter require more features than are expressly recited in each claim. On the contrary, as reflected in the appended claims, the invention comprises less than all the features of any individual disclosed embodiment. The appended claims are hereby expressly incorporated into the detailed description, with each claim standing on its own as a separate preferred embodiment of the invention.

[0104] The above description of the disclosed embodiments is intended to enable any person skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure is not limited to the embodiments presented herein but is intended to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0105] The foregoing description includes examples of one or more embodiments. Of course, it is not possible to describe all possible combinations of components or methods for the purposes of describing the above embodiments, but one of ordinary skill in the art will recognize that the various embodiments may be further combined and arranged. Therefore, the embodiments described herein are intended to encompass all such changes, modifications and variations that fall within the scope of the appended claims. Furthermore, to the extent the term "comprising" is used in the specification or claims, the term is intended to be encompassed in a manner similar to the term "including," as explained in terms of "including," used as a transitional word in the claims. Furthermore, any use of the term "or" in the specification of the claims is intended to mean a "non-exclusive or."

[0106] Those skilled in the art will also appreciate that the various illustrative logical blocks, units, and steps listed in the embodiments of the present invention can be implemented by electronic hardware, computer software, or a combination of the two. To clearly demonstrate the interchangeability of hardware and software, the various illustrative components, units, and steps described above have generally described their functions. Whether such functions are implemented by hardware or software depends on the specific application and the design requirements of the entire system. Those skilled in the art may use various methods to implement the described functions for each specific application, but such implementation should not be understood as exceeding the scope of protection of the embodiments of the present invention.

[0107] The various illustrative logic blocks or units described in the embodiments of the present invention can be implemented or operated by a general-purpose processor, a digital signal processor, an application-specific integrated circuit (ASIC), a field programmable gate array or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof. The general-purpose processor can be a microprocessor, and optionally, the general-purpose processor can also be any conventional processor, controller, microcontroller or state machine. The processor can also be implemented by a combination of computing devices, such as a digital signal processor and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a digital signal processor core, or any other similar configuration.

[0108] The steps of the methods or algorithms described in the embodiments of the present invention may be directly embedded in hardware, a software module executed by a processor, or a combination of the two. The software module may be stored in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. For example, the storage medium may be connected to the processor so that the processor can read information from the storage medium and write information to the storage medium. Alternatively, the storage medium may also be integrated into the processor. The processor and storage medium may be provided in an ASIC, which may be provided in a user terminal. Alternatively, the processor and storage medium may also be provided in different components in the user terminal.

[0109] In one or more exemplary designs, the above-mentioned functions described in the embodiments of the present invention can be implemented in hardware, software, firmware, or any combination of the three. If implemented in software, these functions can be stored on a computer-readable medium or transmitted in the form of one or more instructions or codes on a computer-readable medium. Computer-readable media include computer storage media and communication media that facilitate the transfer of computer programs from one location to another. Storage media can be any available medium that can be accessed by a general or special computer. For example, such computer-readable media can include but are not limited to RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store program code in the form of instructions or data structures and other forms that can be read by a general or special computer, or a general or special processor. In addition, any connection can be appropriately defined as a computer-readable medium. For example, if the software is transmitted from a website, server or other remote resource via a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless methods such as infrared, wireless, and microwave, it is also included in the definition of computer-readable media. The disks and discs mentioned above include compact disks, laser disks, optical disks, DVDs, floppy disks, and Blu-ray discs. Disks typically reproduce data magnetically, while discs typically reproduce data optically with lasers. Combinations of the above may also be included in computer-readable media.

[0110] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A decoder, characterized in that: include: A transition edge detection module is configured to receive a voltage signal encoded using Manchester II code and converted by a physical layer transceiver, wherein the voltage signal includes two digital level signals: RX and RX#; and detect the transition edges of RX and RX# respectively; An integrator, configured to integrate a positive value to obtain an integral value when the received RX is at a high level, and to integrate a negative value to obtain an integral value when the received RX# is at a high level; The synchronization header detection and window comparator is used to utilize the symmetry of the synchronization header to pre-determine the synchronization header based on the integration value and the starting time of the RX jump edge or the starting time of the RX# jump edge. Then, it appears in the upper decision window or the lower decision window according to the integration value, and determines the code value corresponding to the data bit according to the RX or RX# jump edge. The synchronization header judgment is considered successful when the data bit after the synchronization header is decoded or when the decoding is completed.

2. The decoder according to claim 1, wherein The transition edge refers to the rising edge; The synchronization header detection and window comparator includes a synchronization header decision submodule, and the synchronization header decision submodule is used to: In the process of waiting for the synchronization header, if the integral value corresponding to RX for the first half of the synchronization header is higher than the synchronization header upper threshold in the upper threshold comparator since the moment when RX# has a rising edge, the command / status word is marked as 1 and the data word is marked as 0, wherein the synchronization header upper threshold is a positive value; If, starting from the moment when RX has a rising edge, for the first half of the synchronization header, the integral value corresponding to RX# is lower than the synchronization header lower limit threshold in the lower limit threshold comparator, the instruction / status word is marked as 0, and the data word is marked as 1, wherein the synchronization header lower limit threshold is a negative value.

3. The decoder according to claim 2, wherein: The synchronization header detection and window comparator further includes a decision window, and the decision window includes the upper decision window and the lower decision window, wherein: The judgment window is used to display the integral value corresponding to the data bit after the synchronization header and make a judgment based on the integral value corresponding to the data bit; If the integral value corresponding to the current data bit falls within the upper decision window and RX# has a rising edge within the lower decision window, it indicates that the current data bit is valid and meets the decoding condition for decoding the current data bit into codeword 1, then the current data bit is decoded into a codeword with a codeword value of 1; or If the integral value corresponding to the current data bit falls within the lower decision window and RX has a rising edge within the upper decision window, it indicates that the current data bit is valid and meets the decoding conditions for decoding the current data bit into codeword 0, then the current data bit is decoded into a codeword with a codeword value of 0.

4. The decoder according to claim 3, wherein Also includes: a data receiving shift register, configured to receive the code element value 1 and latch the code element value 1 after decoding the current data bit into the code element value 1; Alternatively, after decoding the current data bit into a codeword with a codeword value of 0, receiving the codeword value 0 and latching the codeword value 0; And after obtaining the next code element value, the previous code element value is shifted by one position in sequence, and then the next code element value is received and latched.

5. The decoder according to claim 3, wherein: The upper decision window has a first upper threshold and a first lower threshold, and the position and range of the upper decision window are determined by the first upper threshold and the first lower threshold; the lower decision window has a second upper threshold and a second lower threshold, and the position and range of the lower decision window are determined by the second upper threshold and the second lower threshold; The judgment window is specifically used for: If the integral value corresponding to the current data bit exceeds the first lower limit threshold of the upper decision window and is less than the first upper limit threshold, it indicates that the integral value corresponding to the current data bit falls within the upper decision window; If the integral value corresponding to the current data bit crosses the second upper threshold of the lower decision window and is greater than the second lower threshold, it indicates that the integral value corresponding to the current data bit falls within the lower decision window.

6. The decoder according to claim 3, wherein: Also included is a state machine, where: The synchronization header judgment submodule is further configured to deem the synchronization header judgment successful when the first data bit after the synchronization header is decoded to obtain the corresponding code element value, and to determine the second half of the synchronization header by utilizing the symmetry of the synchronization header and latch the synchronization header mark; The state machine is used to jump from the current state to the next state according to the state change during the decoding process.

7. The decoder according to claim 3, wherein: The integrator is further configured to correct the integral value corresponding to the current data bit to the integral value corresponding to half the current data bit while decoding the current data bit into a symbol value.

8. The decoder according to claim 6, wherein: The invention also includes a decoding error judgment module, wherein the decoding error judgment module is used to: When the synchronization header is severely distorted and a valid synchronization header cannot be determined, the synchronization header decoding error is determined. If a valid number of code elements cannot be correctly determined within a preset time, the data bit decoding error is determined; or, If the check bit is wrong, it is determined that the data bit decoding is wrong, wherein the check bit is a check result obtained by performing real-time check on the code element value received in the data receiving shift register by a parity check module; or, When the width difference between the first 1.5 bit hours and the last 1.5 bit hours of the synchronization header is greater than a preset value, it is determined that the synchronization header decoding is wrong; When more than one bit of the binary state code representing the state machine is 1 or all bits are 0, it is determined that the state machine has an error.

9. The decoder according to claim 1, wherein: The transition edge detection module is specifically used for: Receives a voltage signal from the 1553B bus that is encoded using Manchester II code and converted by the physical layer transceiver.

10. A launch vehicle, characterized in that: The decoder comprises the decoder according to any one of claims 1 to 9, wherein the decoder is connected to a physical layer transceiver, the physical layer transceiver is connected to a 1553B bus, and the decoder is integrated on an FPGA.

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